semiconductor devices

Abstract

An embodiment relates to a semiconductor device comprising: a first electrode; a first semiconductor layer of a first conductivity type connected to the first electrode; a second semiconductor layer of the first conductivity type arranged on the first semiconductor layer; a third semiconductor layer of the second conductivity type arranged on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type arranged on the third semiconductor layer; a second electrode connected to the third semiconductor layer and the fourth semiconductor layer; a gate extending from the fourth semiconductor layer toward the second semiconductor layer and adjacent to the third semiconductor layer; a field plate electrode extending in a direction from the fourth semiconductor layer toward the second semiconductor layer and adjacent to the second semiconductor layer; and a first insulating film arranged between the field plate electrode and the second semiconductor layer and having a first distance from a lower end to the lower end of the field plate electrode longer than a second distance to the first semiconductor layer.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2020-153263 (filing date: September 11, 2020), the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments relate to a semiconductor device. Background Art

[0003] Semiconductor devices such as MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) include a body diode. Summary of the Invention

[0004] Embodiments provide a semiconductor device having improved reverse recovery characteristics of a body diode.

[0005] A semiconductor device according to an embodiment includes: a first electrode; a first semiconductor layer of a first conductivity type connected to the first electrode; a second semiconductor layer of the first conductivity type provided on the first semiconductor layer and having an impurity concentration lower than the impurity concentration of the first semiconductor layer; a third semiconductor layer of the second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type provided on the third semiconductor layer; a second electrode connected to the third semiconductor layer and the fourth semiconductor layer; a gate extending from the fourth semiconductor layer toward the second semiconductor layer and adjacent to the third semiconductor layer; a field plate electrode extending in a direction from the fourth semiconductor layer toward the second semiconductor layer and extending to a position below the gate and adjacent to the second semiconductor layer; and a first insulating film provided between the gate and the third semiconductor layer, between the field plate electrode and the second semiconductor layer, and between the gate and the field plate electrode, wherein a first distance from a lower end to a lower end of the field plate electrode is longer than a second distance from the lower end to the first semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 It is a perspective view showing the semiconductor device according to the first embodiment.

[0007] Figure 2 It will Figure 1 FIG. 1 is a top view showing an enlarged view of the area surrounded by the dotted line A. FIG.

[0008] Figure 3 yes Figure 2 Cross-sectional view of line BB'.

[0009] Figure 4 yes Figure 2 Cross-sectional view of the C-C' line.

[0010] Figure 5 yes Figure 2 Cross-sectional view of line D-D'.

[0011] Figure 6 (a) represents the position in the vertical direction on the horizontal axis and the impurity concentration on the vertical axis on a logarithmic scale. Figure 3 The impurity concentration distribution curve on the E-E' line is shown in the figure. Figure 6 (b) is the horizontal axis taking the position in the up and down direction, and the vertical axis taking the Figure 6 The absolute value of the tangent line of the curve shown in (a) is expressed as Figure 6 (a) is a graph showing changes in the absolute value of the slope of the tangent line of the curve.

[0012] Figure 7 This is a circuit diagram showing an example of use of the semiconductor device according to the first embodiment.

[0013] Figure 8 is a cross-sectional view showing a semiconductor device according to a reference example.

[0014] Figure 9 (a) is a graph showing a simulation of reverse recovery characteristics of the semiconductor device of the first embodiment and the semiconductor device of the reference example, with time on the horizontal axis, current on the first vertical axis, and voltage on the second vertical axis. Figure 9 (b) is to Figure 9 A graph showing an enlarged portion of (a).

[0015] Figure 10 (a)~ Figure 10 (d) is a map showing the simulation results of the hole concentration distribution of the semiconductor device of the reference example. Figure 10 (e)~ Figure 10 (h) is a map showing the simulation results of the hole concentration distribution of the semiconductor device according to the first embodiment.

[0016] Figure 11 This is a cross-sectional view showing a semiconductor device according to a second embodiment. DETAILED DESCRIPTION

[0017] <First embodiment>

[0018] First, the first embodiment will be described.

[0019] Figure 1 It is a perspective view showing the semiconductor device according to this embodiment.

[0020] Figure 2 It will Figure 1 FIG. 1 is a top view showing an enlarged view of the area surrounded by the dotted line A. FIG.

[0021] Figure 3 yes Figure 2 Cross-sectional view of line BB'.

[0022] Figure 4 yes Figure 2 Cross-sectional view of the C-C' line.

[0023] Figure 5 yes Figure 2 Cross-sectional view of line D-D'.

[0024] The semiconductor device 100 of this embodiment is a MOSFET. Figure 3 In summary, the semiconductor device 100 includes a drain (first electrode) 110, an n + Drain layer (first semiconductor layer) 120, n semiconductor layer (second semiconductor layer) 130, p base diffusion layer (third semiconductor layer) 140, n + A source diffusion layer (fourth semiconductor layer) 150 , a source (second electrode) 160 , a gate 170 , and a field plate electrode 180 .

[0025] The following describes each component of the semiconductor device 100 in detail. For ease of understanding, the following uses an XYZ rectangular coordinate system. The direction from the drain 110 toward the source 160 is referred to as the "Z direction." Furthermore, a direction perpendicular to the Z direction is referred to as the "X direction." Furthermore, a direction perpendicular to both the Z and X directions is referred to as the "Y direction." Furthermore, the Z direction is referred to as "upward," and the direction opposite to the Z direction is referred to as "downward."

[0026] In addition, the following, n + The descriptions of + and n indicate the relative levels of impurity concentrations in each conductivity type. Specifically, descriptions marked with a "+" indicate a higher impurity concentration than those not marked with a "+." Here, "impurity concentration" refers to the net impurity concentration after the cancellation of both donor and acceptor impurities in each region.

[0027] like Figure 1 As shown in FIG. 1 , the drain electrode 110 is in the shape of a substantially flat plate. Figure 3 As shown, an n + The drain layer 120 .

[0028] n + The drain layer 120 is connected to the drain electrode 110. + The drain layer 120 can be formed by, for example, adding impurities that serve as donors to a silicon substrate. + An n-semiconductor layer 130 is disposed on the drain layer 120 .

[0029] The n semiconductor layer 130 includes an n buffer region (first region) 131 and an n drift region (second region) 132 provided on the n buffer region 131. The impurity concentration of the n buffer region 131 is greater than that of the n + The impurity concentration of the drain layer 120 is low. The impurity concentration of the n drift region 132 is lower than the impurity concentration of the n buffer region 131 .

[0030] A p-base diffusion layer 140 is provided on the n-semiconductor layer 130. + Source diffusion layer 150 .

[0031] In the n semiconductor layer 130, the p base diffusion layer 140 and the n + A plurality of channels T are provided in the source diffusion layer 150. Figure 2 As shown, each trench T extends along the Y direction. A plurality of trenches T are arranged in the X direction.

[0032] like Figure 3 As shown, each channel T starts from n + The upper surface 150a of the source diffusion layer 150 extends downward and reaches the n buffer region 131 of the n semiconductor layer 130. However, the channel does not have to reach the n buffer region. + The drain layer 120 is separated. However, the channel can also reach the n + Drain layer. In addition, the bottom portion of each trench T is rounded. However, the bottom portion of each trench T does not need to be rounded.

[0033] The p base diffusion layer 140 and the n + The source diffusion layer 150 is divided into a plurality of regions S by the plurality of trenches T. The plurality of regions S are arranged in the X direction.

[0034] In each trench T, a gate 170 , a field plate electrode 180 , and an insulating film 191 are provided.

[0035] In this embodiment, two gate electrodes 170 are provided in one trench T. The two gate electrodes 170 are arranged at the upper end of each trench T and are separated from each other in the X direction. Each gate electrode 170 is connected to the p base diffusion layer 140 and the n + The source diffusion layers 150 are adjacent to each other in the X direction. Each gate electrode 170 extends along the Y direction.

[0036] In each trench T, the upper end of the field plate electrode 180 is positioned between the two gates 170. The lower end of the field plate electrode 180 is positioned below the lower end of the gate 170. The field plate electrode 180 is adjacent to the n drift region 132 of the n semiconductor layer 130 in the X direction. Each field plate electrode 180 extends along the Y direction.

[0037] Thus, the field plate electrode 180 is provided in the semiconductor device 100. Therefore, it is possible to suppress the electric field concentration in the n-semiconductor layer 130. As a result, the withstand voltage of the semiconductor device 100 can be improved.

[0038] The insulating film 191 is provided in each trench T between the gate 170 and the p base diffusion layer 140 and between the gate 170 and the n + between the source diffusion layers 150, between the field plate electrode 180 and the n-semiconductor layer 130, and between the third electrode and the field plate electrode 180. The insulating film 191 is made of an insulating material such as silicon oxide or silicon nitride.

[0039] The first distance D1 between the lower end of the field plate electrode 180 and the lower end of the insulating film 191 is greater than the distance D2 between the insulating film 191 and the n + The second distance D2 between the drain layers 120 is longer. Furthermore, the first distance D1 is longer than the third distance D3 between the side surface of the field plate electrode 180 and the side surface of the insulating film 191. The first distance D1 is preferably at least twice the third distance D3. Furthermore, the first distance D1 is longer than the fourth distance D4 between two adjacent channels T (or insulating films 191).

[0040] As described above, the lower end of each trench T (or insulating film 191 ) reaches the n buffer region 131 of the n semiconductor layer 130 . Therefore, the lower end of the insulating film 191 is located below the upper end of the n buffer region 131 .

[0041] In n + An insulating film 192 is provided on the source diffusion layer 150 and the insulating film 191. The insulating film 192 is made of the same material as that of the insulating film 191, for example.

[0042] like Figure 1 as well as Figure 2 As shown in FIG. 1 , a source pad 161 and a gate pad 171 are provided on the insulating film 192. The gate pad 171 is arranged so as to surround the source pad 161 in a plan view. Figure 1 as well as Figure 2 In order to facilitate understanding of the description, the regions where the source pad 161 and the gate pad 171 are provided are indicated by different dot patterns.

[0043] like Figure 3 As shown, in the insulating film 192, n + The source diffusion layer 150 and the p-base diffusion layer 140 are provided with a plurality of channels 192a extending downward from the upper surface of the insulating film 192. Each channel 192a (or insulating film 192) is arranged directly below the source pad 161. The plurality of channels 192a (or insulating film 192) are arranged in the X direction. Figure 2As shown, each channel 192a (or insulating film 192) extends along the Y direction.

[0044] like Figure 3 As shown, a source 160 is provided in each channel 192a. The source 160 is connected to the p base diffusion layer 140 and the n + The source diffusion layer 150 is connected.

[0045] In addition, if Figure 4 As shown, a plurality of openings 192b are provided on the insulating films 191 and 192 to expose the plurality of field plate electrodes 180 independently. Each opening 192b is located directly above the field plate electrode 180 and directly below the source pad 161. In addition, the plurality of openings 192b are arranged in the X direction. In addition, as shown in FIG. Figure 2 As shown, each opening 192b is located outside the channel 192a in the Y direction.

[0046] like Figure 4 As shown, conductive connection members 181 are provided in each opening 192 b . Conductive connection members 181 are connected to field plate electrode 180 and source pad 161 .

[0047] In addition, if Figure 5 As shown, a plurality of openings 192 c for independently exposing the plurality of gate electrodes 170 are provided in the insulating films 191 and 192. Each opening 192 c is located directly above the gate electrode 170 and directly below the gate pad 171.

[0048] A conductive connection member 172 is provided in each opening 192 b . The conductive connection member 172 is connected to the gate 170 and the gate pad 171 .

[0049] In the semiconductor device 100 , the n-semiconductor layer 130 and the p-base diffusion layer 140 constitute a body diode 100 b .

[0050] Next, the impurity concentration distribution in the vertical direction of the n-semiconductor layer 130 will be described.

[0051] Figure 6 (a) represents the position in the vertical direction on the horizontal axis and the impurity concentration on the vertical axis on a logarithmic scale. Figure 3 The impurity concentration distribution curve on the E-E' line is shown in the figure. Figure 6 (b) is the horizontal axis taking the position in the up and down direction, and the vertical axis taking the Figure 6 The absolute value of the slope of the tangent line of the curve (a) is expressed as Figure 6 (a) is a graph showing changes in the absolute value of the slope of the tangent line of the curve.

[0052] n +The impurity concentration of the drain layer 120 is substantially constant. The impurity concentration of the n semiconductor layer 130 is greater than that of the n + The drain layer 120 has a low impurity concentration.

[0053] In addition, in this embodiment, the n semiconductor layer 130 includes a region F1 in which the impurity concentration gradually decreases as it moves upward from the lower end 130a of the n semiconductor layer 130, a region F2 located on the region F1 and having a substantially constant impurity concentration at each position in the up and down directions, and a region F3 located on the region F2 and having a gradually decreasing impurity concentration as it moves upward.

[0054] In region F1, the impurity concentration first decreases sharply as it moves upward, then the decrease slows, and then the rate of decrease increases again. Consequently, the absolute value of the slope of the tangent to curve G, representing the vertical distribution of impurity concentration in region F1, reaches its minimum at first position P1, between upper end 130b and lower end 130a of region F1. Furthermore, at second position P2, located above first position P1, impurity concentration N2 is half of impurity concentration N1 at first position P1. That is, N2 = N1 / 2.

[0055] In the n semiconductor layer 130 , the region from the lower end 130 a to the second position P2 corresponds to the n buffer region 131 . In addition, the region from the second position P2 to the upper end 130 c of the n semiconductor layer 130 corresponds to the n drift region 132 .

[0056] Therefore, the impurity concentration of the n buffer region 131 is higher than that of the n + The drain layer 120 has a low impurity concentration, and the n drift region 132 has an impurity concentration lower than that of the n buffer region 131 .

[0057] For example, by + An n-type semiconductor layer is epitaxially grown on the drain layer 120 to form an n-type semiconductor layer 130. At this time, the concentration of the impurity gas can be adjusted to form an n-type semiconductor layer. Figure 6 However, the concentration distribution in the vertical direction of the n-semiconductor layer 130 is not limited to Figure 6 The concentration distribution shown in (a).

[0058] Figure 7 This is a circuit diagram showing an example of use of the semiconductor device of this embodiment.

[0059] The semiconductor device 100 is used, for example, to connect to an inductive load L and control the current flowing through the inductive load L. In this case, the body diode 100b of the semiconductor device 100 may be used as a freewheeling diode. Specifically, when the inductive load L is switched, a flyback voltage may be generated due to the self-inductance of the inductive load L. When the body diode 100b is used as the freewheeling diode, the current Ir generated by the self-inductance is directed to the body diode 100b, thereby suppressing the flyback voltage from being applied to the connection terminal of the inductive load L.

[0060] When the body diode 100b is used as a freewheeling diode, the switching time and switching loss of the body diode 100b are preferably small. By improving the reverse recovery characteristics of the body diode 100b, the switching time and switching loss of the body diode 100b can be reduced.

[0061] When the body diode 100b is forward biased, current flows in the forward direction. As a result, a small amount of carriers (holes) are injected from the p-base diffusion layer 140 into the n-semiconductor layer 130. Therefore, when the body diode 100b is switched from this state to a reverse biased state, current flows in the reverse direction for a certain period of time, that is, until the injected holes are discharged from the n-semiconductor layer 130. "Reverse recovery characteristics" refers to the recovery characteristics of the body diode when the bias is changed from the forward direction to the reverse direction in this way. Here, "forward bias" means applying a voltage to the drain 110 and the source 160 so that the potential of the source 160 becomes higher than the potential of the drain 110. In addition, "reverse bias" means applying a voltage to the drain 110 and the source 160 so that the potential of the drain 110 becomes higher than the potential of the source 160.

[0062] Figure 8 is a cross-sectional view showing a semiconductor device according to a reference example.

[0063] The reverse recovery characteristics of the semiconductor device 100 of this embodiment will be described below, compared with the reverse recovery characteristics of the semiconductor device 900 of the reference example. The difference between the semiconductor device 900 of the reference example and the semiconductor device 100 of this embodiment is that the first distance D1 is shorter than the second distance D2, the third distance D3, and the fourth distance D4. Hereinafter, the n-type semiconductor layer 130 and the p-type base diffusion layer 140 in the semiconductor device 900 of the reference example are referred to as the "body diode 900b."

[0064] Figure 9 (a) is a graph showing a simulation of reverse recovery characteristics of the semiconductor device of the present embodiment and the semiconductor device of the reference example, with time on the horizontal axis, current on the first vertical axis, and voltage on the second vertical axis. Figure 9 (b) is to Figure 9 A graph showing an enlarged portion of (a).

[0065] exist Figure 9 (a) and Figure 9 In (b), “current” refers to the current flowing between the drain 110 and the source 160, and voltage refers to the voltage between the drain 110 and the source 160. Figure 9 (a) and Figure 9 In (b), the forward current, that is, the current flowing from the source 160 toward the drain 110, is defined as the positive direction. Figure 9 In (a), the voltage when the potential of the drain 110 is higher than the potential of the source 160 is defined as a positive direction.

[0066] First, the body diodes 100b and 900b of the semiconductor devices 100 and 900 are forward biased. This causes a current to flow in the forward direction in the body diodes 100b and 900b, injecting holes from the p-base diffusion layer 140 into the n-semiconductor layer 130. Next, at time tx, the body diodes 100b and 900b are reverse biased. Figure 9 As shown in (a), the current flowing in the forward direction of each body diode 100b and 900b gradually decreases, and the current begins to flow in the reverse direction. Then, the current flowing in the reverse direction gradually decreases, and eventually stops flowing. In other words, the current value converges to zero. Furthermore, the voltage between the drain 110 and the source 160 converges to the voltage V applied between the drain 110 and the source 160.

[0067] Hereinafter, the time when current begins to flow in the forward direction through each body diode 100b or 900b is referred to as "time t1." Furthermore, the time when current begins to flow in the reverse direction is referred to as "time t2." Furthermore, the time when the absolute value of the current flowing in the reverse direction reaches its maximum in the body diode 900b of the reference example is referred to as "time t31," and the time when the absolute value of the current flowing in the reverse direction reaches its maximum in the body diode 100b of the present embodiment is referred to as "time t32." Furthermore, in the body diode 900b of the reference example, the time when the absolute value of the current flowing in the reverse direction reaches 10% of the absolute value of the current at time t31 is referred to as "time t41," and in the body diode 100b of the present embodiment, the time when the absolute value of the current flowing in the reverse direction reaches 10% of the absolute value of the current at time t32 is referred to as "time t42."

[0068] Figure 10 (a)~ Figure 10 (d) is a map showing the simulation results of the hole concentration distribution in the semiconductor device of the reference example. Figure 10 (e)~ Figure 10(h) is a map showing the simulation results of the hole concentration distribution in the semiconductor device of this embodiment.

[0069] in addition, Figure 10 (a) shows the hole concentration distribution at time t1 of the semiconductor device 900 of the reference example. Figure 10 (b) shows the hole concentration distribution at time t2 of the semiconductor device 900 of the reference example. Figure 10 (c) shows the hole concentration distribution at time t31 of the semiconductor device 900 of the reference example. Figure 10 (d) shows the hole concentration distribution at time t41 of the semiconductor device 900 of the reference example. Figure 10 (e) shows the hole concentration distribution at time t1 of the semiconductor device 100 according to this embodiment. Figure 10 (f) shows the hole concentration distribution at time t2 of the semiconductor device 100 according to this embodiment. Figure 10 (g) shows the hole concentration distribution at time t32 of the semiconductor device 100 according to this embodiment. Figure 10 (h) shows the hole concentration distribution at time t42 of the semiconductor device 100 according to this embodiment.

[0070] At time t1, if Figure 10 As shown in (a), current flows in the forward direction, and holes are injected from the p-base diffusion layer 140 into the n-semiconductor layer 130. Then, at time tx, the body diode 900b is reverse biased. As a result, the current flowing in the forward direction in the body diode 900b gradually decreases, and the current begins to flow in the reverse direction.

[0071] At time t2, t31, and t41, the current flows in the body diode 900b in the reverse direction. Figure 10 (b)~ Figure 10 As shown in (d), the hole concentration in the n-semiconductor layer 130 gradually decreases. In particular, since the current flows upward, the holes in the upper part of the n-semiconductor layer 130 close to the source 160 are likely to decrease. Figure 10 As shown in (d), the hole concentration in the upper portion of the n semiconductor layer 130 is higher than that in the lower portion of the n semiconductor layer 130, especially the hole concentration between the insulating film 191 and the n semiconductor layer 130. + The hole concentration is low in the portion between the drain layers 120 . Thus, it is difficult for the holes to decrease in the lower portion of the n-semiconductor layer 130 .

[0072] In contrast, the first distance D1 of the semiconductor device 100 of the present embodiment is longer than the first distance D1 of the semiconductor device 900 of the reference example. Therefore, the volume of the lower portion of the n-semiconductor layer 130 can be reduced.

[0073] The results, such as Figure 10(a) and Figure 10 As shown in (e), the amount of holes generated in the n-semiconductor layer 130 at time t1 in the semiconductor device 100 of this embodiment is smaller than the amount of holes generated in the n-semiconductor layer 130 at time t1 in the semiconductor device 900 of the reference example.

[0074] Furthermore, in the semiconductor device 100 of this embodiment, the volume of the lower portion of the n-type semiconductor layer 130, that is, the portion where the holes in the n-type semiconductor layer 130 are difficult to reduce, is reduced. Figure 10 (b)~ Figure 10 (d) and Figure 10 (f)~ Figure 10 As shown in (h), the hole reduction rate in the semiconductor device 100 of this embodiment is faster than the hole reduction rate in the semiconductor device 900 of the reference example.

[0075] Furthermore, as described above, the total amount of holes generated in the semiconductor device 100 of this embodiment is smaller than the total amount of holes generated in the semiconductor device 900 of the reference example. Figure 9 As shown in (b), the absolute value of the current flowing at time t32 in the semiconductor device 100 of the present embodiment is smaller than the absolute value of the current flowing at time t31 in the semiconductor device 100 of the reference example.

[0076] Furthermore, the total amount of current Q1 flowing from time t2 to time t42 in the semiconductor device 100 of this embodiment is smaller than the total amount of current Q2 flowing from time t2 to time t41 in the semiconductor device 900 of the reference example. The total amounts of current Q1 and Q2 are also referred to as "reverse recovery charge." The value obtained by multiplying the reverse recovery charge by the voltage corresponds to power loss. Therefore, reducing the reverse recovery charge can reduce switching losses in the body diode 100b.

[0077] Furthermore, the time Δt2 from time t2 to time t42 in the semiconductor device 100 of this embodiment can be shorter than the time Δt1 from time t2 to time t41 in the semiconductor device 900 of the reference example. The times Δt1 and Δt2 are also referred to as "reverse recovery time." By shortening the reverse recovery time, the switching time of the body diode 100b can be shortened.

[0078] Next, the effects of this embodiment will be described.

[0079] In the semiconductor device 100 of this embodiment, the first distance D1 between the lower end of the field plate electrode 180 and the lower end of the insulating film 191 is greater than the first distance D1 between the insulating film 191 and the lower end of the insulating film 191. +The second distance D2 between drain layers 120 is long. This reduces the volume of the lower portion of n-semiconductor layer 130. Consequently, the total amount of carriers generated within n-semiconductor layer 130 when forward biased can be reduced. Consequently, a semiconductor device 100 with improved reverse recovery characteristics can be provided.

[0080] The channel T in the n semiconductor layer 130 (or the lower end of the insulating film 191) and the n + The portion between drain layers 120 is where on-current is less likely to flow when semiconductor device 100 functions as a transistor. Therefore, even if the volume of this portion is reduced, the effect on on-resistance when semiconductor device 100 functions as a transistor is minimal. As a result, increases in on-resistance can be suppressed, and reverse recovery characteristics can be improved.

[0081] Furthermore, in the semiconductor device 100, the volume of the lower portion of the n-type semiconductor layer 130 can be reduced, and the field plate electrode 180 can be prevented from approaching the n-type semiconductor layer 130. + Therefore, in the n semiconductor layer 130, it is possible to suppress the electric field from concentrating on the channel T and the n + The portion between the drain layers 120 may reduce the withstand voltage of the semiconductor device 100 .

[0082] Furthermore, the channel T (or the lower end of the insulating film 191) reaches the n buffer region 131. This reduces the volume of the lower portion of the n semiconductor layer 130. Therefore, the total amount of carriers generated in the n semiconductor layer 130 when forward biased can be reduced.

[0083] Furthermore, the first distance D1 is longer than the third distance D3 between the side surface of the field plate electrode 180 and the side surface of the insulating film 191. This reduces the volume of the lower portion of the n-semiconductor layer 130. Consequently, the total amount of carriers generated in the n-semiconductor layer 130 when forward biased can be reduced.

[0084] Furthermore, the first distance D1 is at least twice the third distance D3. This reduces the volume of the lower portion of the n-semiconductor layer 130. Consequently, the total amount of carriers generated in the n-semiconductor layer 130 when forward biased can be reduced.

[0085] Furthermore, the first distance D1 is longer than the fourth distance D4 between adjacent trenches T (or insulating films 191 ). Therefore, the total amount of carriers generated in the n-semiconductor layer 130 when forward biased can be reduced.

[0086] Furthermore, in the semiconductor device 100 of this embodiment, the lower end of the insulating film 191 is located below the second position P2. This reduces the volume of the lower portion of the n-semiconductor layer 130. Consequently, the total amount of carriers generated within the n-semiconductor layer 130 when forward biased can be reduced. Consequently, a semiconductor device 100 with improved reverse recovery characteristics can be provided.

[0087] <Second embodiment>

[0088] Next, a second embodiment will be described.

[0089] Figure 11 : is a cross-sectional view showing the semiconductor device according to this embodiment.

[0090] In addition, in the following description, only the differences from the first embodiment will be described in principle. Except for the matters described below, it is the same as the first embodiment.

[0091] In the semiconductor device 200 of this embodiment, a recombination center 230 is provided in the n-semiconductor layer 130. The recombination center 230 is formed by, for example, a crystal defect or an impurity element. The crystal defect can be formed by, for example, H + Or He + The n-type semiconductor layer 130 is formed by plasma implantation. The impurity element is, for example, titanium (Ti), platinum (Pt), or gold (Au), an element that functions as a recombination center. The recombination center 230 is, for example, located in both the n-type buffer region 131 and the n-type drift region 132. However, the recombination center may also be located in the n-type buffer region instead of the n-type drain region.

[0092] As described above, in the semiconductor device 200 of this embodiment, crystal defects or impurity elements are provided in the n-semiconductor layer 130. This promotes recombination of holes and electrons generated in the n-semiconductor layer 130. Consequently, the semiconductor device 200 having improved reverse recovery characteristics can be provided.

[0093] In the above embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0094] While several embodiments of the present invention have been described above, these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their variations are included within the scope and gist of the invention, and are included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor device comprising: 1st electrode; a first semiconductor layer of a first conductivity type connected to the first electrode; The second semiconductor layer of the first conductivity type is provided on the first semiconductor layer and has an impurity concentration lower than that of the first semiconductor layer; a third semiconductor layer of the second conductivity type, provided on the second semiconductor layer; The fourth semiconductor layer of the first conductivity type is provided on the third semiconductor layer; a second electrode connected to the third semiconductor layer and the fourth semiconductor layer; a gate extending from the fourth semiconductor layer toward the second semiconductor layer and adjacent to the third semiconductor layer; a field plate electrode extending in a direction from the fourth semiconductor layer toward the second semiconductor layer and extending to a position below the gate electrode and adjacent to the second semiconductor layer; as well as The first insulating film is provided between the gate and the third semiconductor layer, between the field plate electrode and the second semiconductor layer, and between the gate and the field plate electrode, and a first distance from a lower end to a lower end of the field plate electrode is longer than a second distance from the lower end to the first semiconductor layer. The first distance is greater than a third distance between a side surface of the field plate electrode and a side surface of the first insulating film.

2. The semiconductor device according to claim 1, wherein The second semiconductor layer includes: a first region located on the first semiconductor layer and having an impurity concentration lower than that of the first semiconductor layer; and The second region is located on the first region and has an impurity concentration lower than that of the first region. The first insulating film reaches the first region.

3. The semiconductor device according to claim 1, wherein The first distance is at least twice the third distance.

4. The semiconductor device according to claim 1 or 2, wherein Crystal defects or impurity elements are provided in the second semiconductor layer.

5. The semiconductor device according to claim 1 or 2, wherein A second insulating film is further provided, the second insulating film extending from the fourth semiconductor layer toward the second semiconductor layer and adjacent to the first insulating film, The first distance is greater than a fourth distance between the first insulating film and the second insulating film.

6. A semiconductor device comprising: 1st electrode; a first semiconductor layer of a first conductivity type connected to the first electrode; The second semiconductor layer of the first conductivity type is provided on the first semiconductor layer and has a region in which the impurity concentration gradually decreases from the bottom end toward the top, and the absolute value of the slope of a tangent line of a curve representing the distribution of the impurity concentration in the vertical direction in the region becomes minimum at a first position; a third semiconductor layer of the second conductivity type, provided on the second semiconductor layer; The fourth semiconductor layer of the first conductivity type is provided on the third semiconductor layer; a second electrode connected to the third semiconductor layer and the fourth semiconductor layer; a gate extending from the fourth semiconductor layer toward the second semiconductor layer and adjacent to the third semiconductor layer; a field plate electrode, adjacent to the second semiconductor layer; as well as The insulating film is provided between the gate and the third semiconductor layer, between the field plate electrode and the second semiconductor layer, and between the gate and the field plate electrode, and has a lower end located below a second position where the impurity concentration is half of the impurity concentration at the first position.

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