A method for preparing a capacitor structure

Abstract

The present invention discloses a method for preparing a capacitor structure, wherein a stacking structure including a first dielectric layer, a first supporting layer, a second dielectric layer, a second supporting layer and a barrier layer in a preset pattern is deposited on a substrate, a plurality of openings are etched in the stacking structure, wherein the bottom of the openings exposes an electrical connection pad located in the substrate, a conductive layer covering the top surface of the barrier layer in a preset pattern and the sidewalls and bottom surfaces of the openings is deposited, at least a portion of the conductive layer is etched to form a lower electrode, a first distance from the top surface of the lower electrode to the substrate is less than a second distance from the top surface of the second supporting layer to the substrate, the first dielectric layer, the second dielectric layer and the barrier layer in a preset pattern are removed, and a capacitor dielectric layer and an upper electrode covering at least the lower electrode are formed. When the conductive layer is back-etched to form the lower electrode, the barrier layer can avoid over-etching the second supporting layer used to support the top of the lower electrode, thereby facilitating the stability of the entire capacitor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a capacitor structure. Background Art

[0002] As a semiconductor storage device, capacitors are continuously miniaturized with the advancement of manufacturing technology and market demand. In order to ensure the storage capacity of capacitors on the basis of miniaturization, electrodes are usually extended in a direction perpendicular to the substrate. For example, a lower electrode extending in a direction perpendicular to the substrate and having a columnar structure can be provided. However, the stability of the lower electrode of this structure is poor. In order to avoid deformation, a support structure is provided on the outside of the lower electrode.

[0003] In the process of preparing a capacitor in the prior art, multiple grooves are formed in a laminated structure formed by an interlayer dielectric layer and a support layer on a substrate, and then a conductive layer is deposited to conformally cover the sidewalls, bottom surface and upper surface of the groove, and finally the conductive layer located on the upper surface of the support layer and at least part of the sidewalls of the groove is etched back to form a lower electrode. When the conductive layer is etched back, the support layer adjacent to the conductive layer will also be partially etched, resulting in insufficient strength of the support layer used to support the top of the lower electrode, thereby affecting the stability of the entire capacitor structure. Summary of the invention

[0004] The technical problem to be solved by the present invention is that in the existing capacitor structure preparation process, the top support layer adjacent to the conductive layer will be over-etched when the conductive layer is etched back, resulting in insufficient strength of the support layer used to support the top of the lower electrode, thereby affecting the stability of the entire capacitor structure.

[0005] In order to solve the above technical problems, the present invention provides a method for preparing a capacitor structure, which comprises:

[0006] forming a stacked structure on a substrate, the stacked structure comprising a first dielectric layer, a first support layer, a second dielectric layer, a second support layer and a barrier layer in a preset pattern sequentially deposited on the substrate;

[0007] Using the barrier layer in a preset pattern as a mask, a plurality of openings are etched in the stacked structure, wherein the bottoms of the openings expose electrical connection pads located in the substrate;

[0008] Depositing a conductive layer, the conductive layer covering the top surface of the barrier layer in the preset pattern and the sidewalls and bottom surface of the opening;

[0009] Etching at least a portion of the conductive layer to form a lower electrode, wherein a first distance from a top surface of the lower electrode to the substrate is smaller than a second distance from a top surface of the second supporting layer to the substrate;

[0010] removing the first dielectric layer, the second dielectric layer and the barrier layer in a predetermined pattern;

[0011] A capacitor dielectric layer and an upper electrode are formed which at least cover the lower electrode.

[0012] In some embodiments, before etching at least a portion of the conductive layer to form a lower electrode, the method further comprises:

[0013] A protection layer is deposited, the protection layer covering at least the conductive layer on the sidewalls and the bottom surface of the opening.

[0014] In some embodiments, the protective layer has a porous structure.

[0015] In some embodiments, etching at least a portion of the conductive layer to form a lower electrode includes:

[0016] Etching a portion of the protective layer and a portion of the conductive layer to form a lower electrode, wherein after etching, a third distance between the top surface of the protective layer and the substrate is smaller than a fourth distance between the bottom surface of the second supporting layer and the substrate;

[0017] The remaining protective layer is removed.

[0018] In some embodiments, the barrier layer having a predetermined pattern is provided in a single layer or multiple layers.

[0019] In some embodiments, the barrier layer with a predetermined pattern directly contacting the second supporting layer and the second dielectric layer are made of the same material.

[0020] In some embodiments, the barrier layer having a predetermined pattern is provided with a single layer, and removing the first dielectric layer, the second dielectric layer, and the barrier layer having a predetermined pattern comprises:

[0021] Simultaneously removing the second dielectric layer and the barrier layer having a predetermined pattern;

[0022] The first dielectric layer is removed.

[0023] In some embodiments, the material of the barrier layer with a predetermined pattern directly contacting the second supporting layer is plasma enhanced tetraethyl orthosilicate.

[0024] In some embodiments, the first distance is greater than a fourth distance from the bottom surface of the second supporting layer to the substrate.

[0025] In some embodiments, the forming of a capacitor dielectric layer and an upper electrode at least covering the lower electrode comprises:

[0026] Depositing the capacitor dielectric layer covering the exposed surface of the lower electrode, the first supporting layer and the second supporting layer;

[0027] The upper electrode is deposited to cover the capacitor dielectric layer.

[0028] Compared with the prior art, one or more embodiments of the above scheme may have the following advantages or beneficial effects:

[0029] The capacitor structure preparation method provided by the present invention is applied, by depositing a stacking structure including a first dielectric layer, a first supporting layer, a second dielectric layer, a second supporting layer and a barrier layer in a preset pattern on a substrate, using the barrier layer in a preset pattern as a mask, etching a plurality of openings in the stacking structure, wherein the bottom of the openings exposes an electrical connection pad located in the substrate, depositing a conductive layer covering the top surface of the barrier layer in a preset pattern and the sidewalls and bottom surfaces of the openings, etching at least part of the conductive layer to form a lower electrode, wherein the first distance from the top surface of the lower electrode to the substrate is less than the second distance from the top surface of the second supporting layer to the substrate, removing the first dielectric layer, the second dielectric layer and the barrier layer in a preset pattern, and forming a capacitor dielectric layer and an upper electrode that at least covers the lower electrode. By providing a barrier layer between the second supporting layer and the conductive layer, when the conductive layer is back-etched to form the lower electrode, over-etching of the second supporting layer used to support the top of the lower electrode can be avoided, thereby facilitating the stability of the entire capacitor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The scope of the present disclosure may be better understood by reading the following detailed description of exemplary embodiments in conjunction with the accompanying drawings. The drawings included are:

[0031] Figure 1 A schematic diagram showing a process of a method for preparing a capacitor structure provided by an embodiment of the present invention;

[0032] Figures 2 to 7 The cross-sectional structure schematic diagram corresponding to each step in the capacitor structure preparation method provided in the first embodiment of the present invention is shown;

[0033] Figure 8 A schematic diagram showing a process of another method for preparing a capacitor structure provided by an embodiment of the present invention;

[0034] FIG9(1) shows a schematic cross-sectional structure diagram corresponding to step S204 in the method for preparing a capacitor structure according to the second embodiment of the present invention; FIG9(2) shows another schematic cross-sectional structure diagram corresponding to step S204 in the method for preparing a capacitor structure according to the second embodiment of the present invention;

[0035] Fig.10 A schematic diagram of the surface structure corresponding to step S205 in the capacitor structure preparation method provided in the second embodiment of the present invention is shown. DETAILED DESCRIPTION

[0036] In order to make the objectives, technical solutions and advantages of the present invention clearer, the implementation method of the present invention will be described in detail below in conjunction with the accompanying drawings and embodiments, so that the implementation process of how the present invention applies technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.

[0037] As a semiconductor storage device, capacitors are continuously miniaturized with the advancement of manufacturing technology and market demand. In order to ensure the storage capacity of capacitors on the basis of miniaturization, electrodes are usually extended in a direction perpendicular to the substrate. For example, a lower electrode extending in a direction perpendicular to the substrate and having a columnar structure can be provided. However, the stability of the lower electrode of this structure is poor. In order to avoid deformation, a support structure is provided on the outside of the lower electrode.

[0038] In the process of preparing a capacitor in the prior art, a plurality of grooves are formed in a laminated structure formed by an interlayer dielectric layer and a support layer on a substrate, and then a conductive layer is deposited to conformally cover the sidewalls, bottom surface and upper surface of the groove, and finally the conductive layer located on the upper surface of the support layer and at least partly on the sidewalls of the groove is etched back to form a lower electrode. When the conductive layer is etched back, the support layer adjacent to the conductive layer will also be partially etched, resulting in insufficient strength of the support layer used to support the upper part of the lower electrode, thereby affecting the stability of the entire capacitor structure.

[0039] In view of this, the present application provides a method for preparing a capacitor structure, by depositing a stacking structure including a first dielectric layer, a first supporting layer, a second dielectric layer, a second supporting layer and a barrier layer in a preset pattern on a substrate, using the barrier layer in a preset pattern as a mask, etching a plurality of openings in the stacking structure, wherein the bottom of the openings exposes an electrical connection pad located in the substrate, depositing a conductive layer covering the top surface of the barrier layer in a preset pattern and the sidewalls and bottom surfaces of the openings, etching at least part of the conductive layer to form a lower electrode, wherein a first distance from the top surface of the lower electrode to the substrate is less than a second distance from the top surface of the second supporting layer to the substrate, removing the first dielectric layer, the second dielectric layer and the barrier layer in a preset pattern, and forming a capacitor dielectric layer and an upper electrode that at least covers the lower electrode. By providing a barrier layer between the second supporting layer and the conductive layer, when the conductive layer is back-etched to form the lower electrode, over-etching of the second supporting layer used to support the top of the lower electrode can be avoided, thereby facilitating the stability of the entire capacitor structure.

[0040] Embodiment 1

[0041] See also Figures 1 to 7 As shown, Figure 1 A schematic flow chart of a method for preparing a capacitor structure provided by an embodiment of the present invention is shown, which may include:

[0042] Step S101: forming a stacked structure on a substrate 10, wherein the stacked structure includes a first dielectric layer 11, a first supporting layer 12, a second dielectric layer 13, a second supporting layer 14 and a barrier layer 15 having a preset pattern which are sequentially deposited on the substrate 10;

[0043] Step S102: using the barrier layer 15 in a preset pattern as a mask, a plurality of openings 16 are etched in the stacked structure, wherein the bottom of the openings 16 exposes the electrical connection pads 17 located in the substrate 10;

[0044] Step S103: depositing a conductive layer 18, wherein the conductive layer 18 covers the top surface of the barrier layer 15 in a preset pattern and the sidewalls and bottom surface of the opening 16;

[0045] Step S104: etching at least a portion of the conductive layer 18 to form a lower electrode 19, wherein a first distance H1 from the top surface of the lower electrode 19 to the substrate 10 is smaller than a second distance H2 from the top surface of the second supporting layer 14 to the substrate 10;

[0046] Step S105: removing the first dielectric layer 11, the second dielectric layer 13 and the barrier layer 15 in a preset pattern;

[0047] Step S106 : forming a capacitor dielectric layer 20 and an upper electrode 21 at least covering the lower electrode 19 .

[0048] In some embodiments, the first dielectric layer 11 and / or the second dielectric layer 13 may include at least one material selected from silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), borophosphosilicate glass, and plasma-enhanced tetraethyl orthosilicate. As an example, the first dielectric layer 11 may include a stack of borophosphosilicate glass and plasma-enhanced tetraethyl orthosilicate, and the second dielectric layer 13 may be prepared from plasma-enhanced tetraethyl orthosilicate. In the embodiment of the present invention, the first dielectric layer 11 and the second dielectric layer 13 may be arranged in the same manner or in different manners, which will not be particularly limited in the embodiment of the present invention.

[0049] In the embodiment of the present invention, a material having selective etching properties with the first dielectric layer 11 and the second dielectric layer 13 can be selected as the first support layer 12 and the second support layer 14. In some embodiments, the first support layer 12 and the second support layer 14 can be prepared using the same material. As an example, the first support layer 12 and the second support layer 14 can be prepared using silicon carbide nitride (SiCN). It should be noted that the first support layer 12 and the second support layer 14 can be set to have different layer thicknesses. In some embodiments, the layer thickness of the second support layer 14 can be set to be greater than the layer thickness of the first support layer 12. In other embodiments, the first support layer 12 and the second support layer 14 can also be prepared using different materials and / or set to have the same layer thickness.

[0050] In the embodiment of the present invention, the barrier layer 15 with a preset pattern in step S101 can be set as a single layer, see Figure 2 In some embodiments, the barrier layer 15 in a predetermined pattern directly contacting the second support layer 14 can be made of the same material as the second dielectric layer 13. In some embodiments, the materials of the second dielectric layer 13 and the barrier layer 15 in a predetermined pattern are both plasma enhanced tetraethyl orthosilicate.

[0051] In other embodiments, the barrier layer 15 in the preset pattern in step S101 may be provided with multiple layers, wherein the barrier layer 15 in the preset pattern directly in contact with the second support layer 14 and the second dielectric layer 13 are made of the same material. In some embodiments, the second dielectric layer 13 and the barrier layer 15 in the preset pattern directly in contact with the second support layer 14 are made of plasma enhanced tetraethyl orthosilicate. As an example, plasma enhanced tetraethyl orthosilicate, amorphous silicon, and plasma enhanced tetraethyl orthosilicate may be sequentially deposited on the second support layer 14, and the plasma enhanced tetraethyl orthosilicate, amorphous silicon, and plasma enhanced tetraethyl orthosilicate may be etched to form multiple layers of the barrier layer 15 in the preset pattern.

[0052] In some embodiments, step S102 may be specifically to use the barrier layer 15 having a preset pattern as a mask, and to etch a plurality of openings 16 in the stacked structure by a dry etching process or a wet etching process, wherein the bottom of the opening 16 reveals an electrical connection pad 17 located in the substrate 10, and the electrical connection pad 17 is used to realize the electrical connection between the capacitor structure and the substrate 10, and the details can be seen in Figure 3 shown.

[0053] In the embodiment of the present invention, step S103 may specifically include depositing a conductive layer 18 by a physical vapor deposition process or a chemical vapor deposition process, wherein the conductive layer 18 covers the top surface of the barrier layer 15 having a preset pattern and the sidewalls and bottom surface of the opening 16, see Figure 4 shown.

[0054] In the embodiment of the present invention, step S104 may be specifically to etch at least a portion of the conductive layer 18 using a dry etching process or a wet etching process to form a lower electrode 19, wherein the bottom surface of the lower electrode 19 is in contact with the electrical connection pad 17, and a first distance H1 from the top surface of the lower electrode 19 to the substrate 10 is less than a second distance H2 from the top surface of the second supporting layer 14 to the substrate 10, see Figure 5 In some embodiments, a first distance H1 from the top surface of the lower electrode 19 to the substrate 10 is greater than a fourth distance H4 from the bottom surface of the second supporting layer 14 to the substrate 10 to ensure that the second supporting layer 14 supports the upper portion of the lower electrode 19 and improve the stability of the lower electrode 19.

[0055] It should be noted that, in the process of etching back the conductive layer 18 in step S104 , the barrier layer 15 in the preset pattern will also be partially etched, so that the barrier layer 15 in the preset pattern becomes thinner.

[0056] In some embodiments, when the barrier layer 15 with a preset pattern is set as a single layer and is made of the same material as the second dielectric layer 13, step S105 can be specifically as follows: the second dielectric layer 13 and the barrier layer 15 with a preset pattern are removed simultaneously; and then the first dielectric layer 11 is removed. It should be noted that when the barrier layer 15 with a preset pattern, the second dielectric layer 13 and the first dielectric layer 11 are all made of the same material, the barrier layer 15 with a preset pattern, the second dielectric layer 13 and the first dielectric layer 11 can also be removed simultaneously; in other embodiments, the barrier layer 15 with a preset pattern, the second dielectric layer 13 and the first dielectric layer 11 can also be removed in steps. The structure after removing the barrier layer 15 with a preset pattern, the second dielectric layer 13 and the first dielectric layer 11 can be seen in Figure 6 shown.

[0057] In some embodiments, step S106 may specifically include:

[0058] Depositing a capacitor dielectric layer 20 covering the exposed surface of the lower electrode 19, the first supporting layer 12 and the second supporting layer 14;

[0059] An upper electrode 21 covering the capacitor dielectric layer 20 is deposited.

[0060] The capacitor structure after depositing the upper electrode 21 is as follows Figure 7 As shown, the capacitor dielectric layer 20 can cover the exposed surface of the lower electrode 19, the upper surface and the lower surface of the first support layer 12, the upper surface and the lower surface of the second support layer 14, and a portion of the upper surface of the substrate 10, and the upper electrode 21 can completely cover the capacitor dielectric layer 20. In some embodiments, the upper electrode 21 can also fill the area between adjacent lower electrodes 19, such as Figure 7 shown.

[0061] The above is a method for preparing a capacitor structure provided by an embodiment of the present invention, by depositing a stacking structure including a first dielectric layer 11, a first supporting layer 12, a second dielectric layer 13, a second supporting layer 14 and a barrier layer 15 with a preset pattern on a substrate 10, using the barrier layer 15 with a preset pattern as a mask, etching a plurality of openings 16 in the stacking structure, wherein the bottom of the opening reveals an electrical connection pad 17 located in the substrate 10, depositing a conductive layer 18 covering the top surface of the barrier layer 15 with a preset pattern and the sidewall and bottom surface of the opening, etching at least a portion of the conductive layer 18 to form a lower electrode 19, a first distance H1 from the top surface of the lower electrode 19 to the substrate 10 is less than a second distance H2 from the top surface of the second supporting layer 14 to the substrate 10, removing the first dielectric layer 11, the second dielectric layer 13 and the barrier layer 15 with a preset pattern, and forming a capacitor dielectric layer 20 and an upper electrode 21 covering at least the lower electrode 19. By providing a barrier layer between the second supporting layer 14 and the conductive layer 18, when the conductive layer 18 is etched back to form the lower electrode 19, over-etching of the second supporting layer 14 for supporting the top of the lower electrode 19 can be avoided, thereby facilitating the stability of the entire capacitor structure.

[0062] Before the conductive layer 18 is back-etched to form the lower electrode 19, in order to avoid the influence of the conductive layer 18 located in the opening 16 during the back-etching process, a protective layer can also be deposited to at least cover the conductive layer 18 located at the bottom and side walls of the opening 16. For details, please refer to the description in the following embodiment 2.

[0063] Embodiment 2

[0064] See also Figure 8 As shown, Figure 8 A schematic flow chart of another method for preparing a capacitor structure provided by an embodiment of the present invention is shown, which may include:

[0065] Step S201: forming a stacked structure on a substrate 10, wherein the stacked structure includes a first dielectric layer 11, a first supporting layer 12, a second dielectric layer 13, a second supporting layer 14 and a barrier layer 15 having a preset pattern which are sequentially deposited on the substrate 10;

[0066] Step S202: using the barrier layer 15 in a preset pattern as a mask, a plurality of openings 16 are etched in the stacked structure, wherein the bottom of the openings 16 exposes the electrical connection pads 17 located in the substrate 10;

[0067] Step S203: depositing a conductive layer 18, wherein the conductive layer 18 covers the top surface of the barrier layer 15 in a preset pattern and the sidewalls and bottom surface of the opening 16;

[0068] Step S204: depositing a protection layer 22, wherein the protection layer 22 at least covers the conductive layer 18 located on the sidewall and bottom surface of the opening 16;

[0069] Step S205: etching a portion of the protective layer 22 and a portion of the conductive layer 18 to form a lower electrode 19, wherein after etching, a third distance H3 between the top surface of the protective layer 22 and the substrate 10 is smaller than a fourth distance H4 between the bottom surface of the second supporting layer 14 and the substrate 10, and a first distance H1 between the top surface of the lower electrode 19 and the substrate 10 is smaller than a second distance H2 between the top surface of the second supporting layer 14 and the substrate 10;

[0070] Step S206: removing the remaining protective layer 22;

[0071] Step S207: removing the first dielectric layer 11, the second dielectric layer 13 and the barrier layer 15 in a preset pattern;

[0072] Step S208 : forming a capacitor dielectric layer 20 and an upper electrode 21 at least covering the lower electrode 19 .

[0073] Among them, steps S201 to S203 can be implemented in the same manner as steps S101 to S103 in Example 1, and steps S207 and S208 can also be implemented in the same manner as steps S105 and S106 in Example 1, which will not be repeated here for the sake of brevity.

[0074] In an embodiment of the present invention, step S204 may specifically include depositing a protective layer 22 by a chemical vapor deposition process or a physical vapor deposition process, wherein the protective layer 22 at least covers the conductive layer 18 located on the sidewall and bottom surface of the opening 16, as shown in FIG9 (1), the protective layer 22 may completely fill the opening 16, and the protective layer 22 may also cover the conductive layer 18 located on the barrier layer 15 in a preset pattern, and the part of the protective layer 22 may be removed in step S205; in other embodiments, the protective layer 22 may also have a pore structure 23, and the pore structure 23 is located in the protective layer 22 near the bottom surface of the lower electrode 19, as shown in FIG9 (2). The protective layer 22 may be an insulating material having a different etching rate from the conductive layer 18.

[0075] In some embodiments, step S205 may specifically include etching the protective layer 22 on the barrier layer 15 with a preset pattern to expose the conductive layer 18 between the protective layer 22 and the barrier layer 15 with a preset pattern, etching a portion of the protective layer 22 filling the opening 16, etching the conductive layer 18 on the barrier layer 15 with a preset pattern and a portion of the conductive layer 18 on the sidewall of the opening 16 to form the lower electrode 19, see Fig.10As shown, the third distance H3 between the top surface of the etching protection layer 22 and the substrate 10 is smaller than the fourth distance H4 between the bottom surface of the second supporting layer 14 and the substrate 10, and the first distance H1 between the top surface of the lower electrode 19 and the substrate 10 is smaller than the second distance H2 between the top surface of the second supporting layer 14 and the substrate 10, and the first distance H1 is greater than the fourth distance H4 between the bottom surface of the second supporting layer 14 and the substrate 10.

[0076] It should be noted that, in the process of etching back the conductive layer 18 in step S205 , the barrier layer 15 in the preset pattern will also be partially etched, so that the barrier layer 15 in the preset pattern becomes thinner.

[0077] Step S206 may specifically include removing the remaining protective layer 22 in the opening 16. The structure after removing the remaining protective layer 22 is shown in FIG. Figure 5 shown.

[0078] The above is another method for preparing a capacitor structure provided by an embodiment of the present invention, by forming a stacked structure on a substrate 10, the stacked structure includes a first dielectric layer 11, a first supporting layer 12, a second dielectric layer 13, a second supporting layer 14 and a barrier layer 15 in a preset pattern deposited sequentially on the substrate 10; using the barrier layer 15 in a preset pattern as a mask, etching a plurality of openings 16 in the stacked structure, wherein the bottom of the opening 16 reveals an electrical connection pad 17 located in the substrate 10; depositing a conductive layer 18, the conductive layer 18 covers the top surface of the barrier layer 15 in a preset pattern and the sidewalls and bottom surfaces of the opening 16; depositing a protective layer 22, the protective layer 22 at least Cover the conductive layer 18 located on the sidewall and bottom surface of the opening 16; etch part of the protective layer 22 and part of the conductive layer 18 to form a lower electrode 19, wherein after etching, the third distance H3 between the top surface of the protective layer 22 and the substrate 10 is less than the fourth distance H4 between the bottom surface of the second support layer 14 and the substrate 10, and the first distance H1 between the top surface of the lower electrode 19 and the substrate 10 is less than the second distance H2 between the top surface of the second support layer 14 and the substrate 10; remove the remaining protective layer 22; remove the first dielectric layer 11, the second dielectric layer 13 and the barrier layer 15 in a preset pattern; form a capacitor dielectric layer 20 and an upper electrode 21 that at least cover the lower electrode 19. This method can achieve the same beneficial effects as the above embodiment 1, and by depositing a protective layer 22 to cover the conductive layer 18 located at the bottom and sidewalls of the opening 16 before etching back the conductive layer 18 to form the lower electrode 19, the influence on the conductive layer 18 located in the opening 16 during the etching back process is avoided.

[0079] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted for facilitating the understanding of the present invention and are not intended to limit the present invention. Any technician in the technical field to which the present invention belongs can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present invention, but the protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A method for preparing a capacitor structure, characterized in that: include: forming a stacked structure on a substrate, the stacked structure comprising a first dielectric layer, a first support layer, a second dielectric layer, a second support layer and a barrier layer in a preset pattern sequentially deposited on the substrate; Using the barrier layer in a preset pattern as a mask, a plurality of openings are etched in the stacked structure, wherein the bottoms of the openings expose electrical connection pads located in the substrate; Depositing a conductive layer, the conductive layer covering the top surface of the barrier layer in the predetermined pattern and the sidewalls and bottom surface of the opening; Etching at least a portion of the conductive layer to form a lower electrode, wherein a first distance from a top surface of the lower electrode to the substrate is smaller than a second distance from a top surface of the second supporting layer to the substrate; removing the first dielectric layer, the second dielectric layer and the barrier layer in a predetermined pattern; forming a capacitor dielectric layer and an upper electrode at least covering the lower electrode; Before etching at least a portion of the conductive layer to form a lower electrode, the method further comprises: Depositing a protective layer, the protective layer at least covering the conductive layer located on the sidewall and the bottom surface of the opening; etching a portion of the protective layer and a portion of the conductive layer to form a lower electrode, wherein after etching, a third distance between the top surface of the protective layer and the substrate is smaller than a fourth distance between the bottom surface of the second supporting layer and the substrate; removing the remaining protective layer; The protective layer has a pore structure therein; the pore structure is located in a region of the protective layer close to the bottom surface of the lower electrode.

2. The method according to claim 1, characterized in that The barrier layer in a preset pattern is provided with a single layer or multiple layers.

3. The method according to claim 2, characterized in that The barrier layer with a preset pattern directly contacting the second supporting layer and the second dielectric layer are made of the same material.

4. The method according to claim 3, characterized in that The barrier layer having a preset pattern is provided with a single layer, and the first dielectric layer, the second dielectric layer and the barrier layer having a preset pattern are removed, comprising: Simultaneously removing the second dielectric layer and the barrier layer having a predetermined pattern; The first dielectric layer is removed.

5. The method according to claim 2, characterized in that: The material of the barrier layer with a preset pattern directly contacting the second supporting layer is plasma enhanced tetraethyl orthosilicate.

6. The method according to claim 1, characterized in that The first distance is greater than a fourth distance from the bottom surface of the second supporting layer to the substrate.

7. The method according to claim 1, characterized in that The forming of a capacitor dielectric layer and an upper electrode at least covering the lower electrode comprises: Depositing the capacitor dielectric layer covering the exposed surface of the lower electrode, the first supporting layer and the second supporting layer; The upper electrode is deposited to cover the capacitor dielectric layer.

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