A reconfigurable ultra-wideband high-precision variable gain amplifier core circuit

Abstract

The present invention discloses a reconfigurable ultra-wideband, high-precision variable-gain amplifier core circuit. The core circuit primarily comprises a three-stage wideband variable-gain unit and a digitally controllable current source array. This circuit utilizes a novel gain control method, achieving not only high-precision gain control but also complete independence between coarse and fine gain adjustments. This significantly reduces circuit complexity and improves broadband performance. Furthermore, the bandwidth remains constant across the entire variable gain range, ensuring that the core circuit maintains constant group delay at varying gains. Furthermore, the core circuit features configurable gain and bandwidth, enabling configuration of both gain and bandwidth without affecting the variable gain range, thus meeting the gain-bandwidth and other performance requirements of diverse broadband systems.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuit design, and in particular relates to a reconfigurable ultra-wideband high-precision variable gain amplifier core circuit. Background Art

[0002] Driven by the demand for wireless communication technology, transceivers for high-data-rate millimeter-wave communication systems are rapidly developing. During millimeter-wave signal transmission, due to free-space transmission losses, the power of the millimeter-wave signal emitted by the transmitter varies significantly by the time it reaches the receiver, significantly exceeding the signal amplitude range that the baseband circuitry can handle. To optimize the signal amplitude for the baseband circuitry and minimize bit error rates, a variable-gain amplifier (VGA) must be used in the receiver for gain adjustment. The performance of the VGA directly determines the performance of the entire receiver system. For these reasons, VGAs are subject to stringent requirements in communication and radar system design. On the one hand, they must meet performance requirements such as broadband, low power consumption, high accuracy, a wide dynamic range, high gain, and high linearity. On the other hand, to account for factors such as process and temperature, the VGA's bandwidth and gain performance must be configurable to enable calibration and compatibility with other receivers. A literature search reveals that many current VGAs fail to meet these requirements. Summary of the Invention

[0003] The present invention aims to provide a reconfigurable ultra-wideband high-precision variable gain amplifier core circuit to solve the technical problem that variable gain amplifiers cannot meet the performance requirements of broadband, low power consumption, high precision, large dynamic range, high gain and high linearity, and cannot meet the needs of various broadband receivers.

[0004] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows:

[0005] A reconfigurable ultra-wideband high-precision variable gain amplifier core circuit includes a first circuit and a second circuit; the first circuit is a cascade amplifier for amplifying an input signal; the second circuit is a digitally controlled programmable current source for providing current to the first circuit;

[0006] The first circuit adopts a three-stage variable gain unit circuit cascade scheme, and the three-stage variable gain unit circuits are a first variable gain unit VGA1 circuit, a second variable gain unit VGA2 circuit and a third variable gain unit VGA3 circuit; wherein the differential input terminal of the first variable gain unit VGA1 circuit is V ip and V in, which is also the differential input end of the entire core circuit; the differential input end of the second variable gain unit VGA2 circuit is connected to the differential output end of the first variable gain unit VGA1 circuit through a coupling capacitor to eliminate the DC offset voltage of the first variable gain unit VGA1 circuit; the differential input end of the third variable gain unit VGA3 circuit is connected to the differential output end of the second variable gain unit VGA2 circuit through a coupling capacitor to eliminate the DC offset voltage of the second variable gain unit VGA2 circuit; the differential output end of the third variable gain unit VGA3 circuit is V op and V on , which is also the differential output end of the entire core circuit; the second variable gain unit VGA2 circuit and the third variable gain unit VGA3 circuit have the same architecture, achieving a 6dB gain adjustment step; the first variable gain unit VGA1 circuit adds a multiplication unit on the basis of the second and third variable gain unit circuits to achieve a 3dB gain adjustment step;

[0007] The second circuit includes three independent digitally controlled variable current sources I C1 , variable current source I C2 and variable current source I C3 , the variable current source I C1 Provides current for the first variable gain unit VGA1, the variable current source I C2 is the second variable gain unit VGA2, the variable current source I C3 Provides current to the third variable gain unit VGA3.

[0008] Furthermore, the first variable gain unit VGA1 circuit is composed of two parts, namely a transconductance stage and a transimpedance stage;

[0009] The input of the transconductance stage is the differential input voltage V i+ and V i- The connection points of the transconductance stage and the transresistance stage are nodes A and B respectively; the transconductance stage serves as the output stage of the variable gain unit, and its output is the differential output voltage Vo+ and Vo-; the transconductance stage consists of five variable transconductance units, namely the first variable transconductance unit T1, the second variable transconductance unit T2, the third variable transconductance unit T3, the fourth variable transconductance unit T4 and the fifth variable transconductance unit T5; the differential input positive terminals of the five variable transconductance units are all connected to V i+ connected, the negative terminals of the differential inputs are connected to V i-The first variable transconductance unit T1, the second variable transconductance unit T2 and the fourth variable transconductance unit T4 have differential output positive terminals connected to the node A, and differential output negative terminals connected to the node B to achieve forward output; the third variable transconductance unit T3 and the fifth variable transconductance unit T5 have differential output positive terminals connected to the node B, and differential output negative terminals connected to the node A to achieve reverse output; the second variable transconductance unit T2 and the third variable transconductance unit T3 form a complementary transconductance pair, and the fourth variable transconductance unit T4 and the fifth variable transconductance unit T5 form a complementary transconductance pair; the first variable transconductance unit T1, the second variable transconductance unit T2, the third variable transconductance unit T3, the fourth variable transconductance unit T4 and the fifth variable transconductance unit T5 each include a switch multiplication unit, which is controlled by the digital control signal B0 to change the total transconductance value of the entire transconductance unit;

[0010] The transimpedance stage has a gain of A V The circuit is composed of a differential amplifier and two feedback networks, wherein the feedback network is used to reconfigure the gain and bandwidth; the feedback network forms negative feedback by connecting between node A, node Vo+ and node B, node Vo-.

[0011] Furthermore, the first variable transconductance unit T1 is composed of a first differential pair transistor, a second differential pair transistor, a controllable tail current source for implementing a switch multiplication unit, and a programmable tail current source; the node A is the differential output positive terminal, and the node B is the differential output negative terminal;

[0012] The first differential pair transistors are the same as the second differential pair transistors; the first differential pair transistors include a sixth transistor M6 and a seventh transistor M7; the second differential pair transistors include a fourth transistor M4 and a fifth transistor M5; for the fourth transistor M4 and the sixth transistor M6, their gates are connected to the input terminal V ip The drains of the fifth transistor M5 and the seventh transistor M7 are connected to the input terminal V in connected, and their drains are connected to node A;

[0013] The tail current source of the first differential pair is the third transistor M3, whose gate is connected to the node V through the multiplexer MUX1. b connected to the earth;

[0014] The tail current source of the second differential pair is the first transistor M1 and the second transistor M2, whose gates are connected to the node V through the multiplexer MUX2. b connected to the earth;

[0015] The controllable tail current source for realizing the switch multiplication unit is a first transistor M1, a second transistor M2 and a third transistor M3;

[0016] The programmable tail current source is the eighth transistor M8;

[0017] The first transistor M1, the second transistor M2 and the third transistor M3 have the same size and all generate a current of I under the same bias voltage;

[0018] The digital control signal B0 directly controls the multiplexer MUX2, and the multiplexer MUX1 is controlled by the output signal of B0 after passing through the first-stage inverter; the node V b The voltage of the digitally controlled current source array is determined by I C1 and transistor M8; the source of transistor M8 is connected to the ground, and the gate and drain are connected to I in the digital controllable current source array. C1 connected to form a digitally controllable current mirror, and by controlling I C1 The change of changes the current of the first transistor M1, the second transistor M2 and the third transistor M3.

[0019] Furthermore, the feedback network is composed of a variable capacitance array of node A to ground, a variable capacitance array of node Vo+ to ground, and a series variable resistor array;

[0020] The variable capacitance array at node A to ground consists of capacitance C 00 , capacitor C 10 , capacitor C 20 , capacitor C 30 and switch B 00 , switch B 10 , switch B 20 , switch B 30 Composition; the capacitor C 00 , capacitor C 10 , capacitor C 20 , capacitor C 30 The upper plate of the capacitor is connected to node A, and the lower plate is connected to switch B. 00 , switch B 10 , switch B 20 , switch B 30 connected, and the branch is controlled to be turned on by it; the switch B 00 , switch B 10 , switch B 20 , switch B 30 The other end is connected to the ground;

[0021] The variable capacitance array of the node Vo+ to ground is composed of capacitor C 01 , capacitor C 11 , capacitor C 21 , capacitor C 31 and switch B 01 , switch B 11 , switch B 21, switch B 31 Composition; the capacitor C 01 , capacitor C 11 , capacitor C 21 , capacitor C 31 The upper plate of the capacitor is connected to node A, and the lower plate is connected to switch B. 01 , switch B 11 , switch B 21 , switch B 31 connected, and the branch is controlled to be turned on by it; the switch B 01 , switch B 11 , switch B 21 , switch B 31 The other end is connected to the ground;

[0022] The series variable resistor array consists of resistors R f1 , resistor R f2 and MOS tube M f Composition: The MOS tube M f The drain is connected through the resistor R f1 Connected to node A, MOS tube M f The source is connected through the resistor R f2 Connected to the node Vop, MOS tube M f Gate and control voltage V C connected; when the source voltage remains unchanged, the on-resistance is changed by controlling the gate voltage, thereby changing the total gain of the variable gain amplifier without affecting the variable transconductance array and the variable gain range.

[0023] Furthermore, the first transistor M1 , the second transistor M2 , the third transistor M3 , the fourth transistor M4 , the fifth transistor M5 , the sixth transistor M6 , the seventh transistor M7 , and the eighth transistor M8 are all N-type transistors.

[0024] Furthermore, the MOS tube M f It is a P-type transistor.

[0025] The reconfigurable ultra-wideband high-precision variable gain amplifier core circuit of the present invention has the following advantages:

[0026] 1. The gain control method adopted by the circuit of the present invention makes the coarse gain adjustment and the fine gain adjustment completely independent, greatly reducing the complexity of the circuit, improving the broadband performance of the circuit, and achieving high-precision gain control;

[0027] 2. The circuit of the present invention can keep the bandwidth constant within the entire variable gain range, ensuring that the group delay of the core circuit remains unchanged at different gains;

[0028] 3. The circuit of the present invention can realize the configurability of gain and bandwidth at the same time, and does not affect the variable gain range while performing gain and bandwidth configuration, thus meeting various system requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a schematic diagram of the core circuit architecture of the reconfigurable ultra-wideband high-precision variable gain amplifier of the present invention;

[0030] Figure 2 This is a schematic diagram of the principle of the variable gain unit used in the present invention;

[0031] Figure 3 Schematic diagram of the principle of the variable transconductance unit T1 of the present invention;

[0032] Figure 4 It is a schematic diagram of the principle of the feedback network 1002 in the three-stage variable gain amplifier of the present invention.

[0033] Explanation of the symbols in the figure: 100, first circuit; 101, transconductance stage; 1001, first variable transconductance unit T1; 102, transresistance stage; 1002, feedback network; 200, second circuit. DETAILED DESCRIPTION

[0034] In order to better understand the purpose, structure and function of the present invention, the following further describes in detail a reconfigurable ultra-wideband high-precision variable gain amplifier core circuit of the present invention in conjunction with the accompanying drawings.

[0035] Figure 1 The figure shows an architecture diagram of an embodiment of a reconfigurable ultra-wideband high-precision variable gain amplifier core circuit disclosed in the present invention, including a first circuit 100 and a second circuit 200; the first circuit 100 is a cascade amplifier that amplifies the input signal; the second circuit 200 is a digitally controlled programmable current source that provides current to the first circuit 100.

[0036] In order to effectively improve the variable gain range and bandwidth while taking into account the requirements of noise and linearity, the present invention adopts a three-stage variable gain unit circuit cascade scheme. The three-stage variable gain unit circuits are the first variable gain unit VGA1 circuit, the second variable gain unit VGA2 circuit and the third variable gain unit VGA3 circuit. ip and V inIt is the differential input end of the first variable gain unit VGA1 circuit, and is also the differential input end of the entire core circuit; the differential input end of the second variable gain unit VGA2 circuit is connected to the differential output end of the first variable gain unit VGA1 circuit through a coupling capacitor to eliminate the DC offset voltage of the VGA1 circuit; the differential input end of the third variable gain unit VGA3 circuit is connected to the differential output end of the second variable gain unit VGA2 circuit through a coupling capacitor to eliminate the DC offset voltage of the VGA2 circuit; V op and V on It is the differential output end of the third variable gain unit VGA3 circuit, and also the differential output end of the entire core circuit; the current of the three-stage variable gain unit circuit is provided by a digitally controllable current source array, which includes three independent variable current sources I C1 , I C2 and I C3 , the variable current source I C1 Provides current for the first variable gain unit VGA1, the variable current source I C2 is the second variable gain unit VGA2, the variable current source I C3 Provide current for VGA3. Under the control of the gain coarse adjustment digital control signal, VGA1 can achieve a gain step of 3dB and a variable gain range of 15dB, and VGA2 and VGA3 can achieve a gain step of 6dB and a variable gain range of 12dB. High-precision gain fine adjustment is achieved by a digitally controllable current source array controlled by the gain fine adjustment digital control signal. Each level of variable gain unit achieves a high-precision gain step of 0.5dB and a variable gain range of 1dB. Therefore, the three-level variable gain unit can achieve a total gain step of 0.5dB and a variable gain range of 3dB. Combined with the minimum step of 3dB for coarse gain adjustment, the core circuit of the variable gain amplifier can achieve a high-precision gain step of 0.5dB and a variable gain range of up to 42dB. The gain adjustment mechanism disclosed in the present invention is that coarse gain adjustment and fine gain adjustment are completely independent, which greatly reduces the circuit complexity, improves the broadband performance of the circuit, and achieves high-precision gain control. In addition, this solution can keep the bandwidth constant throughout the entire variable gain range, ensuring that the group delay of the core circuit remains unchanged at different gains.

[0037] like Figure 2 As shown in FIG, the circuit architecture of the first variable gain unit VGA1 consists of two parts, namely the transconductance stage 101 and the transresistance stage 102. The transconductance stage consists of five variable transconductance units, namely the first variable transconductance unit T11001, the second variable transconductance unit T2, the third variable transconductance unit T3, the fourth variable transconductance unit T4 and the fifth variable transconductance unit T5. The differential input positive terminals of the five variable transconductance units are all connected to V i+ connected, the negative terminals of the differential inputs are connected to V i-The first variable transconductance unit T11001, the second variable transconductance unit T2, and the fourth variable transconductance unit T4 have their differential output positive terminals connected to node A, and their differential output negative terminals connected to node B, to achieve forward output. The third variable transconductance unit T3 and the fifth variable transconductance unit T5 have their differential output positive terminals connected to node B, and their differential output negative terminals connected to node A, to achieve reverse output. The second variable transconductance unit T2 and the third variable transconductance unit T3 form a complementary transconductance pair, and the fourth variable transconductance unit T4 and the fifth variable transconductance unit T5 form a complementary transconductance pair. The two variable transconductance units in the complementary transconductance pair have completely symmetrical circuit structures, differing in that their output polarities are opposite. T2 and T3 are controlled by digital control signal B1, and T4 and T5 are controlled by digital control signal B2. The complementary transconductance pairs work exclusively, that is, only one variable transconductance unit works in each gain state, so that a variety of transconductance value combinations can be achieved, and the impedance of nodes A and B does not change with the transconductance value, ensuring the consistency of bandwidth. In addition, each variable transconductance unit contains a switch multiplication unit, which is controlled by digital control signal B0 to change the total transconductance value of the entire transconductance unit. The transimpedance stage is composed of a gain of A V The differential amplifier and two RC feedback networks 1002 are mainly used for reconfiguring gain and bandwidth. The network forms negative feedback by connecting across the input and output of the differential amplifier. This negative feedback greatly reduces the voltage between nodes A, B and the output node V op 、V on The impedance is reduced, thus expanding the bandwidth. It should be noted that the second and third variable gain units have a similar circuit architecture to the first variable gain unit. By removing the multiplication unit from the first variable gain unit VGA1, the circuit architecture of the second variable gain unit VGA2 and the third variable gain unit VGA3 is obtained. This meets various system requirements.

[0038] Table 1 Correspondence between B0B1B2 and the total transconductance value of the transconductance stage

[0039]

[0040] In this embodiment, to ensure that the bandwidth remains constant within the set gain variable range, the present invention adopts a gain control method that uses complementary transconductance pairs to change the transconductance of the transconductance stage to achieve high-precision coarse gain control, while simultaneously using a scheme to change the tail current of the transconductance stage to achieve high-precision fine gain control. In this architecture, coarse gain adjustment and fine gain adjustment are relatively independent. This control method achieves high-precision, wide-range variable gain while avoiding the use of a large number of complementary transconductance pairs. Its advantages are reduced circuit complexity and transistor parasitic effects, improved bandwidth performance, and avoided the impact of transistor mismatch on gain accuracy. Coarse gain adjustment is mainly controlled by digital control signals B0, digital control signal B1, and digital control signal B2. Under the control of digital control signal B1, the two transconductance pairs of the second variable transconductance unit T2 and the third variable transconductance unit T3 are exclusive, and only one group is turned on at a time; similarly, under the control of digital control signal B2, the two transconductance pairs of the fourth variable transconductance unit T4 and the fifth variable transconductance unit T5 are only one group turned on at a time; digital control signal B0 controls whether the transconductance values ​​of the five transconductance pairs are reduced at the same time. times. In order to achieve the set gain step, the transconductance g m1 、g m2 and g m3 The ratio can be set to 3:2:3. The corresponding relationship between the digital control bits B0B1B2 and the total transconductance value of the transconductance stage is shown in Table 1. As can be seen from the table, under this setting, a 3dB step size gain coarse adjustment and a 15dB variable gain range can be achieved. The gain fine adjustment is mainly achieved through the variable current sources in the first variable transconductance unit T11001 to the fifth variable transconductance unit T5 of the five transconductance pairs. According to the relationship between current and transconductance As can be seen, when transistor size remains constant, transistor current is proportional to the square of its transconductance. Therefore, a digitally controllable current source array can be used to precisely adjust the transconductance stage current, enabling high-precision fine tuning of transconductance and gain, while ensuring complete independence between coarse and fine gain adjustments.

[0041] Figure 3 FIG. 4 is a schematic diagram of an embodiment of a first variable transconductance unit T1 according to the present disclosure.

[0042] For the input signal of the first variable transconductance unit T11001, the differential input positive terminal is V i+ , the negative terminal of the differential input is V i- ; For the output signal of the first variable transconductance unit T11001, node A is the differential output positive terminal, and node B is the differential output negative terminal.

[0043] In this embodiment, the first variable transconductance unit T11001 is composed of two pairs of identical differential pair transistors, a controllable tail current source for realizing a switch multiplication unit, and a programmable tail current source. The sixth transistor M6 and the seventh transistor M7 are the first differential pair transistors, and the fourth transistor M4 and the fifth transistor M5 are the second differential pair transistors. For the fourth transistor M4 and the sixth transistor M6, their gates are connected to the input terminal V i+ The drains of the fifth transistor M5 and the seventh transistor M7 are connected to the input terminal V i- The third transistor M3 is connected to the node A, and its drain is connected to the node A; the third transistor M3 serves as the tail current source of the first differential pair tube, and its gate is connected to the node V through the multiplexer MUX1. b The first transistor M1 and the second transistor M2 serve as the tail current source of the second differential pair tube, and their gates are connected to the node V through the multiplexer MUX2. b The first transistor M1, the second transistor M2, and the third transistor M3 are of the same size and all generate a current of I under the same bias voltage. The digital control signal B0 directly controls the multiplexer MUX2, and the multiplexer MUX1 is controlled by the output signal of the digital control signal B0 after passing through a first-stage inverter. Node V b The voltage of the digitally controlled current source array is determined by I C1 The eighth transistor M8 has a source connected to the ground, a gate and a drain connected to the I in the digital controllable current source array. C1 connected to form a digitally controllable current mirror, and by controlling I C1 The change of changes the current of the first transistor M1, the second transistor M2 and the third transistor M3. Its specific working principle is as follows: In the gain coarse adjustment mode, when B0 is low, the gate of the second transistor M2 is connected to V b , the gate of the third transistor M3 is grounded, so the current flowing through the fourth transistor M4 and the fifth transistor M5 is 2I, and the sixth transistor M6 and the seventh transistor M7 have no current. On the contrary, when B0 is high, the gate of the third transistor M3 is connected to V b , the gate of the second transistor M2 is grounded, and the current of 2I is evenly distributed to the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7; compared with when B0 is high, when B0 is low, it can be considered that the current remains unchanged while the gate width of the transistor is halved. According to the relationship between current and transconductance It can be seen that the gain is the original times, that is, the gain is reduced by 3dB, thus achieving a high-precision 3dB gain step; in the gain fine adjustment mode, also according to the relationship between current and transconductance When the transistor size remains unchanged, the current is proportional to the square of the transconductance. Therefore, I C1The current is fine-tuned, and by adjusting the adjustment step of the digitally controlled current source, accurate control of the gain fine-tuning accuracy is achieved, thereby achieving high-precision fine-tuning of the transconductance and gain.

[0044] Figure 4 FIG1 is a schematic diagram of an embodiment of a feedback network 1002 in a three-stage variable gain amplifier according to the present invention. The feedback network 1002 includes a variable capacitance array at node A to ground, a variable capacitance array at node V o+ The feedback network 1002 consists of a variable capacitance array to ground and a series variable resistor array. o+ The variable capacitance array to ground is composed of a series variable resistor array. The variable capacitance array to ground of node A consists of capacitor C 00 , capacitor C 10 , capacitor C 20 , capacitor C 30 and switch B 00 , switch B 10 , switch B 20 , switch B 30 Composition; Capacitor C 00 , capacitor C 10 , capacitor C 20 , capacitor C 30 The upper plate is connected to the node A, and the lower plate is connected to the switch B 00 , switch B 10 , switch B 20 , switch B 30 connected, and controls whether the branch is conductive; switch B 00 , switch B 10 , switch B 20 , switch B 30 The other end is connected to the ground. o+ The variable capacitance array to ground consists of capacitor C 01 , capacitor C 11 , capacitor C 21 , capacitor C 31 and switch B 01 , switch B 11 , switch B 21 , switch B 31 Composition; Capacitor C 01 , capacitor C 11 , capacitor C 21 , capacitor C 31 The upper plate is connected to the node A, and the lower plate is connected to the switch B 01 , switch B 11 , switch B 21 , switch B 31 connected, and controls whether the branch is conductive; switch B 01 , switch B11 , switch B 21 , switch B 31 The other end is connected to the ground. Figure 2 It can be seen that node A, node B and V o+ 、V o- It is the main pole of the three-stage variable gain amplifier. The bandwidth of the amplifier depends on the capacitance introduced by the above node. Therefore, by controlling the switch of the capacitor branch, the bandwidth of the entire variable gain amplifier can be adjusted. On the one hand, it can meet the requirements of different bandwidths, and on the other hand, it can compensate for the bandwidth errors under different processes and temperatures. In this embodiment, the capacitance value weight is set to binary. Using a 4-bit control signal, 16 groups of different capacitance values ​​can be realized, realizing 16 groups of different bandwidth configurations.

[0045] It should be understood that the capacitor array disclosed in the present invention is not limited to this, and the number of switched capacitor arrays, the size of switched capacitors, and the weights can be changed according to actual system requirements. As mentioned above, the total gain is proportional to the transresistance of the transresistance stage, and the total gain performance can be changed by controlling the transresistance value. In this structure, the amplifier transconductance and transresistance value do not affect each other. Changing the transresistance value does not affect the overall variable gain range and is the optimal solution to achieve gain reconfiguration. In this way, on the one hand, it can be used to meet the gain requirements of various systems, and can effectively compensate for the gain errors caused by process and temperature changes. As the transresistance in this embodiment, the series variable resistor array is composed of resistors R f1 、R f2 and MOS tube M f Composition, MOS tube M f The drain is connected through the resistor R f1 Connected to node A, MOS tube M f The source is connected through the resistor R f2 With node V op Connected, M f Gate and control voltage V C Since the on-resistance of the MOS tube is directly related to the gate and source voltages, when the source voltage remains unchanged, its on-resistance can be changed by controlling the gate voltage, thereby changing the total gain of the variable gain amplifier without affecting the variable transconductance array and the variable gain range.

Claims

1. A reconfigurable ultra-wideband high-precision variable gain amplifier core circuit, characterized in that: The invention comprises a first circuit (100) and a second circuit (200); the first circuit (100) is a cascade amplifier for amplifying an input signal; the second circuit (200) is a digitally controlled programmable current source for providing current to the first circuit (100); The first circuit (100) adopts a three-stage variable gain unit circuit cascade scheme, wherein the three-stage variable gain unit circuits are respectively a first variable gain unit VGA1 circuit, a second variable gain unit VGA2 circuit and a third variable gain unit VGA3 circuit; The differential input terminal of the first variable gain unit VGA1 circuit is V ip and V in , which is also the differential input end of the entire core circuit; the differential input end of the second variable gain unit VGA2 circuit is connected to the differential output end of the first variable gain unit VGA1 circuit through a coupling capacitor to eliminate the DC offset voltage of the first variable gain unit VGA1 circuit; The differential input end of the third variable gain unit VGA3 circuit is connected to the differential output end of the second variable gain unit VGA2 circuit via a coupling capacitor to eliminate a DC offset voltage of the second variable gain unit VGA2 circuit; The differential output terminal of the third variable gain unit VGA3 circuit is V op and V on , which is also the differential output end of the entire core circuit; the second variable gain unit VGA2 circuit and the third variable gain unit VGA3 circuit have the same architecture, achieving a 6dB gain adjustment step; the first variable gain unit VGA1 circuit adds a multiplication unit on the basis of the second and third variable gain unit circuits to achieve a 3dB gain adjustment step; The second circuit (200) includes three independent digitally controlled variable current sources I C1 , variable current source I C2 and variable current source I C3 , the variable current source I C1 Provides current for the first variable gain unit VGA1, the variable current source I C2 The second variable gain unit VGA2, the variable current source I C3 Providing current to the third variable gain unit VGA3; The first variable gain unit VGA1 circuit consists of two parts, namely a transconductance stage (101) and a transresistance stage (102); The input of the transconductance stage (101) is a differential input voltage V i+ and V i- The connection points of the transconductance stage (101) and the transresistance stage (102) are nodes A and B, respectively. The transconductance stage (101) serves as an output stage of a variable gain unit, and its output is a differential output voltage Vo+ and Vo-. The transconductance stage (101) is composed of five variable transconductance units, namely a first variable transconductance unit T1 (1001), a second variable transconductance unit T2, a third variable transconductance unit T3, a fourth variable transconductance unit T4, and a fifth variable transconductance unit T5. The differential input positive terminals of the five variable transconductance units are all connected to Vi+, and the differential input negative terminals are all connected to Vi-; the differential output positive terminals of the first variable transconductance unit T1 (1001), the second variable transconductance unit T2, and the fourth variable transconductance unit T4 are all connected to node A, and the differential output negative terminals are all connected to node B, so as to achieve forward output; the differential output positive terminals of the third variable transconductance unit T3 and the fifth variable transconductance unit T5 are all connected to node B, and the differential output negative terminals are all connected to node A, so as to achieve reverse output; The second variable transconductance unit T2 and the third variable transconductance unit T3 are a set of complementary transconductance pairs, and the fourth variable transconductance unit T4 and the fifth variable transconductance unit T5 are a set of complementary transconductance pairs; the first variable transconductance unit T1 (1001), the second variable transconductance unit T2, the third variable transconductance unit T3, the fourth variable transconductance unit T4 and the fifth variable transconductance unit T5 each include a switch multiplication unit, and the multiplication unit is controlled by a digital control signal B0 to change the total transconductance value of the entire transconductance unit; The transimpedance stage (102) has a gain of A V The invention is composed of a differential amplifier and two feedback networks (1002), wherein the feedback network (1002) is used for reconfiguring the gain and bandwidth; the feedback network (1002) forms a negative feedback by crossing the node A, the node Vo+ and the node B, the node Vo-.

2. The reconfigurable ultra-wideband high-precision variable gain amplifier core circuit according to claim 1, characterized in that: The first variable transconductance unit T1 (1001) is composed of a first differential pair transistor, a second differential pair transistor, a controllable tail current source for realizing a switch multiplication unit, and a programmable tail current source; the node A is a differential output positive terminal, and the node B is a differential output negative terminal; The first differential pair transistors are the same as the second differential pair transistors; the first differential pair transistors include a sixth transistor M6 and a seventh transistor M7; the second differential pair transistors include a fourth transistor M4 and a fifth transistor M5; for the fourth transistor M4 and the sixth transistor M6, their gates are connected to the input terminal V ip The drains of the fifth transistor M5 and the seventh transistor M7 are connected to the input terminal V in connected, and their drains are connected to node A; The tail current source of the first differential pair is the third transistor M3, whose gate is connected to the node V through the multiplexer MUX1. b connected to the earth; The tail current source of the second differential pair is the first transistor M1 and the second transistor M2, whose gates are connected to the node V through the multiplexer MUX2. b connected to the earth; The controllable tail current source for realizing the switch multiplication unit is a first transistor M1, a second transistor M2 and a third transistor M3; The programmable tail current source is the eighth transistor M8; The first transistor M1, the second transistor M2 and the third transistor M3 have the same size and all generate a current of I under the same bias voltage; The digital control signal B0 directly controls the multiplexer MUX2, and the multiplexer MUX1 is controlled by the output signal of B0 after passing through the first-stage inverter; the node V b The voltage of the digitally controlled current source array is I C1 and transistor M8 generates; The source of transistor M8 is connected to the ground, and the gate and drain are connected to the digital controllable current source array. I C1 connected to form a digitally controllable current mirror, and by controlling I C1 The change of changes the current of the first transistor M1, the second transistor M2 and the third transistor M3.

3. The reconfigurable ultra-wideband high-precision variable gain amplifier core circuit according to claim 2, characterized in that: The feedback network (1002) is composed of a variable capacitance array of node A to ground, a variable capacitance array of node Vo+ to ground, and a series variable resistor array; The variable capacitance array at node A to ground consists of capacitance C 00 , capacitor C 10 , capacitor C 20 , capacitor C 30 and switch B 00 , switch B 10 , switch B 20 , switch B 30 Composition; the capacitor C 00 , capacitor C 10 , capacitor C 20 , capacitor C 30 The upper plate of the capacitor is connected to node A, and the lower plate is connected to switch B. 00 , switch B 10 , switch B 20 , switch B 30 connected, and the variable capacitance array to ground is turned on by its control node A; the switch B 00 , switch B 10 , switch B 20 , switch B 30 The other end is connected to the ground; The variable capacitance array of the node Vo+ to ground is composed of capacitor C 01 , capacitor C 11 , capacitor C 21 , capacitor C 31 and switch B 01 , switch B 11 , switch B 21 , switch B 31 Composition; the capacitor C 01 , capacitor C 11 , capacitor C 21 , capacitor C 31 The upper plate of the capacitor is connected to node A, and the lower plate is connected to switch B. 01 , switch B 11 , switch B 21 , switch B 31 connected, and the variable capacitance array to ground is turned on by its control node Vo+; the switch B 01 , switch B 11 , switch B 21 , switch B 31 The other end is connected to the ground; The series variable resistor array consists of resistors R f1 ,resistance R f2 and MOS tube M f Composition: The MOS tube M f Drain through resistor R f1 Connected to node A, MOS tube M f Source through resistor R f2 Connected to the node Vop, MOS tube M f Gate and control voltage V C connected; when the source voltage remains unchanged, the on-resistance is changed by controlling the gate voltage, thereby changing the total gain of the variable gain amplifier without affecting the variable transconductance array and the variable gain range.

4. The reconfigurable ultra-wideband high-precision variable gain amplifier core circuit according to claim 3, characterized in that: The first transistor M1 , the second transistor M2 , the third transistor M3 , the fourth transistor M4 , the fifth transistor M5 , the sixth transistor M6 , the seventh transistor M7 , and the eighth transistor M8 are all N-type transistors.

5. The reconfigurable ultra-wideband high-precision variable gain amplifier core circuit according to claim 4, characterized in that: The MOS tube M f It is a P-type transistor.

Images