Thin-film transistors, semiconductor substrates, and X-ray flat-panel detectors

Abstract

The embodiment of the present disclosure provides a thin film transistor, comprising: a gate, an active layer, a gate insulating layer located between the gate and the active layer, and a source and a drain electrically connected to the active layer. The active layer comprises a channel layer and at least one channel protection layer overlapped in a stacking direction, and the material of each of the channel layer and the at least one channel protection layer is a metal oxide semiconductor material. At least one channel protection layer is a crystalline layer, and the metal element of at least one channel protection layer includes a non-rare earth metal element, and the non-rare earth metal element includes In, Ga, Zn and Sn.

Description

[0001] For all purposes, this application claims priority to Chinese Patent Application No. 202010591840.5 filed on June 24, 2020, and the contents of the above-mentioned Chinese patent application disclosure are hereby cited in their entirety as a part of this application. Technical Field

[0002] The embodiments of the present disclosure relate to a thin film transistor, a semiconductor substrate and an X-ray flat panel detector. Background Art

[0003] Amorphous semiconductor materials are widely used in display technology driver devices. For example, amorphous silicon thin film transistors dominate the display semiconductor substrate backplane due to their simple process, good device uniformity and low temperature process. Metal oxide semiconductor thin film transistors with amorphous metal oxide semiconductors as channels, such as amorphous indium gallium zinc oxide (a-IGZO) and amorphous indium zinc oxide (a-IZO), are expected to replace amorphous silicon thin film transistors as mainstream display driver devices because of their high channel mobility and good large-area uniformity. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a thin film transistor, comprising: a gate, an active layer, a gate insulating layer located between the gate and the active layer, and a source and a drain electrically connected to the active layer. The active layer comprises a channel layer and at least one channel protection layer overlapped in a stacking direction, and the material of each of the channel layer and the at least one channel protection layer is a metal oxide semiconductor material. The at least one channel protection layer is a crystalline layer, and the metal element of the at least one channel protection layer includes a non-rare earth metal element, and the non-rare earth metal element includes In, Ga, Zn and Sn.

[0005] In one example, the at least one channel protection layer includes a first channel protection layer located on a side of the channel layer close to the source and the drain; the metal element of the first channel protection layer further includes at least one rare earth metal element.

[0006] In one example, the channel layer includes a first channel portion adjacent to the first channel protection layer, the first channel portion includes at least a first surface of the channel layer that is in direct contact with the first channel protection layer, the first channel portion includes at least one rare earth metal element that is the same as the at least one rare earth metal element in the first channel protection layer, and the absolute value of the energy band gap of the first channel portion is smaller than the absolute value of the energy band gap of the first channel protection layer.

[0007] In one example, the channel layer also includes a second channel portion located on a side of the first channel portion away from the first channel protection layer in the stacking direction, and the absolute value of the energy band gap of the second channel portion is smaller than the absolute value of the energy band gap of the first channel portion, so that the first channel portion serves as a transition layer between the second channel portion and the first channel protection layer.

[0008] In one example, the second channel portion includes at least a second surface of the channel layer away from the first channel protection layer, and the second channel portion does not contain any rare earth metal element that is the same as the at least one rare earth metal element in the first channel protection layer.

[0009] In one example, the second channel portion includes at least a second surface of the channel layer away from the first channel protection layer, the second channel portion includes at least one rare earth metal element that is the same as the at least one rare earth metal element in the first channel protection layer and the first channel portion, and the atomic percentage of the at least one rare earth metal element in the second channel portion is less than the atomic percentage of the at least one rare earth metal element in the first channel portion.

[0010] In one example, the at least one channel protection layer is formed by target deposition.

[0011] In one example, the metal elements of the channel layer include In, Ga, and Zn.

[0012] In one example, the at least one rare earth metal element of the first channel protection layer is selected from the group consisting of Pr, Ir, Tb and Sm.

[0013] In one example, the at least one rare earth metal element of the first channel protection layer includes two selected from the group consisting of Pr, Ir, Tb, and Sm.

[0014] In one example, the at least one rare earth metal element of the first channel protection layer includes Pr and Sm.

[0015] In one example, the number of species of the at least one rare earth metal element of the first channel protection layer is greater than the number of species of the at least one rare earth metal element in the surface of the channel layer.

[0016] In one example, the at least one rare earth metal element of the first channel protection layer includes a first rare earth metal element and a second rare earth metal element different from each other, and the at least one rare earth metal element in the first channel portion includes the first rare earth metal element but does not include the second rare earth metal element.

[0017] In one example, the first rare earth metal element is Pr, and the second rare earth metal element is Sm.

[0018] In one example, a difference between the absolute value of any one of the energy band gap of the first channel portion and the energy band gap of the second channel portion and the absolute value of the energy band gap of the first channel protection layer is greater than zero and less than or equal to 1.5 eV.

[0019] In one example, in the at least one channel protection layer, the atomic percentage of at least one of the non-rare earth metal elements relative to all the metal elements is greater than or equal to 40 at %.

[0020] In one example, in the at least one channel protection layer, the number of atoms of one of the non-rare earth metal elements is greater than the total number of atoms of the remaining metal elements.

[0021] In one example, in the at least one channel protection layer, the one of the non-rare earth metal elements is Zn or Sn.

[0022] In one example, in the at least one channel protection layer, a ratio of the sum of the number of atoms of the at least one rare earth metal element to the sum of the number of atoms of the non-rare earth metal element is in a range of 0.1% to 5%.

[0023] In one example, the channel layer is a crystalline layer or an amorphous layer.

[0024] In one example, in the metal oxide semiconductor material of at least one channel protection layer, the number of types of the non-rare earth metal elements is N, and the ratio of the number of atoms of any one of the non-rare earth metal elements to the total number of atoms of the other non-rare earth metal elements is greater than or equal to 1 / N.

[0025] In one example, the at least one channel protection layer further includes a second channel protection layer located on a side of the channel layer away from the source and the drain.

[0026] In one example, in the stacking direction, the thickness of the at least one channel protection layer is greater than or equal to the thickness of the channel layer.

[0027] In one example, in the stacking direction, the thickness of the channel layer is in a range of 1 nm to 50 nm.

[0028] In one example, in the stacking direction, the thickness of the channel layer is in a range of 5 nm to 20 nm.

[0029] In one example, in the stacking direction, the thickness of the at least one channel protection layer is in a range of 20 nm to 100 nm.

[0030] In one example, in the stacking direction, the thickness of the at least one channel protection layer is in a range of 30 nm to 60 nm.

[0031] In one example, the carrier concentration of the at least one channel protection layer is less than the carrier concentration of the channel layer.

[0032] At least another embodiment of the present disclosure provides a thin film transistor, comprising: a gate, a gate insulating layer, an active layer, and a source electrode and a drain electrode electrically connected to the active layer, wherein:

[0033] The active layer includes a channel layer and at least one channel protection layer which are overlapped in a stacking direction, and the materials of the channel layer and the at least one channel protection layer are both metal oxide semiconductor materials.

[0034] The at least one channel protection layer is a crystalline layer, and the metal elements of the at least one channel protection layer include non-rare earth metal elements and at least one rare earth metal element, wherein the non-rare earth metal elements include at least two selected from the group consisting of In, Ga, Zn and Sn, and the at least two selected from the group consisting of In, Ga, Zn and Sn include at least one of In and Zn.

[0035] At least another embodiment of the present disclosure provides a semiconductor substrate, including a base substrate and a thin film transistor located on the base substrate, wherein the thin film transistor is any one of the above-mentioned thin film transistors.

[0036] At least another embodiment of the present disclosure provides an X-ray flat panel detector, comprising any of the above-mentioned thin film transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other implementation methods can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 is a schematic cross-sectional structural diagram of a semiconductor substrate according to at least one embodiment of the present disclosure; and

[0039] Figures 2A to 2G A schematic diagram of a substrate structure corresponding to each step in a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0041] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" and the like mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0042] The channel layer of the related back channel etched metal oxide semiconductor thin film transistor is usually a single layer of high mobility metal oxide semiconductor layer. When etching to form the source and drain electrodes, this structure may cause the back channel to be corroded by the source and drain etchant. Since the source and drain etchant causes great damage to the metal oxide semiconductor channel layer, a large number of defects are formed on the back of the channel, resulting in a significant reduction in the mobility of the channel layer and the stability of the thin film transistor, which adversely affects the device characteristics. In addition, since there will be a certain amount of interface defects on the interface where the channel layer contacts the gate insulation layer and the passivation layer, these defects will also reduce the mobility of the channel layer and the stability of the thin film transistor. The channel layer is easily affected by backlight, OLED emission light or ambient light, resulting in a large number of photogenerated carriers generated inside the channel layer. Under long-term working conditions, it is easy to cause the characteristics of the thin film transistor to be negatively biased (negative bias will cause problems such as sand point mura), which adversely affects the stability of the thin film transistor.

[0043] At least one embodiment of the present disclosure provides a thin film transistor, comprising: a gate, an active layer, a gate insulating layer located between the gate and the active layer, and a source and a drain electrically connected to the active layer. The active layer comprises a channel layer and at least one channel protection layer overlapped in a stacking direction, and the material of each of the channel layer and the at least one channel protection layer is a metal oxide semiconductor material. The at least one channel protection layer is a crystalline layer, and the metal element of the at least one channel protection layer includes a non-rare earth metal element, and the non-rare earth metal element includes In, Ga, Zn and Sn.

[0044] At least another embodiment of the present disclosure provides a thin film transistor, comprising: a gate, a gate insulating layer, an active layer, and a source and a drain electrically connected to the active layer. The active layer comprises a channel layer and at least one channel protection layer overlapped in a stacking direction, and the materials of the channel layer and the at least one channel protection layer are both metal oxide semiconductor materials. The at least one channel protection layer is a crystalline layer, and the metal element of the at least one channel protection layer comprises a non-rare earth metal element and at least one rare earth metal element. The non-rare earth metal element comprises at least two selected from the group consisting of In, Ga, Zn and Sn, and the at least two selected from the group consisting of In, Ga, Zn and Sn comprise at least one of In and Zn.

[0045] In this way, defects in the channel layer can be effectively reduced, thereby effectively improving the overall electrical stability (eg, voltage resistance stability, current resistance stability) of the thin film transistor.

[0046] Figure 1 A schematic diagram of the cross-sectional structure of a semiconductor substrate 10 provided in at least one embodiment of the present disclosure.

[0047] At least one embodiment of the present disclosure provides a thin film transistor TFT. Figure 1 The thin film transistor TFT provided in at least one embodiment of the present disclosure is, for example, included in the semiconductor substrate 10 provided in at least one embodiment of the present disclosure.

[0048] The semiconductor substrate 10 includes, for example, a base substrate 110 and a thin film transistor TFT formed on the base substrate 110 .

[0049] See also Figure 1 At least one embodiment of the present disclosure provides a thin film transistor TFT including: a gate 170, an active layer SL, a gate insulating layer 160 between the gate 170 and the active layer SL, and a source electrode 181 and a drain electrode 182 electrically connected to the active layer SL. The thin film transistor TFT may be a TFT with a top gate and a bottom gate structure, for example, a back channel etching (BCE) type TFT with a bottom gate structure.

[0050] The active layer SL includes a channel layer CL, a first channel protection layer PL1, and a second channel protection layer PL2 which are overlapped in a stacking direction. The first channel protection layer PL1 and the second channel protection layer PL2 are located at opposite sides of the channel layer CL.

[0051] Here, the stacking direction may be a direction perpendicular to the main surface of the base substrate 110, such as Figure 1 As indicated by the arrow in .

[0052] In the stacking direction, the first channel protection layer PL1 is located on one side of the channel layer CL close to the source 181 and the drain 182 , and the second channel protection layer PL2 is located on the other side of the channel layer CL away from the source 181 and the drain 182 .

[0053] The channel layer CL, the first channel protection layer PL1 and the second channel protection layer PL2 are each made of a metal oxide semiconductor material. The first channel protection layer PL1 and the second channel protection layer PL2 are each a crystalline layer.

[0054] Here, "crystalline layer" refers to a material layer that is mainly crystalline, and may also contain tiny amorphous parts. For example, the crystalline layer may include crystals larger than 10 nm in size, or crystals of nanometer size (1 nm to 10 nm), or crystals that are crystallized in all directions, or crystals that are C-axis crystallized (CAAC crystals).

[0055] The first channel protection layer PL1 of the crystalline layer is used as at least a barrier layer. It is possible to avoid or reduce the back channel etching defects caused by the etching solution on one side of the channel layer CL close to the source 181 and the drain 182, or avoid the injection of atoms such as PVX or metal electrodes such as O or H, Cu, Al into the channel layer caused by the annealing process. The first channel protection layer PL1 and the second channel protection layer PL2 of the crystalline layer can also avoid or reduce interface defects on two opposite surfaces of the channel layer CL. In addition, the first channel protection layer PL1 and the second channel protection layer PL2 of the crystalline layer can effectively block the diffusion of undesirable impurity elements (such as Cu, Al, H, etc.) into the channel layer CL. Therefore, the thin film transistor TFT has improved overall electrical stability.

[0056] If the first channel protection layer PL1 is formed separately on the substrate and an X-ray diffraction test is performed (for example, the diffraction angle scanning range is 20o to 70o, and the scanning step length is 0.02o / s), a protruding crystalline diffraction peak can be observed on the XRD spectrum after denoising. For example, when the material of the first channel protection layer PL1 is an oxide semiconductor containing indium, gallium and zinc, there is a crystalline diffraction peak at a diffraction angle position of 25 to 35o on its XRD ray diffraction spectrum. For the same material of the same thickness, in the XRD spectrum obtained by the same XRD test, the higher the intensity of the crystalline diffraction peak at the same position, the smaller the half-height width, and the greater the ratio of the integrated area of ​​the crystalline peak to the total integrated area, the higher the degree of crystallization. In addition, the high-resolution transmission electron microscope photograph and its selected area electron diffraction spectrum can also be used to determine whether the material layer being tested is a crystalline layer.

[0057] The materials of the first channel protection layer PL1 and the second channel protection layer PL2 can be the same or different. Here, the same materials of two or more layers means that the two or more layers not only contain the same type and number of elements, but also the same proportion of each element in all elements (here, the corresponding proportion is allowed to have an error of less than 5% due to process accuracy). Therefore, the different materials of two or more layers means that the two or more layers contain different types of elements or different numbers of elements or different proportions of each element in all elements.

[0058] For example, the metal element of the first channel protection layer PL1 and / or the second channel protection layer PL2 includes a non-rare earth metal element including In, Ga, Zn, and Sn.

[0059] The first channel protection layer PL1 and / or the second channel protection layer PL2 include Sn, which can stabilize the entire oxide active layer system on the one hand, and can also provide certain carriers; on the other hand, the etching of the oxide active layer system can be optimized under certain conditions. For example, the etching rate of the active layer SL including the first channel protection layer PL1 and / or the second channel protection layer PL2 in the etching solution for aluminum is significantly reduced, so the content of Sn in the first channel protection layer PL1 can be adjusted to match the etching rate of the channel layer CL, thereby reducing the stacking etching process problems (undercut, tail, etc.) and risks.

[0060] In another example, the metal elements of the first channel protection layer PL1 and / or the second channel protection layer PL2 include non-rare earth metal elements and at least one rare earth metal element; the non-rare earth metal elements include at least two of In, Ga, Zn and Sn, and at least two of In, Ga, Zn and Sn include at least one of In and Zn.

[0061] Here, rare earth metal elements are 17 chemical elements in the third group of the periodic table, including scandium, yttrium, and lanthanide. Non-rare earth metal elements are other metal elements except rare earth metal elements.

[0062] In this way, on the one hand, the thin film transistor as a whole can have higher mobility and good structural stability; on the other hand, rare earth metal elements are added to the first channel protection layer PL1 and / or the second channel protection layer PL2, so that the first channel protection layer PL1 and / or the second channel protection layer PL2 itself can absorb part of the light and reduce the amount of light incident on the channel layer CL, thereby improving the light resistance and water vapor resistance of the thin film transistor device.

[0063] In addition, in one example, the pre-annealing precursor stack structure 140 of the active layer SL is formed by a sputtering process, see the following description. Figures 2B to 2D . In the precursor stack structure 140 before annealing, the precursor layer 143 containing rare earth metal elements is used to form the first channel protection layer PL1; the precursor layer 141 containing rare earth metal elements is used to form the second channel protection layer PL2; the precursor layer 142 not containing rare earth metal elements is used to form the channel layer. The rare earth metal elements from the precursor layer 143 and / or the precursor layer 141 may diffuse into the precursor layer 142 during the annealing process to dope it, so that the material of the formed channel layer CL forms a transition state in the band gap due to the doping of rare earth metal elements. The transition state becomes a step for the photogenerated carriers to transition to the conduction band and then return to the valence band, so that the photogenerated carriers can quickly meet, thereby reducing the photogenerated carriers and improving the light stability of the channel layer.

[0064] For example, the first channel protection layer PL1 and / or the second channel protection layer PL2 may have a different material from that of the channel layer CL.

[0065] For example, the first channel protection layer PL1 and / or the second channel protection layer PL2 are formed by target deposition. For example, the first channel protection layer PL1 and / or the second channel protection layer PL2 are formed by a physical vapor deposition process using a target material, and the target material includes a non-rare earth metal element and at least one rare earth metal element.

[0066] For example, in different regions of the first channel protection layer PL1 and / or the second channel protection layer PL2 formed by target deposition, the same metal element has approximately the same atomic percentage. For example, in different regions of the first channel protection layer PL1 and / or the second channel protection layer PL2 formed by target deposition away from the surface of the channel layer CL, the same metal element has approximately the same atomic percentage. Here, the atomic percentage is the proportion of a single atom in the total number of atoms.

[0067] The physical vapor deposition process is, for example, a sputtering process. The sputtering process bombards the surface of a solid target material with particles (ions, neutral atoms or molecules) of a certain energy, so that atoms or molecules on the surface of the solid target material are separated from the target material and fall on the surface of a substrate with a certain energy to form a film on the substrate.

[0068] For example, the metal elements of the first channel protective layer PL1 and / or the second channel protective layer PL2 include In, Ga, Zn, Sn, and at least one rare earth metal element.

[0069] For example, at least one rare earth metal element is selected from the group consisting of praseodymium (Pr), iridium (Ir), terbium (Tb), and samarium (Sm).

[0070] For example, the at least one rare earth metal element of the first channel protection layer PL1 and / or the second channel protection layer PL2 includes two selected from the group consisting of praseodymium Pr, Ir, Tb, and Sm.

[0071] For example, the at least one rare earth metal element of the first channel protection layer PL1 and / or the second channel protection layer PL2 includes Pr and Sm.

[0072] For example, the metal elements of the channel layer CL include In, Ga, and Zn.

[0073] Here, the crystal state of the channel layer CL is not limited. For example, the channel layer CL is a crystal layer or an amorphous layer.

[0074] The “amorphous layer” refers to a material layer that is mainly in an amorphous state, but may also contain a tiny crystalline portion.

[0075] For example, the metal element of the channel layer CL includes at least two of In, Ga, Zn, and Sn, and the at least two of In, Ga, Zn, and Sn include at least one of In and Zn.

[0076] In one example, the material of the channel layer CL is indium gallium zinc oxide (IGZO, where I represents indium element (In), G represents gallium element (Ga), Z represents zinc element (Zn), and O represents oxygen element). The material of the first channel protection layer PL1 and / or the second channel protection layer PL2 is indium gallium zinc tin rare earth oxide (IGZTMO, where I represents indium element (In), G represents gallium element (Ga), Z represents zinc element (Zn), T represents tin element (Sn), M represents rare earth element, and O represents oxygen element).

[0077] It is understandable that although Figure 1The thin film transistor TFT shown includes both the first channel protection layer PL1 and the second channel protection layer PL2. It is understood that the embodiments of the present disclosure are not limited thereto. In another example, the thin film transistor may include only one of the first channel protection layer PL1 and the second channel protection layer PL2.

[0078] exist Figure 1 In the illustrated embodiment, the channel layer CL and the first and second channel protection layers PL1 and PL2 are in direct contact with each other.

[0079] In the stacking direction, a surface of the channel layer CL facing the first channel protection layer PL1 or a surface of the channel layer CL facing the source electrode 181 and the drain electrode 182 is a first surface S1 .

[0080] In the stacking direction, a surface of the channel layer CL facing the second channel protection layer PL2 or a surface of the channel layer CL facing away from the source electrode 181 and the drain electrode 182 is a second surface S2 .

[0081] For example, the first channel protection layer PL1 includes at least one rare earth metal element, and the first surface S1 of the channel layer CL includes at least one rare earth metal element. The rare earth metal element in the first surface S1 of the channel layer CL is diffused from the first channel protection layer PL1 into the first surface S1 of the channel layer CL. The second channel protection layer PL2 includes at least one rare earth metal element, and the second surface S2 of the channel layer CL includes at least one rare earth metal element. The rare earth metal element in the second surface S2 of the channel layer CL is diffused from the second channel protection layer PL2 into the second surface S2 of the channel layer CL.

[0082] In another example, the first channel protection layer PL1 includes at least one rare earth metal element, and the first surface S1 of the channel layer CL includes at least one rare earth metal element. The rare earth metal element in the first surface S1 of the channel layer CL is diffused from the first channel protection layer PL1 into the first surface S1 of the channel layer CL. For example, the second channel protection layer PL2 does not include any rare earth metal element, and the second surface S2 of the channel layer CL does not include any rare earth metal element, and the rare earth metal element may also be diffused from the first surface S1.

[0083] In another example, the second channel protection layer PL2 includes at least one rare earth metal element, and the second surface S2 of the channel layer CL includes at least one rare earth metal element. The rare earth metal element in the second surface S2 of the channel layer CL is diffused from the second channel protection layer PL2 into the second surface S2 of the channel layer CL. For example, the first channel protection layer PL1 does not include any rare earth metal element, and the first surface S1 of the channel layer CL may not include any rare earth metal element or may be a rare earth metal element diffused from the second surface S2.

[0084] Rare earth metal elements diffuse into the channel layer CL for doping, so that a transition state is formed in the material band gap of the channel layer CL due to the doping treatment. The transition state becomes a step for photogenerated carriers to transition to the conduction band and then return to the valence band, so that the photogenerated carriers can quickly meet, thereby reducing the photogenerated carriers and improving the light stability of the channel layer.

[0085] For example, the number of kinds of at least one rare earth metal element of the first channel protection layer PL1 and / or the second channel protection layer PL2 is greater than the number of kinds of rare earth metal elements in the channel layer CL.

[0086] For example, the number of kinds of rare earth metal elements of the first channel protection layer PL1 and / or the second channel protection layer PL2 is 2, and the number of kinds of rare earth metal elements in the first surface S1 and / or the first surface S2 of the channel layer CL is 1.

[0087] For example, at least one rare earth metal element of the first channel protection layer PL1 and / or the second channel protection layer PL2 includes a first rare earth metal element and a second rare earth metal element different from each other, and the rare earth metal elements in the first surface S1 and / or the first surface S2 of the channel layer CL include the first rare earth metal element but not the second rare earth metal element.

[0088] For example, the first rare earth metal element is Pr, and the second rare earth metal element is Sm.

[0089] In one example, the pre-annealing precursor stack structure 140 of the active layer SL is formed by a sputtering process, see the following description. Figures 2B to 2D . In the precursor stack structure 140 before annealing, the precursor layer 143 for forming the first channel protection layer PL1 or the precursor layer 141 for forming the second channel protection layer PL2 includes a first sublayer and a second sublayer, and the first sublayer is located between the precursor layer 142 for forming the channel layer CL and the second sublayer that does not contain any rare earth metal elements. The first sublayer, for example, includes one rare earth metal element (for example, Pr). The second sublayer includes another rare earth metal element (for example, Sm). After the precursor stack structure 140 before annealing is subjected to an annealing process, a portion of Pr at least diffuses into the corresponding surface of the precursor layer 142, and Sm does not diffuse into the corresponding surface of the precursor layer 142. In this way, the first channel protection layer PL1 and / or the second channel protection layer PL2 include two rare earth metal elements (for example, Pr and Sm), and the first surface S1 or the second surface S2 of the channel layer CL includes only one rare earth metal element (for example, Pr).

[0090] In this way, the mobility and / or the on-current of the thin film transistor can be improved while the light stability of the thin film transistor is improved.

[0091] For example, a surface of the first channel protection layer PL1 and / or the second channel protection layer PL2 facing away from the channel layer CL does not include any rare earth metal element.

[0092] In one example, the pre-annealing precursor stack structure 140 of the active layer SL is formed by a sputtering process, see the following description. Figures 2B to 2D . In the precursor stack structure 140 before annealing, the precursor layer 143 for forming the first channel protection layer PL1 or the precursor layer 141 for forming the second channel protection layer PL2 includes a first sublayer and a second sublayer, and the first sublayer is located between the precursor layer 142 for forming the channel layer CL and the second sublayer that does not contain any rare earth metal elements. The first sublayer includes, for example, only one rare earth metal element (for example, Pr). The second sublayer does not include any rare earth metal element. After the precursor stack structure 140 before annealing is subjected to an annealing process, a portion of Pr diffuses at least into the corresponding surface of the precursor layer 142. In this way, the first channel protection layer PL1 and / or the second channel protection layer PL2 only include one rare earth metal element (for example, Pr), and the first surface S1 or the second surface S2 of the channel layer CL also only includes the one rare earth metal element (for example, Pr). In addition, the rare earth metal element, for example, does not diffuse into the surface of the first channel protection layer PL1 or the second channel protection layer PL2 away from the channel layer CL.

[0093] In the process of wet etching to form the source 181 and the drain 182, back defects may be formed on the side of the first channel protection layer PL1 away from the channel CL; the side of the second channel protection layer PL2 away from the channel CL contacts the gate insulating layer to form some interface defects. In addition, when the thin film transistor is working, due to the band gap difference, the channel layer CL is a high carrier concentration material layer, and the carriers generated by it need to cross the band gap difference barrier of the first channel protection layer PL1 and / or the second channel protection layer PL2 before they can jump to other film layers. Therefore, most of the carriers are confined in the channel layer CL. In this way, the stability of the thin film transistor in terms of high voltage resistance and current resistance is improved.

[0094] In one example, the active layer SL may include only the first channel protection layer PL1 but not the second channel protection layer PL2;

[0095] In one example, the active layer SL includes a first channel protection layer PL1 and a second channel protection layer PL2 , and a metal element of the first channel protection layer PL1 includes at least one rare earth metal element and the second channel protection layer PL2 does not include any rare earth metal element.

[0096] For example, the channel layer CL includes a first channel portion CL1 and a second channel portion CL2. In the stacking direction, the first channel portion CL1 is adjacent to the first channel protection layer PL1; the second channel portion CL2 is located on a side of the first channel portion CL1 away from the first channel protection layer PL1. The first channel portion CL1 includes at least a first surface S1 of the channel layer CL that is in direct contact with the first channel protection layer PL1. The second channel portion CL2 includes at least a second surface S2 of the channel layer CL that is away from the first channel protection layer PL1, and here, there may be no obvious interface between the first channel portion CL1 and the second channel portion CL2.

[0097] For example, the first channel portion CL1 includes at least one rare earth metal element that is the same as at least one rare earth metal element in the first channel protection layer PL1; and an absolute value of an energy bandgap of the first channel portion CL1 is smaller than an absolute value of an energy bandgap of the first channel protection layer.

[0098] For example, an absolute value of the energy band gap of the second channel portion CL2 is smaller than an absolute value of the energy band gap of the first channel portion CL1 , so that the first channel portion CL1 serves as a transition layer between the second channel portion CL2 and the first channel protection layer PL1 .

[0099] For example, the second channel portion CL2 does not include any rare earth metal element that is the same as at least one rare earth metal element in the first channel protection layer PL1.

[0100] For example, the second surface S2 does not include any rare earth metal element that is the same as the at least one rare earth metal element in the first channel protection layer PL1 .

[0101] For example, the second channel portion CL2 includes at least one rare earth metal element that is the same as at least one rare earth metal element in the first channel protection layer PL1 and the first channel portion CL1.

[0102] For example, the second surface S2 includes at least one rare earth metal element that is the same as at least one rare earth metal element in the first channel protection layer PL1 and the first channel portion CL1 .

[0103] For example, the atomic percentage of the at least one rare earth metal element in the second channel portion CL2 is less than the atomic percentage of the at least one rare earth metal element in the first channel portion.

[0104] In one example, the pre-annealing precursor stack structure 140 of the active layer SL is formed by a sputtering process, see the following description. Figures 2B to 2DIn the precursor stack structure 140 before annealing, the metal elements of the precursor layer 143 used to form the first channel protection layer PL1 include In, Ga, Zn, Sn and at least one rare earth metal element, the metal elements of the precursor layer 142 used to form the channel layer CL include In, Ga, Zn, and the precursor layer 141 used to form the second channel protection layer PL2 does not include any rare earth metal element. After the precursor stack structure 140 before annealing is subjected to an annealing process, a portion of the rare earth metal elements in the precursor layer 143 at least diffuse into the corresponding surface of the precursor layer 142. For example, a portion of the rare earth metal elements in the precursor layer 143 diffuses to a position between two opposite surfaces of the precursor layer 142 in the overlapping direction (for example, for Figure 1 Thus, in the formed channel layer CL, the first channel portion CL1 includes at least one rare earth metal element diffused from the precursor layer 143, while the second channel portion CL2 does not include any rare earth metal element.

[0105] For another example, a portion of the rare earth metal elements in the precursor layer 143 diffuses to the surface of the precursor layer 142 in the overlapping direction away from the precursor layer 143. In this way, the formed channel layer CL includes at least one rare earth metal element diffused from the precursor layer 143 over the entire thickness range in the stacking direction. That is, the first channel portion CL1 includes at least one rare earth metal element diffused from the precursor layer 143, and the second channel portion CL2 also includes at least one rare earth metal element diffused from the precursor layer 143.

[0106] For example, the channel layer CL has a bandgap Eg1, and the first channel protection layer PL1 has a bandgap Eg2. The absolute value of the bandgap Eg2 is greater than that of the bandgap Eg1, and the difference between the absolute values ​​of the bandgap Eg2 and the bandgap Eg1 is less than or equal to 1.5 eV.

[0107] For example, the second channel protection layer PL2 has an energy band gap Eg3 , the absolute value of which is greater than the absolute value of the energy band gap Eg1 , and the difference between the absolute value of the energy band gap Eg3 and the absolute value of the energy band gap Eg1 is less than or equal to 1.5 eV.

[0108] For example, the energy band gap Eg2 and the energy band gap Eg3 are each in the range of 3.2 eV to 3.6 eV.

[0109] For example, when the channel layer CL includes the first channel portion CL1 and the second channel portion CL2, the difference between the absolute value of the energy band gap of either the first channel portion CL1 or the second channel portion CL2 and the absolute value of the energy band gap Eg2 of the first channel protection layer PL1 is greater than zero and less than or equal to 1.5 eV.

[0110] Improving the crystallinity (or density) of the first channel protection layer PL1 and / or the second channel protection layer PL2 is beneficial for blocking back channel etching defects and undesirable impurity elements from diffusing into the channel layer. When the first channel protection layer PL1 and / or the second channel protection layer PL2 of the metal oxide semiconductor material are deposited using a sputtering process, factors such as the temperature of the substrate, the oxygen partial pressure in the deposition chamber, and the deposition process can affect the crystallinity of the first channel protection layer PL1 and / or the second channel protection layer PL2. The temperature of the substrate is one of the main influencing factors. The higher the temperature, the easier it is to form a first channel protection layer PL1 and / or a second channel protection layer PL2 with high crystallinity. In addition, the crystallinity of the metal oxide semiconductor layer also depends to a certain extent on the atomic ratio of a certain metal element therein. In order to obtain a metal oxide semiconductor material layer that is easier to crystallize and has good crystallinity, it is more preferred that the atomic percentage of a certain metal element relative to all metal elements is greater than or equal to 40at%.

[0111] For example, in the first channel protection layer PL1 and / or the second channel protection layer PL2 , the atomic percentage of at least one of the non-rare earth metal elements relative to all metal elements is greater than or equal to 40 at %.

[0112] For example, in the first channel protection layer PL1 and / or the second channel protection layer PL2 , the number of atoms of one of the non-rare earth metal elements is greater than the total number of atoms of the remaining metal elements.

[0113] This is more conducive to obtaining the first channel protection layer PL1 and / or the second channel protection layer PL2 with good crystallinity.

[0114] For example, in the first channel protection layer PL1 and / or the second channel protection layer PL2 , the number of atoms of Zn is greater than the total number of atoms of other metal elements.

[0115] For another example, in the first channel protection layer PL1 and / or the second channel protection layer PL2 , the number of atoms of Sn is greater than the total number of atoms of other metal elements.

[0116] In this way, the first channel protection layer PL1 and / or the second channel protection layer PL2 can be easily formed with good crystallinity and low carrier concentration.

[0117] For example, in the first channel protection layer PL1 and / or the second channel protection layer PL2, the ratio of the sum of the number of atoms of at least one rare earth metal element to the sum of the number of atoms of non-rare earth metal elements is in the range of 0.15 to 40%, preferably, in the range of 0.1% to 5%.

[0118] For example, the carrier concentration of the first channel protection layer PL1 and / or the second channel protection layer PL2 is lower than the carrier concentration of the channel layer CL.

[0119] Thus, when the thin film transistor is working, due to the band gap difference, the first channel protection layer PL1 and / or the second channel protection layer PL2 has a lower carrier concentration, thereby reducing the probability of back channel defects and / or interface defects capturing carriers, thereby improving the electrical performance of the thin film transistor.

[0120] For example, the carrier concentration of the first channel protection layer PL1 and / or the second channel protection layer PL2 is in the range of 1×10 14 to 1×10 15 .

[0121] For example, the material of the first channel protection layer PL1 and / or the second channel protection layer PL2 is IGZMO, and the ratio of the number of atoms of each metal element is any one of the following: In:Ga:Zn=1:3:6 and Pr / (In+Ga+Zn)=0.1%~2%; In:Ga:Zn=0.5:4:4.5 and Pr / (In+Ga+Zn)=0.1%~2%; In:Ga:Zn=1:3:6 and Sm / (In+Ga+Zn)=0.1%~2%, In:Ga:Zn=1:4:4 and Sm / (In+Ga+Zn)=0.1%~2%, In :Ga:Zn=1:3:6 and (Pr+Sm) / (In+Ga+Zn)=0.1%~2%、In:Ga:Zn=1:4:4 and (Pr+Sm) / (In+Ga+Zn)=0.1%~2%、In:Ga:Zn=1:3:6 and (Pr+Sm) / (In+Ga+Zn)=0.1%~2%、In:Ga:Zn=1:4:4 and (Pr+Sm) / (In+Ga+Zn)=0.1%~2%、In:Ga:Zn=0.5:3:6.5 and (Pr+Sm) / (In+Ga+Zn)=0.1%~2%。Here, In:Ga:Zn represents the ratio of the number of atoms of the three non-rare earth metal elements In, Ga and Zn in this material. For example, In:Ga:Zn=1:3:6 means that in this material, the ratio of the number of atoms of the three non-rare earth metal elements In, Ga and Zn is 1:3:6. Pr / (In+Ga+Zn) means the ratio of the number of atoms of the only rare earth metal element Pr in this material to the sum of the number of atoms of the three non-rare earth metal elements In, Ga and Zn; Sm / (In+Ga+Zn) means the ratio of the number of atoms of the only rare earth metal element Sm in this material to the sum of the number of atoms of the three non-rare earth metal elements In, Ga and Zn; Pr+Sm / (In+Ga+Zn) means the ratio of the sum of the number of atoms of the rare earth metal elements Pr and Sm in this material to the sum of the number of atoms of the three non-rare earth metal elements In, Ga and Zn.

[0122] The channel layer CL has a first thickness in the stacking direction, the first channel protection layer has a second thickness in the stacking direction, the second channel protection layer has a third thickness in the stacking direction, and a ratio of either the second thickness or the third thickness to the first thickness is greater than or equal to 1.

[0123] For example, the thickness of the channel layer in the stacking direction is in the range of 1 nm to 50 nm.

[0124] For another example, in the stacking direction, the thickness of the channel layer is in a range of 5 nm to 20 nm.

[0125] For example, in the stacking direction, the thickness of the first channel protection layer PL1 and / or the second channel protection layer PL2 is in the range of 20 nm to 100 nm.

[0126] For another example, in the stacking direction, the thickness of the first channel protection layer PL1 and / or the second channel protection layer PL2 is in the range of 30 nm to 60 nm.

[0127] In this way, it is more advantageous for the first channel protection layer PL1 and / or the second channel protection layer PL2 to block back channel etching defects and undesired impurity elements from diffusing into the channel layer CL.

[0128] Figure 1 The thin film transistor TFT provided in the illustrated embodiment is a bottom gate thin film transistor. However, the embodiments of the present disclosure are not limited thereto. In another embodiment, the thin film transistor TFT may be a top gate thin film transistor.

[0129] Figures 2A to 2G A schematic diagram of a substrate structure corresponding to each step in a method for manufacturing a semiconductor substrate 10 according to an embodiment of the present disclosure is shown.

[0130] Below, see Figures 1 to 2G A method for manufacturing a semiconductor substrate 10 provided by at least one embodiment of the present disclosure is described.

[0131] See also Figure 2A , a base substrate 110 is provided, and a gate 170 and a gate insulating layer 160 are formed on the base substrate 110. The base substrate 110 may be a rigid substrate or a flexible substrate. For example, the material of the base substrate 110 may be glass, polyimide, polycarbonate, polyethylene, polyacrylate, or polyethylene terephthalate, etc. The gate insulating layer 160 may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiO2) or a stacked layer of silicon nitride (SiNx) and silicon oxide (SiO2).

[0132] See also Figures 2B to 2DA metal oxide semiconductor stack 140 is formed on the gate insulating layer 160 by a physical vapor deposition process, such as a sputtering process. The metal oxide semiconductor stack 140 includes a metal oxide semiconductor layer 141 , a metal oxide semiconductor layer 142 and a metal oxide semiconductor layer 143 .

[0133] Here, the material of the metal oxide semiconductor layer 142 is indium gallium zinc oxide (IGZO); the material of the metal oxide semiconductor layer 141 and the metal oxide semiconductor layer 143 is indium gallium zinc tin rare earth oxide (IGZMO) as an example for illustration. The embodiments of the present disclosure are not limited to this. In another example, the metal elements of the metal oxide semiconductor layer 141 and the metal oxide semiconductor layer 143 include at least two of In, Ga, Zn and Sn and at least one rare earth metal element. At least two of In, Ga, Zn and Sn include at least one of In and Zn. The material and crystallinity of the metal oxide semiconductor layer 142 are not specifically limited, as long as it has a large carrier concentration and mobility.

[0134] Here, the metal oxide semiconductor stack 140 includes a three-layer structure of a metal oxide semiconductor layer 141, a metal oxide semiconductor layer 142, and a metal oxide semiconductor layer 143. The embodiments of the present disclosure are not limited thereto. In other embodiments, the metal oxide semiconductor stack 140 may include only one of the metal oxide semiconductor layer 141 and the metal oxide semiconductor layer 143 and the metal oxide semiconductor layer 142, that is, the metal oxide semiconductor stack 140 is a two-layer structure. In other embodiments, the metal oxide semiconductor stack 140 may also include other metal oxide semiconductor layers, so it may be a 4-layer or more layer structure, as long as it includes at least one of the metal oxide semiconductor layer 141 and the metal oxide semiconductor layer 143 and the metal oxide semiconductor layer 142.

[0135] See also Figure 2B The metal oxide semiconductor layer 141 is deposited on the gate insulating layer 160 by a physical vapor deposition process (such as a sputtering process) using a first target. The metal oxide semiconductor layer 141 is a crystalline layer. The metal oxide semiconductor layer 141 serves as a precursor layer of the second channel protection layer PL2 in the active layer SL to be formed subsequently.

[0136] For example, the metal oxide semiconductor layer 141 has a low carrier concentration (e.g., the carrier concentration is 1×1014 - 1×1015) and a large bandgap (e.g., 3.2 eV to 3.6 eV). For example, the materials of the first target and the metal oxide semiconductor layer 141 are IGZMO, and the atomic ratio of each metal element is any of the following: In:Ga:Zn = 1:3:6 and Pr / (In + Ga + Zn) = 0.1% - 2%; In:Ga:Zn = 0.5:4:4.5 and Pr / (In + Ga + Zn) = 0.1% - 2%; In:Ga:Zn = 1:3:6 and Sm / (In + Ga + Zn) = 0.1% - 2%, In:Ga:Zn = 1:4:4 and Sm / (In + Ga + Zn) = 0.1% - 2%, In:Ga:Zn = 1:3:6 and (Pr + Sm) / (In + Ga + Zn) = 0.1% - 2%, In:Ga:Zn = 1:4:4 and (Pr + Sm) / (In + Ga + Zn) = 0.1% - 2%, In:Ga:Zn = 1:3:6 and (Pr + Sm) / (In + Ga + Zn) = 0.1% - 2%, In:Ga:Zn = 1:4:4 and (Pr + Sm) / (In + Ga + Zn) = 0.1% - 2%, In:Ga:Zn = 0.5:3:6.5 and (Pr + Sm) / (In + Ga + Zn) = 0.1% - 2%. Here, In:Ga:Zn represents the atomic ratio of the three non-rare-earth metal elements In, Ga, and Zn in this material. For example, In:Ga:Zn = 1:3:6 means that in this material, the atomic ratio of the three non-rare-earth metal elements In, Ga, and Zn is 1:3:6. Pr / (In + Ga + Zn) represents the ratio of the number of atoms of the only rare-earth metal element Pr in this material to the total number of atoms of the three non-rare-earth metal elements In, Ga, and Zn; Sm / (In + Ga + Zn) represents the ratio of the number of atoms of the only rare-earth metal element Sm in this material to the total number of atoms of the three non-rare-earth metal elements In, Ga, and Zn; Pr + Sm / (In + Ga + Zn) represents the ratio of the total number of atoms of the rare-earth metal elements Pr and Sm in this material to the total number of atoms of the three non-rare-earth metal elements In, Ga, and Zn.

[0137] See Figure 2C , the metal oxide semiconductor layer 142 is deposited on the metal oxide semiconductor layer 141 by a physical vapor deposition process (such as a sputtering process) using a second target. The metal oxide semiconductor layer 142 serves as a precursor layer for the channel layer CL in the active layer SL to be formed subsequently.

[0138] For example, the metal element of the metal oxide semiconductor layer 142 includes a material such as IGZMO. Here, there is no limitation on the crystal state of the metal oxide semiconductor layer 142. For example, the metal oxide semiconductor layer 142 is a crystal layer or an amorphous layer.

[0139] See also Figure 2D The third target is used to deposit a metal oxide semiconductor layer 143 on the metal oxide semiconductor layer 141 through a physical vapor deposition process (eg, a sputtering process). The metal oxide semiconductor layer 143 is a crystalline layer. The metal oxide semiconductor layer 143 serves as a precursor layer of the first channel protection layer PL1 in the active layer SL to be formed subsequently.

[0140] For example, the metal oxide semiconductor layer 143 has a low carrier concentration (e.g., the carrier concentration is 1×1014 - 1×1015) and a large bandgap (e.g., 3.2 eV - 3.6 eV). For example, the materials of the third target and the metal oxide semiconductor layer 141 are IGZMO, and the atomic ratio of each metal element is any of the following: In:Ga:Zn = 1:3:6 and Pr / (In + Ga + Zn) = 0.1% - 2%; In:Ga:Zn = 0.5:4:4.5 and Pr / (In + Ga + Zn) = 0.1% - 2%; In:Ga:Zn = 1:3:6 and Sm / (In + Ga + Zn) = 0.1% - 2%, In:Ga:Zn = 1:4:4 and Sm / (In + Ga + Zn) = 0.1% - 2%, In:Ga:Zn = 1:3:6 and (Pr + Sm) / (In + Ga + Zn) = 0.1% - 2%, In:Ga:Zn = 1:4:4 and (Pr + Sm) / (In + Ga + Zn) = 0.1% - 2%, In:Ga:Zn = 1:3:6 and (Pr + Sm) / (In + Ga + Zn) = 0.1% - 2%, In:Ga:Zn = 1:4:4 and (Pr + Sm) / (In + Ga + Zn) = 0.1% - 2%, In:Ga:Zn = 0.5:3:6.5 and (Pr + Sm) / (In + Ga + Zn) = 0.1% - 2%. Here, In:Ga:Zn represents the atomic ratio of the three non-rare earth metal elements In, Ga, and Zn in this material. For example, In:Ga:Zn = 1:3:6 means that in this material, the atomic ratio of the three non-rare earth metal elements In, Ga, and Zn is 1:3:6. Pr / (In + Ga + Zn) represents the ratio of the number of atoms of the only rare earth metal element Pr in this material to the total number of atoms of the three non-rare earth metal elements In, Ga, and Zn; Sm / (In + Ga + Zn) represents the ratio of the number of atoms of the only rare earth metal element Sm in this material to the total number of atoms of the three non-rare earth metal elements In, Ga, and Zn; Pr + Sm / (In + Ga + Zn) represents the ratio of the total number of atoms of the rare earth metal elements Pr and Sm in this material to the total number of atoms of the three non-rare earth metal elements In, Ga, and Zn. The material of the third target can be the same as or different from that of the first target.

[0141] Thus, the pre-annealing precursor stack structure 140 is formed.

[0142] See Figure 2E , and an annealing process and a patterning process are performed on the pre-annealing precursor stack structure 140 to form the active layer SL.

[0143] For example, the annealing process is a heat treatment performed in an air atmosphere at a temperature of 300° C. to 380° C. The heat treatment time is, for example, 30 minutes to 2 hours.

[0144] For example, performing a patterning process on the stacked structure 140 includes: coating a photoresist layer on the stacked structure 140; performing exposure and development on the photoresist layer to form a photoresist pattern P; using the photoresist pattern as a shield to wet-etch the semiconductor stack 140 to obtain the active layer SL. For example, the wet etching uses H2SO4+HNO3+H2O as an etching solution or uses HNO3+CH3COOH+H3PO4+H2O as an etching solution; and removing the photoresist pattern.

[0145] See also Figure 2F , forming a source electrode 181 and a drain electrode 182 on the base substrate 110 formed with the active layer SL by a wet etching process; and forming a passivation layer 150 on the base substrate 110 formed with the source electrode 181 and the drain electrode 182. The source electrode 181 and the drain electrode 182 are directly overlapped on the active layer SL, for example.

[0146] The source electrode 181 and the drain electrode 182 may include one or more of Au, Ag, Cu, Ni, Pt, Pd, Al, Mo, etc. The source electrode 181 and the drain electrode 182 may be a single-layer metal or a multi-layer metal.

[0147] See also Figure 2G , a resin layer 210 , a first electrode layer 220 , and a passivation layer 230 are sequentially formed on the passivation layer 150 .

[0148] Return to see Figure 1 , a through hole exposing the drain electrode 182 is formed in the insulating stack formed by the passivation layer 150, the resin layer 210 and the passivation layer 230; and then the second electrode layer 240 is formed, so that a part of the second electrode layer 240 is filled in the through hole and electrically connected to the drain electrode 182, and another part of the second electrode layer 240 overlaps with the first electrode layer 210 in the stacking direction. For example, the first electrode layer 220 serves as a common electrode, and the second electrode layer 210 serves as a pixel electrode for controlling the deflection of the liquid crystal material.

[0149] It is understandable that in Figure 1 In the illustrated embodiment, the semiconductor substrate 10 including the metal oxide TFT of the embodiment of the present disclosure is an array substrate of a liquid crystal display device. However, the semiconductor substrate provided by the embodiment of the present disclosure is not limited thereto. In another embodiment, the semiconductor substrate provided may be any one selected from the group consisting of an organic light emitting diode (OLED) array substrate, an electronic paper display substrate, a flexible transparent display substrate, a Micro-LED display substrate, a Mini-LED display substrate, and a substrate with a fingerprint recognition function.

[0150] At least one embodiment of the present disclosure provides an X-ray flat panel detector, comprising the thin film transistor provided by any of the above embodiments.

[0151] In this article, there are several points to note:

[0152] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0153] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is enlarged or reduced, that is, these drawings are not drawn according to the actual scale.

[0154] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0155] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A thin film transistor, comprising: A gate electrode, an active layer, a gate insulating layer located between the gate electrode and the active layer, and a source electrode and a drain electrode electrically connected to the active layer, wherein: The active layer includes a channel layer and at least one channel protection layer which are overlapped in a stacking direction, and the material of each of the channel layer and the at least one channel protection layer is a metal oxide semiconductor material. The at least one channel protection layer is a crystalline layer, and the metal element of the at least one channel protection layer includes a non-rare earth metal element, and the non-rare earth metal element includes In, Ga, Zn and Sn, Wherein, the at least one channel protection layer includes a first channel protection layer located on a side of the channel layer close to the source and the drain; the metal element of the first channel protection layer also includes at least one rare earth metal element, The channel layer includes a first channel portion adjacent to the first channel protection layer, the first channel portion includes at least a first surface of the channel layer directly contacting the first channel protection layer, the first channel portion includes at least one rare earth metal element that is the same as the at least one rare earth metal element in the first channel protection layer, and an absolute value of an energy band gap of the first channel portion is smaller than an absolute value of an energy band gap of the first channel protection layer, The channel layer also includes a second channel portion located on a side of the first channel portion away from the first channel protection layer in the stacking direction, and the absolute value of the energy band gap of the second channel portion is smaller than the absolute value of the energy band gap of the first channel portion, so that the first channel portion serves as a transition layer between the second channel portion and the first channel protection layer.

2. The thin film transistor according to claim 1, wherein: The second channel portion at least includes a second surface of the channel layer away from the first channel protection layer, and the second channel portion does not contain any rare earth metal element that is the same as the at least one rare earth metal element in the first channel protection layer.

3. The thin film transistor according to claim 1, wherein: The second channel portion includes at least a second surface of the channel layer away from the first channel protection layer, the second channel portion includes at least one rare earth metal element that is the same as the at least one rare earth metal element in the first channel protection layer and the first channel portion, An atomic percentage of the at least one rare earth metal element in the second channel portion is less than an atomic percentage of the at least one rare earth metal element in the first channel portion.

4. The thin film transistor according to any one of claims 1 to 3, wherein: The at least one channel protection layer is formed by depositing a target material.

5. The thin film transistor according to any one of claims 1 to 3, wherein: The metal elements of the channel layer include In, Ga and Zn.

6. The thin film transistor according to any one of claims 1 to 3, wherein: The at least one rare earth metal element of the first channel protection layer is selected from the group consisting of Pr, Ir, Tb and Sm.

7. The thin film transistor according to claim 6, wherein: The at least one rare earth metal element of the first channel protection layer includes two selected from the group consisting of Pr, Ir, Tb and Sm.

8. The thin film transistor according to claim 7, wherein: The at least one rare earth metal element of the first channel protection layer includes Pr and Sm.

9. The thin film transistor according to claim 2 or 3, wherein: The number of kinds of the at least one rare earth metal element of the first channel protection layer is greater than the number of kinds of the at least one rare earth metal element of at least one of the first surface and the second surface of the channel layer.

10. The thin film transistor according to claim 9, wherein: The at least one rare earth metal element of the first channel protection layer includes a first rare earth metal element and a second rare earth metal element different from each other, and the at least one rare earth metal element in the first channel portion includes the first rare earth metal element but does not include the second rare earth metal element.

11. The thin film transistor according to claim 10, wherein: The first rare earth metal element is Pr, and the second rare earth metal element is Sm.

12. The thin film transistor according to any one of claims 1 to 3, wherein: A difference between the absolute value of any one of the energy band gap of the first channel portion and the energy band gap of the second channel portion and the absolute value of the energy band gap of the first channel protection layer is greater than zero and less than or equal to 1.5 eV.

13. The thin film transistor according to any one of claims 1 to 3, wherein: In the at least one channel protection layer, the atomic percentage of at least one of the non-rare earth metal elements relative to all the metal elements is greater than or equal to 40 at %.

14. The thin film transistor according to claim 13, wherein: In the at least one channel protection layer, the number of atoms of one of the non-rare earth metal elements is greater than the total number of atoms of the remaining metal elements.

15. The thin film transistor according to claim 14, wherein: In the at least one channel protection layer, the one of the non-rare earth metal elements is Zn or Sn.

16. The thin film transistor according to any one of claims 1 to 3, wherein: In the at least one channel protection layer, a ratio of a sum of the number of atoms of the at least one rare earth metal element to a sum of the number of atoms of the non-rare earth metal element is in a range of 0.1% to 5%.

17. The thin film transistor according to any one of claims 1 to 3, wherein: The channel layer is a crystalline layer or an amorphous layer.

18. The thin film transistor according to any one of claims 1 to 3, wherein: In the metal oxide semiconductor material of at least one channel protection layer, the number of types of the non-rare earth metal elements is N, and the ratio of the number of atoms of any one of the non-rare earth metal elements to the total number of atoms of the other non-rare earth metal elements is greater than or equal to 1 / N.

19. The thin film transistor according to any one of claims 1 to 3, wherein: The at least one channel protection layer further includes a second channel protection layer located on a side of the channel layer away from the source and the drain.

20. The thin film transistor according to any one of claims 1 to 3, wherein: In the stacking direction, the thickness of the at least one channel protection layer is greater than or equal to the thickness of the channel layer.

21. The thin film transistor according to any one of claims 1 to 3, wherein: In the stacking direction, the thickness of the channel layer is in the range of 1 nm to 50 nm.

22. The thin film transistor according to claim 21, wherein: In the stacking direction, the thickness of the channel layer is in the range of 5 nm to 20 nm.

23. The thin film transistor according to any one of claims 1 to 3, wherein: In the stacking direction, a thickness of the at least one channel protection layer is in a range of 20 nm to 100 nm.

24. The thin film transistor according to claim 23, wherein: In the stacking direction, the at least one channel protection layer has a thickness in the range of 30 nm to 60 nm.

25. The thin film transistor according to any one of claims 1 to 3, wherein: The carrier concentration of the at least one channel protection layer is lower than the carrier concentration of the channel layer.

26. A thin film transistor, comprising: A gate electrode, a gate insulating layer, an active layer, and a source electrode and a drain electrode electrically connected to the active layer, wherein: The active layer includes a channel layer and at least one channel protection layer which are overlapped in a stacking direction, and the materials of the channel layer and the at least one channel protection layer are both metal oxide semiconductor materials. The at least one channel protection layer is a crystalline layer, and the metal element of the at least one channel protection layer includes a non-rare earth metal element and at least one rare earth metal element, wherein the non-rare earth metal element includes two or three selected from the group consisting of In, Ga, Zn and Sn, and the two or three selected from the group consisting of In, Ga, Zn and Sn include at least one of In and Zn, The at least one channel protection layer includes a first channel protection layer located on a side of the channel layer close to the source and the drain; the metal element of the first channel protection layer also includes at least one rare earth metal element, The channel layer includes a first channel portion adjacent to the first channel protection layer, the first channel portion includes at least a first surface of the channel layer directly contacting the first channel protection layer, the first channel portion includes at least one rare earth metal element that is the same as the at least one rare earth metal element in the first channel protection layer, and an absolute value of an energy band gap of the first channel portion is smaller than an absolute value of an energy band gap of the first channel protection layer, The channel layer also includes a second channel portion located on a side of the first channel portion away from the first channel protection layer in the stacking direction, and the absolute value of the energy band gap of the second channel portion is smaller than the absolute value of the energy band gap of the first channel portion, so that the first channel portion serves as a transition layer between the second channel portion and the first channel protection layer.

27. A semiconductor substrate, comprising a base substrate and a thin film transistor located on the base substrate, wherein: The thin film transistor is the thin film transistor according to any one of claims 1 to 26.

28. An X-ray flat panel detector comprising the thin film transistor according to any one of claims 1 to 26.

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