A FPGA design method capable of realizing parallel wiring

Abstract

The present application discloses an FPGA design method capable of realizing parallel wiring, and relates to the field of FPGA. The method divides the programmable logic resources inside the FPGA into a normal layout area and a reserved blank area. During layout, the netlist input by the user is laid out in each normal layout area inside the FPGA to obtain an initial layout result. The original wire net whose endpoints are distributed in at least two different normal layout areas can be split into a plurality of wire nets to be wired corresponding to different normal layout areas by using a pair of predetermined connection ends in the reserved blank area. Thus, each area has its own netlist and wiring resource map. Therefore, during parallel wiring, the wiring results in each area are independent of each other and do not interfere with each other. The results can be directly merged globally after the wiring is performed separately, and there is no need to resolve conflicts in different areas. The operation results are not affected by the netlist processing order and the design environment, and the design efficiency can be effectively improved.

Description

Technical Field

[0001] The invention relates to the field of FPGA, and in particular to an FPGA design method capable of realizing parallel wiring. Background Art

[0002] FPGA routing is the process of connecting the occupied logic units using the device's programmable interconnection resources after the chip is laid out. During FPGA routing, it is generally necessary to abstract the programmable logic resources on the FPGA, including the interconnection resources, into a wiring diagram. The wiring diagram has representations of all underlying modules, architectures, and interconnection resources. Then, a signal to be processed is selected in a predetermined order, and the source and drain module locations related to the signal are found according to the chip layout results. The wiring diagram is searched using a wiring algorithm such as a negotiated pathfinding algorithm to find unoccupied resources to obtain a winding path from the source to the drain. If no path with completely unoccupied resources is found, the winding path of this signal can be forcibly used to use resources that have been occupied by other signals. At this time, the resource is repeatedly occupied by multiple signals to form a conflict, and the conflict needs to be resolved later. The winding path used by this signal is recorded on the wiring diagram, and the corresponding resource is marked as occupied. The above process is repeated until all signals have a winding path, and then the signals with duplication or conflict are rewound to resolve the conflict until there is no conflict in which the winding resources are reused by multiple signals to obtain the wiring result.

[0003] As the scale of FPGAs continues to increase significantly, the scale of wiring diagrams increases (that is, the device capacity is large), and the utilization rate of FPGAs also gradually increases. This leads to an accumulation of possible paths that need to be considered when searching for paths during the wiring process, a large increase in the search space, and greater difficulty in completely resolving conflicts, making the wiring process run too long. Wiring takes up a lot of running time in the FPGA application development process, and the quality of wiring efficiency directly affects the application development efficiency and user experience.

[0004] In order to improve the efficiency of wiring and reduce the wiring time, multi-core and multi-core computing platforms are often used to reduce the running time of the wiring process through parallelization. That is, the global wiring problem is divided into multiple sub-problems, and each sub-problem is processed in parallel by the multi-core platform before the results are merged into the global wiring diagram. However, in actual operation, it is found that the effect of this approach is not ideal. There are two problems: (1) When the wiring of each sub-problem is completed and then merged, new conflicts often occur due to the influence of the signal across the sub-problem. Further re-winding is required to resolve the conflict, resulting in the efficiency improvement of multi-core parallelism being lower than the theoretical expectation. For example, the use of 4-core parallelism can actually only achieve the effect of halving the running time, which is far from achieving the theoretical effect of 1 / 4 of the running time. (2) Each sub-problem runs independently, but due to the configuration of the software running platform and the load, the winding time used by each core to complete each sub-problem is uncertain, which makes it difficult to keep the winding order consistent. When routing a specific signal, different paths will be obtained due to different resource occupancy on the wiring diagram. Therefore, changing the winding order of each network will directly change the final wiring result. As a result, different conflict points will appear when global routing is executed multiple times for the same routing problem. After the conflict is resolved, the final routing results will also be different. This is difficult to accept in engineering applications, especially as it will cause difficulties in debugging. One approach is to force the winding order of each network, but in this way, in order to comply with the specific winding order, each core often needs to wait for each other, which increases the running time and fails to achieve true multi-core parallelism, further reducing the efficiency of multi-core parallelism. Summary of the invention

[0005] In view of the above problems and technical requirements, the inventors have proposed an FPGA design method that can realize parallel wiring. The technical solution of the present invention is as follows:

[0006] An FPGA design method capable of realizing parallel wiring, the method comprising:

[0007] The user input netlist is placed in each normal placement area inside the FPGA to obtain the initial placement result. The programmable logic resources inside the FPGA are divided into a normal placement area and a reserved blank area. Every two adjacent normal placement areas are separated by a reserved blank area.

[0008] Determine the positions of all the wire net endpoints in each original wire net according to the initial layout result of the FPGA, where the wire net endpoints include a source terminal and a plurality of drain terminals connected thereto;

[0009] The original wire nets with all the wire net endpoints located in the same normal layout area are directly mapped to the normal layout area as the wire net to be routed;

[0010] An original wire net whose wire net endpoints are distributed in at least two different normal layout areas is split into a plurality of wire nets to be routed corresponding to different normal layout areas by using a reserved blank area, each wire net to be routed includes a connection relationship between newly added wire net endpoints formed by a portion of the original wire net in the current normal layout area and a predetermined connection end of a reserved blank area at a boundary of the current normal layout area, and the wire nets to be routed corresponding to each two adjacent normal layout areas obtained by splitting an original wire net are respectively connected to a pair of predetermined connection ends of a reserved blank area between the two normal layout areas;

[0011] The to-be-wired nets corresponding to each normal layout area and the predetermined connection terminals to be connected in each reserved blank area are processed in parallel to obtain the wiring results in each normal layout area and each reserved blank area respectively, and the wiring results of each normal layout area and each reserved blank area are merged to obtain the global wiring result corresponding to the FPGA, thus completing the design of the FPGA.

[0012] A further technical solution is that a pair of predetermined connection ends in the reserved blank area belong to connection ends of a same switch box in the reserved blank area, and the pair of predetermined connection ends are connected through an internal path of the switch box.

[0013] A further technical solution is that a pair of predetermined connection ends of the reserved blank area belong to connection ends of different switch boxes in the reserved blank area, and the pair of predetermined connection ends are connected through an internal path of the switch box and an external path between different switch boxes.

[0014] A further technical solution is that the reserved blank areas are arranged in a matrix along the horizontal direction and / or the vertical direction inside the FPGA.

[0015] A further technical solution is that the reserved blank areas arranged along the horizontal direction and the vertical direction are connected to form a rectangular frame, and the normal layout area inside the rectangular frame is used to realize the predetermined IP node.

[0016] A further technical solution is that there is a reserved blank area that overlaps with the clock domain.

[0017] Its further technical solution is that the FPGA is a multi-die structure, and there is a reserved blank area that overlaps with the cross-die connection area between two adjacent FPGA dies. The cross-die connection area includes the connection point lead-out terminals in the two FPGA dies and the cross-die connections in the silicon connection layer for connecting the connection point lead-out terminals of the two FPGA dies.

[0018] Its further technical solution is to perform layout planning on the user input netlist and divide the programmable logic resources inside the FPGA into several normal layout areas and reserved blank areas according to the layout planning results, and the number of connection terminals contained in each reserved blank area is greater than the number of signals crossing the reserved blank area.

[0019] Its further technical solution is that the method further comprises:

[0020] After processing all original nets into corresponding nets to be routed and obtaining nets to be routed corresponding to each normal layout area, the local netlist corresponding to each normal layout area is updated, and the layout of the corresponding normal layout area is optimized according to the local netlist to obtain the final global layout result.

[0021] A further technical solution is to use the normal layout area where the source end in the original network is located as the first-level normal layout area, and the adjacent normal layout area of ​​the i-th level normal layout area in the direction from the source end to the corresponding drain end in the original network as the i+1-th level normal layout area, where i is a parameter and the initial value of i is 1;

[0022] Then, a predetermined connection terminal in the reserved blank area between the i-th level normal layout area and the i+1-th level normal layout area, which is connected to the i-th level normal layout area, is formed as a newly added drain terminal in the i-th level normal layout area, and another corresponding predetermined connection terminal connected to the i+1-th level normal layout area is formed as a newly added source terminal in the i+1-th level normal layout area. The source terminals in each level of the normal layout area are connected to and point to all the drain terminals in the current normal layout area.

[0023] A further technical solution is that when determining two predetermined connection ends of the reserved blank area between the i-th level normal layout area and the (i+1)-th level normal layout area:

[0024] Determine two predetermined connection ends respectively based on the cross-area connection line crossing the reserved blank area;

[0025] Alternatively, a predetermined connection terminal formed as a newly added drain terminal in the i-th level normal layout area is determined based on the source terminal in the i-th level normal layout area, and another predetermined connection terminal formed as a newly added source terminal in the (i+1)-th level normal layout area is determined based on the reference drain terminal in the direction where the source terminal in the i-th level normal layout area is located;

[0026] Alternatively, a predetermined connection end is determined first, and a connection end closest to the determined predetermined connection end is used as another predetermined connection end;

[0027] Alternatively, a predetermined connection terminal is determined first, and another predetermined connection terminal is determined by using the determined predetermined connection terminal in combination with a source terminal in the i-th level normal layout area and / or a reference drain terminal in the direction thereof;

[0028] The reference drain terminal in the direction of the source terminal in the i-th level normal layout area includes the drain terminal in the first level normal layout area closest to the i-th level normal layout area, or the drain terminals in all the subsequent level normal layout areas.

[0029] A further technical solution is to determine two predetermined connection ends based on the cross-area connection crossing the reserved blank area, including:

[0030] When there are multiple cross-region connection lines, for all connection terminals connected between the reserved blank area and the i-th level normal layout area, the connection terminals closest to each cross-region connection line are respectively determined as candidate connection terminals, and the candidate connection terminal closest to the source terminal in the i-th level normal layout area is used as a predetermined connection terminal to form a newly added drain terminal in the i-th level normal layout area; for all connection terminals connected between the reserved blank area and the i+1-th level normal layout area, the connection terminals closest to each cross-region connection line are respectively determined as candidate connection terminals, and the candidate connection terminal with the smallest total distance to all reference drain terminals or the shortest maximum distance is used as a predetermined connection terminal to form a newly added source terminal in the i+1-th level normal layout area;

[0031] When there is one cross-region connection line, for all connection terminals connected to the reserved blank area and the i-th level normal layout area, the connection terminal closest to the cross-region connection line is determined as a predetermined connection terminal to form a newly added drain terminal in the i-th level normal layout area; for all connection terminals connected to the reserved blank area and the i+1-th level normal layout area, the connection terminal closest to the cross-region connection line is determined as a predetermined connection terminal to form a newly added source terminal in the i+1-th level normal layout area.

[0032] A further technical solution is that the cross-region connection crossing the reserved blank region includes the connection between the source terminal in the i-th level normal layout region and each reference drain terminal in the direction thereof.

[0033] A further technical solution is that the cross-region connection line crossing the reserved blank region includes a connection line between a source terminal in the i-th level normal layout region and a center of gravity point formed by a reference drain terminal in the direction thereof.

[0034] A further technical solution is that the cross-area connection crossing the reserved blank area includes a connection between a source terminal in the i-th level normal layout area and a predetermined reference drain terminal among the reference drain terminals in the direction thereof, and the predetermined reference drain terminal is a reference drain terminal that is closest to and / or farthest from the source terminal in the i-th level normal layout area among all the reference drain terminals.

[0035] A further technical solution is that the cross-area connection crossing the reserved blank area is an edge crossing the reserved blank area in a minimum spanning tree formed by sequentially connecting all the network endpoints inside the original network through a minimum spanning tree algorithm.

[0036] A further technical solution is to determine another predetermined connection terminal formed as a newly added source terminal in the (i+1)th level normal layout area based on a reference drain terminal in the direction where the source terminal in the i-th level normal layout area is located, including:

[0037] For all connection terminals connected to the reserved blank area and the i+1th level normal layout area, the connection terminal with the smallest total distance to all reference drain terminals or the shortest maximum distance is formed as a predetermined connection terminal as a newly added source terminal in the i+1th level normal layout area.

[0038] A further technical solution is to determine another predetermined connection terminal formed as a newly added source terminal in the (i+1)th level normal layout area based on a reference drain terminal in the direction where the source terminal in the i-th level normal layout area is located, including:

[0039] A Steiner tree is formed by all reference drain terminals, and the connection terminal closest to a predetermined Steiner node in the formed Steiner tree among all connection terminals connecting the reserved blank area with the i+1th level normal layout area is used as a predetermined connection terminal to form a newly added source terminal in the i+1th level normal layout area.

[0040] The beneficial technical effects of the present invention are:

[0041] The present application discloses an FPGA design method capable of realizing parallel wiring. The method divides the programmable logic resources inside the FPGA into a normal layout area and a reserved blank area. During layout, the netlist input by the user is laid out in each normal layout area inside the FPGA to obtain an initial layout result, and instances to be laid out are not placed in the reserved blank area. The original wire net whose endpoints are distributed in at least two different normal layout areas can be split into a plurality of wire nets to be wired corresponding to different normal layout areas by using a pair of predetermined connection ends in the reserved blank area. Thus, each area has its own netlist and wiring resource map. Therefore, during parallel wiring, the wiring results in each area are independent of each other and do not interfere with each other. After the wiring is performed separately, the results can be directly merged globally without conflict resolution for different areas. The operation result is predictable and is not affected by the netlist processing order and the design environment. The method is suitable for parallel processing and wiring, and can effectively improve the wiring efficiency and obtain the wiring result. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a method flow chart of the FPGA design method capable of realizing parallel wiring of the present application.

[0043] Figure 2 It is a schematic diagram of dividing the programmable logic resources inside the FPGA in this application into a normal layout area and a reserved blank area.

[0044] Figure 3 It is a schematic diagram of the splitting of the original wire network during the execution of the method of the present application. DETAILED DESCRIPTION

[0045] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings.

[0046] This application discloses a FPGA design method that can realize parallel wiring. The method includes the following steps. Please refer to Figure 1 The flowchart shown:

[0047] Step 1: Place the user input netlist in each normal layout area inside the FPGA to obtain the initial layout result. The programmable logic resources inside the FPGA are divided into a normal layout area and a reserved blank area. Every two adjacent normal layout areas are separated by a reserved blank area.

[0048] First, the user design is synthesized according to conventional methods to obtain a netlist, and then the binning or non-binning is determined according to the design process to obtain the user input netlist to be laid out. The user input netlist to be laid out is analyzed to determine the number of reserved blank areas, the exact location and size of each reserved blank area. Specifically, floorplanning is performed on the user input netlist and the location of the reserved blank area is determined based on the floorplanning results, thereby dividing the programmable logic resources inside the FPGA into several normal layout areas and reserved blank areas.

[0049] Existing FPGAs usually adopt a Column-Based architecture. Programmable logic resources are arranged in a column-based structure inside the FPGA. Programmable logic resources mainly include configurable functional modules and interconnection resource modules (INT). Configurable functional modules mainly include programmable logic units (CLBs or PLBs) and input and output ports (IOBs), and sometimes also include some other functional modules, such as BRAM, DSP, PC, etc. These configurable functional modules have an interconnection resource module (INT) with the same structure distributed around the configurable functional module. The horizontal or vertical connections between the configurable functional modules are connected via the INT module. Figure 2 The types and relative sizes of different configurable functional modules are not shown, and only the boxes are used to illustrate their matrix arrangement structure and the interconnection relationship between them through INT. The reserved blank area can be located at any suitable place inside the FPGA as needed. A typical approach is that the reserved blank area is arranged in a matrix along the horizontal direction and / or vertical direction inside the FPGA, such as Figure 2 For example, a reserved blank area forms a vertical area inside the FPGA and occupies two rows of programmable logic resources. When selecting a specific location, an embodiment provides a method in which a reserved blank area overlaps with the clock domain.

[0050] In another typical application, the reserved blank areas arranged along the horizontal and vertical directions are connected to form a rectangular border, and the normal layout area inside the rectangular border is used to implement a predetermined IP node, that is, there is a normal layout area inside the FPGA, and all boundaries are provided with reserved blank areas, that is, a normal layout area isolated from the external normal layout area is circled out by the reserved blank area inside the FPGA, and the internal normal layout area is used to implement a predetermined IP node, and is customized for the predetermined IP node in combination with the method provided in the present application. The wire network to connect this predetermined IP node must pass through the reserved blank area, so the performance of the predetermined IP node can be ensured to be stable, because its wiring in the internal normal layout area can remain unchanged.

[0051] The FPGA in this application can be a conventional single-die structure or a multi-die structure. In this case, there is a reserved blank area in the FPGA that overlaps with the cross-die connection area between two adjacent FPGA dies. The cross-die connection area includes the connection point lead-out terminals in the two FPGA dies and the cross-die connection wires in the silicon connection layer for connecting the connection point lead-out terminals of the two FPGA dies. The reserved blank area occupies resources in the silicon connection layer and is connected to different FPGA dies. In this scenario, each FPGA die can also be divided into a reserved blank area according to the above method.

[0052] The programmable logic resources in each reserved blank area and the programmable logic resources in the normal layout area have conventional programmable logic resources, including at least interconnection resources such as switch boxes, but the reserved blank area is not used to place the unit instance to be laid out, and is only reserved for cross-area connection. Each reserved blank area provides a number of input terminals and output terminals to the outside for connection with the programmable logic resources in the normal layout area, and different input terminals and output terminals in the reserved blank area can be connected using the programmable logic resources in the reserved blank area. After the layout is completed, the layout position of each unit instance to be laid out can be determined, so that the number of cross-area signals that cross each reserved blank area to connect different normal layout areas can be determined. A pair of connection terminals formed by an input terminal and an output terminal in the reserved blank area is used to realize a group of signals that cross the reserved blank, so the number of pairs of connection terminals contained in each reserved blank area needs to be greater than the number of signals that cross the reserved blank area. The number of pairs of connection terminals contained in the reserved blank area is determined by the programmable logic resources in the reserved blank area, and can actually be considered to be determined by the size of the reserved blank area. Therefore, after layout, if the number of pairs of connection terminals provided by the reserved blank area cannot meet the number of cross-area signals, it is necessary to increase the reserved blank area to include more programmable logic resources to provide more input terminals and output terminals, readjust the area division of the normal layout area and the reserved blank area, and then re-layout until the number of pairs of connection terminals contained in all reserved blank areas is greater than the number of signals crossing the reserved blank area, and then obtain the initial layout result. The larger the reserved blank area, the more input terminals and output terminals provided to the outside, and the easier the subsequent winding, but it will cause the layout area to become smaller. Generally, the width of the reserved blank area is about 1 to 3 columns of switch boxes.

[0053] The sizes of different normal layout areas and the types and / or quantities of programmable logic resources contained therein are the same or different, and the sizes of different reserved blank areas and the types and / or quantities of programmable logic resources contained therein are the same or different.

[0054] Step 2: Determine the positions of all the endpoints of each original net according to the initial layout result of the FPGA. The net endpoints include the source and several drains connected to it. This not only determines in which normal layout area each net endpoint is located, but also determines which specific programmable logic resource in the normal layout area it is located. The original net that needs to be routed may be completely located in one normal layout area, or it may span multiple normal layout areas.

[0055] Step 3: All the original nets whose endpoints are located in the same normal layout area are directly mapped to the normal layout area as the net to be routed. For example, please refer to Figure 3, the source terminal S11 of the original line net Net1 and the drain terminals T11, T12 and T13 connected thereto are all located in the normal layout area 1, so the original line net Net1 is directly used as the line to be wired and corresponds to the normal layout area 1.

[0056] Figure 3 Relative to Figure 2 The structure of programmable logic resources is simplified, and the connection relationship between programmable logic resources is omitted. The inside of FPGA is divided into three reserved blank areas and four normal layout areas. Every two adjacent normal layout areas are separated by a reserved blank area.

[0057] Step 4, splitting the original wire net whose wire net endpoints are distributed in at least two different normal layout areas into several wire nets to be routed corresponding to different normal layout areas using the reserved blank area, each wire net to be routed includes the part of the original wire net in the current normal layout area and the connection relationship between the newly added wire net endpoints formed by the predetermined connection ends of the reserved blank area at the boundary of the current normal layout area.

[0058] The portion of the original net in the current normal layout area may include the net endpoints in the original net or may not include the net endpoints in the original net, for example Figure 3 , the source terminal S21 of the original network Net2 is connected to the drain terminals T21, T22, T23 and T24 respectively. The original network Net2 includes the source terminal S21 and the drain terminal T21 in the normal layout area 1, but does not include any original network endpoints in the normal layout area 2, includes the original drain terminals T23 and T24 in the normal layout area 3, and includes the original drain terminal T22 in the normal layout area 4.

[0059] The portion of the original network in the current normal layout area at least includes a signal path of the original network in the normal layout area. The signal path can be directly a connection between different network endpoints in the original network, such as Figure 3 In the figure, the portion of the original network Net2 in the normal layout area 1 also includes the signal path between the source terminal S21 and the drain terminal T21, which is directly the connection between S21 and T21 in the original network Net2. Alternatively, the signal path is not a connection in the original network, but reflects the transmission direction of the connection of the original network in the normal layout area. The reflection here does not necessarily mean that the transmission direction is exactly the same, but only needs to be within the acceptable straight line angle range. For example Figure 3In the figure, the dotted lines show the connections between S21 and T22, T23 and T24 in the original network. The signal path of the original network Net2 in the normal layout area 2 is the signal path from S2 to S3. This signal path is not a connection in the original network, but the transmission direction of the connection of the original network Net2 in the normal layout area 2 is from the normal layout area 1 to the normal layout area 3, and the signal path from S2 to S3 also reflects this transmission direction. Similarly, in the normal layout area 3, although the signal path from S23 to T24 is not a connection in the original network Net2, the transmission direction from S23 to T24 is the same as the transmission direction from S21 to S24. The same applies to the others.

[0060] For an original wire network to be split, when the predetermined connection end of the reserved blank area forms a newly added wire network endpoint of the original wire network, a set of source ends and target points are actually inserted, and the input end of the predetermined connection end of the reserved blank area forms a new drain end in a normal layout area, and the corresponding other output end forms a new source end in another normal layout area. In order to reflect the transmission path, the application takes the normal layout area where the source end in the original wire network is located as the first-level normal layout area, and the adjacent normal layout area of ​​the i-th level normal layout area in the direction from the source end to the corresponding drain end in the original wire network as the i+1-th level normal layout area, i is a parameter and the starting value of i is 1, so that each newly added wire network endpoint can be determined outward in sequence starting from the first-level normal layout area where the source end in the original wire network is located. Then, a predetermined connection terminal connected to the i-th level normal layout area in the reserved blank area between the i-th level normal layout area and the i+1-th level normal layout area is used as an input terminal to form a newly added drain terminal in the i-th level normal layout area, and another corresponding predetermined connection terminal connected to the i+1-th level normal layout area is used as an output terminal to form a newly added source terminal in the i+1-th level normal layout area. The source terminals in each level of normal layout area are connected and point to all drain terminals in the current normal layout area. For example, Figure 3 In the example, normal layout areas 1 to 4 are respectively the first to fourth level normal layout areas, and an input end of the reserved blank area 1 between normal layout area 1 and normal layout area 2 is used as the newly added drain end T25 of normal layout area 1, and the output end corresponding to T25 is used as the newly added source end S22 of normal layout area 2. T25 is connected and points to S22 through the programmable logic resources in the reserved blank area 1 to form a pair of predetermined connection ends. The source end S21 in the normal layout area 1 points to the newly added drain end T25, and the source end S22 in the normal layout area 2 points to the drain end in the normal layout area. In general, only a group of newly added source and drain ends are formed by using the predetermined connection ends at the reserved blank area across the original line network, but multiple groups can actually be formed. For example Figure 3In the example, for the original line net Net2, only a set of newly added source and drain terminals (T25 / S22) are inserted between the normal layout area 1 and the normal layout area 2, but in practice, another set of newly added source and drain terminals can be inserted for the original line net Net2 between the normal layout area 1 and the normal layout area 2. However, this may result in insufficient input / output terminals in the reserved blank area, or increase wiring complexity, so this application will only take the example of forming a set of newly added source and drain terminals across the reserved blank area of ​​the original line net for explanation.

[0061] It can be seen that when a new line network endpoint is inserted into an original line network using the reserved blank area, a pair of predetermined connection ends in the reserved blank area actually needs to be occupied. One implementation method is that the pair of predetermined connection ends in the reserved blank area belong to the connection ends of the same switch box in the reserved blank area, and the pair of predetermined connection ends are connected through the internal path of the switch box. Another implementation method is that the pair of predetermined connection ends in the reserved blank area belong to the connection ends of different switch boxes in the reserved blank area, and the pair of predetermined connection ends are connected through the internal path of the switch box and the external path between different switch boxes.

[0062] In addition, since an original network often occupies a pair of predetermined connection terminals in the reserved blank area when it is split, and a reserved blank area includes a certain number of input terminals and output terminals, different input terminals and output terminals can be connected to form multiple pairs of different predetermined connection terminals by utilizing the programmable logic resources in the reserved blank area. Therefore, a reserved blank area is used to implement a newly added network endpoint of an original network, or a reserved blank area is used to implement newly added network endpoints of multiple original networks at the same time, and different original networks occupy different pairs of predetermined connection terminals in the reserved blank area.

[0063] Since the reserved blank area includes a number of input terminals and output terminals and can form multiple pairs of different predetermined connection terminals, when inserting a newly added line network endpoint for an original line network, it is necessary to determine which pair of predetermined connection terminals to select. The present application introduces the method of determining the two predetermined connection terminals of the reserved blank area between the i-th level normal layout area and the i+1-th level normal layout area according to different situations as follows:

[0064] 1. Two predetermined connection ends are determined based on the cross-area connection across the reserved blank area. The cross-area connection in this case can have multiple meanings:

[0065] (1) The cross-region connection line crossing the reserved blank area includes the connection lines between the source terminal in the i-th level normal layout area and each reference drain terminal in the direction thereof. The reference drain terminal in the direction where the source terminal in the i-th level normal layout area is located includes the drain terminal in the first level normal layout area closest to the i-th level normal layout area, or the drain terminals in all the normal layout areas of the subsequent level.

[0066] The first level normal layout area closest to the i-th level normal layout area is not necessarily the i+1-th level normal layout area, but refers to the normal layout area that contains the drain end in the original line network in the subsequent stage of the i-th level normal layout area and is closest to the i-th level normal layout area. This is because the i+1-th level normal layout area does not necessarily contain the drain end in the original line network. For example, for Figure 3 For example, when i=1, the next level of normal layout area 1, namely normal layout area 2, does not include the drain terminal in the original network. At this time, normal layout area 3 is the normal layout area that includes the drain terminal in the original network and is closest to the i-th level normal layout area.

[0067] Only the drain terminal in the original line net in the nearest level normal layout area can be used as the reference drain terminal in the direction, or the drain terminal in the original line net in the nearest multi-level normal layout area can be used as the reference drain terminal in the direction, or the drain terminal in the original line net in all multi-level normal layout areas of the subsequent stage can be used as the reference drain terminal in the direction. For example, when i=1, only T23 and T24 in normal layout area 3 can be used as the reference drain terminal in the direction. T23 and T24 in normal layout area 3 and T22 in normal layout area 4 can also be used as the reference drain terminal in the direction.

[0068] In this case, the number of cross-region connection lines crossing the reserved blank area is determined by the number of reference drain terminals in the direction of the source terminals in the i-th level normal layout area, so there may be one or more cross-region connection lines.

[0069] (2) The cross-region connection line crossing the reserved blank area includes the connection line between the source terminal in the i-th level normal layout area and the center of gravity formed by the reference drain terminal in the direction thereof. As described above, no matter there is one or more reference drain terminals in the direction thereof, the center of gravity of these reference drain terminals is unique. Therefore, in this case, there is generally only one cross-region connection line.

[0070] (3) The cross-region connection line across the reserved blank area includes a connection line between a source terminal in the i-th level normal layout area and a predetermined reference drain terminal among the reference drain terminals in the direction thereof. The reference drain terminal in the direction of the source terminal in the i-th level normal layout area is as described above, and the predetermined reference drain terminal is a reference drain terminal selected therefrom. More commonly, the predetermined reference drain terminal is the reference drain terminal that is closest and / or farthest from the source terminal in the i-th level normal layout area among all the reference drain terminals. Depending on the number of the selected predetermined reference drain terminals, in this case, there may be one or more cross-region connection lines.

[0071] (4) The cross-region connection that crosses the reserved blank area is an edge that crosses the reserved blank area in the minimum spanning tree formed by connecting all the network endpoints in the original network through the minimum spanning tree algorithm. Common minimum spanning tree algorithms include Prim's algorithm and Kruskal's algorithm. In this case, there is generally only one cross-region connection. For example, for the original network Net2, the order of the network endpoints in the minimum spanning tree formed by connecting the network endpoints in sequence through the minimum spanning tree algorithm is S21, T21, T24, T23, T22. Then the cross-region connection that crosses the reserved blank area 1 in the minimum spanning tree is the edge formed between T21 and T24.

[0072] As described above, in different situations, there may be one or more cross-region connection lines crossing a reserved blank area. According to the number of cross-region connection lines, the method of using the cross-region connection lines to determine two predetermined connection ends is introduced as follows:

[0073] When there is one cross-region connection line, for all connection terminals connected between the reserved blank area and the i-th level normal layout area, the connection terminal closest to the cross-region connection line is determined as a predetermined connection terminal to form a newly added drain terminal in the i-th level normal layout area. For all connection terminals connected between the reserved blank area and the i+1-th level normal layout area, the connection terminal closest to the cross-region connection line is determined as a predetermined connection terminal to form a newly added source terminal in the i+1-th level normal layout area.

[0074] When there are multiple cross-region connection lines, for all connection terminals connected between the reserved blank area and the i-th level normal layout area, the connection terminals closest to each cross-region connection line are determined as candidate connection terminals, and the candidate connection terminal closest to the source terminal in the i-th level normal layout area is used as a predetermined connection terminal to form a newly added drain terminal in the i-th level normal layout area. For all connection terminals connected between the reserved blank area and the i+1-th level normal layout area, the connection terminals closest to each cross-region connection line are determined as candidate connection terminals, and the candidate connection terminal with the smallest total distance or the shortest maximum distance to all reference drain terminals is used as a predetermined connection terminal to form a newly added source terminal in the i+1-th level normal layout area.

[0075] 2. A predetermined connection terminal formed as a newly added drain terminal in the i-th level normal layout area is determined based on the source terminal in the i-th level normal layout area. Another predetermined connection terminal formed as a newly added source terminal in the (i+1)-th level normal layout area is determined based on the reference drain terminal in the direction where the source terminal in the i-th level normal layout area is located. The meaning of the reference drain terminal in the direction where the source terminal in the i-th level normal layout area is as above.

[0076] When a predetermined connection terminal is determined to be formed by a source terminal in the i-th level normal layout area as a drain terminal newly added in the i-th level normal layout area, generally, a connection terminal which is closest to the source terminal in the i-th level normal layout area among all the connection terminals connected to the reserved blank area and the i-th level normal layout area is used as a predetermined connection terminal to form a drain terminal newly added in the i-th level normal layout area.

[0077] When another predetermined connection point is determined by the reference drain terminal in the direction of the source terminal in the i-th level normal layout area, there are two implementation methods:

[0078] (1) For all connection terminals connected to the reserved blank area and the (i+1)th level normal layout area, the connection terminal with the smallest total distance to all reference drain terminals or the shortest maximum distance is used as a predetermined connection terminal to form a newly added source terminal in the (i+1)th level normal layout area.

[0079] (2) A Steiner tree is formed by all reference drain terminals, and the connection terminal that is closest to a predetermined Steiner node in the formed Steiner tree among all the connection terminals connecting the reserved blank area with the i+1th level normal layout area is used as a predetermined connection terminal to form a newly added source terminal in the i+1th level normal layout area. The predetermined Steiner node can be any pre-set Steiner node.

[0080] 3. First determine a predetermined connection terminal, and use the connection terminal that is closest to the predetermined connection terminal and connected to another normal layout area as another predetermined connection terminal. The predetermined connection terminal determined first can be used to form a newly added drain terminal in the i-th level normal layout area, or can also be used to form a newly added source terminal in the i+1-th level normal layout area. The method of first determining a predetermined connection terminal can adopt any of the above-mentioned methods of case 1 or case 2, and case 3 will not be repeated.

[0081] Fourth, first determine a predetermined connection terminal, and use the determined predetermined connection terminal in combination with the source terminal in the i-th level normal layout area and / or the reference drain terminal in the direction to determine another predetermined connection terminal. Similar to case three, the first determined predetermined connection terminal can be used to form a newly added drain terminal in the i-th level normal layout area, or it can also be used to form a newly added source terminal in the i+1-th level normal layout area. The method of first determining a predetermined connection terminal can adopt any of the above-mentioned methods of case one or case two, and case four will not be repeated.

[0082] If the newly added drain terminal in the i-th level normal layout area is determined first, another predetermined connection terminal is determined based on the determined predetermined connection terminal combined with the reference drain terminal in the direction of the source terminal in the i-th level normal layout area. The meaning of the reference drain terminal in the direction of the source terminal in the i-th level normal layout area is as described above. Specifically, the method (1) (2) (3) of the first case can be used to form a cross-region connection by using the determined predetermined connection terminal combined with the reference drain terminal in the direction of the source terminal in the i-th level normal layout area, and then another predetermined connection terminal is determined based on the cross-region connection according to the method of the first case.

[0083] If the newly added source end in the normal layout area of ​​the i+1th level is determined first, another predetermined connection end is determined based on the determined predetermined connection end and the source end in the normal layout area of ​​the ith level. Specifically, the source end in the normal layout area of ​​the ith level of the determined predetermined connection end is used to form a cross-area connection, and then another predetermined connection end is determined based on the cross-area connection according to the method of situation 1.

[0084] In all the above cases, the distance can be calculated by Manhattan distance. It should be noted that when splitting an original network, the same method or different methods can be used when inserting network endpoints in the reserved blank area between different normal layout areas. Figure 3 When inserting the T25 / S22 group of line network endpoints, the method of the above situation 1 can be used, and when inserting the T26 / S23 group of line network endpoints, the method of the above situation 1 can also be used, or the method of the above situation 2 can be used instead. This application does not limit this.

[0085] Through the above method, the predetermined connection end in the reserved blank area can be selected between different normal layout areas to realize the newly added line net endpoints, and in each normal layout area, the source end is connected and points to the drain end in the normal layout area, thereby forming a network to be wired in each normal layout area, each network to be wired includes the connection relationship between the portion of the original network in the current normal layout area and the newly added network endpoints formed by the predetermined connection end of the reserved blank area at the boundary of the current normal layout area. The network to be wired corresponding to each two adjacent normal layout areas obtained by splitting an original network is respectively connected to a pair of predetermined connection ends of the reserved blank area between the two normal layout areas. For example, four nets to be wired are split from the original net Net2, namely, the net to be wired Net2a in normal layout area 1, the net to be wired Net2b in normal layout area 2, the net to be wired Net2c in normal layout area 3, and the net to be wired Net2d in normal layout area 4. The net to be wired Net2a includes a source terminal S21 and drain terminals T21 and T25 connected thereto, respectively; the net to be wired Net2b includes a source terminal S22 and a drain terminal T26 connected thereto, the net to be wired Net2c includes a source terminal S23 and drain terminals T23, T24 and T27 connected thereto, respectively; and the net to be wired Net2d includes a source terminal S24 and a drain terminal T22 connected thereto. The network to be wired Net2a is connected to the network to be wired Net2b through a pair of connection points for implementing T25 / S22, the network to be wired Net2b is connected to the network to be wired Net2c through a pair of connection points for implementing T26 / S23, and the network to be wired Net2c is connected to the network to be wired Net2d through a pair of connection points for implementing T27 / S24.

[0086] Step 5, perform parallel wiring processing on the to-be-wired nets corresponding to each normal layout area and each predetermined connection terminal to be connected in each reserved blank area to obtain the wiring results in each normal layout area and each reserved blank area respectively, merge the wiring results of each normal layout area and each reserved blank area to obtain the global wiring result corresponding to the FPGA, and complete the design of the FPGA. Figure 1 The flowchart shown takes parallel routing of M normal layout areas and N reserved blank areas as an example.

[0087] According to the above steps 3 or 4, the original wire nets are preprocessed respectively to directly obtain or split the corresponding wire nets to be routed. After all the original wire nets are preprocessed, the wire nets to be routed in each normal layout area can be obtained. Figure 3In the example, normal layout area 1 includes the net to be routed obtained directly from the original net Net1, and the net to be routed Net2a obtained by splitting the original net Net2. Normal layout area 2 includes the net to be routed Net2b obtained by splitting the original net Net2, normal layout area 3 includes the net to be routed Net2c obtained by splitting the original net Net2, and normal layout area 4 includes the net to be routed Net2d obtained by splitting the original net Net2.

[0088] Optionally, after processing all original wire nets into corresponding nets to be wired and obtaining nets to be wired corresponding to each normal layout area, before performing parallel winding processing, update the local netlist corresponding to each normal layout area, and optimize the layout of the corresponding normal layout area according to the local netlist to obtain the final global layout result, that is, optimize and update the layout results in each normal layout area according to the predetermined connection ends selected in the reserved blank area.

[0089] Then use the multi-core processing platform to complete the FPGA wiring task. The number of normal layout areas and reserved blank areas matches the number of processing cores of the multi-core platform, and is no more than the number of processing cores. Each processing core handles the wiring problem of one area, including processing the to-be-wired nets in the normal layout area and processing the winding problems in the reserved blank area. Each processing core works in parallel. Due to the processing of this application, each area has its own netlist and wiring resource map. Therefore, when winding in parallel, the winding results in each area are independent of each other and do not interfere with each other. The results can be directly merged globally after winding separately, and there is no need to resolve conflicts in different areas. The operation results are predictable and are not affected by the netlist processing order and the design environment. It is suitable for parallel processing and wiring, and can effectively improve the wiring efficiency and obtain wiring results. Finally, subsequent common operations such as timing analysis and code stream generation are performed to complete the FPGA design process.

Claims

1. A FPGA design method that can achieve parallel wiring, It is characterized in that The method comprises: Performing layout on the user input netlist in each normal layout area inside the FPGA to obtain an initial layout result, wherein the programmable logic resources inside the FPGA are divided into a normal layout area and a reserved blank area, and each two adjacent normal layout areas are separated by a reserved blank area; Determine the positions of all the wire net endpoints in each original wire net according to the initial layout result of the FPGA, where the wire net endpoints include a source terminal and a plurality of drain terminals connected thereto; The original wire nets with all the wire net endpoints located in the same normal layout area are directly mapped to the normal layout area as the wire net to be routed; An original wire net whose wire net endpoints are distributed in at least two different normal layout areas is split into a plurality of wire nets to be routed corresponding to different normal layout areas by using a reserved blank area, each wire net to be routed includes a connection relationship between newly added wire net endpoints formed by a portion of the original wire net in the current normal layout area and a predetermined connection end of a reserved blank area at a boundary of the current normal layout area, and the wire nets to be routed corresponding to each two adjacent normal layout areas obtained by splitting an original wire net are respectively connected to a pair of predetermined connection ends of a reserved blank area between the two normal layout areas; Perform parallel routing processing on the to-be-wired nets corresponding to each normal layout area and each predetermined connection end to be connected in each reserved blank area to obtain the routing results in each normal layout area and each reserved blank area respectively, merge the routing results of each normal layout area and each reserved blank area to obtain the global routing result corresponding to the FPGA, and complete the design of the FPGA; The normal layout area where the source end in the original line network is located is taken as the first-level normal layout area, and the adjacent normal layout area of ​​the i-th level normal layout area in the direction from the source end to the corresponding drain end in the original line network is taken as the i+1-th level normal layout area, i is a parameter and the initial value of i is 1; then a predetermined connection end connected to the i-th level normal layout area in the reserved blank area between the i-th level normal layout area and the i+1-th level normal layout area is formed as a newly added drain end in the i-th level normal layout area, and the corresponding other predetermined connection end connected to the i+1-th level normal layout area is formed as a newly added source end in the i+1-th level normal layout area, and the source ends in each level of normal layout area are connected to and point to all the drain ends in the current normal layout area.

2. The method according to claim 1, It is characterized in that A pair of predetermined connection ends in the reserved blank area belong to connection ends of the same switch box in the reserved blank area, and the pair of predetermined connection ends are connected through an internal path of the switch box.

3. The method according to claim 1, It is characterized in that A pair of predetermined connection ends in the reserved blank area belong to connection ends of different switch boxes in the reserved blank area, and the pair of predetermined connection ends are connected through an internal path of the switch box and an external path between different switch boxes.

4. The method according to claim 1, It is characterized in that The reserved blank areas arranged along the horizontal direction and the vertical direction are connected to form a rectangular frame, and the normal layout area inside the rectangular frame is used to implement the predetermined IP node.

5. The method according to claim 1, It is characterized in that There is a reserved blank area that coincides with the clock domain.

6. The method according to claim 1, It is characterized in that The FPGA is a multi-die structure, and there is a reserved blank area that overlaps with the cross-die connection area between two adjacent FPGA dies. The cross-die connection area includes the connection point lead-out terminals in the two FPGA dies and the cross-die connection lines in the silicon connection layer for connecting the connection point lead-out terminals of the two FPGA dies.

7. The method according to claim 1, It is characterized in that The user input netlist is layout-planned and the programmable logic resources inside the FPGA are divided into a number of normal layout areas and reserved blank areas according to the layout-planning results, and the number of pairs of connection terminals contained in each reserved blank area is greater than the number of signals crossing the reserved blank area.

8. The method according to claim 1, It is characterized in that The method further comprises: After processing all original nets into corresponding nets to be routed and obtaining nets to be routed corresponding to each normal layout area, the local netlist corresponding to each normal layout area is updated, and the layout of the corresponding normal layout area is optimized according to the local netlist to obtain the final global layout result.

9. The method according to claim 1, It is characterized in that When determining two predetermined connection ends of the reserved blank area between the i-th level normal layout area and the (i+1)-th level normal layout area: Determine two predetermined connection ends respectively based on the cross-area connection line crossing the reserved blank area; Alternatively, a predetermined connection terminal formed as a newly added drain terminal in the i-th level normal layout area is determined based on the source terminal in the i-th level normal layout area, and another predetermined connection terminal formed as a newly added source terminal in the (i+1)-th level normal layout area is determined based on the reference drain terminal in the direction where the source terminal in the i-th level normal layout area is located; Alternatively, a predetermined connection end is determined first, and a connection end closest to the determined predetermined connection end is used as another predetermined connection end; Alternatively, a predetermined connection terminal is determined first, and another predetermined connection terminal is determined by using the determined predetermined connection terminal in combination with the source terminal in the i-th level normal layout area and / or the reference drain terminal in the direction thereof; The reference drain terminal in the direction of the source terminal in the i-th level normal layout area includes the drain terminal in the first level normal layout area closest to the i-th level normal layout area, or the drain terminals in all the subsequent level normal layout areas.

10. The method according to claim 9, It is characterized in that The determining two predetermined connection ends based on the cross-area connection crossing the reserved blank area respectively includes: When there are multiple cross-region connection lines, for all connection terminals connected between the reserved blank area and the i-th level normal layout area, the connection terminals closest to each cross-region connection line are respectively determined as candidate connection terminals, and the candidate connection terminal closest to the source terminal in the i-th level normal layout area is used as a predetermined connection terminal to form a newly added drain terminal in the i-th level normal layout area; for all connection terminals connected between the reserved blank area and the i+1-th level normal layout area, the connection terminals closest to each cross-region connection line are respectively determined as candidate connection terminals, and the candidate connection terminal with the smallest total distance to all reference drain terminals or the shortest maximum distance is used as a predetermined connection terminal to form a newly added source terminal in the i+1-th level normal layout area; When there is one cross-region connection line, for all connection terminals connected between the reserved blank area and the i-th level normal layout area, the connection terminal closest to the cross-region connection line is determined as a predetermined connection terminal to form a newly added drain terminal in the i-th level normal layout area; for all connection terminals connected between the reserved blank area and the (i+1)-th level normal layout area, the connection terminal closest to the cross-region connection line is determined as a predetermined connection terminal to form a newly added source terminal in the (i+1)-th level normal layout area.

11. The method according to claim 10, It is characterized in that The cross-region connection lines crossing the reserved blank area include connection lines between the source terminals in the i-th level normal layout area and each reference drain terminal in the direction thereof.

12. The method according to claim 10, It is characterized in that The cross-region connection line crossing the reserved blank region includes a connection line between a source terminal in the i-th level normal layout region and a center of gravity point formed by a reference drain terminal in the direction thereof.

13. The method according to claim 10, It is characterized in that The cross-area connection across the reserved blank area includes a connection between a source terminal in the i-th level normal layout area and a predetermined reference drain terminal among the reference drain terminals in the direction thereof, and the predetermined reference drain terminal is the reference drain terminal that is closest to and / or farthest from the source terminal in the i-th level normal layout area among all the reference drain terminals.

14. The method according to claim 10, It is characterized in that The cross-area connection line crossing the reserved blank area is an edge crossing the reserved blank area in a minimum spanning tree formed by sequentially connecting all the wire network endpoints inside the original wire network through a minimum spanning tree algorithm.

15. The method according to claim 9, It is characterized in that The method of determining another predetermined connection terminal formed as a newly added source terminal in the (i+1)th level normal layout area based on the reference drain terminal in the direction where the source terminal in the i-th level normal layout area is located includes: For all connection terminals connected to the reserved blank area and the i+1th level normal layout area, the connection terminal with the smallest total distance to all reference drain terminals or the shortest maximum distance is formed as a predetermined connection terminal as a newly added source terminal in the i+1th level normal layout area.

16. The method according to claim 9, It is characterized in that The method of determining another predetermined connection terminal formed as a newly added source terminal in the (i+1)th level normal layout area based on the reference drain terminal in the direction where the source terminal in the i-th level normal layout area is located includes: A Steiner tree is formed by all reference drain terminals, and the connection terminal closest to a predetermined Steiner node in the formed Steiner tree among all connection terminals connecting the reserved blank area with the i+1th level normal layout area is used as a predetermined connection terminal to form a newly added source terminal in the i+1th level normal layout area.

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