Read-only memory array structure, chip, electronic device and encoding method

Abstract

The application provides a read-only memory array structure, which comprises m*n memory cells arranged in a matrix, m word lines and n bit lines, wherein m and n are natural numbers greater than or equal to 1. Each memory cell comprises a gate, a source and a drain; the m word lines correspond to m rows of memory cells one by one; the n bit lines correspond to n columns of memory cells one by one, and each bit line is connected with the drain of the memory cell in the corresponding column; wherein the source of each memory cell is grounded; according to whether the data stored in each memory cell is '0' or '1', the gate of each memory cell is connected with the corresponding word line or grounded. The application further provides a chip and an electronic device comprising the chip. The application further provides an encoding method. The application can effectively reduce the load of the word line and improve the storage performance.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a read-only memory array structure, chip, electronic device and encoding method. Background Technology

[0002] Currently, with the development of technology, electronic devices (such as smartphones, tablets, and personal computers) are widely used. Memory, as the information storage device in electronic devices, is an indispensable part of them, and memory and storage technology have become one of the key technological areas driving the development of the information age. Among these, a typical type of memory widely used is Read Only Memory (ROM). Currently, the most common type of ROM is the N-type field-effect transistor ROM. Generally speaking, the array arrangement structure of ROM has a significant impact on memory performance. Therefore, how to provide a ROM array arrangement structure to improve memory performance has become a problem that needs to be solved. Summary of the Invention

[0003] This application provides a read-only memory array structure, chip, electronic device, and encoding method, which can effectively reduce word line load and improve memory performance.

[0004] In a first aspect, embodiments of this application provide a read-only memory array structure, including m*n memory cells arranged in a matrix, m word lines, and n bit lines, where m and n are natural numbers greater than or equal to 1. Each memory cell includes a gate, a source, and a drain; the m word lines correspond one-to-one with m rows of memory cells; the n bit lines correspond one-to-one with n columns of memory cells, and each bit line is connected to the drain of the memory cell in the corresponding column; wherein, the source of each memory cell is grounded; depending on whether the data stored in each memory cell is "0" or "1", the gate of each memory cell is connected to or grounded to the corresponding word line.

[0005] Secondly, embodiments of this application provide a chip, the chip including a read-only memory array structure. The read-only memory array structure includes m*n memory cells arranged in a matrix, m word lines, and n bit lines, where m and n are natural numbers greater than or equal to 1. Each memory cell includes a gate, a source, and a drain; the m word lines correspond one-to-one with m rows of memory cells; the n bit lines correspond one-to-one with n columns of memory cells, and each bit line is connected to the drain of the memory cell in the corresponding column; wherein, the source of each memory cell is grounded; depending on whether the data stored in each memory cell is "0" or "1", the gate of each memory cell is connected to the corresponding word line or grounded.

[0006] Thirdly, embodiments of this application provide an electronic device, the electronic device including a chip, the chip including a read-only memory array structure. The read-only memory array structure includes m*n memory cells arranged in a matrix, m word lines and n bit lines, where m and n are natural numbers greater than or equal to 1. Each memory cell includes a gate, a source and a drain; the m word lines correspond one-to-one with m rows of memory cells; the n bit lines correspond one-to-one with n columns of memory cells, and each bit line is connected to the drain of the memory cell in the corresponding column; wherein, the source of each memory cell is grounded; depending on whether the data stored in each memory cell is "0" or "1", the gate of each memory cell is connected to the corresponding word line or grounded.

[0007] As can be seen, in this embodiment of the application, since the word line is only connected to a portion of the storage units, the number of storage units connected by the word line can be effectively reduced. While storing data "0" or "1" as needed, the load on the word line can be reduced, and the overall performance of the read-only memory array structure can be improved. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other modifications can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of a read-only memory array structure in one embodiment of this application.

[0010] Figure 2 This is a schematic diagram of the connection between the storage unit and the word line in one embodiment of this application.

[0011] Figure 3 This is a schematic diagram of a storage unit connected to a second ground wire in one embodiment of this application.

[0012] Figure 4 This is a plan view illustrating a multi-layer structure of a read-only memory array in one embodiment of this application.

[0013] Figure 5 This is a side view of a multilayer structure illustrating a read-only memory array structure in one embodiment of this application.

[0014] Figure 6 This is a top view schematic diagram illustrating the structure of the memory cell in a read-only memory array structure according to an embodiment of this application.

[0015] Figure 7This is a structural block diagram of a chip in one embodiment of this application.

[0016] Figure 8 This is a structural block diagram of an electronic device according to an embodiment of this application.

[0017] Figure 9 This is a flowchart of an encoding method in one embodiment of this application. Detailed Implementation

[0018] The terminology used in this application is for the purpose of explaining specific embodiments of the application only and is not intended to limit the application. The terms "first," "second," "third," and "fourth," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0019] Unless otherwise specified, the term "connection" in this application primarily refers to "electrical connection".

[0020] The electronic devices in this application may include handheld devices including memory, such as mobile phones and tablets, as well as in-vehicle devices, wearable devices, computing devices or other processing devices connected to a wireless modem, and various forms of user equipment (UE), mobile station (MS), terminal device, etc., including memory.

[0021] Please see Figure 1 This is a schematic diagram of the read-only memory array structure 1 in one embodiment of this application. Figure 1 As shown, the read-only memory array structure 1 includes m*n memory cells 11 arranged in a matrix, m word lines WL, and n bit lines BL, where m and n are natural numbers greater than or equal to 1. Each memory cell 11 includes a gate G, a source S, and a drain D; the m word lines WL correspond one-to-one with the m rows of memory cells 11; the n bit lines correspond one-to-one with the n columns of memory cells 11, and each bit line is connected to the drain of the memory cell 11 in the corresponding column; the source S of each memory cell 11 is grounded; and the gate G of each memory cell 11 is connected to or grounded with the corresponding word line WL depending on whether the data stored in each memory cell 11 is "0" or "1".

[0022] Therefore, in this application, since the word line WL is only connected to a portion of the memory cells 11, the number of memory cells 11 connected to the word line WL can be effectively reduced. This reduces the load on the word line WL while still storing data "0" or "1" as needed, thus improving the overall performance of the read-only memory array structure 1. This improvement in overall performance may include, for example, performance enhancements such as reduced power consumption.

[0023] In some embodiments, such as Figure 1 As shown, each word line WL extends along the row direction through a corresponding row of storage cells 11; each bit line BL extends along the column direction through a corresponding column of storage cells 11. That is, in some embodiments, the m word lines WL correspond one-to-one with the m rows of storage cells 11 as follows: each word line WL extends along the row direction through a corresponding row of storage cells 11, and corresponds to the position of the storage cell 11 in the corresponding row; while the n bit lines BL correspond one-to-one with the n columns of storage cells 11 as follows: each bit line extends along the column direction through a corresponding column of storage cells, and corresponds to the position of the storage cell 11 in the corresponding column.

[0024] Among them, such as Figure 1 As shown, the read-only memory array structure 1 further includes n first ground lines VSS1 and n second ground lines VSS2. Each first ground line VSS1 extends along the column direction through a corresponding column of memory cells 11 and is connected to the source of the corresponding column of memory cells 11 to ground the source of each memory cell 11. Each second ground line VSS2 extends along the column direction through a corresponding column of memory cells 11. Depending on whether the data stored in each memory cell 11 is "0" or "1", the gate G of each memory cell 11 is connected to the corresponding word line WL or to the corresponding second ground line VSS2 to ground.

[0025] Wherein, m and n can be any natural number greater than or equal to 1, and m and n can be equal or unequal. Figure 1 The read-only memory array structure 1 in the figure only shows three rows and three columns of storage cells 11, that is, m = n = 3. Obviously, the number of storage cells 11 included in the read-only memory array structure 1 can be determined according to the size of the total data stored.

[0026] in, Figure 1 The positions where the word line WL intersects with the bit line BL, the first ground line VSS1, and the second ground line VSS2 are not connection points, but rather points where they coincide on the projection. Figure 1The second ground line VSS2 shown extends through the gate G of each column of memory cells 11, but this does not mean that the second ground line VSS2 is connected to the gate G of each column of memory cells 11. As mentioned earlier, depending on whether the data stored in each memory cell 11 is "0" or "1", the gate G of each memory cell 11 is connected to the corresponding word line WL or to the corresponding second ground line VSS2. To avoid too many lines, the first ground line VSS1... Figure 1 The symbols used in the text represent this.

[0027] In this application, "row direction" refers to the arrangement direction of a row of storage cells 11, and "column direction" refers to the arrangement direction of a column of storage cells 11.

[0028] in, Figure 1 This is an equivalent schematic diagram of the read-only memory array structure 1, and not a physical schematic diagram.

[0029] The aforementioned one-to-one correspondence between the m word lines WL and the m rows of memory cells 11 mainly refers to the fact that the m word lines WL are word lines used for the m rows of memory cells 11 respectively, and the one-to-one correspondence between the n bit lines BL and the n columns of memory cells 11 refers to the fact that the n bit lines BL are bit lines used for the n columns of memory cells 11 respectively. Obviously, the m word lines WL can also be set in any position; however, when the gate G of some memory cells 11 in a certain row needs to be connected to the word lines WL, they can be connected to the corresponding word lines WL of that row of memory cells 11 through electrical connectors such as wires or flexible circuit boards. In other embodiments, the n bit lines BL can also be set in any position, and each bit line can be further connected to the drain D of the corresponding column of memory cells 11 through electrical connectors such as wires or flexible circuit boards.

[0030] In other embodiments, the read-only memory array structure may not include the n first ground lines VSS1 and n second ground lines VSS2. The source of each memory cell 11 can be directly connected to ground through electrical connectors such as wires and flexible circuit boards. When the gate G of some memory cells 11 needs to be grounded, it can be directly connected to ground through electrical connectors such as wires and flexible circuit boards.

[0031] Please refer to the following: Figure 2 and Figure 3 , Figure 2 This is a schematic diagram showing the connection between storage cell 11 and word line WL. Figure 3 This is a schematic diagram showing the connection between storage cell 11 and the second ground line VSS2. (See diagram below.) Figure 2 and Figure 3As shown, when the data stored in a certain memory cell 11 is "0", the gate G of the memory cell 11 is connected to the corresponding word line WL. When the data stored in a certain memory cell 11 is "1", the gate G of the memory cell 11 is connected to the corresponding second ground line VSS2.

[0032] Specifically, when the data stored in a certain storage cell 11 is "0", the structure of the storage cell 11 is designed such that the gate G is connected to the corresponding word line WL. When the data stored in a certain storage cell 11 is "1", the structure of the storage cell 11 is designed such that the gate G is connected to the corresponding second ground line VSS2.

[0033] like Figure 2 and Figure 3 As shown, the drain D of the memory cell 11 is connected to the bit line BL, and the source S is connected to the first ground line VSS1. The first ground line VSS1 and the second ground line VSS2 are used for grounding and are at zero potential, i.e., at a low level. The first ground line VSS1 and the second ground line VSS2 can be connected to the same ground or different grounds. The bit line BL is generally pre-charged to a high level before data is read, i.e., it is generally at a high level. The word line WL is used to apply a high-level signal; for example, the word line WL can be continuously applied with a high-level signal or applied with a high-level signal during data reading.

[0034] In this embodiment, the memory cell 11 is an N-type field-effect transistor (NMOSFET, short for N-channel metal-oxide-semiconductor field-effect transistor). Therefore, when the gate G of the memory cell 11 is connected to the corresponding word line WL, the gate G of the memory cell 11 is at a high level, thus the memory cell 11 is in the on state. The drain D and source S of the memory cell 11 are effectively short-circuited, therefore, the drain D of the memory cell 11 connected to the bit line BL is pulled low. When the gate G of the memory cell 11 is connected to the corresponding second ground line VSS2, the gate G of the memory cell 11 is at a low level, thus the memory cell 11 is in the off state. The drain D and source S of the memory cell 11 are effectively open-circuited, therefore, the drain D of the memory cell 11 connected to the bit line BL remains at a high level.

[0035] The bit line BL serves as the data output terminal of the storage unit 11. Since a high level corresponds to "1" and a low level corresponds to "0", the data stored in the storage unit 11, i.e., whether the stored bit is "0" or "1", can be read by reading the level of the bit line BL.

[0036] Therefore, the aforementioned statement that "when the data stored in a certain memory cell 11 is "0", the gate G of the memory cell 11 is connected to the corresponding word line WL, and when the data stored in a certain memory cell 11 is "1", the gate G of the memory cell 11 is connected to the corresponding second ground line VSS2" can actually be interpreted as follows: when the data to be stored in a certain memory cell 11 is "0", the structure of the memory cell 11 is designed such that the gate G is connected to the corresponding word line WL, thereby causing the memory cell 11 to output a low level through the bit line BL and be read as the data "0"; when the data to be stored in a certain memory cell 11 is "1", the structure of the memory cell 11 is designed such that the gate G is connected to the corresponding second ground line VSS2, thereby causing the memory cell 11 to output a high level through the bit line BL and be read as the data "1".

[0037] In this configuration, the read-only memory array structure 1 is not writable, but can only be read. The process of reading data from the read-only memory array structure 1 can be performed through row scanning. In some embodiments, the specific scanning method is as follows.

[0038] Please return to the reference. Figure 1 The m character lines WL are distributed across m rows, including WL0, WL1, ..., WLm. Figure 1 Only three lines of word lines are shown: WL0, WL1, and WL2. The multiple bit lines BL are distributed across multiple columns, including BL0, BL1...BLn. Figure 1 Only three bit lines are shown: BL0, BL1, and BL2. When a high level is sequentially applied to the multiple word lines WL, the gate G of the memory cell 11 with data "0" stored in the corresponding row of memory cell 11 is connected to the word line WL. Therefore, the corresponding column bit line BL will output a low level and be read as "0". Conversely, the gate of the memory cell 11 with data "1" stored in the corresponding row of memory cell 11 is connected to the second ground line VSS2, causing the corresponding column bit line BL to output a high level and be read as "1". Since the intersection of a word line WL and a column bit line BL indicates the position of the memory cell 11, the row position can be determined based on the currently high-level word line WL, and the column position can be determined based on the currently high- or low-level bit line BL. Therefore, the identity of the memory cell 11 and the data read from it can be uniquely determined. Therefore, we can know that one bit of data is read from each row and each column of storage unit 11. Then, based on the position of each row and each column of storage unit 11 in a multi-bit data position, the corresponding multi-bit data can be combined.

[0039] Correspondingly, during the manufacturing process of the read-only memory array structure 1, the data to be stored in each storage unit can be determined as "1" or "0" based on the multi-bit data corresponding to the specific content to be stored in the read-only memory array structure and the position of the storage unit in each row and column of the multi-bit data.

[0040] The multi-bit data can be one or more bytes, each byte including 8 bits of data, or the multi-bit data can be a data string including any number of bits, for example, 4 bits of data, 9 bits of data, etc. The specific content can be read-only content such as the product serial number and manufacturing information of the electronic device where the read-only memory array structure 1 is located.

[0041] Please refer to the attached diagram above as well. Figure 4 and Figure 5 , Figure 4 This is a schematic plan view illustrating the multi-layer structure of the read-only memory array structure 1 in one embodiment of this application. Figure 5 This is a side view illustrating the multi-layer structure of the read-only memory array structure 1 according to an embodiment of this application. Figure 4 Only four storage units (11) are shown in a 2x2 matrix arrangement. Figure 5 The diagram shows a side view of two storage cells 11 located in the same row, which are visible in a single row.

[0042] In some embodiments of this application, the gate G of the memory cell 11 is connected to the corresponding word line WL through a first conductive via K1, and the gate G of the memory cell 11 is connected to the corresponding second ground line VSS2 through a second conductive via K2.

[0043] That is, when the data to be stored in a certain storage cell 11 is "0", the gate G of the storage cell 11 is connected to the corresponding word line WL by forming a first conductive via K1; when the data to be stored in a certain storage cell 11 is "1", the gate G is connected to the corresponding second ground line VSS2 by forming a second conductive via K2.

[0044] like Figure 4 and Figure 5As shown, the read-only memory array structure 1 further includes n word line connecting strips 12, each word line connecting strip 12 extending along the column direction through a corresponding column of memory cells 11. The n word line connecting strips 12 are parallel to and alternately arranged on the same layer as the n second ground lines VSS2. Each memory cell 11 also includes a gate connection line GL, which is connected to the gate G of the memory cell 11. The n word line connecting strips 12 and the n second ground lines VSS2 are arranged on the side of the memory cell 11 where the gate connection line GL is arranged. The m word lines WL are specifically arranged on the side of the n word line connecting strips 12 opposite to the memory cell 11.

[0045] Specifically, when the data stored in a certain memory cell 11 is "0", a first conductive via K11 is opened on the corresponding word line WL, and a second conductive via K12 is opened on the corresponding word line connecting strip 12 at the position where it intersects with the gate connection line GL. The first conductive via K11 and the second conductive via K12 are connected to form the first conductive via K1, so that the word line WL is connected to the gate connection line GL through the first conductive via K11 and the second conductive via K12, thereby connecting the gate G of the memory cell 11 to the corresponding word line WL. When the data stored in a certain memory cell 11 is "1", a second conductive via K2 is opened on the corresponding second ground line VSS2 at the position where it intersects with the gate connection line GL, so that the second ground line VSS2 is connected to the gate connection line GL, thereby connecting the gate G of the memory cell 11 to the corresponding second ground line VSS.

[0046] Among them, such as Figure 5 As shown, the word line connector 12 and the gate connection line GL are disposed on different layers, while the second ground line VSS2 and the word line connector 12 are located on the same layer, and the second ground line VSS2 is also disposed on a different layer from the gate connection line GL. The aforementioned intersection of the second ground line VSS2 and the gate connection line GL refers to the position where the projection of the second ground line VSS2 onto the memory cell 11 coincides with the gate connection line GL.

[0047] Each word line WL, each second ground line VSS2, and each word line connecting strip 12 is a conductive wire wrapped with insulating material. The gate connecting line GL is a bare conductive wire, that is, a conductive wire with exposed conductive material without insulating material. When the word line WL has the first conductive via K11, the word line WL can be electrically connected through the first conductive via K11. That is, the conductive material of the word line WL is exposed through the first conductive via K11 and can be electrically connected to other conductive objects, such as the second conductive via K12. When the word line connecting strip 12 has the second conductive via K12, the word line connecting strip 12 can be electrically connected through the second conductive via K12. That is, the conductive material of the word line connecting strip 12 is exposed through the second conductive via K12 and can be electrically connected to other conductive objects, such as the first conductive via K11 and the gate connecting line GL. When the second conductive via K2 is opened on the second ground wire VSS2, the second ground wire VSS2 can be electrically connected through the second conductive via K2. That is, the conductive material of the second ground wire VSS2 is exposed through the second conductive via K2 and can be electrically connected to other conductive objects, such as the gate connection line GL.

[0048] Among them, such as Figure 5 As shown, the first conductive via K11 and the second conductive via K12 are directly opposite each other, meaning that the projection of the first conductive via K11 onto the word line connecting strip 12 completely coincides with the second conductive via K12. Obviously, in another embodiment, the projection of the first conductive via K11 onto the word line connecting strip 12 only partially coincides with the second conductive via K12. Thus, a conductive channel is formed through the contact of the overlapping areas of the first conductive via K11 and the second conductive via K12.

[0049] In other embodiments, the projection of the first conductive via K11 on the word line connecting strip 12 does not overlap with the second conductive via K12 at all, i.e., there is no overlapping area. The first conductive via K1 may also include a third conductive via (not shown in the figure). The third conductive via is opened on the word line connecting strip 12 and corresponds to the position of the first conductive via K11, and is electrically connected to the first conductive via K11. The third conductive via and the second conductive via K12 are electrically connected through the conductive material of the word line connecting strip 12, and then can be electrically connected to the gate connection line GL through the second conductive via K12.

[0050] In order to better demonstrate the various structures, Figure 4The word line WL is represented by a dashed box. As mentioned earlier, the word line WL is located on the side of the word line connector 12 opposite to the storage cell 11. Figure 4 In the 2x2 matrix shown, the gate G of the storage cell 11 in the first row and first column (i.e., the upper left corner shown in the figure) is connected to the corresponding second ground line VSS2 through the second conductive via K2, and the data stored in this storage cell 11 is "1"; the gate G of the storage cell 11 in the first row and second column (i.e., the upper right corner shown in the figure) is connected to the corresponding word line WL and word line connecting strip 12 through the first conductive via K1, and the data stored in this storage cell 11 is "0"; the gate G of the storage cell 11 in the second row and second column (i.e., the lower left corner shown in the figure) is connected to the corresponding word line WL and word line connecting strip 12 through the first conductive via K1, and the data stored in this storage cell 11 is "0"; the gate G of the storage cell 11 in the second row and second column (i.e., the lower right corner shown in the figure) is connected to the corresponding second ground line VSS2 through the second conductive via K2, and the data stored in this storage cell 11 is "1".

[0051] Among them, such as Figure 4 and Figure 5 As shown, each memory cell 11 further includes a substrate layer 111. The source S and drain D of the memory cell 11 are formed on the substrate layer 111 at intervals. The source G of the memory cell 11 is stacked above the source S and drain D and is connected to both the source S and drain D. The source connection line GL extends a predetermined distance from the source S along the row direction.

[0052] in, Figure 5 This is merely a side view of a row of storage cells 11 in the read-only memory array structure 1, not a cross-sectional view, and is only intended to illustrate the spatial stacking relationship of the various structures in the read-only memory array structure 1. It should also be noted that... Figure 5 This is just an example, and the stacking relationship of some structures is not limited to this. For example, the bit line BL and the first ground line VSS1 can be disposed below the gate line GL or above the gate line GL.

[0053] Among them, such as Figure 4 As shown, the storage cells 11 in the same column share the same substrate layer 111. That is, the substrate layer 111 can be arranged in multiple columns, and the source S and drain D of each column of storage cells 11 are formed on the substrate layer 111 of the corresponding column.

[0054] In some embodiments, each bit line BL can be connected to the drain D of the corresponding column of memory cell 11 via a via, such as through the aforementioned conductive via. The connection between each bit line and the source of the corresponding column of memory cell 11 can also be via a via, such as through the aforementioned conductive via. Figure 4 As shown, each bit line BL is connected to the drain D of the corresponding column memory cell 11 through a conductive via V1, and each first ground line VSS1 is connected to the source of the corresponding column memory cell 11 through a conductive via V2.

[0055] like Figure 4 As shown, the gate connection line GL extends along the row direction, and the read-only memory array structure 1 also includes a gate disconnect layer 13 extending along the column direction, which is used to separate the gate connection lines GL of different memory cells 11.

[0056] The gate disconnect layer 13 is an insulating material layer. There are n-1 gate disconnect layers 13, each located between two adjacent columns of memory cells 11. During manufacturing, the gate connection line GL of the memory cells 11 in the same row is a single line. By setting the gate disconnect layer 13 between two adjacent columns of memory cells 11, the entire row of gate connection lines GL can be divided into n independent gate connection lines GL. More specifically, the conductive material portion of the gate connection line GL corresponding to the location of the gate disconnect layer 13 can be removed first, and then the gate disconnect layer 13 can be set in that portion.

[0057] Specifically, each word line WL extends along the row direction through a corresponding row of storage cells 11, each bit line extends along the column direction through a corresponding column of storage cells, each first ground line VSS1 extends along the column direction through a corresponding column of storage cells 11, and each second ground line VSS2 extends along the column direction through a corresponding column of storage cells 11. This is mainly to facilitate the use of... Figure 4 as well as Figure 5 The method of opening conductive vias shown achieves electrical connection with the storage unit 11.

[0058] Obviously, as mentioned above, in other embodiments, the m word lines WL can also be set at any position. However, when the gates G of certain memory cells 11 in a row need to be connected to the word lines WL, they can be connected to the corresponding word lines WL of that row of memory cells 11 via electrical connectors such as wires or flexible circuit boards. In other embodiments, the n bit lines BL can also be set at any position, and each bit line can be further connected to the drain D of the corresponding column of memory cells 11 via electrical connectors such as wires or flexible circuit boards. The read-only memory array structure may also exclude the n first ground lines VSS1 and the n second ground lines VSS2. The source of each memory cell 11 can be directly connected to ground via electrical connectors such as wires or flexible circuit boards, and when the gates G of certain memory cells 11 need to be grounded, they can be directly connected to ground via electrical connectors such as wires or flexible circuit boards. That is, in other embodiments, the gate G, drain D and source S of each memory cell 11 can be connected to the corresponding word line WL or ground, bit line BL and ground without opening conductive vias, but can be connected through electrical connectors such as wires and flexible circuit boards.

[0059] Please refer to the following: Figure 6 This is a top view schematic diagram illustrating the structure of the storage cell 11 in a read-only memory array structure 1 according to an embodiment of this application. Figure 6 The example uses a 3x3 matrix structure.

[0060] like Figure 6 As shown, the source S and drain D of the memory cells 11 arranged in the same column are staggered. That is, the source S and drain D of the same memory cell 11 are respectively disposed on opposite sides of the substrate layer 111 in a predetermined direction, and their projections in the predetermined direction do not coincide. In other words, the source S and drain D of the same memory cell 11 are diagonally distributed in the region of the substrate layer 111 corresponding to the memory cell 11. The predetermined direction is the row direction.

[0061] like Figure 6 As shown, the source S of two adjacent memory cells 11 is shared, and / or the drain D of two adjacent memory cells 11 is shared. Specifically, as... Figure 6 As shown, when a certain storage cell 11 is not located in the first or last row, the storage cell 11 is located between two storage cells 11. The source S of the storage cell 11 is shared with the source S of an adjacent storage cell 11, and the drain D of the storage cell 11 is shared with the drain D of another adjacent storage cell 11 on the other side. Figure 6As shown, the drain D of the memory cell 11 in the first row is an independent drain, while only the source S is shared with the source S of the adjacent memory cell 11 in the second row. The source S of the memory cell 11 in the last row is an independent source, while only the drain D is shared with the drain D of the adjacent memory cell 11 in the second row.

[0062] That is, in this application, the source S of two adjacent memory cells 11 is shared, and / or the drain D of two adjacent memory cells 11 is shared. This also means that when there is an adjacent memory cell 11 on the side of the source S of each memory cell 11, the source S of the adjacent memory cell 11 is shared, and when there is an adjacent memory cell 11 on the side of the drain D of each memory cell 11, the drain D of the adjacent memory cell 11 is shared.

[0063] Therefore, in this application, by sharing the source S of two adjacent memory cells 11 and / or sharing the drain D of two adjacent memory cells 11, the size of the read-only memory array structure 1 can be effectively reduced.

[0064] Therefore, the read-only memory array structure 1 of this application, while storing data "0" or "1" as needed, can effectively reduce the number of memory cells 11 connected by word lines WL, reduce the load on word lines WL, and improve the overall performance of the read-only memory array structure 1. Furthermore, since the source S of two adjacent memory cells 11 is shared, and / or the drain D of two adjacent memory cells 11 is shared, the size of the read-only memory array structure 1 can be effectively reduced.

[0065] Please see Figure 7 This is a structural block diagram of chip 100 in one embodiment of this application. The chip 100 includes the aforementioned read-only memory array structure 1.

[0066] The chip 100 can be any chip including read-only memory devices, such as a processor chip, a memory chip, a graphics card chip, etc.

[0067] Please see Figure 8 This is a structural block diagram of an electronic device 200 according to an embodiment of this application. The electronic device 200 includes the chip 100.

[0068] The electronic device 200 may be a mobile phone, tablet computer, personal computer, server, wireless network device, vehicle device, etc., including the chip 100 with read-only memory device.

[0069] Please see Figure 9 The diagram below is a flowchart of an encoding method according to an embodiment of this application. The encoding method can be used to encode storage data generated by a read-only memory array structure. The encoding method includes the following steps:

[0070] Determine the data to be stored in each storage cell of the read-only memory array structure (S901).

[0071] Depending on whether the data stored in each memory cell is "0" or "1", the gate of each memory cell is connected to the corresponding word line or grounded (S903).

[0072] The read-only memory array structure includes m*n columns of storage units, where m and n are natural numbers greater than or equal to 1. Step S901 may include: determining whether the data to be stored in each storage unit is "1" or "0" based on the position of the storage unit in each row and column of the multi-bit data, according to the multi-bit data corresponding to the specific content to be stored in the read-only memory array structure. The multi-bit data may be one or more bytes, each byte including 8 bits of data, or it may be a data string including any number of bits, for example, 4 bits or 9 bits of data.

[0073] In some embodiments, the read-only memory array structure further includes m word lines, n bit lines, n first ground lines, and n second ground lines. Each memory cell includes a gate, a source, and a drain; each word line extends along the row direction through a corresponding row of memory cells; each bit line extends along the column direction through a corresponding column of memory cells and is connected to the drain of the corresponding column of memory cells; each first ground line extends along the column direction through a corresponding column of memory cells and is connected to the source of the corresponding column of memory cells; each second ground line extends along the column direction through a corresponding column of memory cells. Step S903 includes: when the data stored in a memory cell is "0", the gate of the memory cell is connected to the corresponding word line; when the data stored in a memory cell is "1", the gate of the memory cell is connected to the corresponding second ground line.

[0074] The statement that "when the data stored in a certain memory cell is "0", the gate of the memory cell is connected to the corresponding word line" may further include: when the data stored in a certain memory cell is "0", the gate of the memory cell is connected to the corresponding word line by forming a first conductive via. The statement that "when the data stored in a certain memory cell is "1", the gate of the memory cell is connected to the corresponding second ground line" may further include: when the data to be stored in a certain memory cell is "1", the gate is connected to the corresponding second ground line by forming a second conductive via.

[0075] The first conductive via and the second conductive via can be formed by chemical or physical drilling methods, such as laser drilling.

[0076] In some embodiments, the read-only memory array structure further includes n word line connecting strips, each word line connecting strip extending along the column direction through a corresponding column of memory cells, and the n word line connecting strips are parallel to and alternately disposed on the same layer as the n second ground lines. Each memory cell further includes a gate connection line, the gate connection line being connected to the gate of the memory cell. The n word line connecting strips and the n second ground lines are disposed on the side of the memory cell where the gate connection line is disposed, and the m word lines are disposed on the side of the n word line connecting strips opposite to the memory cell.

[0077] The step "when the data stored in a certain memory cell is "0", the gate of the memory cell is connected to the corresponding word line by forming a first conductive via" may further include: when the data stored in a certain memory cell is "0", a first conductive via is opened on the corresponding word line WL and a second conductive via is opened at the position where it intersects with the gate connection line on the corresponding word line connection strip. The second conductive via is connected to the first conductive via to form the first conductive via, so that the word line is connected to the gate connection line through the first conductive via and the second conductive via, thereby connecting the gate of the memory cell to the corresponding word line.

[0078] The phrase "when the data to be stored in a certain storage cell is "1", the gate is connected to the corresponding second ground line through the formed second conductive via" can specifically include: when the data stored in a certain storage cell is "1", the second conductive via is opened at the position where it intersects with the gate connection line on the corresponding second ground line, so that the second ground line is connected to the gate connection line, thereby connecting the gate of the storage cell to the corresponding second ground line.

[0079] Therefore, during the manufacturing process of the read-only memory array structure 1, the data to be stored in each storage cell can be determined as "0" or "1" based on the multi-bit data corresponding to the specific content to be stored in the read-only memory array structure and the position of the storage cell in each row and column of the multi-bit data. Then, by forming the aforementioned first conductive via or second conductive via, the gate of the storage cell can be connected to the corresponding word line to store the data "0", or the gate of the storage cell can be connected to the corresponding second ground line to store the data "1".

[0080] Specifically, the encoding method of this application can be used to manufacture the aforementioned read-only memory array structure 1. The content of the encoding method and the content of the read-only memory array structure 1 can be referenced to each other. For more specific details, please refer to the aforementioned description of the read-only memory array structure 1.

[0081] This application also provides a computer storage medium storing a computer program for electronic data interchange, which causes a computer to perform some or all of the steps of any of the methods described in the above method embodiments, wherein the computer includes an electronic device.

[0082] This application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods described in the above method embodiments. The computer program product may be a software installation package, and the computer may include an electronic device.

[0083] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0084] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0085] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0086] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0087] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0088] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0089] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: flash drive, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0090] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A read-only memory array structure, characterized in that, include: There are m*n memory cells arranged in a matrix. Each memory cell includes a gate, a source, and a drain, where m and n are natural numbers greater than or equal to 1. m word lines correspond one-to-one with m rows of storage units; There are n bit lines, each corresponding to one of the n columns of memory cells, and each bit line is connected to the drain of the memory cell in the corresponding column. In this configuration, the source of each memory cell is grounded; depending on whether the data stored in each memory cell is "0" or "1", the gate of each memory cell is connected to the corresponding word line or grounded. Each word line extends along the row direction through a corresponding row of storage units; Each bit line extends along the column direction through a corresponding column of memory cells; The read-only memory array structure also includes: There are n first ground lines, each of which extends along the column direction through a corresponding column of memory cells and is connected to the source of the memory cell in the corresponding column to ground the source of each memory cell. There are n second ground lines, each of which extends along the column direction through a corresponding column of memory cells. Depending on whether the data stored in each memory cell is "0" or "1", the gate of each memory cell is connected to the corresponding word line or to the corresponding second ground line to be grounded. When the data stored in a certain memory cell is "0", the gate of the memory cell is connected to the corresponding word line. When the data stored in a certain memory cell is "1", the gate of the memory cell is connected to the corresponding second ground line.

2. The read-only memory array structure according to claim 1, characterized in that, The gate of the memory cell is connected to the corresponding word line through a first conductive via, and the gate of the memory cell is connected to the corresponding second ground line through a second conductive via.

3. The read-only memory array structure according to claim 2, characterized in that, The read-only memory array structure further includes n word line connecting strips, each extending along the row direction through a corresponding column of memory cells. The n word line connecting strips are parallel to and alternately arranged on the same layer as the n second ground lines. Each memory cell also includes a gate connection line connected to the gate of the memory cell. The n word line connecting strips and the n second ground lines are located on the side of the memory cell where the gate connection line is located. The m word lines are located on the side of the n word line connecting strips opposite to the memory cell. When the data stored in a memory cell is "0", a first conductive electronic via is opened on the corresponding word line. A second conductive via is formed at the position where it intersects with the gate connection line on the corresponding word line connection strip. The second conductive via is connected to the first conductive via to form the first conductive via, so that the word line is connected to the gate connection line through the first conductive via and the second conductive via, thereby connecting the gate of the memory cell to the corresponding word line. When the data stored in a memory cell is "1", the second conductive via is formed at the position where it intersects with the gate connection line on the corresponding second ground line, so that the second ground line is connected to the gate connection line, thereby connecting the gate of the memory cell to the corresponding second ground line.

4. The read-only memory array structure according to claim 3, characterized in that, Each word line, each second ground line, and each word line connecting strip are conductive wires wrapped with insulating material. The gate connecting line is an exposed conductive wire. When the word line has a first conductive via, the word line can be electrically connected through the first conductive via. When the word line connecting strip has a second conductive via, the word line connecting strip can be electrically connected through the second conductive via. When the second ground line has a second conductive via, the second ground line can be electrically connected through the second conductive via.

5. The read-only memory array structure according to claim 3, wherein the gate connection lines extend along the row direction, and the read-only memory array structure further includes a gate disconnect layer extending along the column direction for separating the gate connection lines of different memory cells.

6. The read-only memory array structure according to any one of claims 1-5, characterized in that, In the same column of memory cells, the source of two adjacent memory cells is shared, and / or the drain of two adjacent memory cells is shared.

7. A chip, characterized in that, The chip includes a read-only memory array structure as described in any one of claims 1-6.

8. An electronic device, characterized in that, The electronic device includes the chip as described in claim 7.

9. An encoding method, characterized in that, The encoding method for encoding storage data to generate a read-only memory array structure includes: Determine the data to be stored in each storage unit; Depending on whether the data stored in each memory cell is "0" or "1", the gate of each memory cell is connected to the corresponding word line or grounded. The read-only memory array structure includes m*n memory cells arranged in a matrix, m word lines, n bit lines, n first ground lines, and n second ground lines. Each memory cell includes a gate, a source, and a drain, where m and n are natural numbers greater than or equal to 1. The m word lines correspond one-to-one with m rows of memory cells, and the n bit lines correspond one-to-one with n columns of memory cells, with each bit line connected to the drain of the corresponding column of memory cells. Each word line extends along the row direction through a corresponding row of memory cells; each bit line extends along the column direction through a corresponding column of memory cells and connects to the drain of the corresponding column of memory cells; each first ground line extends along the column direction through a corresponding column of memory cells and connects to the source of the corresponding column of memory cells; and each second ground line extends along the column direction through a corresponding column of memory cells. The step of controlling the connection or grounding of the gate of each memory cell to the corresponding word line based on whether the data stored in each memory cell is "0" or "1" includes: Depending on whether the data stored in each memory cell is "0" or "1", control the gate of each memory cell to be connected to the corresponding word line or to the corresponding second ground line to be grounded, including: when the data stored in a memory cell is "0", control the gate of the memory cell to be connected to the corresponding word line; when the data stored in a memory cell is "1", control the gate of the memory cell to be connected to the corresponding second ground line.

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