A semiconductor substrate and a method of forming the same

Abstract

The present application provides a semiconductor substrate and a forming method thereof. The forming method forms a total polysilicon thin layer by forming a first polysilicon thin layer and a second polysilicon thin layer in stages, so that the total polysilicon thin layer has lower stress, more random grain orientation and smaller grain size, maintains high grain boundary density, and improves interlayer charge trapping capability. The interaction of the polysilicon thin layers grown at different deposition temperatures and the combination of two cooling rates after each constant temperature annealing process slow down the shrinkage rate between the first polysilicon thin layer, the second polysilicon thin layer and the initial semiconductor substrate, reduce the degree of thermal expansion mismatch of the semiconductor substrate, reduce the stretching degree between the polysilicon thin layer and the initial semiconductor substrate, further reduce the warpage of the semiconductor substrate, and further reduce the stress generated in the growth process of the polysilicon thin layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a semiconductor substrate and a forming method thereof. BACKGROUND

[0002] The polycrystalline silicon thin layer can provide strong charge capture ability due to its internal texture characteristics and high grain boundary density characteristics, and is applied to the basic substrate material in the radio frequency field as a trap-rich layer to capture the residual free charge under the action of high frequency. The internal grain boundary and stress distribution of the polycrystalline silicon thin layer substrate are the key to the overall quality of the polycrystalline silicon thin layer substrate. Since the polycrystalline silicon will have preferred orientation and grain aggregation phenomenon during epitaxial growth, the grain boundary at different thickness levels will have different density distribution. The total grain boundary number of the polycrystalline silicon can directly determine the final charge capture ability. Due to the lattice mismatch and the difference in thermal expansion coefficient between the polycrystalline silicon thin layer and the single crystal silicon substrate, there is a large stress between the polycrystalline silicon thin layer and the single crystal silicon substrate of the polycrystalline silicon thin layer substrate, so that the deposition of the polycrystalline silicon thin layer substrate will have a certain degree of bending and warping, and with the increase of the thickness of the polycrystalline silicon thin layer, the warping and bending of the polycrystalline silicon thin layer substrate will also increase. In addition, the size of the polycrystalline silicon grains inside the polycrystalline silicon thin layer and the existence of defects and impurities will also affect the stress and warping of the semiconductor substrate. High warping and high stress will also affect the subsequent process flow, limiting the application of semiconductor substrates with polycrystalline silicon thin layers. SUMMARY

[0003] The purpose of the present application is to provide a semiconductor substrate and a forming method thereof to reduce the stress generated during the formation of the polycrystalline silicon thin layer, thereby reducing the bending and warping of the semiconductor substrate.

[0004] In order to achieve the above-mentioned purpose, the present application provides a forming method of a semiconductor substrate, comprising the following steps:

[0005] S1: providing an initial semiconductor substrate, wherein a first surface oxide layer is formed on the initial semiconductor substrate;

[0006] S2: forming a first polycrystalline silicon thin layer on the first surface oxide layer at a first target temperature;

[0007] S3: increasing the temperature from the first target temperature to a second target temperature, and performing a constant temperature annealing process on the initial semiconductor substrate at the second target temperature;

[0008] S4: starting the first cooling from the second target temperature, and starting the first natural cooling of the semiconductor substrate when the first cooling is cooled to the first target temperature, wherein the cooling rate of the first cooling is smaller than the cooling rate of the first natural cooling;

[0009] S5: oxidizing the surface of the first polysilicon thin layer to thin the thickness of the first polysilicon thin layer and form a second surface oxide layer;

[0010] S6: forming a second polysilicon thin layer on the second surface oxide layer at a third target temperature to form a semiconductor substrate;

[0011] S7: increasing the temperature from the third target temperature to a fourth target temperature and performing a constant temperature annealing process on the semiconductor substrate at the fourth target temperature; and

[0012] S8: starting a second temperature decrease from the fourth target temperature and starting a second natural temperature decrease on the semiconductor substrate when the temperature decreases to the third target temperature, wherein the temperature decrease rate of the second temperature decrease is smaller than the temperature decrease rate of the second natural temperature decrease.

[0013] Optionally, the step S2 comprises:

[0014] putting the initial semiconductor substrate into a CVD reaction chamber and starting a first temperature increase until the temperature reaches a first target temperature;

[0015] growing a first polysilicon thin layer on the first surface oxide layer by using an atmospheric pressure chemical vapor deposition method at the first target temperature; and

[0016] wherein the atmosphere of the first temperature increase is a hydrogen atmosphere and the atmosphere is switched to a mixed atmosphere of hydrogen and trichlorosilane when the temperature reaches the first target temperature.

[0017] Further, the gas flow of hydrogen during the first temperature increase is 40 slm-80 slm; the gas flow of hydrogen in the mixed atmosphere is 40 slm-80 slm, the gas flow of trichlorosilane is 3 slm-12 slm, and the first target temperature is 900°C-1000°C.

[0018] Further, the step S3 comprises:

[0019] starting a second temperature increase while switching the atmosphere to a hydrogen atmosphere, and starting a constant temperature annealing process on the initial semiconductor substrate when the second temperature increase reaches a second target temperature, wherein the second target temperature is 1050°C-1200°C.

[0020] Optionally, the step S4 comprises:

[0021] starting a first temperature decrease in the CVD reaction chamber while keeping the atmosphere as a hydrogen atmosphere;

[0022] when the second target temperature is decreased to the first target temperature, the initial semiconductor substrate is taken out of the CVD reaction chamber; and

[0023] the semiconductor substrate is subjected to a first natural temperature decrease in an external environment, wherein the first natural temperature decrease has a temperature decrease rate of 0.5-3℃ / s.

[0024] Optionally, step S5 comprises:

[0025] the thickness of the first polysilicon thin layer is thinned by natural placement, and a second surface oxide layer is formed on the first polysilicon thin layer, wherein the thickness of the second surface oxide layer is 1-1.5nm; or

[0026] the thickness of the first polysilicon thin layer is thinned by an oxidation process in a dry oxygen and / or wet oxygen atmosphere, and a second surface oxide layer is formed on the first polysilicon thin layer, wherein the thinned first polysilicon thin layer has a thickness of 1-1.5nm.

[0027] Optionally, step S6 comprises:

[0028] the initial semiconductor substrate device is put into a CVD reaction chamber, and a third temperature increase is started until the temperature reaches a third target temperature;

[0029] at the third target temperature, a second polysilicon thin layer is grown on the second surface oxide layer by an atmospheric pressure chemical vapor deposition method to form a semiconductor substrate; and

[0030] wherein the third temperature increase is in a hydrogen atmosphere, and when the temperature reaches the third target temperature, the atmosphere is switched to a mixed atmosphere of hydrogen and trichlorosilane.

[0031] Further, the hydrogen gas flow rate during the third temperature increase is 40-80slm; the hydrogen gas flow rate in the mixed atmosphere is 40-80slm, the trichlorosilane gas flow rate is 3-12slm, and the third target temperature is 900-1000℃.

[0032] Further, step S7 comprises:

[0033] a fourth temperature increase is started, and the atmosphere is switched to a hydrogen atmosphere, and when the fourth temperature increase reaches a fourth target temperature, a constant temperature annealing treatment is started on the semiconductor substrate, wherein the fourth target temperature is 1050-1200℃.

[0034] Optionally, step S8 comprises:

[0035] The second temperature reduction is started in the CVD reaction chamber while the atmosphere is kept as a hydrogen atmosphere;

[0036] When the fourth target temperature is reduced to the third target temperature, the semiconductor substrate is transferred out of the CVD reaction chamber; and

[0037] The semiconductor substrate is subjected to a second natural temperature reduction in an external environment, wherein the second natural temperature reduction has a temperature reduction rate of 0.5-3℃ / s.

[0038] In another aspect, the present application also provides a semiconductor substrate prepared by the above method.

[0039] Compared with the prior art, the present application has at least the following technical effects:

[0040] The application provides a semiconductor substrate and a forming method thereof, the forming method comprises the following steps: S1, providing an initial semiconductor substrate, a first surface oxide layer is formed on the initial semiconductor substrate; S2, forming a first polysilicon thin layer on the first surface oxide layer at a first target temperature; S3, increasing the temperature from the first target temperature to a second target temperature, and performing a constant temperature annealing treatment on the initial semiconductor substrate at the second target temperature; S4, starting the first cooling from the second target temperature, and starting the first natural cooling of the semiconductor substrate when the first cooling is cooled to the first target temperature, wherein the cooling rate of the first cooling is smaller than that of the first natural cooling; S5, performing an oxidation treatment on the surface of the first polysilicon thin layer to thin the thickness of the first polysilicon thin layer and form a second surface oxide layer; S6, forming a second polysilicon thin layer on the second surface oxide layer at a third target temperature to form a semiconductor substrate; S7, increasing the temperature from the third target temperature to a fourth target temperature, and performing a constant temperature annealing treatment on the semiconductor substrate at the fourth target temperature; and S8, starting the second cooling from the fourth target temperature, and starting the second natural cooling of the semiconductor substrate when the second cooling is cooled to the third target temperature, wherein the cooling rate of the second cooling is smaller than that of the second natural cooling. The application forms the first polysilicon thin layer and the second polysilicon thin layer to form the total polysilicon thin layer in batches, so that the initial semiconductor substrate has lower stress with the polysilicon thin layer, the grain orientation of the polysilicon thin layer is more random and the grain size is smaller, the high grain boundary density of the polysilicon thin layer is maintained, the polysilicon thin layer formed by two times of epitaxy can have smaller lattice mismatch effect under the same thickness requirement compared with the polysilicon thin layer formed once, so that the overall stress is reduced, the shrinkage rate between the first polysilicon thin layer and the second polysilicon thin layer and the initial semiconductor substrate is slowed down by combining the two cooling rates (i.e. the first cooling in CVD and the first natural cooling in the natural environment, and the second cooling in CVD and the second natural cooling in the natural environment) after each constant temperature annealing treatment, the degree of thermal expansion mismatch of the semiconductor substrate is reduced, the stretching degree between the polysilicon thin layer and the initial semiconductor substrate is reduced, the warpage of the semiconductor substrate is further reduced, and the stress generated in the growth process of the polysilicon thin layer is further reduced. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 It is a flowchart of a forming method of a semiconductor substrate according to an embodiment of the application;

[0042] Figure 2a It is a structural schematic diagram of an initial semiconductor substrate according to an embodiment of the application;

[0043] Figure 2b is a structural schematic diagram of an initial semiconductor substrate after forming a first polysilicon thin layer according to an embodiment of the present application;

[0044] Figure 2c is a structural schematic diagram of a semiconductor substrate after forming a second surface oxide layer according to an embodiment of the present application;

[0045] Figure 2d is a structural schematic diagram of a semiconductor substrate after forming a second polysilicon thin layer according to an embodiment of the present application;

[0046] Figure 3 is a temperature-time curve diagram of a semiconductor substrate forming process according to an embodiment of the present application.

[0047] BRIEF DESCRIPTION OF DRAWINGS

[0048] 100 - initial semiconductor substrate; 110 - first surface oxide layer; 120 - first polysilicon thin layer; 130 - second surface oxide layer; 140 - second polysilicon thin layer; Tl - first target temperature; T2 - second target temperature. DETAILED DESCRIPTION

[0049] A semiconductor substrate and a method for forming the same according to the present application will be described in further detail below. The present application will be described in more detail with reference to the accompanying drawings, in which the preferred embodiments of the present application are shown. It should be understood that the present application can be modified in various ways by one skilled in the art and still achieve the advantages of the present application. Therefore, the following description should be understood not necessarily to limit the scope of the application, but to explain the broadest scope of the present application to a person having ordinary skill in the art.

[0050] For clarity, not all of the features of an actual implementation can be described in this description. In the following description, numerous specific details are set forth to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without such specific details. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring the present application. It should be understood that the detailed description and specific examples, while indicating preferred embodiments of the application, are intended for purposes of illustration only and are not intended to limit the scope of the application.

[0051] To make the objects, features and characteristics of the present application more apparent, specific embodiments of the present application will be described in further detail below with reference made to the accompanying drawings. It should be noted that the drawings are very simplified and use non-precise ratios, and are only used to facilitate and clarify the purpose of explaining the embodiments of the present application.

[0052] Figure 1 is a flowchart of a method for forming a semiconductor substrate according to an embodiment of the present application. As shown in FIG. 1, the method for forming a semiconductor substrate according to the present application includes the following steps: Figure 1As shown, the embodiment provides a method for forming a semiconductor substrate, comprising the following steps:

[0053] S1: providing an initial semiconductor substrate, wherein a first surface oxide layer is formed on the initial semiconductor substrate;

[0054] S2: forming a first polysilicon thin layer on the first surface oxide layer at a first target temperature;

[0055] S3: increasing the temperature from the first target temperature to a second target temperature, and performing a constant temperature annealing process on the initial semiconductor substrate at the second target temperature;

[0056] S4: starting a first temperature decreasing from the second target temperature, and starting a first natural temperature decreasing on the semiconductor substrate when the first temperature decreasing to the first target temperature, wherein the temperature decreasing rate of the first temperature decreasing is smaller than that of the first natural temperature decreasing;

[0057] S5: performing an oxidation process on the surface of the first polysilicon thin layer to thin the thickness of the first polysilicon thin layer, and forming a second surface oxide layer;

[0058] S6: forming a second polysilicon thin layer on the second surface oxide layer at a third target temperature to form a semiconductor substrate;

[0059] S7: increasing the temperature from the third target temperature to a fourth target temperature, and performing a constant temperature annealing process on the semiconductor substrate at the fourth target temperature; and

[0060] S8: starting a second temperature decreasing from the fourth target temperature, and starting a second natural temperature decreasing on the semiconductor substrate when the second temperature decreasing to the third target temperature, wherein the temperature decreasing rate of the second temperature decreasing is smaller than that of the second natural temperature decreasing.

[0061] The following will be described in detail Figures 1-3 The method for forming a semiconductor substrate disclosed in the embodiment will be described in detail.

[0062] Figure 2a is a structural schematic diagram of the initial semiconductor substrate provided in the embodiment. Figure 3 is a temperature-time curve diagram in the process of forming the semiconductor substrate in the embodiment. As shown in the diagram, Figure 2a and Figure 3As shown, step S1 is first performed, providing an initial semiconductor substrate 100 on which a first surface oxide layer 110 is formed. The initial semiconductor substrate 100 is, for example, a single-crystal silicon substrate, and the first surface oxide layer 110 is an oxide film formed by the natural oxidation of the single-crystal silicon substrate in an external environment (oxygen-containing environment). The thickness of the first surface oxide layer 110 is, for example, 1 nm to 1.5 nm.

[0063] Figure 2b This is a schematic diagram of the structure after the formation of the polycrystalline silicon thin layer in this embodiment. For example... Figure 2b As shown, please also refer to Figure 3 Then, step S2 is performed to form a polycrystalline silicon thin layer 120 on the first surface oxide layer 110 at the first target temperature T1.

[0064] This step specifically includes:

[0065] First, the initial semiconductor substrate 100 is placed into the CVD reaction chamber, where the device temperature is 500℃~800℃, the device atmosphere is a hydrogen atmosphere, and the gas flow rate of the device atmosphere is 40slm~80slm.

[0066] Next, the first heating begins until the temperature reaches the first target temperature T1. The atmosphere for the first heating is maintained as a hydrogen atmosphere, and the gas flow rate of the first heating atmosphere remains at 40 slm to 80 slm. The first target temperature T1 is 900℃ to 1000℃.

[0067] Next, upon reaching the first target temperature T1 for the first time, the process enters the first stage I (specifically, the first isothermal stage). At the first target temperature T1, the atmosphere of the first stage is switched to a mixed atmosphere of hydrogen and trichlorosilane to grow a first polycrystalline silicon thin layer 120 on the first surface oxide layer 110 using atmospheric pressure chemical vapor deposition. The hydrogen gas flow rate is 40 slm to 80 slm, and the trichlorosilane gas flow rate is 3 slm to 12 slm.

[0068] Please continue reading. Figure 3 Next, step S3 is executed, raising the temperature from the first target temperature T1 to the second target temperature T2, and performing isothermal annealing on the initial semiconductor substrate 100 at the second target temperature T2. Specifically, the process proceeds to the second stage II to perform isothermal annealing on the initial semiconductor substrate 100. The second stage II includes a second heating stage and a second isothermal stage.

[0069] This step specifically includes:

[0070] The second temperature rising is started to enter the second temperature rising stage, and the atmosphere is switched to the hydrogen atmosphere, and the second constant temperature stage is entered when the second temperature rising to the second target temperature T2, the atmosphere of the second constant temperature stage is kept as the hydrogen atmosphere, the second target temperature T2 is 1050-1200℃, to perform the constant temperature annealing treatment to the initial semiconductor substrate 100, to release the stress between the first polysilicon thin layer 120 and the initial semiconductor substrate 100, to improve the warping and bending of the initial semiconductor substrate 100.

[0071] Please continue to see Figure 3 , then step S4 is executed to enter the cooling stage III, in detail, the first temperature rising is started from the second target temperature T2, and the first natural cooling is started to the initial semiconductor substrate 100 when the first temperature rising to the first target temperature T1, wherein the temperature rising speed of the first temperature rising is smaller than that of the first natural cooling. The first natural cooling is started from the first target temperature T1 in this step, the temperature rising speed of the initial semiconductor substrate 100 is slowed down, the shrinkage speed between the first polysilicon thin layer 120 and the initial semiconductor substrate 100 is slowed down, the degree of thermal expansion mismatch of the initial semiconductor substrate 100 is reduced, the stretching degree between the first polysilicon thin layer 120 and the initial semiconductor substrate 100 is reduced, the warping of the initial semiconductor substrate 100 is further reduced, and the stress generated in the growth process of the first polysilicon thin layer is further reduced.

[0072] This step specifically includes:

[0073] The first temperature rising is started in the CVD reaction chamber, and the atmosphere is kept as the hydrogen atmosphere, and the temperature rising speed is slow, and the temperature rising speed is usually the normal temperature rising speed in the CVD. When the temperature rising from the second target temperature T2 to the first target temperature T1, the initial semiconductor substrate 100 is taken out from the CVD reaction chamber, and the first natural cooling is slowly performed in the external environment, wherein the temperature rising speed of the first natural cooling is 0.5-3℃ / s.

[0074] Figure 2c is the structure schematic diagram of the semiconductor substrate after the second surface oxide layer is formed in this embodiment. As Figure 2c shown, then step S5 is executed to oxidize the surface of the first polysilicon thin layer 120 to thin the thickness of the first polysilicon thin layer 120, and the second surface oxide layer 130 is formed.

[0075] In detail, the step can be: the initial semiconductor substrate 100 is transferred into an oxidation furnace, and the surface of the first polysilicon thin layer 120 is oxidized under a dry oxygen and / or wet oxygen atmosphere (i.e. the oxidation atmosphere can be dry oxygen, wet oxygen or a mixture of dry oxygen and wet oxygen) to form a second surface oxide layer 130, and the oxidation temperature is 800-1000°C, preferably, the oxidation temperature is 900-950°C. The oxidation process thins the first polysilicon thin layer 120, and the thinned first polysilicon thin layer 120 has a thickness of 1-1.5 nm.

[0076] The step can also be: the initial semiconductor substrate 100 is placed in a natural environment, and the surface of the first polysilicon thin layer 120 reacts with oxygen in the natural environment to form a second surface oxide layer 130, which is a natural oxide layer, and the thickness of the generated natural oxide layer is 1-1.5 nm, and further, the thickness of the generated natural oxide layer is about 1.5 nm.

[0077] Figure 2d is a structural schematic diagram of the semiconductor substrate after the second polysilicon thin layer is formed in the embodiment. As shown in Figure 2d Step S6 is then performed, and a second polysilicon thin layer 140 is formed on the second surface oxide layer 130 at a third target temperature to form a semiconductor substrate.

[0078] The step specifically includes:

[0079] First, the initial semiconductor substrate 100 is again arranged into a CVD reaction chamber, wherein the device temperature is also 500-800°C, and the device atmosphere is also a hydrogen atmosphere, and the gas flow of the device atmosphere is also 40-80 slm.

[0080] Then, a third temperature rise is started until the temperature reaches a third target temperature, the third temperature rise atmosphere remains a hydrogen atmosphere, the gas flow of the third temperature rise atmosphere is still 40-80 slm, and the third target temperature is 900-1000°C.

[0081] Then, a third constant temperature stage is entered when the third temperature rise reaches the third target temperature, at the third target temperature, and the atmosphere of the third constant temperature stage is switched to a mixed atmosphere of hydrogen and trichlorosilane to grow a second polysilicon thin layer 140 on the second surface oxide layer 130 by using a normal pressure chemical vapor deposition method. Among them, the gas flow of hydrogen is 40-80 slm, and the gas flow of trichlorosilane is 3-12 slm. In the embodiment, the value of the third target temperature is the same as the value of the first target temperature.

[0082] Then, step S7 is performed, and the semiconductor substrate is subjected to a constant temperature annealing process at a fourth target temperature, which is increased from the third target temperature.

[0083] This step specifically includes:

[0084] The third temperature increase is started to enter the temperature increase phase, and the atmosphere is switched to a hydrogen atmosphere. When the fourth temperature increase to a fourth target temperature is started, a fourth constant temperature phase is entered, and the atmosphere is kept as a hydrogen atmosphere. The fourth target temperature is 1050°C to 1200°C. The initial semiconductor substrate 100 is subjected to a constant temperature annealing process, so that the stress between the second polysilicon thin layer 140 and the initial semiconductor substrate 100 is released, and the warpage and the bending of the initial semiconductor substrate 100 are improved. In this embodiment, the fourth target temperature has the same value as the second target temperature.

[0085] Then, step S8 is performed, and the semiconductor substrate is subjected to a second natural temperature decrease, when the second temperature decrease to the third target temperature is started. The temperature decrease rate of the second temperature decrease is smaller than that of the second natural temperature decrease. This step can slow down the temperature decrease rate of the initial semiconductor substrate 100, so that the shrinkage rate between the second polysilicon thin layer 140 and the initial semiconductor substrate 100 is slowed down, the thermal expansion mismatch degree of the initial semiconductor substrate 100 is further reduced, the stretching degree between the second polysilicon thin layer 140 and the initial semiconductor substrate 100 is reduced, and the warpage of the initial semiconductor substrate 100 is further reduced, so that the stress generated in the growth of the second polysilicon thin layer is further reduced.

[0086] This step specifically includes:

[0087] The second temperature decrease is started in the CVD reaction chamber, and the atmosphere is kept as a hydrogen atmosphere. The temperature decrease rate is fast, and is usually the normal temperature decrease rate in CVD. When the initial semiconductor substrate 100 is taken out of the CVD reaction chamber, and is subjected to a second natural temperature decrease in the external environment. The temperature decrease rate of the second natural temperature decrease is 0.5°C / s to 3°C / s.

[0088] In the initial stage of growth of the polycrystalline silicon thin layer, due to the random distribution of nucleation points, random crystal orientations are generated at the interface between the polycrystalline silicon thin layer and the natural oxide layer, thereby causing the generation of many twin boundaries, and further increasing the grain boundary density of the polycrystalline silicon thin layer. With the growth of the polycrystalline silicon thin layer (i.e. with the increase of the thickness of the polycrystalline silicon thin layer), the polycrystalline silicon thin layer gradually grows along the selective growth of part of the crystal orientation, i.e. the preferred orientation, and gradually evolves into columnar grains, so that the thickness distribution of the grain boundary density gradually flattens. The double-layer polycrystalline silicon thin layer (i.e. the first polycrystalline silicon thin layer and the second polycrystalline silicon thin layer) of the embodiment is formed by two growth processes, each polycrystalline silicon thin layer is always grown on the surface of the polycrystalline silicon close to the initial semiconductor substrate, and is in the high grain boundary density state in the initial stage. Compared with the prior art, the embodiment improves the number of grain boundaries of the polycrystalline silicon thin layer as a whole under the condition of the same thickness of the polycrystalline silicon thin layer, to a certain extent, can increase the charge capture probability and quantity, and also relieves the phenomenon of excessive warpage caused by the overall stress of the polycrystalline silicon thin layer.

[0089] The embodiment also provides a semiconductor substrate prepared by the above method.

[0090] In summary, the present application provides a semiconductor substrate and a forming method thereof, the forming method comprising the following steps: S1: providing an initial semiconductor substrate, the initial semiconductor substrate being formed with a first surface oxide layer; S2: forming a first polysilicon thin layer on the first surface oxide layer at a first target temperature; S3: increasing the temperature from the first target temperature to a second target temperature, and performing a constant temperature annealing treatment on the initial semiconductor substrate at the second target temperature; S4: starting a first temperature drop from the second target temperature, and starting a first natural temperature drop of the semiconductor substrate when the first temperature drop reaches the first target temperature, wherein the temperature drop rate of the first temperature drop is smaller than that of the first natural temperature drop; S5: performing an oxidation treatment on the surface of the first polysilicon thin layer to thin the thickness of the first polysilicon thin layer and form a second surface oxide layer; S6: forming a second polysilicon thin layer on the second surface oxide layer at a third target temperature to form a semiconductor substrate; S7: increasing the temperature from the third target temperature to a fourth target temperature, and performing a constant temperature annealing treatment on the semiconductor substrate at the fourth target temperature; and S8: starting a second temperature drop from the fourth target temperature, and starting a second natural temperature drop of the semiconductor substrate when the second temperature drop reaches the third target temperature, wherein the temperature drop rate of the second temperature drop is smaller than that of the second natural temperature drop. The present application forms a first polysilicon thin layer and a second polysilicon thin layer to form a total polysilicon thin layer in stages, so that the initial semiconductor substrate and the polysilicon thin layer have lower stress, and the grain orientation of the polysilicon thin layer is more random and the grain size is smaller, thereby maintaining the high grain boundary density of the polysilicon thin layer; the polysilicon thin layer formed by two times of epitaxy has smaller lattice mismatch effect than the thin film deposited by one time at the same thickness requirement, thereby reducing the overall stress; and the combination of the two temperature drop rates (i.e., the first temperature drop in CVD and the first natural temperature drop in a natural environment, and the second temperature drop in CVD and the second natural temperature drop in a natural environment) after each constant temperature annealing treatment slows down the shrinkage rate between the first polysilicon thin layer and the second polysilicon thin layer and the initial semiconductor substrate, reduces the degree of thermal expansion mismatch of the semiconductor substrate, reduces the stretching degree between the polysilicon thin layer and the initial semiconductor substrate, and further reduces the warpage of the semiconductor substrate, thereby further reducing the stress generated by the polysilicon thin layer during the growth process.

[0091] In addition, it should be noted that, unless specifically described or indicated, the terms "first", "second" in the specification are merely used to distinguish the components, elements, steps, etc. in the specification, and do not mean to indicate the logical relationship or sequence relationship between the components, elements, steps, etc.

[0092] It is to be understood that even though numerous characteristics and embodiments of the application have been set forth in the foregoing disclosure, the above disclosure is not intended to be exhaustive or limiting of the application. The application is intended to encompass all techniques capable of attaining the same or similar results as described herein. Accordingly, many modifications and variations of the application can be made without departing from its spirit or scope, as set forth in the appended claims.

Claims

1. A method for forming a semiconductor substrate, characterized in that, Includes the following steps: S1: Provide an initial semiconductor substrate, on which a first surface oxide layer is formed; S2: At the first target temperature, a first polycrystalline silicon thin layer is formed on the first surface oxide layer; S3: Raise the temperature from the first target temperature to the second target temperature, and perform isothermal annealing on the initial semiconductor substrate at the second target temperature; S4: In the CVD reaction chamber, the first cooling is performed starting from the second target temperature, and when the temperature drops to the first target temperature, the semiconductor substrate is transferred to the external environment, and the semiconductor substrate is subjected to the first natural cooling. The cooling rate of the first cooling is smaller than the cooling rate of the first natural cooling. S5: Oxidize the surface of the first polycrystalline silicon thin layer to reduce the thickness of the first polycrystalline silicon thin layer and form a second surface oxide layer; S6: At the third target temperature, a second polycrystalline silicon thin layer is formed on the second surface oxide layer to form a semiconductor substrate; S7: Raise the temperature from the third target temperature to the fourth target temperature, and perform isothermal annealing on the semiconductor substrate at the fourth target temperature; and S8: In the CVD reaction chamber, a second cooling process is performed starting from the fourth target temperature. When the temperature drops to the third target temperature, the semiconductor substrate is transferred to the external environment, and a second natural cooling process is started on the semiconductor substrate. The cooling rate of the second cooling process is smaller than the cooling rate of the second natural cooling process.

2. The method for forming a semiconductor substrate as described in claim 1, characterized in that, Step S2 includes: The initial semiconductor substrate device is placed into the CVD reaction chamber, and the first heating is started until the temperature reaches the first target temperature. At the first target temperature, a first polycrystalline silicon thin layer is grown on the first surface oxide layer using atmospheric pressure chemical vapor deposition; and The atmosphere for the first heating is a hydrogen atmosphere, and when the temperature reaches the first target temperature, the atmosphere is switched to a mixed atmosphere of hydrogen and trichlorosilane.

3. The method for forming a semiconductor substrate as described in claim 2, characterized in that, The hydrogen gas flow rate during the first heating is 40 slm to 80 slm; the hydrogen gas flow rate in the mixed atmosphere is 40 slm to 80 slm; the trichlorosilane gas flow rate is 3 slm to 12 slm; and the first target temperature is 900℃ to 1000℃.

4. The method for forming a semiconductor substrate as described in claim 2, characterized in that, Step S3 includes: The second heating process begins, and the atmosphere is switched to a hydrogen atmosphere. When the second heating reaches the second target temperature, the initial semiconductor substrate is subjected to isothermal annealing, wherein the second target temperature is 1050℃~1200℃.

5. The method for forming a semiconductor substrate as described in claim 1, characterized in that, Step S4 includes: The first cooling process begins in the CVD reaction chamber, while the atmosphere is maintained as hydrogen. When the second target temperature is cooled to the first target temperature, the initial semiconductor substrate is removed from the CVD reaction chamber; and The semiconductor substrate is subjected to a first natural cooling in the external environment, wherein the cooling rate of the first natural cooling is 0.5℃ / s to 3℃ / s.

6. The method for forming a semiconductor substrate as described in claim 1, characterized in that, Step S5 includes: The thickness of the first polycrystalline silicon thin layer is reduced by natural placement, and a second surface oxide layer is formed on the first polycrystalline silicon thin layer, wherein the thickness of the second surface oxide layer is 1 nm to 1.5 nm; or, In a dry oxygen and / or wet oxygen atmosphere, the thickness of the first polycrystalline silicon thin layer is reduced by an oxidation process, and a second surface oxide layer is formed on the first polycrystalline silicon thin layer, wherein the thickness of the first polycrystalline silicon thin layer after reduction is 1 nm to 1.5 nm.

7. The method for forming a semiconductor substrate as described in claim 1, characterized in that, Step S6 includes: The initial semiconductor substrate device is placed into the CVD reaction chamber, and the third heating is started until the temperature reaches the third target temperature; At the third target temperature, a second polycrystalline silicon thin layer is grown on the second surface oxide layer using atmospheric pressure chemical vapor deposition to form a semiconductor substrate; and The atmosphere for the third heating is a hydrogen atmosphere, and when the temperature reaches the third target temperature, the atmosphere is switched to a mixed atmosphere of hydrogen and trichlorosilane.

8. The method for forming a semiconductor substrate as described in claim 7, characterized in that, The hydrogen gas flow rate during the third heating is 40 slm to 80 slm; the hydrogen gas flow rate in the mixed atmosphere is 40 slm to 80 slm; the trichlorosilane gas flow rate is 3 slm to 12 slm; and the third target temperature is 900℃ to 1000℃.

9. The method for forming a semiconductor substrate as described in claim 7, characterized in that, Step S7 includes: The fourth heating process begins, and the atmosphere is switched to hydrogen. When the fourth heating reaches the fourth target temperature, the semiconductor substrate is subjected to isothermal annealing, wherein the fourth target temperature is 1050℃~1200℃.

10. The method for forming a semiconductor substrate as claimed in claim 1, characterized in that, Step S8 includes: The second cooling process begins in the CVD reaction chamber, while the atmosphere remains hydrogen. When the fourth target temperature is cooled to the third target temperature, the semiconductor substrate is removed from the CVD reaction chamber; and The semiconductor substrate is subjected to a second natural cooling in the external environment, wherein the cooling rate of the second natural cooling is 0.5℃ / s to 3℃ / s.

11. A semiconductor substrate, characterized in that, It is prepared by the forming method according to any one of claims 1 to 10.

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