Semiconductor devices

Abstract

A semiconductor device includes a substrate, a first semiconductor layer, a second semiconductor layer, a first, a second, and a third insulating layer, and a first and a second conductive layer. The first semiconductor layer is disposed on the substrate and has a first portion. The first insulating layer is disposed on the first semiconductor layer. The first conductive layer is disposed on the first insulating layer and has a first portion. The second insulating layer is disposed on the first conductive layer. The second semiconductor layer is disposed on the second insulating layer and has a first portion. The first portion of the first semiconductor layer, the first portion of the first conductive layer, and the first portion of the second semiconductor layer are sequentially arranged in a direction away from the substrate. The third insulating layer is disposed on the second semiconductor layer. The second conductive layer is disposed on the third insulating layer. The second conductive layer has a first, a second, a third, and a fourth portion. The first and second portions of the second conductive layer are separated from each other and are electrically connected to two different regions of the first portion of the first semiconductor layer through a plurality of contact windows of the third insulating layer. The third and fourth portions of the second conductive layer are separated from each other and are electrically connected to two different regions of the first portion of the second semiconductor layer through the plurality of contact windows.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] The micro-LED display panel includes a driving backplane and a plurality of micro-LED elements transferred to the driving backplane. Inheriting the characteristics of LEDs, the micro-LED display panel has the advantages of power saving, high efficiency, high brightness and fast response time. In addition, compared with the organic light-emitting diode display panel, the micro-LED display panel also has the advantages of easy color adjustment, long light-emitting life and no image burn-in. Therefore, the micro-LED display panel is regarded as the next generation of display technology.

[0003] Micro LED components are current-driven components, so the driving transistor in the driving backplane must be able to provide a large current. Generally speaking, the current that the driving transistor can provide is related to the layout area of ​​the driving transistor. However, when the resolution of the micro LED display panel is improved, the layout area of ​​the driving transistor is limited. Therefore, how to realize a driving transistor that can provide a large current within a limited layout area is a major challenge for researchers. Summary of the invention

[0004] The present invention provides a semiconductor device with excellent characteristics.

[0005] The semiconductor device of the present invention comprises a substrate, a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second semiconductor layer, a third insulating layer and a second conductive layer. The first semiconductor layer is disposed on the substrate and has a first portion. The first insulating layer is disposed on the first semiconductor layer. The first conductive layer is disposed on the first insulating layer and has a first portion. The second insulating layer is disposed on the first conductive layer. The second semiconductor layer is disposed on the second insulating layer and has a first portion. The first portion of the first semiconductor layer, the first portion of the first conductive layer and the first portion of the second semiconductor layer are sequentially disposed in a direction away from the substrate. The third insulating layer is disposed on the second semiconductor layer. The second conductive layer is disposed on the third insulating layer. The second conductive layer has a first portion, a second portion, a third portion and a fourth portion. The first portion and the second portion of the second conductive layer are separated from each other and are electrically connected to two different regions of the first portion of the first semiconductor layer through a plurality of contact windows of the third insulating layer. The third portion and the fourth portion of the second conductive layer are separated from each other and are electrically connected to two different regions of the first portion of the second semiconductor layer through a plurality of contact windows of the third insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a cross-sectional schematic diagram of a semiconductor device 10 according to an embodiment of the present invention;

[0007] Figure 2is a cross-sectional schematic diagram of a semiconductor device 10A according to an embodiment of the present invention;

[0008] Figure 3 is a partially enlarged schematic diagram of a semiconductor device 10A according to an embodiment of the present invention;

[0009] Figure 4 is a partially enlarged schematic diagram of a semiconductor device 10B according to an embodiment of the present invention;

[0010] Figure 5 is a partially enlarged schematic diagram of a semiconductor device 10C according to an embodiment of the present invention;

[0011] Figure 6 is a cross-sectional schematic diagram of a semiconductor device 10D according to an embodiment of the present invention;

[0012] Figure 7 is a top view schematically showing a semiconductor device 10D according to an embodiment of the present invention;

[0013] Figure 8 is a cross-sectional schematic diagram of a semiconductor device 10E according to an embodiment of the present invention;

[0014] Fig. 9 FIG. 1 is a circuit diagram of a semiconductor device 10E according to an embodiment of the present invention.

[0015] Explanation of symbols

[0016] 10, 10A, 10B, 10C, 10D, 10E: Electronic devices

[0017] 110:Substrate

[0018] 120: first semiconductor layer

[0019] 121, 141, 161, 181, 201: Part 1

[0020] 122, 142, 162, 182, 202: Part 2

[0021] 123, 143, 183, 203: Part 3

[0022] 130: first insulating layer

[0023] 131, 132, 135, 136, 151, 152, 155, 156, 157, 158, 159, 171, 172, 173, 174, 175, 176, 177, 178, 179, 191, 192, 193, 194, 195, 196, 197: contact window

[0024] 140: first conductive layer

[0025] 150: Second insulation layer

[0026] 160: Second semiconductor layer

[0027] 161a: First sublayer

[0028] 161a-1, 161a-2: doping region

[0029] 161b: Second sublayer

[0030] 161b-1, 161b-2: doping area

[0031] 170: Fourth insulation layer

[0032] 180: third conductive layer

[0033] 190: The third insulation layer

[0034] 200: second conductive layer

[0035] 204: Part 4

[0036] 205: Part 5

[0037] 206: Part 6

[0038] 207: Part 7

[0039] 210, 210C: fifth insulating layer

[0040] BS-TFT: Back-side Sub-Transistor

[0041] C1: First capacitor

[0042] C2: Second capacitor

[0043] C st : Storage capacitor

[0044] E1, E2, E3, E4: Electrodes

[0045] FS-TFT: Front Side Sub-Transistor

[0046] L1: First length

[0047] L2: Second length

[0048] MUX: Multiplexer

[0049] R: Local

[0050] T1, T2, T D , T S :transistor

[0051] W1: First width

[0052] W2: Second width

[0053] x: first arrangement direction

[0054] y: Second arrangement direction

[0055] z: direction

[0056] I-I': section line DETAILED DESCRIPTION

[0057] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0058] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it may be directly on or connected to another element, or an intermediate element may also exist. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements. As used herein, "connection" may refer to physical and / or electrical connection. Furthermore, "electrical connection" or "coupling" may be the presence of other elements between two elements.

[0059] As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within an acceptable deviation range of the particular value determined by one of ordinary skill in the art, taking into account the measurement in question and the particular amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately", or "substantially" can select a more acceptable deviation range or standard deviation depending on the optical property, etching property or other property, and can apply to all properties without a single standard deviation.

[0060] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present invention, and will not be interpreted as an idealized or overly formal meaning unless explicitly defined as such herein.

[0061] Figure 1 FIG. 1 is a schematic cross-sectional view of a semiconductor device 10 according to an embodiment of the present invention.

[0062] Please refer to Figure 1The semiconductor device 10 includes a substrate 110. For example, in the present embodiment, the substrate 110 may be made of glass, quartz, organic polymer, or opaque / reflective material (eg, wafer, ceramic, or other applicable material), or other applicable materials.

[0063] The semiconductor device 10 further includes a first semiconductor layer 120 disposed on the substrate 110 and having a first portion 121. In the present embodiment, the first semiconductor layer 120 may further selectively have a second portion 122 and a third portion 123. In the present embodiment, the third portion 123 of the first semiconductor layer 120 may be separated from the first portion 121 and the second portion 122 of the first semiconductor layer 120, but the present invention is not limited thereto.

[0064] For example, in this embodiment, the material of the first semiconductor layer 120 may be polycrystalline silicon. However, the present invention is not limited thereto, and in other embodiments, the material of the first semiconductor layer 120 may also be amorphous silicon, microcrystalline silicon, single crystal silicon, organic semiconductor material, oxide semiconductor material (e.g., indium zinc oxide, indium gallium zinc oxide, or other suitable materials, or a combination thereof), or other suitable materials, or dopants contained in the above materials, or a combination thereof.

[0065] The semiconductor device 10 further includes a first insulating layer 130 disposed on the first semiconductor layer 120. The first semiconductor layer 120 is located between the first insulating layer 130 and the substrate 110. In the present embodiment, the first insulating layer 130 may have a plurality of contact windows 131, 132 respectively overlapping two different regions of the first portion 121 of the first semiconductor layer 120. In the present embodiment, the first insulating layer 130 may also have a plurality of contact windows 135, 136 respectively overlapping two different regions of the second portion 122 of the first semiconductor layer 120.

[0066] For example, in the present embodiment, the material of the first insulating layer 130 may be an inorganic material (eg, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material, or a combination thereof.

[0067] The semiconductor device 10 further includes a first conductive layer 140 disposed on the first insulating layer 130. The first insulating layer 130 is located between the first conductive layer 140 and the first semiconductor layer 120. The first conductive layer 140 has a first portion 141. The first portion 121 of the first semiconductor layer 120 and the first portion 141 of the first conductive layer 140 are sequentially disposed along a direction z away from the substrate 110. In the present embodiment, the first conductive layer 140 may further include a second portion 142, wherein the second portion 122 of the first semiconductor layer 120 and the second portion 142 of the first conductive layer 140 are sequentially disposed along a direction z away from the substrate 110, and the second portion 142 of the first conductive layer 140 may be separated from the first portion 141 of the first conductive layer 140. In this embodiment, the first conductive layer 140 may also have a third portion 143, wherein the third portion 123 of the first semiconductor layer 120 and the third portion 143 of the first conductive layer 140 are sequentially arranged along a direction z away from the substrate 110, and the third portion 143 of the first conductive layer 140 may be separated from the first portion 141 and the second portion 142 of the first conductive layer 140.

[0068] In this embodiment, based on the consideration of conductivity, the first conductive layer 140 may be made of metal material. However, the present invention is not limited thereto, and in other embodiments, the first conductive layer 140 may also be made of other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or stacked layers of metal materials and other conductive materials.

[0069] The semiconductor device 10 further includes a second insulating layer 150 disposed on the first conductive layer 140. The first conductive layer 140 is located between the second insulating layer 150 and the first conductive layer 130. In the present embodiment, the second insulating layer 150 may have a plurality of contact windows 151, 152, respectively overlapping the plurality of contact windows 131, 132 of the first conductive layer 130. In the present embodiment, the second insulating layer 150 may further have a plurality of contact windows 155, 156, respectively overlapping the plurality of contact windows 135, 136 of the first conductive layer 130. In the present embodiment, the second insulating layer 150 may further have a plurality of contact windows 157, 158, respectively overlapping two different regions of the third portion 143 of the first conductive layer 140. In the present embodiment, the second insulating layer 150 may further have a contact window 159, overlapping the second portion 142 of the first conductive layer 140.

[0070] For example, in this embodiment, the material of the second insulating layer 150 may be an inorganic material (eg, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material, or a combination thereof.

[0071] The semiconductor device 10 further includes a second semiconductor layer 160 disposed on the second insulating layer 150. The second insulating layer 150 is located between the second semiconductor layer 160 and the first conductive layer 140. The second semiconductor layer 160 has a first portion 161. The first portion 121 of the first semiconductor layer 120, the first portion 141 of the first conductive layer 140, and the first portion 161 of the second semiconductor layer 160 are sequentially disposed along a direction z away from the substrate 110. In the present embodiment, the second semiconductor layer 160 may further include a second portion 162 separated from the first portion 161 of the second semiconductor layer 160; the third portion 123 of the first semiconductor layer 120, the third portion 143 of the first conductive layer 140, and the second portion 162 of the second semiconductor layer 160 are sequentially disposed along a direction z away from the substrate 110.

[0072] For example, in this embodiment, the material of the second semiconductor layer 160 may be polycrystalline silicon. However, the present invention is not limited thereto, and in other embodiments, the material of the second semiconductor layer 160 may also be amorphous silicon, microcrystalline silicon, single crystal silicon, organic semiconductor material, oxide semiconductor material (e.g., indium zinc oxide, indium gallium zinc oxide, or other suitable materials, or a combination thereof), or other suitable materials, or dopants contained in the above materials, or a combination thereof.

[0073] In the present embodiment, the semiconductor device 10 further includes a fourth insulating layer 170 disposed on the second semiconductor layer 160. The second semiconductor layer 160 is located between the fourth insulating layer 170 and the second insulating layer 150. In the present embodiment, the fourth insulating layer 170 may have a plurality of contact windows 171, 172, respectively overlapping the plurality of contact windows 151, 152 of the second insulating layer 150. In the present embodiment, the fourth insulating layer 170 may also have a plurality of contact windows 175, 176, respectively overlapping the plurality of contact windows 155, 156 of the second insulating layer 150. In the present embodiment, the fourth insulating layer 170 may also have a plurality of contact windows 173, 174, respectively overlapping two different regions of the first portion 161 of the second semiconductor layer 160. In the present embodiment, the fourth insulating layer 170 may also have a contact window 179, overlapping the contact window 159 of the second insulating layer 150. In the present embodiment, the fourth insulating layer 170 may also have a contact window 177, overlapping the contact window 157 of the second insulating layer 150. In this embodiment, the fourth insulating layer 170 may further have a contact window 178 overlapping the contact window 158 of the second insulating layer 150 .

[0074] For example, in this embodiment, the material of the fourth insulating layer 170 may be an inorganic material (eg, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material, or a combination thereof.

[0075] In the present embodiment, the semiconductor device 10 further includes a third conductive layer 180 disposed on the fourth insulating layer 170. The fourth insulating layer 170 is located between the third conductive layer 180 and the second semiconductor layer 160. The third conductive layer 180 has a first portion 181. The first portion 121 of the first semiconductor layer 120, the first portion 141 of the first conductive layer 140, the first portion 161 of the second semiconductor layer 160, and the first portion 181 of the third conductive layer 180 are sequentially disposed along a direction z away from the substrate 110.

[0076] In the present embodiment, the third conductive layer 180 may further include a second portion 182 separated from the first portion 181 of the third conductive layer 180. The second portion 122 of the first semiconductor layer 120, the second portion 122 of the first conductive layer 140, and the second portion 182 of the third conductive layer 180 are sequentially disposed along a direction z away from the substrate 110. The second portion 182 of the third conductive layer 180 may be electrically connected to the second portion 142 of the first conductive layer 140 through the fourth insulating layer 179 and the contact window 159 of the second insulating layer 150.

[0077] In the present embodiment, the third conductive layer 180 may further include a third portion 183, which is separated from the first portion 181 and the second portion 182 of the third conductive layer 180. The third portion 123 of the first semiconductor layer 120, the third portion 143 of the first conductive layer 140, the second portion 162 of the second semiconductor layer 160, and the third portion 183 of the third conductive layer 180 are sequentially disposed along a direction z away from the substrate 110. The third portion 183 of the third conductive layer 180 may be electrically connected to the third portion 143 of the first conductive layer 140 through the contact window 178 of the fourth insulating layer 170 and the contact window 158 of the second insulating layer 150.

[0078] In this embodiment, the second portion 162 of the second semiconductor layer 160 may be a heavily doped region of the second semiconductor layer 160. A storage capacitor C st The third portion 183 of the third conductive layer 180, the second portion 162 of the second semiconductor layer 160, the third portion 143 of the first conductive layer 140, the third portion 123 of the first semiconductor layer 120, a portion of the first insulating layer 130 interposed therebetween, a portion of the second insulating layer 150, and a portion of the fourth insulating layer 170. The third portion 183 of the third conductive layer 180 and the third portion 143 of the first conductive layer 140 may be electrically connected to form an electrode E1 of the first capacitor C1, and the second portion 162 of the second semiconductor layer 160 may be another electrode E2 of the first capacitor C1. The third portion 123 of the first semiconductor layer 120 may be an electrode E3 of the second capacitor C2, and the third portion 143 of the first conductive layer 140 may be another electrode E4 of the second capacitor C2. Due to the storage capacitor C st The first capacitor C1 and the second capacitor C2 are electrically connected to each other, and the storage capacitor C stThe capacitance value is large.

[0079] The semiconductor device 10 further includes a third insulating layer 190 disposed on the second semiconductor layer 160. The second semiconductor layer 160 is located between the third insulating layer 190 and the second insulating layer 150. In the present embodiment, the fourth insulating layer 170 is located between the third insulating layer 190 and the second semiconductor layer 160. In the present embodiment, the third insulating layer 190 may have a plurality of contact windows 191, 192, respectively overlapping the plurality of contact windows 171, 172 of the fourth insulating layer 170. In the present embodiment, the third insulating layer 190 may also have a plurality of contact windows 193, 194, respectively overlapping the plurality of contact windows 173, 174 of the fourth insulating layer 170. In the present embodiment, the third insulating layer 190 may also have a plurality of contact windows 195, 196, respectively overlapping the plurality of contact windows 175, 176 of the fourth insulating layer 170. In the present embodiment, the third insulating layer 190 may also have a contact window 197, overlapping the contact window 177 of the fourth insulating layer 170.

[0080] For example, in the present embodiment, the material of the third insulating layer 190 may be an inorganic material (eg, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material, or a combination thereof.

[0081] The semiconductor device 10 further includes a second conductive layer 200 disposed on the third insulating layer 190. In the present embodiment, the third insulating layer 190 is located between the second conductive layer 200 and the third conductive layer 180. In the present embodiment, the fourth insulating layer 170 is disposed on the second semiconductor layer 160 and between the third insulating layer 190 and the second semiconductor layer 160. In the present embodiment, the third conductive layer 180 is disposed on the fourth insulating layer 170 and between the third insulating layer 190 and the fourth insulating layer 170.

[0082] In this embodiment, based on the consideration of conductivity, a metal material may be used for the second conductive layer 200. However, the present invention is not limited thereto, and in other embodiments, the second conductive layer 200 may also be made of other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or stacked layers of metal materials and other conductive materials.

[0083] The second conductive layer 200 has a first portion 201 and a second portion 202. The first portion 201 and the second portion 202 of the second conductive layer 200 are separated from each other and are electrically connected to two different regions of the first portion 121 of the first semiconductor layer 120 through a plurality of contact windows 191 and 192 of the third insulating layer 190, respectively. Specifically, in the present embodiment, the first portion 201 of the second conductive layer 200 may be electrically connected to one region of the first portion 121 of the first semiconductor layer 120 through the contact window 191 of the third insulating layer 190, the contact window 171 of the fourth insulating layer 170, the contact window 151 of the second insulating layer 150, and the contact window 131 of the first insulating layer 130, and the second portion 202 of the second conductive layer 200 may be electrically connected to another region of the first portion 121 of the first semiconductor layer 120 through the contact window 192 of the third insulating layer 190, the contact window 172 of the fourth insulating layer 170, the contact window 152 of the second insulating layer 150, and the contact window 132 of the first insulating layer 130.

[0084] The second conductive layer 200 also has a third portion 203 and a fourth portion 204. The third portion 203 and the fourth portion 204 of the second conductive layer 200 are separated from each other and are respectively electrically connected to two different regions of the first portion 161 of the second semiconductor layer 160 through a plurality of contact windows 193 and 194 of the third insulating layer 190. Specifically, in the present embodiment, the third portion 203 of the second conductive layer 200 can be electrically connected to one region of the first portion 161 of the second semiconductor layer 160 through the contact windows 193 of the third insulating layer 190 and the contact windows 173 of the fourth insulating layer 170, and the fourth portion 204 of the second conductive layer 200 can be electrically connected to another region of the first portion 161 of the second semiconductor layer 160 through the contact windows 194 of the third insulating layer 190 and the contact windows 174 of the fourth insulating layer 170.

[0085] In this embodiment, the first portion 201 and the third portion 203 of the second conductive layer 200 may be selectively directly connected, and the second portion 202 and the fourth portion 204 of the second conductive layer 200 may be selectively directly connected. In addition, in this embodiment, the first portion 141 of the first conductive layer 140 and the first portion 181 of the third conductive layer 180 may be electrically connected.

[0086] In this embodiment, the first portion 201 and the third portion 203 of the second conductive layer 200 connected to each other can form a transistor T D The second portion 202 and the fourth portion 204 of the second conductive layer 200 connected thereto can form a transistor T D The drain of the first conductive layer 140 and the first conductive layer 180 electrically connected to form a transistor T DThe gate of the transistor T may be formed by at least a portion of the first portion 121 of the first semiconductor layer 120 and at least a portion of the first portion 161 of the second semiconductor layer 160. D channel. Since transistor T D The channel of the transistor T includes at least a portion of the first semiconductor layer 120 and at least a portion of the second semiconductor layer 160. D Can have high carrier mobility.

[0087] In this embodiment, the semiconductor device 10 can be used as a driving backplane of a micro light emitting diode display panel. D The high carrier mobility characteristic makes it suitable for use as a driving transistor of a pixel driving circuit driving a backplane, but the present invention is not limited thereto.

[0088] In this embodiment, the second conductive layer 200 may further include a fifth portion 205 and a sixth portion 206 separated from each other. The fifth portion 205 and the sixth portion 206 of the second conductive layer 200 are electrically connected to two different regions of the second portion 122 of the first semiconductor layer 120 through a plurality of contact windows 195 and 196 of the third insulating layer 190, respectively. Specifically, in the present embodiment, the fifth portion 205 of the second conductive layer 200 may be electrically connected to a region of the second portion 122 of the first semiconductor layer 120 through the contact window 195 of the third insulating layer 190, the contact window 175 of the fourth insulating layer 170, the contact window 155 of the second insulating layer 150, and the contact window 135 of the first insulating layer 130, and the sixth portion 206 of the second conductive layer 200 may be electrically connected to another region of the second portion 122 of the first semiconductor layer 120 through the contact window 196 of the third insulating layer 190, the contact window 176 of the fourth insulating layer 170, the contact window 156 of the second insulating layer 150, and the contact window 136 of the first insulating layer 130.

[0089] In this embodiment, the fifth portion 205 of the second conductive layer 200 may be a transistor T S The sixth portion 206 of the second conductive layer 200 may be a source of the transistor T S The drain of the first conductive layer 140 and the second portion 182 of the third conductive layer 180 electrically connected to each other can form a transistor T S The gate of the first semiconductor layer 120 may be formed by at least a portion of the second region 121 of the first semiconductor layer 120. S The channel of transistor T S The gate of the transistor T is formed by electrically connecting the second portion 142 of the first conductive layer 140 and the second portion 182 of the third conductive layer 180. S It has the characteristics of low resistance.

[0090] In this embodiment, the semiconductor device 10 can be used as a driving backplane of a micro light emitting diode display panel. S The low resistance characteristic makes it suitable for use as a switching transistor of a pixel driving circuit driving a backplane, but the present invention is not limited thereto.

[0091] In this embodiment, the second conductive layer 200 may further include a seventh portion 207, which is electrically connected to the sixth portion 206 of the second conductive layer 200 and the third portion 143 of the first conductive layer 140. In this embodiment, the semiconductor device 10 may be used as a driving backplane of a micro light emitting diode display panel, and the seventh portion 207 of the second conductive layer 200 may be used as a connection transistor T S With storage capacitor C st The bridge element is used.

[0092] It must be noted that the following embodiments use the component numbers and some contents of the previous embodiments, wherein the same number is used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the previous embodiments, and the following embodiments will not be repeated.

[0093] Figure 2 FIG. 1 is a schematic cross-sectional view of a semiconductor device 10A according to an embodiment of the present invention.

[0094] Figure 3 FIG. 1 is a partially enlarged schematic diagram of a semiconductor device 10A according to an embodiment of the present invention. Figure 3 correspond Figure 2 The local R.

[0095] Please refer to Figure 2 and Figure 3 In this embodiment, the first portion 161 of the second semiconductor layer 160 includes a first sub-layer 161a (indicated at Figure 3 ) and the second sub-layer 161b (indicated at Figure 3 ), wherein the first sub-layer 161a is disposed on the second insulating layer 150, the second sub-layer 161b is disposed above the first sub-layer 161a, and the semiconductor device 10A further includes a fifth insulating layer 210 (shown in FIG. Figure 3 ), and the fifth insulating layer 210 is disposed between the first sublayer 161a and the second sublayer 161b of the second semiconductor layer 160.

[0096] In this embodiment, the second sub-layer 161b of the second semiconductor layer 160 has a plurality of doped regions 161b-1, 161b-2 (indicated by Figure 3), which are electrically connected to the third part 203 and the fourth part 204 of the second conductive layer 200 respectively; the first sublayer 161a of the second semiconductor layer 160 has a plurality of doped regions 161a-1, 161a-2, which overlap with the plurality of doped regions 161b-1, 161b-2 of the second sublayer 161b respectively; the fifth insulating layer 210 is arranged between the plurality of doped regions 161a-1, 161a-2 of the first sublayer 161a and the plurality of doped regions 161b-1, 161b-2 of the second sublayer 161b.

[0097] In the present embodiment, the front-side sub-transistor FS-TFT includes the third portion 203 and the fourth portion 204 of the second conductive layer 200, the first portion 181 of the third conductive layer 180, and the second sub-layer 161b of the first portion 161 of the second semiconductor layer 160, wherein the third portion 203 and the fourth portion 204 of the second conductive layer 200 may be at least a portion of the source and at least a portion of the drain of the front-side sub-transistor FS-TFT, the first portion 181 of the third conductive layer 180 may be at least a portion of the gate of the front-side sub-transistor FS-TFT, and at least a portion of the second sub-layer 161b of the second semiconductor layer 160 may be at least a portion of the channel of the front-side sub-transistor FS-TFT.

[0098] In the present embodiment, the back-side sub-transistor BS-TFT includes the third portion 203 and the fourth portion 204 of the second conductive layer 200, the first portion 141 of the first conductive layer 140 and the first sub-layer 161a of the second semiconductor layer 160, wherein the third portion 203 and the fourth portion 204 of the second conductive layer 200 may be at least a portion of the source and at least a portion of the drain of the back-side sub-transistor BS-TFT, the first portion 141 of the first conductive layer 140 may be at least a portion of the gate of the back-side sub-transistor, and at least a portion of the first sub-layer 161a may be at least a portion of the channel of the back-side sub-transistor BS-TFT.

[0099] In the present embodiment, in the manufacturing process of the semiconductor device 10A, a first sub-semiconductor material layer (not shown), a fifth insulating material layer (not shown) and a second sub-semiconductor material layer (not shown) may be formed in sequence; then, the first sub-semiconductor material layer, the fifth insulating material layer and the second sub-semiconductor material layer are patterned to form a first sub-layer 161a, a fifth insulating layer 210 and a second sub-layer 161b, respectively; then, a laser annealing process is performed on the first sub-layer 161a and the second sub-layer 161b, wherein the fifth insulating layer 210 may be used as a barrier layer between the first sub-layer 161a and the second sub-layer 161b, so as to optimize the first sub-layer 161a and the second sub-layer 161b; then, a doping process is performed on the first sub-layer 161a and the second sub-layer 161b to form doped regions 161a-1 and 161a-2 of the first sub-layer 161a and doped regions 161b-1 and 161b-2 of the second sub-layer 161b; then, the current / voltage is increased to cause breakdown between the doped regions 161a-1 and 161a-2 of the first sub-layer 161a and the doped regions 161b-1 and 161b-2 of the second sub-layer 161b, thereby, the front sub-transistor FS-TFT and the back sub-transistor BS-TFT can be connected in parallel to form a transistor T with a double gate. D Since the transistor T D The transistor T comprises a front sub-transistor FS-TFT and a back sub-transistor BS-TFT connected in parallel with each other. D The turn-on current is large.

[0100] Figure 4 FIG. 1 is a partial enlarged schematic diagram of a semiconductor device 10B according to an embodiment of the present invention. Figure 4 Also available Figure 2 The local R.

[0101] Figure 4 The semiconductor device 10B and Figure 3 The semiconductor device 10A is similar to the semiconductor device 10A, and the difference between the two is: Figure 4 The semiconductor device 10B and Figure 3 The manufacturing process of the semiconductor device 10A is different. Figure 4 In the manufacturing process of the semiconductor device 10B, the timing of the laser annealing and doping steps is Figure 3 The embodiments are different.

[0102] Please refer to Figure 4Specifically, in this embodiment, in the manufacturing process of the semiconductor device 10B, a first sublayer 161a can be formed; then, the first sublayer 161a is subjected to laser annealing and doping processes to form doping regions 161a-1 and 161a-2 of the first sublayer 161a; then, a fifth insulating layer 210 and a second sublayer 161b are formed on the first sublayer 161a; then, the second sublayer 161b is subjected to laser annealing and doping processes to form doping regions 161b-1 and 161b-2 of the second sublayer 161b.

[0103] In short, in this embodiment, the first sublayer 161a and the second sublayer 161b are subjected to respective laser annealing and doping processes, and the doping concentration of the doping regions 161a-1 and 161a-2 of the first sublayer 161a may be the same as or different from the doping concentration of the doping regions 161b-1 and 161b-2 of the second sublayer 161b.

[0104] Figure 5 FIG. 1 is a partial enlarged schematic diagram of a semiconductor device 10C according to an embodiment of the present invention. Figure 5 Also available Figure 2 The local R.

[0105] Please refer to Figure 5 In the present embodiment, the second sublayer 161b of the second semiconductor layer 160 has a plurality of doped regions 161b-1 and 161b-2, which are respectively electrically connected to the third portion 203 and the fourth portion 204 of the second conductive layer 200; the first sublayer 161a of the second semiconductor layer 160 has a plurality of doped regions 161a-1 and 161a-2, which are respectively directly connected to the plurality of doped regions 161b-1 and 161b-2 of the second sublayer 161b.

[0106] In this embodiment, in the manufacturing process of the semiconductor device 10C, a first sublayer 161a can be formed; then, the first sublayer 161a is subjected to laser annealing and doping processes to form doping regions 161a-1 and 161a-2 of the first sublayer 161a; then, a fifth insulating layer 210C is formed on the first sublayer 161a, wherein the fifth insulating layer 210C does not cover the doping regions 161a-1 and 161a-2 of the first sublayer 161a; then, a second sublayer 161b is formed on the fifth insulating layer 210C; then, the second sublayer 161a is subjected to laser annealing and doping processes to form doping regions 161b-1 and 161b-2 of the second sublayer 161b, wherein the doping regions 161b-1 and 161b-2 of the second sublayer 161b are respectively in contact with the doping regions 161a-1 and 161a-2 of the first sublayer 161a.

[0107] Figure 6 FIG. 1 is a schematic cross-sectional view of a semiconductor device 10D according to an embodiment of the present invention.

[0108] Figure 7 FIG. 1 is a top view of a semiconductor device 10D according to an embodiment of the present invention. Figure 6 correspond Figure 7 Section line I-I'.

[0109] Please refer to Figure 6 and Figure 7 In this embodiment, in the top view of the semiconductor device 10D (ie Figure 7 ), the first portion 121 of the first semiconductor layer 120 and the first portion 161 of the second semiconductor layer 160 are arranged alternately. In the present embodiment, the first portion 121 of the first semiconductor layer 120 has a first length L1 in a first arrangement direction x of the first portion 201 and the second portion 202 of the second conductive layer 200, and the first portion 121 of the first semiconductor layer 120 has a first width W1 in a direction perpendicular to the first arrangement direction x (for example, but not limited to: the second arrangement direction y); the first portion 161 of the second semiconductor layer 160 has a second length L2 in a second arrangement direction y of the third portion 203 and the fourth portion 204 of the second conductive layer 200, and the first portion 161 of the second semiconductor layer 160 has a second width W2 in a direction perpendicular to the second arrangement direction y (for example, but not limited to: the first arrangement direction y); (W1 / L1)<(W2 / L2).

[0110] The first portion 121 of the first semiconductor layer 120 and the first portion 161 of the second semiconductor layer 160 are arranged alternately, which helps to reduce the overall layout area of ​​the semiconductor device 10D. In addition, by staggering the first portion 121 of the first semiconductor layer 120 and the first portion 161 of the second semiconductor layer 160, the width-to-length ratio (i.e., W2 / L2) of the first portion 161 of the second semiconductor layer 160 can be increased without excessively increasing the layout area, so as to further improve the transistor T D The turn-on current.

[0111] Figure 8 FIG. 1 is a schematic cross-sectional view of a semiconductor device 10E according to an embodiment of the present invention.

[0112] Fig. 9 FIG. 1 is a circuit diagram of a semiconductor device 10E according to an embodiment of the present invention. Figure 8 Omit Fig. 9 Illustration of a multiplexer MUX.

[0113] Please refer to Figure 8 and Fig. 9 In this embodiment, the first portion 201 and the third portion 203 of the second conductive layer 200 are separated from each other, and the second portion 202 and the fourth portion 204 of the second conductive layer 200 are separated from each other.

[0114] In this embodiment, the first portion 201 of the second conductive layer 200, the second portion 202 of the second conductive layer 200, the first portion 121 of the first semiconductor layer 120 and the first portion 141 of the first conductive layer 140 can form a transistor T1, wherein the first portion 201 and the second portion 202 of the second conductive layer 200 can be the source and the drain of the transistor T1, at least a portion of the first portion 121 of the first semiconductor layer 120 can be the channel of the transistor T1, and the first portion 141 of the first conductive layer 140 can be the gate of the transistor T1.

[0115] In this embodiment, the third portion 203 of the second conductive layer 200, the fourth portion 204 of the second conductive layer 200, the first portion 161 of the second semiconductor layer 160 and the first portion 141 of the first conductive layer 140 can form a transistor T2, wherein the third portion 203 and the fourth portion 204 of the second conductive layer 200 can be the source and the drain of the transistor T2, at least a portion of the first portion 161 of the second semiconductor layer 160 can be the channel of the transistor T2, and the first portion 141 of the first conductive layer 140 can be the gate of the transistor T2.

[0116] The transistor T1 and the transistor T2 can be used for different applications. For example, in this embodiment, the semiconductor device 10E can selectively further include a multiplexer MUX (shown in FIG. Fig. 9 ), wherein the gate of the transistor T1 and the gate of the transistor T2 (i.e., the first portion 141 of the first conductive layer 140) can be electrically connected to a multiplexer MUX. The multiplexer MUX is used to switch the signals input to the transistor T1 and the transistor T2, so that the transistor T1 and the transistor T2 can be used as a driving transistor of the pixel driving circuit and a sensing transistor of the sensing circuit, respectively, but the present invention is not limited thereto.

Claims

1. A semiconductor device comprising: substrate; A first semiconductor layer is disposed on the substrate and has a first portion; A first insulating layer is disposed on the first semiconductor layer; A first conductive layer is disposed on the first insulating layer and has a first portion; A second insulating layer is disposed on the first conductive layer; A second semiconductor layer is disposed on the second insulating layer and has a first portion, wherein the first portion of the first semiconductor layer, the first portion of the first conductive layer, and the first portion of the second semiconductor layer are sequentially disposed along a direction away from the substrate; A third insulating layer is disposed on the second semiconductor layer; A second conductive layer is disposed on the third insulating layer, wherein the second conductive layer has a first portion, a second portion, a third portion and a fourth portion, the first portion and the second portion of the second conductive layer are separated from each other and are respectively electrically connected to two different regions of the first portion of the first semiconductor layer through a plurality of contact windows of the third insulating layer, and the third portion and the fourth portion of the second conductive layer are separated from each other and are respectively electrically connected to two different regions of the first portion of the second semiconductor layer through a plurality of contact windows of the third insulating layer; a fourth insulating layer, disposed on the second semiconductor layer and located between the third insulating layer and the second semiconductor layer; as well as a third conductive layer disposed on the fourth insulating layer and between the third insulating layer and the fourth insulating layer, wherein the third conductive layer has a first portion, and the first portion of the first semiconductor layer, the first portion of the first conductive layer, the first portion of the second semiconductor layer, and the first portion of the third conductive layer are sequentially disposed along the direction away from the substrate, The first portion of the second conductive layer is directly connected to the third portion of the second conductive layer, and the second portion of the second conductive layer is directly connected to the fourth portion of the second conductive layer, and the first portion of the first conductive layer is electrically connected to the first portion of the third conductive layer.

2. A semiconductor device comprising: substrate; A first semiconductor layer is disposed on the substrate and has a first portion; A first insulating layer is disposed on the first semiconductor layer; A first conductive layer is disposed on the first insulating layer and has a first portion; A second insulating layer is disposed on the first conductive layer; A second semiconductor layer is disposed on the second insulating layer and has a first portion, wherein the first portion of the first semiconductor layer, the first portion of the first conductive layer, and the first portion of the second semiconductor layer are sequentially disposed along a direction away from the substrate; A third insulating layer is disposed on the second semiconductor layer; A second conductive layer is disposed on the third insulating layer, wherein the second conductive layer has a first portion, a second portion, a third portion and a fourth portion, the first portion and the second portion of the second conductive layer are separated from each other and are respectively electrically connected to two different regions of the first portion of the first semiconductor layer through a plurality of contact windows of the third insulating layer, and the third portion and the fourth portion of the second conductive layer are separated from each other and are respectively electrically connected to two different regions of the first portion of the second semiconductor layer through a plurality of contact windows of the third insulating layer; a fourth insulating layer, disposed on the second semiconductor layer and located between the third insulating layer and the second semiconductor layer; as well as a third conductive layer disposed on the fourth insulating layer and between the third insulating layer and the fourth insulating layer, wherein the third conductive layer has a first portion, and the first portion of the first semiconductor layer, the first portion of the first conductive layer, the first portion of the second semiconductor layer, and the first portion of the third conductive layer are sequentially disposed along the direction away from the substrate, The first semiconductor layer also has a second portion; the first conductive layer also has a second portion; the third conductive layer also has a second portion, which is separated from the first portion of the third conductive layer; the second conductive layer also has a fifth portion and a sixth portion separated from each other; the second portion of the first semiconductor layer, the second portion of the first conductive layer and the second portion of the third conductive layer are arranged in sequence along the direction away from the substrate; the second portion of the third conductive layer is electrically connected to the second portion of the first conductive layer through a contact window of the second insulating layer; the fifth portion and the sixth portion of the second conductive layer are respectively electrically connected to two different regions of the second portion of the first semiconductor layer through multiple contact windows of the third insulating layer.

3. The semiconductor device as described in claim 2, wherein the first semiconductor layer also has a third portion, which is separated from the first portion and the second portion of the first semiconductor layer; the first conductive layer also has a third portion, which is separated from the first portion and the second portion of the first conductive layer; the second semiconductor layer also has a second portion, which is separated from the first portion of the second semiconductor layer; the third conductive layer also has a third portion, which is separated from the first portion and the second portion of the third conductive layer; the second conductive layer also has a seventh portion, which is electrically connected to the sixth portion of the second conductive layer and the third portion of the first conductive layer; the third portion of the third conductive layer is electrically connected to the third portion of the first conductive layer through the contact window of the fourth insulating layer and the contact window of the second insulating layer; the third portion of the first semiconductor layer, the third portion of the first conductive layer, the second portion of the second semiconductor layer and the third portion of the third conductive layer are arranged in sequence along the direction away from the substrate. 4 . The semiconductor device as claimed in claim 3 , wherein the second portion of the second semiconductor layer is a heavily doped region of the second semiconductor layer. 5 . The semiconductor device as claimed in claim 1 , wherein in a top view of the semiconductor device, the first portion of the first semiconductor layer and the first portion of the second semiconductor layer are alternately disposed.

6. The semiconductor device as described in claim 5, wherein the first portion of the first semiconductor layer has a first length L1 in a first arrangement direction between the first portion and the second portion of the second conductive layer, and the first portion of the first semiconductor layer has a first width W1 in a direction perpendicular to the first arrangement direction; the first portion of the second semiconductor layer has a second length L2 in a second arrangement direction between the third portion and the fourth portion of the second conductive layer, and the first portion of the second semiconductor layer has a second width W2 in a direction perpendicular to the second arrangement direction; (W1 / L1)<(W2 / L2).

7. A semiconductor device comprising: substrate; A first semiconductor layer is disposed on the substrate and has a first portion; A first insulating layer is disposed on the first semiconductor layer; A first conductive layer is disposed on the first insulating layer and has a first portion; A second insulating layer is disposed on the first conductive layer; A second semiconductor layer is disposed on the second insulating layer and has a first portion, wherein the first portion of the first semiconductor layer, the first portion of the first conductive layer, and the first portion of the second semiconductor layer are sequentially disposed along a direction away from the substrate; A third insulating layer is disposed on the second semiconductor layer; as well as a second conductive layer, disposed on the third insulating layer, wherein the second conductive layer has a first portion, a second portion, a third portion and a fourth portion, the first portion and the second portion of the second conductive layer are separated from each other and are respectively electrically connected to two different regions of the first portion of the first semiconductor layer through a plurality of contact windows of the third insulating layer, the third portion and the fourth portion of the second conductive layer are separated from each other and are respectively electrically connected to two different regions of the first portion of the second semiconductor layer through a plurality of contact windows of the third insulating layer, The first portion of the second semiconductor layer comprises: A first sublayer is disposed on the second insulating layer; as well as The second sub-layer is disposed above the first sub-layer, wherein the semiconductor device further comprises a fifth insulating layer, and the fifth insulating layer is disposed between the first sub-layer and the second sub-layer of the second semiconductor layer.

8. A semiconductor device as described in claim 7, wherein the second sublayer of the second semiconductor layer has a plurality of doped regions, which are respectively electrically connected to the third portion and the fourth portion of the second conductive layer; the first sublayer of the second semiconductor layer has a plurality of doped regions, which respectively overlap with the doped regions of the second sublayer; and the fifth insulating layer is arranged between the doped regions of the first sublayer and the doped regions of the second sublayer.

9. The semiconductor device as described in claim 7, wherein the second sublayer of the second semiconductor layer has a plurality of doped regions, respectively electrically connected to the third portion and the fourth portion of the second conductive layer; and the first sublayer of the second semiconductor layer has a plurality of doped regions, respectively directly connected to the doped regions of the second sublayer.

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