Semiconductor device and manufacturing method thereof

Abstract

The present disclosure discloses a method for fabricating a semiconductor device, comprising the following steps: providing a semiconductor structure comprising a stacked structure of alternating first and second material layers, the stacked structure comprising a terrace region and a step region adjacent to the terrace region, the terrace region and the step region being topped by the second material layer; forming a third material layer covering the upper surface of the terrace region and the surface of the step region; forming a fourth material layer filling the step region and covering the terrace region; removing the third and fourth material layers on the terrace region, while retaining the third and fourth material layers located on the edge of the terrace region near the step region; and performing a first planarization step, wherein the first planarization step removes the raised fourth material layer and leaves the second and third material layers on the upper surface of the terrace region. This fabrication method increases the connection window of the contact hole and effectively avoids over-grinding at the edge of the terrace region.

Description

[0001] This disclosure is a divisional application for a patent with application number 202011546787.3, application date December 24, 2020, and invention name three-dimensional memory and method for forming the same. Technical Field

[0002] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a three-dimensional memory and a method for forming the same. Background Art

[0003] With the development of planar flash memory, semiconductor production processes have made tremendous progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limitations, the limitations of existing development technology, and the limits of stored electron density. Against this backdrop, to address the difficulties faced by planar flash memory and pursue lower unit cell production costs, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D Not-Or) flash memory and 3D NAND (3D Not-And) flash memory.

[0004] Among them, 3D NAND memory takes its small size and large capacity as its starting point, and uses a highly integrated design concept of stacking storage units in a three-dimensional pattern to produce memory with high storage density per unit area and efficient storage unit performance. It has become the mainstream process for the design and production of emerging memories.

[0005] To improve the integration density of three-dimensional memories, such as 3D NAND memories, three-dimensional memories with dual-layer channel holes have emerged. These typically consist of a lower channel hole in a lower stacked structure and an upper channel hole in an upper stacked structure. However, due to process limitations in the upper and lower channel hole fabrication processes, the resulting three-dimensional memories still exhibit significant structural and performance deficiencies. Furthermore, the manufacturing process is cumbersome and costly.

[0006] Therefore, how to simplify the manufacturing process of three-dimensional memory, reduce the manufacturing cost of three-dimensional memory, and at the same time improve the performance and manufacturing yield of three-dimensional memory is a technical problem that needs to be solved urgently. Summary of the Invention

[0007] The present disclosure provides a three-dimensional memory and a method for forming the same, which are used to solve the problems of complicated manufacturing process and high manufacturing cost of existing three-dimensional memories, while improving the performance and manufacturing yield of the three-dimensional memories.

[0008] In order to solve the above problems, the present disclosure provides a method for forming a three-dimensional memory, comprising the following steps:

[0009] Providing a substrate, wherein a surface of the substrate has a first stacking structure and a connection layer covering the surface of the first stacking structure;

[0010] forming an opening penetrating the connection layer and a first channel hole penetrating the first stacked structure, wherein the opening is in communication with the first channel hole;

[0011] Etching only the connection layer using a dry etching process to enlarge the characteristic size of the opening so that the characteristic size of the bottom of the enlarged opening is larger than the characteristic size of the top of the first channel hole; the dry etching process at least includes a first stage dry etching and a second stage dry etching using different radio frequency powers;

[0012] A filling layer is formed in the opening and in the empty first channel hole.

[0013] In some embodiments of the present disclosure, before enlarging the characteristic size of the opening, the following steps are further included:

[0014] An epitaxial semiconductor layer is formed at the bottom of the first channel hole.

[0015] In some embodiments of the present disclosure, the specific steps of etching only the connection layer using a dry etching process include:

[0016] performing a first-stage dry etching on the connecting layer;

[0017] The connection layer is subjected to a second-stage dry etching, wherein the radio frequency power used in the second-stage dry etching is less than the radio frequency power used in the first-stage dry etching.

[0018] In some embodiments of the present disclosure, the specific steps of performing the first-stage dry etching on the connection layer include:

[0019] An etching gas is introduced under the conditions of a first radio frequency frequency and a first radio frequency power, and a regulating gas is introduced under the conditions of a second radio frequency frequency and a second radio frequency power to perform a first-stage dry etching on the connection layer, wherein the first radio frequency frequency is lower than the second radio frequency frequency, and the first radio frequency power is higher than the second radio frequency power. The etching gas is used to etch the connection layer, and the regulating gas is used to adjust the etching rate of the etching gas for etching the connection layer;

[0020] The specific steps of performing the second stage dry etching on the connection layer include:

[0021] The etching gas is introduced under the conditions of a first RF frequency and a third RF power, and the regulating gas is introduced under the conditions of a second RF frequency and a fourth RF power to perform a second stage of dry etching on the connecting layer, wherein the third RF power is less than the first RF power, and the fourth RF power is less than the second RF power.

[0022] In some embodiments of the present disclosure, the third RF power is equal to the fourth RF power, and both the third RF power and the fourth RF power are less than the second RF power.

[0023] In some embodiments of the present disclosure, the first radio frequency power is 2 to 5 times the second radio frequency power;

[0024] The first radio frequency power is 30 to 120 times greater than the third radio frequency power.

[0025] In some embodiments of the present disclosure, the first radio frequency is 350KHz to 450KHz, and the second radio frequency is 55MHz to 65MHz;

[0026] The first radio frequency power is 17500W to 20000W, the second radio frequency power is 4500W to 6500W, and the third radio frequency power is 200W to 500W.

[0027] In some embodiments of the present disclosure, the flow rate of the regulating gas is greater than that of the etching gas.

[0028] In some embodiments of the present disclosure, the flow rate of the regulating gas is 20 to 300 times the flow rate of the etching gas.

[0029] In some embodiments of the present disclosure, the flow rate of the regulating gas is 1000 sccm to 3000 sccm, and the flow rate of the etching gas is 10 sccm to 50 sccm.

[0030] In some embodiments of the present disclosure, the material of the connecting layer is an oxide material;

[0031] The etching gas is a gas containing carbon and fluorine elements;

[0032] The regulating gas is oxygen.

[0033] In some embodiments of the present disclosure, the specific steps of forming a filling layer in the opening and in the empty first channel hole include:

[0034] A filling material is deposited in the empty first trench hole and the opening to form the filling layer that fills the first trench hole, the opening, and closes the top of the opening.

[0035] In some embodiments of the present disclosure, after forming a filling layer in the first trench hole and the opening, the following steps are further included:

[0036] forming a second stacking structure on the surface of the connecting layer;

[0037] The second stacking structure and part of the filling layer are etched to form the second channel hole penetrating the second stacking structure and extending into the opening, the second channel hole is aligned with the first channel hole, and the filling layer remaining in the opening at least covers the entire side wall of the opening.

[0038] In order to solve the above problems, the present disclosure further provides a three-dimensional memory, comprising:

[0039] A substrate, wherein a surface of the substrate has a first stacking structure and a connection layer covering the surface of the first stacking structure;

[0040] a first channel hole, passing through the first stacking structure;

[0041] an opening located in the connection layer and communicating with the first channel hole, wherein a characteristic dimension of a bottom of the opening is greater than a characteristic dimension of a top of the first channel hole;

[0042] The three-dimensional memory is formed by the method described in any one of the above embodiments.

[0043] The three-dimensional memory and its formation method disclosed herein, after etching a first channel hole in a first stacked structure and forming an opening in a connection layer on top of the first stacked structure that penetrates the first channel hole, enlarges the characteristic dimensions of the opening in the connection layer so that the characteristic dimensions of the bottom of the enlarged opening are larger than the characteristic dimensions of the top of the first channel hole. This not only increases the width of the alignment window for the subsequent second channel hole and the first channel hole, but also prevents damage to the sidewalls of the first channel hole during subsequent processing, effectively improving the performance and manufacturing yield of the three-dimensional memory. Furthermore, because the filling layer is formed through a single filling process within the first channel hole and the opening, the manufacturing steps of the three-dimensional memory are greatly simplified, reducing the manufacturing cost of the three-dimensional memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to make the above-mentioned objects, features and advantages of the present disclosure more clearly understood, the specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, wherein:

[0045] Attachment Figure 1 is a flow chart of a method for forming a three-dimensional memory in a specific embodiment of the present disclosure;

[0046] Attachment Figures 2A-2Fis a schematic cross-sectional view of the main processes in forming a three-dimensional memory in a specific embodiment of the present disclosure;

[0047] Attachment Figure 3 It is a schematic diagram of the structure of a three-dimensional memory provided in a specific embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] The specific embodiments of the three-dimensional memory and the method for forming the same provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0049] In the process of forming a three-dimensional memory with a double-layer channel hole, the current process generally involves first forming a lower stacking structure and a connection layer covering the surface of the lower stacking structure, and etching the lower stacking structure and the connection layer to form a lower channel hole; then, depositing a first filling layer on the sidewalls of the lower channel hole and the surface of the connection layer; then, removing the first filling layer covering the sidewalls of the connection layer and the top sidewalls of the lower channel hole through an etching process, exposing the connection layer at the sidewalls of the lower channel hole; then, removing a portion of the connection layer at the top of the lower channel hole through a wet etching process, forming a trench in the connection layer; finally, depositing a second filling layer on the lower channel hole and in the trench. Although the above process steps can increase the width of the subsequent alignment window between the upper channel hole and the lower channel hole, on the one hand, the wet etching process is expensive and cumbersome to operate; on the other hand, two deposition processes are required, further increasing the complexity of the process. If the trench is not formed in the connection layer through a wet etching process, the upper channel hole and the lower channel hole may be misaligned and the sidewall of the lower channel hole may be damaged.

[0050] In order to simplify the manufacturing steps of the three-dimensional memory and reduce the manufacturing cost of the three-dimensional memory while ensuring that the upper channel hole and the lower channel hole are aligned, this embodiment provides a method for forming a three-dimensional memory. Figure 1 Flowchart of the method for forming a three-dimensional memory in a specific embodiment of the present disclosure, Figures 2A-2F This is a schematic cross-sectional view of the main process in forming a three-dimensional memory in a specific embodiment of the present disclosure. The three-dimensional memory described in this specific embodiment may be, but is not limited to, a 3D NAND memory. Figure 1 and Figure 2A-2E As shown, the method for forming a three-dimensional memory provided in this embodiment includes the following steps:

[0051] Step S11, providing a substrate 20, wherein the surface of the substrate 20 has a first stacking structure 21 and a connection layer 22 covering the surface of the first stacking structure 21, such as Figure 2A shown.

[0052] Specifically, the substrate 20 may be a Si substrate, a Ge substrate, a SiGe substrate, a SOI (Silicon On Insulator) or a GOI (Germanium On Insulator), etc. In this embodiment, the substrate 20 may be a silicon substrate for supporting a device structure thereon.

[0053] The first stacking structure 21 includes a direction along the substrate 20 pointing to the first stacking structure 21 (i.e. Figure 2A The first interlayer insulating layer 211 and the first sacrificial layer 212 are alternately stacked (in the Z-axis direction). The number of layers of the first interlayer insulating layer 211 and the first sacrificial layer 212 alternately stacked can be set by those skilled in the art according to actual needs. The more layers of the first interlayer insulating layer 211 and the first sacrificial layer 212 alternately stacked, the greater the integration of the three-dimensional memory formed. A layer of the first sacrificial layer 212 located on the top of the first stacked structure 21 is in contact with the connecting layer 22. The material of the first interlayer insulating layer 211 can be, but is not limited to, an oxide material, such as silicon dioxide; the material of the first sacrificial layer 212 can be, but is not limited to, a nitride material, such as silicon nitride. In order to facilitate subsequent selective etching, the material of the connecting layer 22 should have a high etching selectivity ratio (for example, an etching selectivity ratio greater than 3) with the material of the first sacrificial layer 212. The material of the connecting layer 22 can be, but is not limited to, an oxide material.

[0054] Step S12: forming an opening 24 penetrating the connection layer 22 and a first channel hole 23 of the first stacked structure 21, wherein the opening 24 is connected to the first channel hole 23. Figure 2A shown.

[0055] Specifically, the connection layer 22 and the first stacking structure 21 can be etched by dry etching or wet etching to form the first channel hole 23 and the opening 24. The first channel hole 23 is directed along the direction of the substrate 20 to the first stacking structure 21 (i.e. Figure 2A The Z-axis direction in FIG2 penetrates the first stacking structure 21 , the opening 24 penetrates the connection layer 22 along the direction of the substrate 20 pointing to the first stacking structure 21 , and the opening 24 is connected to the first channel hole 23.

[0056] Step S13, enlarging the characteristic size of the opening 24 so that the characteristic size of the bottom of the enlarged opening 24 is larger than the characteristic size of the top of the first channel hole 23, as shown in FIG. Figure 2B and Figure 2C As shown, Figure 2C yes Figure 2BTransmission electron microscope image of .

[0057] In some embodiments of the present disclosure, before enlarging the characteristic size of the opening 24, the following steps are further included:

[0058] An epitaxial semiconductor layer 30 is formed at the bottom of the first channel hole 23 .

[0059] Specifically, the epitaxial semiconductor layer 30 is first formed at the bottom of the first channel hole 23 by an epitaxial growth process, and then an oxide protection layer is formed on the surface of the epitaxial semiconductor layer 30 by a wet oxidation process to prevent the epitaxial semiconductor layer 30 from being damaged in subsequent processes.

[0060] In some embodiments of the present disclosure, the specific steps of enlarging the characteristic size of the opening 24 include:

[0061] A dry etching process is used to etch only the connection layer 22 to expand the characteristic size of the opening 24 .

[0062] Specifically, because the wet etching process is cumbersome and costly, in this specific embodiment, after forming the first channel hole 23 in the first stacked structure 21 and the opening 24 in the connection layer 22, a dry etching process is used to etch the connection layer 22. Furthermore, by adjusting the parameters of the dry etching process, such as the RF frequency and RF power, only the connection layer 22 is etched during the dry etching process. In addition, since only the connection layer 22 is etched in this step by adjusting the etching parameters, damage will not be caused to the stacked structure 21 exposed at the sidewall of the first channel hole 23. Therefore, before etching the connection layer 22 using the dry etching process in this step, there is no need to deposit a filling material in the first channel hole 23.

[0063] In some embodiments of the present disclosure, the specific steps of etching only the connection layer 22 using a dry etching process include:

[0064] Performing a first-stage dry etching on the connection layer 22;

[0065] The connection layer 22 is subjected to a second-stage dry etching, wherein the radio frequency power used in the second-stage dry etching is lower than the radio frequency power used in the first-stage dry etching.

[0066] In some embodiments of the present disclosure, the specific steps of performing the first stage dry etching on the connection layer 22 include:

[0067] An etching gas is introduced under the conditions of a first radio frequency frequency and a first radio frequency power, and a regulating gas is introduced under the conditions of a second radio frequency frequency and a second radio frequency power, to perform a first-stage dry etching on the connection layer 22, wherein the first radio frequency frequency is lower than the second radio frequency frequency, and the first radio frequency power is higher than the second radio frequency power. The etching gas is used to etch the connection layer 22, and the regulating gas is used to adjust the etching rate of the etching gas for etching the connection layer;

[0068] The specific steps of performing the second stage dry etching on the connection layer 22 include:

[0069] The etching gas is introduced under the conditions of the first RF frequency and the third RF power, and the regulating gas is introduced under the conditions of the second RF frequency and the fourth RF power to perform the second stage dry etching on the connecting layer 22, wherein the third RF power is less than the first RF power, and the fourth RF power is less than the second RF power.

[0070] Specifically, in the process of expanding the characteristic size of the opening 24 in the connecting layer 22, a combination of a first-stage dry etching and a second-stage dry etching is adopted. During the first-stage dry etching process, a relatively high radio frequency power is used to bombard the connecting layer 22, thereby controlling the etching depth so that the first-stage dry etching process can only etch the connecting layer 22. After the first-stage dry etching process, the bottom of the opening 24 exposes the first sacrificial layer 212 at the top of the first stacked structure 21. Then, using the first sacrificial layer 212 at the top of the first stacked structure 21 as an etching stop layer, the connecting layer 22 is etched at a relatively low radio frequency power, so that the characteristic size of the opening 24 is further increased.

[0071] During the first stage of dry etching, the etching gas is first introduced under the conditions of the first RF frequency and the first RF power, and the regulating gas is introduced under the conditions of the second RF frequency and the second RF power. Through the combined action of the etching gas and the regulating gas, the etching rate of the first stage of dry etching is improved, and etching time is saved. During the second stage of dry etching, the etching gas is introduced under the conditions of the first RF frequency and the third RF power, and the regulating gas is introduced under the conditions of the second RF frequency and the fourth RF power. Through the combined action of the etching gas and the regulating gas, the etching rate of the second stage of dry etching is improved, and etching time is saved. The specific type of the etching gas can be selected by those skilled in the art according to the specific material of the connecting layer 22. The specific type of the regulating gas can be selected according to the specific type of the etching gas and the specific material of the connecting layer 22.

[0072] The specific values ​​of the third RF power and the fourth RF power can be selected by those skilled in the art according to actual needs. To simplify the operation steps, in some embodiments of the present disclosure, the third RF power is equal to the fourth RF power, and the third RF power and the fourth RF power are both less than the second RF power.

[0073] In some embodiments of the present disclosure, the first radio frequency power is 2 to 5 times the second radio frequency power;

[0074] The first radio frequency power is 30 to 120 times greater than the third radio frequency power.

[0075] In some embodiments of the present disclosure, the first radio frequency is 350KHz to 450KHz, and the second radio frequency is 55MHz to 65MHz;

[0076] The first radio frequency power is 17500W to 20000W, the second radio frequency power is 4500W to 6500W, and the third radio frequency power is 200W to 500W.

[0077] In some embodiments of the present disclosure, the flow rate of the regulating gas is greater than that of the etching gas.

[0078] In some embodiments of the present disclosure, the flow rate of the regulating gas is 20 to 300 times the flow rate of the etching gas.

[0079] In some embodiments of the present disclosure, the flow rate of the regulating gas is 1000 sccm to 3000 sccm, and the flow rate of the etching gas is 10 sccm to 50 sccm.

[0080] In some embodiments of the present disclosure, the material of the connection layer 22 is an oxide material;

[0081] The etching gas is a gas containing carbon and fluorine elements;

[0082] The regulating gas is oxygen.

[0083] The following takes the case where the material of the connecting layer 22 is an oxide material (such as silicon dioxide) as an example. The step of etching and etching only the connecting layer 22 is divided into two dry etching stages. In the first stage of dry etching, the etching gas is continuously introduced under the conditions of a radio frequency of 400KHz and a radio frequency power of 17500W to 20000W, and the regulating gas is continuously introduced under the conditions of a radio frequency of 60MHz and a radio frequency power of 4500W to 6500W. Through the combined action of the etching gas and the regulating gas, the connecting layer 22 is etched; in the second stage of dry etching, the etching gas is continuously introduced under the conditions of a radio frequency of 400KHz and a radio frequency power of 200W to 500W, and the regulating gas is continuously introduced under the conditions of a radio frequency of 60MHz and a radio frequency power of 200W to 500W. Through the combined action of the etching gas and the regulating gas, the connecting layer 22 is etched again. The total time of the first-stage dry etching and the second-stage dry etching is greater than 60 seconds. The etching time of the first-stage dry etching is less than the etching time of the second-stage dry etching. For example, the etching time of the first-stage dry etching is 5 seconds to 25 seconds, and the etching time of the second-stage dry etching is 35 seconds to 55 seconds. The specific values ​​of the etching time of the first-stage dry etching and the etching time of the second-stage dry etching can be adjusted according to the thickness of the connecting layer 22 and the type of etching gas used. The etching gas used in the first-stage dry etching and the second-stage dry etching is CF4, and the regulating gas used in the first-stage dry etching and the second-stage dry etching is O2. During the first-stage dry etching and the second-stage dry etching process, the flow rate of CF4 can be 10 sccm to 50 sccm, and the flow rate of O2 can be 1000 sccm to 3000 sccm. By controlling the etching parameters, both the first-stage dry etching process and the second-stage dry etching process etches only the connection layer 22 , and does not etch the stacked structure 21 exposed on the sidewall of the first channel hole 23 .

[0084] This step involves targeted etching and etching only the connection layer 22, so that the characteristic size of the expanded opening 24 is larger than the characteristic size of the first channel hole 23. This not only expands the width of the alignment window between the subsequently formed second channel hole 28 and the first channel hole 23, but also makes the sidewalls of the expanded opening 24 flat, thereby ensuring good subsequent contact with the charge storage layer, and further ensuring good electrical conduction between the first channel hole 23 and the subsequent second channel hole 28.

[0085] The specific cross-sectional shape of the expanded opening 24 may be, but is not limited to, a trapezoid. The characteristic dimension of the bottom of the expanded opening 24 (i.e., the end of the opening 24 contacting the first stacked structure 21) is smaller than the characteristic dimension of the top of the opening 24 (i.e., the end opposite the bottom of the opening 24), and the characteristic dimension of the bottom of the opening 24 is larger than the characteristic dimension of the top of the first channel hole 23 (i.e., the end of the first channel hole 23 contacting the connection layer 22).

[0086] In some embodiments of the present disclosure, in the radial direction of the first channel hole 23 , the distance between the sidewall of the enlarged opening 24 and the sidewall of the first channel hole 23 on the same side is 5 nm to 6 nm.

[0087] Specifically, along Figure 2B In the X-axis direction, the distance between the sidewall of the expanded opening 24 and the sidewall of the first channel hole 23 on the same side is 5 nm to 6 nm, thereby ensuring the alignment of the subsequently formed second channel hole 28 with the first channel hole 23.

[0088] Step S14, forming a filling layer 25 in the opening 24 and the first empty channel hole 23, as shown in FIG. Figure 2D shown.

[0089] In some embodiments of the present disclosure, the specific steps of forming a filling layer in the opening 24 and in the empty first channel hole 23 include:

[0090] A filling material is deposited in the empty first channel hole 23 and the opening 24 to form the filling layer 25 that fills the first channel hole 23 and the opening 24 and closes the top of the opening 24 .

[0091] Specifically, by adjusting the etching parameters, the first stacked structure 21 exposed to the first channel hole 23 can be protected from damage during the process of etching to expand the characteristic dimensions of the opening 24. Therefore, it is not necessary to fill the first channel hole 23 before expanding the opening 24. After expanding the opening 24, a filling layer 25 is formed in a one-step filling process to fill the first channel hole 23, the opening, and seal the top of the opening 24, thereby greatly simplifying the manufacturing steps of the three-dimensional memory device. The material of the filling layer 25 can be, but is not limited to, polysilicon.

[0092] In some embodiments of the present disclosure, after forming the filling layer 25 in the first channel hole 23 and the opening 24 , the following steps are further included:

[0093] A second stacking structure 26 is formed on the surface of the connection layer 22, such as Figure 2EAs shown;

[0094] The second stacked structure 26 and a portion of the filling layer 25 are etched to form a second channel hole 28 that penetrates the second stacked structure 26 and extends into the opening 24. The second channel hole 28 is aligned with the first channel hole 23. The remaining filling layer 25 in the opening 24 at least covers the entire sidewall of the opening 24. Figure 2F shown.

[0095] Specifically, the second stacking structure 26 includes a direction along the substrate 20 pointing to the first stacking structure 21 (ie Figure 2E The second interlayer insulating layer 261 and the second sacrificial layer 262 are alternately stacked (in the Z-axis direction). The number of layers of the second interlayer insulating layer 261 and the second sacrificial layer 262 alternately stacked can be set by those skilled in the art according to actual needs, and can be the same as or different from the number of stacked layers of the first stacking structure 21. The surface of the second stacking structure 26 is also covered with a covering layer 27. A layer of the second sacrificial layer 262 located on the top of the second stacking structure 26 is in contact with the covering layer 27. The material of the second interlayer insulating layer 261 can be, but not limited to, an oxide material, such as silicon dioxide; the material of the second sacrificial layer 262 can be, but not limited to, a nitride material, such as silicon nitride. The material of the covering layer 27 can be, but not limited to, an oxide material.

[0096] The cover layer 27, the second stacking structure 26 and a portion of the filling layer 25 are etched by an etching process to form a direction along the substrate 20 pointing to the first stacking structure 21 (i.e. Figure 2F The second channel hole 28 is formed in the Z-axis direction (in the Z-axis direction) through the second stacked structure 26 and extends to the second channel hole 28 in the opening 24. The position of the second channel hole 28 is aligned with the position of the first channel hole 23. Since the opening 24 is formed to be regular and flat, and the characteristic size of the opening 24 is larger than that of the first channel hole 23, the filling layer 25 remains on the entire surface of the opening 24 during the etching process of the second channel hole 28, thereby preventing damage to the sidewalls of the first channel hole 23.

[0097] In addition, this embodiment also provides a three-dimensional memory. Figure 3 The three-dimensional memory provided in this embodiment can be configured as follows: Figure 1 、 Figure 2A-2F The three-dimensional memory described in this embodiment may be, but is not limited to, a 3D NAND memory. Figure 3 As shown, the three-dimensional memory provided in this embodiment includes:

[0098] A substrate 20 having a first stacking structure 21 and a connection layer 22 covering the surface of the first stacking structure 21;

[0099] A first channel hole 23 passing through the first stack structure 21;

[0100] The opening 24 is located in the connection layer 22 and communicates with the first channel hole 23 . The characteristic size of the bottom of the opening 24 is greater than the characteristic size of the top of the first channel hole 23 .

[0101] The three-dimensional memory and its formation method provided in this embodiment employ a method of etching a first channel hole in a first stacked structure and forming an opening in a connection layer on top of the first stacked structure that penetrates the first channel hole. The characteristic dimensions of the opening in the connection layer are then enlarged, such that the characteristic dimensions of the bottom of the enlarged opening are larger than the characteristic dimensions of the top of the first channel hole. This not only increases the width of the alignment window for the subsequent second channel hole and the first channel hole, but also prevents damage to the sidewalls of the first channel hole during subsequent processing, effectively improving the performance and manufacturing yield of the three-dimensional memory. Furthermore, because the filling layer is formed through a single filling process within the first channel hole and the opening, the manufacturing steps of the three-dimensional memory are significantly simplified, reducing the manufacturing cost of the three-dimensional memory.

[0102] The above are only some embodiments of the present disclosure. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A method for forming a three-dimensional memory, characterized in that: The steps include: Providing a substrate, wherein a surface of the substrate has a first stacking structure and a connection layer covering the surface of the first stacking structure; forming an opening penetrating the connection layer and a first channel hole penetrating the first stacked structure, wherein the opening is in communication with the first channel hole; Etching only the connection layer using a dry etching process to enlarge the characteristic size of the opening so that the characteristic size of the bottom of the enlarged opening is larger than the characteristic size of the top of the first channel hole; the dry etching process at least includes a first stage dry etching and a second stage dry etching using different radio frequency powers; A filling layer is formed in the opening and in the empty first channel hole.

2. The method for forming a three-dimensional memory according to claim 1, wherein: Before enlarging the characteristic size of the opening, the following steps are also included: An epitaxial semiconductor layer is formed at the bottom of the first channel hole.

3. The method for forming a three-dimensional memory according to claim 2, wherein: The specific steps of etching only the connection layer using a dry etching process include: performing a first-stage dry etching on the connecting layer; The connection layer is subjected to a second-stage dry etching, wherein the radio frequency power used in the second-stage dry etching is less than the radio frequency power used in the first-stage dry etching.

4. The method for forming a three-dimensional memory according to claim 3, wherein: The specific steps of performing the first stage dry etching on the connection layer include: An etching gas is introduced under the conditions of a first radio frequency frequency and a first radio frequency power, and a regulating gas is introduced under the conditions of a second radio frequency frequency and a second radio frequency power to perform a first-stage dry etching on the connection layer, wherein the first radio frequency frequency is lower than the second radio frequency frequency, and the first radio frequency power is higher than the second radio frequency power. The etching gas is used to etch the connection layer, and the regulating gas is used to adjust the etching rate of the etching gas for etching the connection layer; The specific steps of performing the second stage dry etching on the connection layer include: The etching gas is introduced under the conditions of a first RF frequency and a third RF power, and the regulating gas is introduced under the conditions of a second RF frequency and a fourth RF power to perform a second stage of dry etching on the connecting layer, wherein the third RF power is less than the first RF power, and the fourth RF power is less than the second RF power.

5. The method for forming a three-dimensional memory according to claim 4, wherein: The third RF power is equal to the fourth RF power, and both the third RF power and the fourth RF power are less than the second RF power.

6. The method for forming a three-dimensional memory according to claim 4, wherein: The first radio frequency power is 2 to 5 times the second radio frequency power; The first radio frequency power is 30 to 120 times greater than the third radio frequency power.

7. The method for forming a three-dimensional memory according to claim 4, wherein: The first radio frequency is 350KHz to 450KHz, and the second radio frequency is 55MHz to 65MHz; The first radio frequency power is 17500W to 20000W, the second radio frequency power is 4500W to 6500W, and the third radio frequency power is 200W to 500W.

8. The method for forming a three-dimensional memory according to claim 4, wherein: The flow rate of the regulating gas is greater than that of the etching gas.

9. The method for forming a three-dimensional memory according to claim 4, wherein: The flow rate of the regulating gas is 20 to 300 times the flow rate of the etching gas.

10. The method for forming a three-dimensional memory according to claim 4, wherein: The flow rate of the regulating gas is 1000 sccm to 3000 sccm, and the flow rate of the etching gas is 10 sccm to 50 sccm.

11. The method for forming a three-dimensional memory according to claim 4, wherein: The material of the connecting layer is an oxide material; The etching gas is a gas containing carbon and fluorine elements; The regulating gas is oxygen.

12. The method for forming a three-dimensional memory according to claim 1, wherein: The specific steps of forming a filling layer in the opening and in the empty first channel hole include: A filling material is deposited in the empty first trench hole and the opening to form the filling layer that fills the first trench hole, the opening, and closes the top of the opening.

13. The method for forming a three-dimensional memory according to claim 1, wherein: After forming a filling layer in the first trench hole and the opening, the method further includes the following steps: forming a second stacking structure on the surface of the connecting layer; The second stacking structure and part of the filling layer are etched to form a second channel hole that penetrates the second stacking structure and extends into the opening, the second channel hole is aligned with the first channel hole, and the filling layer remaining in the opening at least covers the entire side wall of the opening.

14. A three-dimensional memory, characterized in that: A three-dimensional memory device is formed by the method for forming a three-dimensional memory device according to any one of claims 1 to 13, comprising: a substrate having a first stacking structure on a surface of the substrate, and a connection layer covering a surface of the first stacking structure; a first channel hole, passing through the first stacking structure; The opening is located in the connection layer and communicates with the first channel hole. The characteristic size of the bottom of the opening is greater than the characteristic size of the top of the first channel hole.

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