3D memory

Abstract

The present invention provides a method for manufacturing a three-dimensional memory and a three-dimensional memory. In the method for manufacturing the three-dimensional memory provided by the present invention, after depositing an additional dummy gate covering layer on a step structure, only the dummy gate covering layer on the step sidewall is removed, and the dummy gate covering layer remaining on the semiconductor layer is not removed. Instead, a dielectric layer is directly formed on the remaining dummy gate covering layer and etched to form a metal plug. This simplifies the etching process, saves masks, improves production efficiency, and reduces production costs. At the same time, when etching to form contact holes, the contact holes that originally passed through the semiconductor layer are etched to stay in the dummy gate covering layer, thereby reducing the corresponding etching window and enhancing its design flexibility.

Description

[0001] This application is a divisional application of the patent with application date of September 28, 2020, application number 202011037645.4, and invention name “Manufacturing method of three-dimensional memory and three-dimensional memory”. Technical Field

[0002] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a three-dimensional memory. Background Art

[0003] Three-dimensional memory is a technology that stacks data units. Currently, it can achieve stacking of 32 layers or more of data units. It overcomes the practical expansion limits of planar memory, further increases storage capacity, reduces the storage cost of each data bit, and reduces energy consumption.

[0004] However, in the current manufacturing method of three-dimensional memory, when increasing the thickness of the dummy gate covering layer in the step by additionally depositing the dummy gate covering layer, it is necessary not only to remove the dummy gate covering layer deposited on the sidewall of the step, but also to remove the dummy gate covering layer deposited on the semiconductor layer. Moreover, the dummy gate covering layer on the semiconductor layer needs to be etched away using a separate mask, and the process is relatively cumbersome. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for manufacturing a three-dimensional memory that can save process steps, so as to solve the above-mentioned technical problems.

[0006] To achieve the above and other related objectives, the present invention provides a method for manufacturing a three-dimensional memory, comprising:

[0007] Providing a substrate structure, defining an array region and an edge region in the substrate structure, wherein the array region includes a core region and a step region;

[0008] forming a semiconductor layer on the substrate structure;

[0009] forming a through hole penetrating the semiconductor layer on the edge region, and filling the through hole with a first dielectric layer;

[0010] forming a stacked structure on the semiconductor layer in the array region, wherein the stacked structure includes alternately stacked dummy gate layers and second dielectric layers;

[0011] Etching the stacked structure to form a step structure in the step region, wherein the step structure includes a plurality of steps, and each step includes a layer of the dummy gate layer and a layer of the second dielectric layer;

[0012] forming a dummy gate covering layer, wherein the dummy gate covering layer covers the step structure and the semiconductor layer on the edge region, and the dummy gate covering layer is in contact with the dummy gate layer exposed in the step;

[0013] forming a third dielectric layer, wherein the third dielectric layer covers the step structure and the dummy gate covering layer on the edge region;

[0014] Etching the third dielectric layer to form a first contact hole, wherein a projection of the first contact hole on the substrate structure is located within the through hole;

[0015] The first contact hole is filled to form a first metal plug.

[0016] Optionally, the semiconductor layer includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer, the second semiconductor layer is located between the first semiconductor layer and the third semiconductor layer, and the second semiconductor layer is used to contact the side wall of the channel layer passing through the stack structure in a vertical direction.

[0017] Optionally, after forming the dummy gate capping layer and before forming the third dielectric layer, the method for manufacturing the three-dimensional memory further includes:

[0018] The dummy gate covering layer on the sidewall of the step is removed.

[0019] Optionally, after forming the third dielectric layer and before etching the third dielectric layer, the method for manufacturing the three-dimensional memory further includes:

[0020] The dummy gate layer and the dummy gate covering layer on the step region are replaced with a gate layer.

[0021] Optionally, while etching to form the first contact hole, a step contact hole is formed on the step area, the step contact hole is filled to form a second metal plug, and the second metal plug contacts the gate layer corresponding to the step.

[0022] Optionally, the first contact hole passes through the third dielectric layer.

[0023] Optionally, the first contact hole sequentially penetrates the third dielectric layer, the dummy gate capping layer, and at least a portion of the first dielectric layer in the through hole.

[0024] Optionally, the substrate structure includes a base plate and an insulating layer, and the method for manufacturing the three-dimensional memory further includes:

[0025] The substrate structure is removed, and a fourth dielectric layer is formed on a side of the semiconductor layer away from the stacked structure; the fourth dielectric layer is etched to form a second contact hole in the array region that penetrates the fourth dielectric layer and extends to the semiconductor layer, and a third contact hole in the edge region that penetrates the fourth dielectric layer and at least a portion of the first dielectric layer, wherein the third contact hole is connected to the first contact hole.

[0026] Optionally, the method for manufacturing the three-dimensional memory further includes:

[0027] The second contact hole is filled to form a source contact structure; and the third contact hole is filled to form a metal connection structure.

[0028] Optionally, the method for manufacturing the three-dimensional memory further includes:

[0029] The electrical connection with the CMOS control wafer is achieved through the second metal plug.

[0030] Optionally, the method for manufacturing the three-dimensional memory further includes:

[0031] The electrical connection with the external circuit is achieved through the metal connection structure.

[0032] In addition, to achieve the above-mentioned and other related objectives, the present invention further provides a three-dimensional memory, comprising:

[0033] A bottom dielectric layer comprising an array region and an edge region, wherein the array region comprises a core region and a step region;

[0034] a semiconductor layer, disposed on the bottom dielectric layer;

[0035] a middle dielectric layer located in a local area on the edge region and penetrating the semiconductor layer;

[0036] a dummy gate covering layer, at least disposed on the middle dielectric layer;

[0037] A stacked structure is provided on the semiconductor layer on the array region;

[0038] A step structure, provided in a stacked structure on the step region, comprising a plurality of steps, each step comprising a gate layer and a dielectric layer;

[0039] A top dielectric layer is disposed on the step structure and the dummy gate covering layer.

[0040] Optionally, the three-dimensional memory further includes:

[0041] a first metal plug, penetrating the top dielectric layer to the dummy gate capping layer, with its projection on the bottom dielectric layer located within the through hole;

[0042] a second metal plug, penetrating the top dielectric layer and contacting the gate layer of the corresponding step;

[0043] a metal connection structure, penetrating the bottom dielectric layer, the middle dielectric layer, and the dummy gate capping layer, and contacting the first metal plug;

[0044] The source contact structure penetrates the bottom dielectric layer and extends into the semiconductor layer.

[0045] Optionally, the three-dimensional memory further includes:

[0046] a first metal plug, penetrating the top dielectric layer, the dummy gate capping layer, and the middle dielectric layer to the bottom dielectric layer, with its projection on the bottom dielectric layer located within the through hole;

[0047] a second metal plug, penetrating the top dielectric layer and contacting the gate layer of the corresponding step;

[0048] a metal connection structure, penetrating the bottom dielectric layer and extending into the middle dielectric layer, and contacting the first metal plug;

[0049] The source contact structure penetrates the bottom dielectric layer and extends into the semiconductor layer.

[0050] As described above, the method for manufacturing a three-dimensional memory provided by the present invention has the following beneficial effects:

[0051] After forming the dummy gate covering layer, there is no need to etch and remove the remaining dummy gate covering layer on the semiconductor layer in the edge area. Instead, a third dielectric layer is directly formed on the remaining dummy gate covering layer and etched and filled to form a first metal plug, which simplifies the etching process, saves masks, improves production efficiency and reduces production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1-Figure 5 A process flow chart showing a method for manufacturing a three-dimensional memory.

[0053] Figure 6 A schematic diagram showing the steps of a method for manufacturing a three-dimensional memory according to a first embodiment of the present invention.

[0054] Figure 7-Figure 26 Shown is a process flow chart of a method for manufacturing a three-dimensional memory in a first embodiment of the present invention.

[0055] Figures 27-31 It shows a process flow chart of a method for manufacturing a three-dimensional memory in a second embodiment of the present invention.

[0056] Explanation of Figure Numbers

[0057] 1-substrate structure, 101, 103-edge region of substrate structure 1, 102-array region of substrate structure 1, 1021, 1023-step region of substrate structure 1, 1022-core region of substrate structure 1, 100-through hole, 100'-channel hole, 10-substrate, 11-insulating layer, 12-semiconductor layer, 121-first semiconductor layer, 122-second semiconductor layer, 123-third semiconductor layer, 2-step structure, 2a-step, 20-first dielectric layer, 21-second dielectric layer, 22-dummy gate layer, 2 3-pseudo gate covering layer, 24-third dielectric layer, 25-gate layer, 26-fourth dielectric layer, 200-first contact hole, 2'-stacked structure, 3-storage array structure, 31-epitaxial structure, 32-conductive channel structure, 321, 323, 325-dielectric layer, 322-storage layer, 324-channel layer, 300-step contact hole, 400-second contact hole, 401-first metal plug, 402-second metal plug, 500-third contact hole, 601-source contact structure, 602-metal connection structure. DETAILED DESCRIPTION

[0058] The inventors have found that in the current production process of three-dimensional memory, if Figure 1-Figure 5 As shown, in order to enhance the electrical connection between the gate layer of the step in the step structure and the subsequent metal plug, the contact portion between the gate layer and the subsequent metal plug in the step needs to be thickened. The specific process is as follows: the through hole 100 in the semiconductor layer 12 is filled with the first dielectric layer 20 (used as an alignment mark for production) and a step structure 2 is formed on the semiconductor layer 12, as shown in FIG. Figure 1 As shown, the step structure 2 includes a second dielectric layer 21 and a dummy gate layer 22 stacked together, and the step structure includes multiple steps extending sequentially; the second dielectric layer 21 exposed on the top of each step and the semiconductor layer 12 is etched away, and a dummy gate covering layer 23 is deposited to form the dummy gate covering layer 23. The dummy gate covering layer 23 is made of the same material as the dummy gate layer 22. The exposed portion of the dummy gate layer 22 in each step is thickened to obtain a dummy gate contact structure, as shown in FIG. Figure 2 As shown, it can be understood that if the dummy gate layer 22 is exposed on the top surface of each step, the second dielectric layer 21 does not need to be removed, and the dummy gate covering layer 23 can be directly deposited; the dummy gate covering layer 23 on the sidewall of each step is removed so that the dummy gate contact structures between adjacent steps are isolated from each other, as shown in FIG. Figure 3 Remove the dummy gate capping layer 23 on the semiconductor layer 12, so that the dielectric layer filled in the through hole 100 is exposed, as shown Figure 4 As shown, it is convenient to form the metal plug based on the through hole 100 later; further, as Figure 5As shown, a third dielectric layer 24 is formed on the step structure 2 and the semiconductor layer 12. At the same time, a storage array structure (not shown in the figure) is formed on the semiconductor layer 12 next to the step structure 2. At this time, the dummy gate layer 22 and the remaining dummy gate cover layer 23 are replaced by the gate layer 25, and the dummy gate contact structure is replaced by the gate contact structure. Then, a contact hole is first etched in the third dielectric layer 24 and then filled to form a first metal plug 401 and a second metal plug 402. The first metal plug 401 is aligned with the through hole 100 (that is, its projection on the semiconductor layer 12 is located in the through hole 100) and extends to the bottom of the through hole 100. The second metal plug 402 contacts the gate contact structure in the step.

[0059] Among them, when removing the pseudo gate covering layer 23 deposited on the semiconductor layer 12, a separate mask is required for etching, and the process is relatively cumbersome; at the same time, when etching the second dielectric layer 24 to form a contact hole, the contact hole aligned with the through hole 100 requires additional etching to remove the first dielectric layer 20 filled in the through hole 100, and the corresponding etching window is larger, which reduces the flexible selectivity of the etching window.

[0060] Based on this, the present invention proposes a method for manufacturing a three-dimensional memory: after depositing an additional dummy gate covering layer on the step structure, only the dummy gate covering layer on the sidewall of the step is removed, and the dummy gate covering layer remaining on the semiconductor layer is not removed, so as to simplify the etching process; at the same time, when etching to form contact holes, the etching of the contact holes originally passing through the semiconductor layer is changed to stay in the dummy gate covering layer, so as to reduce the corresponding etching window and enhance its design flexibility.

[0061] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0062] See also Figures 6 to 31. It should be noted that the diagrams provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation. The type, quantity and proportion of each component in actual implementation can be changed at will, and the component layout type may also be more complicated. The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read. They are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they have no technical significance. Any modification of the structure, change in the proportional relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "middle" and "first" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0063] Example 1

[0064] The present invention provides a method for manufacturing a three-dimensional memory, such as Figure 6 As shown, it includes the steps of:

[0065] S1. Providing a substrate structure 1, defining an array region 102 and edge regions 101 and 103 in the substrate structure 1, wherein the array region 102 includes a core region 1022 and step regions 1021 and 1023;

[0066] S2, forming a semiconductor layer 12 on the substrate structure 1;

[0067] S3, forming a through hole 100 penetrating the semiconductor layer 12 in the edge regions 101 and 103, and filling the through hole 100 with the first dielectric layer 20;

[0068] S4, forming a stacked structure 2' on the semiconductor layer 12 of the array region 102, wherein the stacked structure 2' includes second dielectric layers 21 and dummy gate layers 22 that are alternately stacked;

[0069] S5, etching the stacked structure 2' to form a step structure 2 on the step regions 1021 and 1023, wherein the step structure 2 includes multiple steps 2a, and each step 2a includes a second dielectric layer 21 and a dummy gate layer 22;

[0070] S6. Forming a dummy gate covering layer 23, the dummy gate covering layer 23 covers the step structure 2 and the semiconductor layer 12 on the edge regions 101 and 103, and the dummy gate covering layer 23 contacts the dummy gate layer 22 exposed in the step 2a;

[0071] S7, forming a third dielectric layer 24, the third dielectric layer 24 covers the step structure 2 and the dummy gate covering layer 23 on the edge regions 101 and 103;

[0072] S8, etching the third dielectric layer 24 to form a first contact hole 200, wherein the projection of the first contact hole 200 on the substrate structure 1 is located within the through hole 100;

[0073] S9 , filling the first contact hole 200 to form a first metal plug 401 .

[0074] In detail, such as Figure 7 As shown, in step S1, an array region 102 and edge regions 101 and 103 are defined in the substrate structure 1, and the array region 102 is located between the edge region 101 and the edge region 103; further, as shown in FIG. Figure 7 As shown, the array region 102 includes a core region 1022 and step regions 1021 and 1023 .

[0075] In more detail, Figure 7 As shown, the substrate structure 1 includes a substrate 10 and an insulating layer 11. The insulating layer 11 is arranged on the substrate 10. The substrate 10 mainly plays a structural support role. The insulating layer 11 is mainly used to prevent the mutual diffusion influence between the subsequently formed semiconductor layer 12 and the substrate 10, so as to enhance the structural stability and reliability; wherein, the substrate 10 can be single crystal silicon, Ge, SiGe, SOI or GOI, etc., and the insulating layer 11 can be a composite layer structure of various insulating materials such as silicon oxide and silicon nitride. Suitable semiconductor materials can be selected according to the actual needs of the device, and are not limited here.

[0076] In detail, such as Figure 8 As shown, in step S2, a semiconductor layer 12 is formed on the substrate structure 1. Optionally, the semiconductor layer 12 is a three-layer composite structure, which includes a first semiconductor layer 121, a second semiconductor layer 122 and a third semiconductor layer 123. The second semiconductor layer 122 is located between the first semiconductor layer 121 and the third semiconductor layer 123, and the second semiconductor layer 122 is used to contact the sidewall of the channel layer passing through the stacked structure 2' in the vertical direction. Among them, the first semiconductor layer 121 and the third semiconductor layer 123 can be polycrystalline silicon, and the second semiconductor layer 122 can be doped polycrystalline silicon to form a SWS structure (doped polycrystalline silicon in the middle and polycrystalline silicon in the upper and lower layers). It can be understood that the specific materials of the first semiconductor layer 121, the second semiconductor layer 122 and the third semiconductor layer 123 are not limited and can be flexibly selected as appropriate.

[0077] In detail, such as Figure 9-10 As shown, in step S3, a through hole 100 penetrating the semiconductor layer 12 is formed on the edge regions 101 and 103, and the through hole 100 is filled with the first dielectric layer 20; Figure 9As shown, a through hole 100 penetrating the semiconductor layer 12 is formed in the region of the semiconductor layer 12 located on the edge regions 101 and 103; Figure 10 As shown, the through hole 100 is filled with a first dielectric layer 20 , and the surface of the formed first dielectric layer 20 is planarized. The first dielectric layer 20 filled in the through hole 100 is mainly used as a subsequent alignment mark.

[0078] In detail, such as Figure 11 As shown, in step S4, multiple layers of alternately stacked second dielectric layers 21 and dummy gate layers 22 are formed on the semiconductor layer 12 of the array region 102 to obtain a stacked structure 2'. That is, the stacked structure 2' is composed of multiple layers of alternately stacked second dielectric layers 21 and dummy gate layers 22. The number of stacked layers of the second dielectric layers 21 and dummy gate layers 22 can be flexibly designed depending on the situation. A layer of the second dielectric layer 21 and an adjacent layer of the dummy gate layer 22 constitute a composite layer, that is, the stacked structure 2' is composed of multiple composite layers.

[0079] In detail, such as Figure 12 As shown, in step S5, the stacked structure 2' is etched to form a step structure 2 in the area where the stacked structure 2' is located on the step areas 1021 and 1023. The step structure 2 includes multiple steps 2a extending in sequence. Each step 2a includes a second dielectric layer 21 and a dummy gate layer 22 stacked together, that is, each step 2a includes a composite layer.

[0080] The stacked structure 2 ′ is subjected to trimming etching or subtracting etching on the step regions 1021 and 1023 to form the step structure 2 . The specific etching process can be found in the prior art and will not be described in detail here.

[0081] In detail, such as Figure 13-14 As shown, step S6 of forming the dummy gate capping layer 23 further includes:

[0082] S61, such as Figure 13 As shown, the second dielectric layer 21 exposed on the step structure 2 and the edge regions 101 and 103 is etched and removed, mainly removing the second dielectric layer 21 exposed on each step 2a and the remaining second dielectric layer 21 on the edge regions 101 and 103;

[0083] S62, such as Figure 14 As shown, a dummy gate covering layer 23 is formed, which covers the step structure 2 and the semiconductor layer 12 on the edge regions 101 and 103 , and is in contact with the dummy gate layer 22 exposed in the step 2 a .

[0084] Optionally, in step S62, the dummy gate covering layer 23 may not cover the area of the stacked structure 2' located on the core area 1022 (even if it is covered, it must be removed later), but it must at least cover the semiconductor layer 12 on the step structure 2 and the edge areas 101 and 103, and be in contact with the dummy gate layer 22 exposed in the step 2a, so as to thicken the dummy gate layer 22 exposed in each step 2a.

[0085] The material of the dummy gate covering layer 23 is the same as that of the dummy gate layer 22. Figure 15 As shown, after forming the dummy gate capping layer 23 and before forming the third dielectric layer 24, that is, between step S6 and step S7, the method for manufacturing the three-dimensional memory further includes:

[0086] The dummy gate covering layer 23 on the sidewall of the step 2 a is removed, and the dummy gate layers 22 in two adjacent steps 2 a are physically isolated.

[0087] The dummy gate capping layer 23 on the stacked structure 2 ′ located on the core region 1022 is also removed at the same time.

[0088] In detail, after removing part of the dummy gate covering layer 23 and before forming the third dielectric layer 24, that is, between step S6 and step S7, the method for manufacturing the three-dimensional memory further includes: forming a memory array structure 3 connected to the step structure 2 in the area where the stacked structure 2' is located on the core area 1022.

[0089] In more detail, Figure 16-18 As shown, the step of forming the memory array structure 3 in the area where the stacked structure 2' is located on the core area 1022 further includes: Figure 16 As shown, the stacked structure 2' is etched in the region located on the core region 1022, and a plurality of channel holes 100' are formed in the region located on the core region 1022 of the stacked structure 2'. The channel holes 100' penetrate the stacked structure 2', and the corresponding etching stops on the semiconductor layer 12; Figure 17-18 As shown, epitaxial growth is first performed in the bottom of the channel hole 100 ′ extending into the semiconductor layer 12 to form an epitaxial structure 31 ; then a multi-layer stacked structure of ONOP is formed at the bottom and sidewalls of the channel hole 100 ′, and finally a dielectric layer is filled to form a conductive channel structure 32 .

[0090] The material of the epitaxial structure 31 can be silicon, germanium or silicon germanium; Figure 17-18As shown, the conductive channel structure 32 includes a dielectric layer 321, a storage layer 322, a dielectric layer 323, a channel layer 324, and a dielectric layer 325, which are sequentially distributed radially inward along the channel hole 100'. The dielectric layer 321, the storage layer 322, and the dielectric layer 323 constitute a storage stack. It is understood that the detailed structure and process of the conductive channel structure 32 can be referred to in the prior art and will not be repeated here.

[0091] In detail, such as Figure 19 As shown, in step S7 , a third dielectric layer 24 is formed, and the third dielectric layer 24 covers the stepped structure 2 , the memory array structure 3 , and the semiconductor layer 12 and the dummy gate covering layer 23 on the edge regions 101 and 103 .

[0092] In addition, if Figure 20 As shown, after forming the third dielectric layer 24 and before etching the third dielectric layer 24, that is, between steps S7 and S8, the method for manufacturing the three-dimensional memory further includes the following steps:

[0093] A gate line dividing groove (not shown) is etched in the area of the stacked structure 2' located on the core area 1022. Through the gate line dividing groove, the dummy gate layer 22 and the dummy gate covering layer 23 on the step areas 1021 and 1023 are replaced with the gate layer 25. Specifically, the remaining dummy gate layer 22 in the stacked structure 2' and the remaining dummy gate covering layer 23 on the step areas 1021 and 1023 (i.e., the remaining portion of the dummy gate covering layer 23 in contact with the dummy gate layer 22) are first removed, and a metal gate layer 25 is formed in the corresponding position. The replacement process requires first etching away the remaining dummy gate layer 22 and the remaining portion of the dummy gate covering layer 23 in contact with the dummy gate layer 22, and then filling and depositing the corresponding position. The material of the gate layer 25 can be metal tungsten.

[0094] In detail, such as Figure 21 As shown, in step S8 , the third dielectric layer 24 is etched to form a first contact hole 200 in the region of the third dielectric layer 24 located on the edge regions 101 , 103 . The projection of the first contact hole 200 on the semiconductor layer 12 is located within the through hole 100 .

[0095] Optionally, the first contact hole 200 penetrates the third dielectric layer 24 and exposes a local area of the dummy gate cover layer 23 located on the edge regions 101 and 103, and the etching stops on the dummy gate cover layer 23. Figure 21 As shown, while etching the third dielectric layer 24 to form the first contact hole 200, a step contact hole 300 is also formed in the area of the third dielectric layer 24 located on the step areas 1021 and 1023. The step contact holes 300 correspond to the steps 2a one by one and expose the top surface of the corresponding steps. Figure 22As shown, in step S9, the first contact hole 200 is filled to form a first metal plug 401; Figure 22 As shown, while the first contact hole 200 is filled to form the first metal plug 401 , the step contact hole 300 is also filled to form the second metal plug 402 . The second metal plug 402 contacts the gate layer 25 corresponding to the step 2 a .

[0096] The first contact hole 200 and the step contact hole 300 are filled with a conductive metal.

[0097] Alternatively, as Figure 23-Figure 25 As shown, the manufacturing method of the three-dimensional memory further includes:

[0098] S10, such as Figure 23 As shown, the substrate structure 1 is removed (ie, the substrate 10 and the insulating layer 11 are removed), and a fourth dielectric layer 26 is formed at a corresponding position, that is, the fourth dielectric layer 26 is formed on a side of the semiconductor layer 12 away from the stacked structure 2 ′;

[0099] S11, such as Figure 24 As shown, the fourth dielectric layer 26 is etched to form a second contact hole 400 penetrating the fourth dielectric layer 26 and extending to the semiconductor layer 12 in the array region 102, and a third contact hole 500 penetrating the fourth dielectric layer 26 and at least a portion of the first dielectric layer 20 in the edge regions 101 and 103. The third contact hole 500 is connected to the first contact hole 200, and the projection of the third contact hole 500 on the semiconductor layer 12 is located within the through hole 100, as shown in FIG. Figure 24 As shown, the third contact hole 500 passes through the dummy gate capping layer 23 and exposes the first metal plug 401;

[0100] S12, such as Figure 25 As shown, the second contact hole 400 is filled to form a source contact structure 601; the third contact hole 500 is filled to form a metal connection structure 602. Figure 24 As shown, in step S11, the fourth dielectric layer 26 is etched to form a second contact hole 400 in the region of the fourth dielectric layer 26 located on the array region 102. The second contact hole 400 exposes the well region (common source structure) formed in the semiconductor layer 12. A third contact hole 500 is formed in the region of the fourth dielectric layer 26 and the semiconductor layer 12 located on the edge regions 101 and 103. The third contact hole 500 is aligned with the through hole 100 (i.e., the projection of the third contact hole 500 on the semiconductor layer 12 is located within the through hole 100). The third contact hole 500 passes through the dummy gate cover layer 23 and exposes the first metal plug 401.

[0101] Among them, such as Figure 24As shown, the etching of the second contact hole 400 stops in the semiconductor layer 12 , and the etching of the third contact hole 500 stops on the third dielectric layer 24 .

[0102] In detail, such as Figure 25 As shown, in step S12, the second contact hole 400 and the third contact hole 500 are filled simultaneously to form a source contact structure 601 and a metal connection structure 602, respectively. The entire filling process is carried out in two steps: first, a filling material (conductive metal material) is deposited on the fourth dielectric layer 26 so that the filling material at least fills the second contact hole 400 and the third contact hole 500, forming a source contact structure 601 and a metal connection structure 602, wherein the source contact structure 601 is a pickup structure (or extension structure) of the well region (or common source structure) for external electrical connection of the well region; then, a surface planarization process is performed to remove the remaining filling material on the surface of the fourth dielectric layer 26.

[0103] Optionally, the method for manufacturing the three-dimensional memory further includes:

[0104] S13 , electrically connecting the second metal plug 402 to the CMOS control wafer to enable the drive control circuit in the CMOS control wafer to drive and control the storage array structure 3 .

[0105] Optionally, the method for manufacturing the three-dimensional memory further includes:

[0106] S14, realize electrical connection with external circuit (or PCB board) through metal connection structure 602, such as Figure 25 As shown, the metal connection structure 602 on the memory array wafer is used to perform packaging connection with an external circuit (or PCB board), which is mainly used for back-end packaging connection of the wafer.

[0107] Through the above series of steps, a three-dimensional memory is finally obtained, such as Figure 26 As shown, it includes:

[0108] The bottom dielectric layer (i.e., the fourth dielectric layer 26 ) includes an array region 102 and edge regions 101 and 103 . The array region 102 includes a core region 1022 and step regions 1021 and 1023 .

[0109] The semiconductor layer 12 is disposed on the bottom dielectric layer 26;

[0110] The middle dielectric layer (i.e., the first dielectric layer 20 ) is located in a local area on the edge regions 101 and 103 and penetrates the semiconductor layer 12 ;

[0111] A dummy gate covering layer 23 is provided at least on the middle dielectric layer;

[0112] The stacked structure 2 ′ is disposed on the semiconductor layer 12 on the array region 102 ;

[0113] The step structure 2 is provided in the stacked structure 2' on the step regions 1021 and 1023, and includes a plurality of steps 2a, each step 2a including a gate layer 25 and a dielectric layer (ie, a second dielectric layer 21);

[0114] The top dielectric layer (ie, the third dielectric layer 24 ) is disposed on the stepped structure 2 and the dummy gate capping layer 23 .

[0115] In detail, such as Figure 26 As shown, the three-dimensional memory further includes:

[0116] The first metal plug 401 penetrates the top dielectric layer to the dummy gate cap layer 23 , and its projection on the bottom dielectric layer (or semiconductor layer 12 ) is located within the through hole 100 ;

[0117] The second metal plug 402 penetrates the top dielectric layer, corresponds to the steps 2a one by one, and contacts the gate layer 25 of the corresponding step;

[0118] The source contact structure 601 penetrates the bottom dielectric layer and extends into the semiconductor layer 12 to electrically lead out the well region (or common source structure);

[0119] The metal connection structure 602 penetrates the bottom dielectric layer, the middle dielectric layer and the dummy gate capping layer 23 and contacts the first metal plug 401 .

[0120] It can be seen that in this embodiment, after depositing an additional dummy gate covering layer 23 on the step structure 2, only the dummy gate covering layer 23 on the side wall of the step 2a is removed, and the dummy gate covering layer 23 remaining on the region of the semiconductor layer 12 located on the edge areas 101 and 103 is not removed. Instead, a third dielectric layer 24 is directly formed on the remaining dummy gate covering layer 23 and etched to fill and form the first metal plug 401, which simplifies the etching process and saves masks, thereby improving production efficiency and reducing production costs. At the same time, when etching to form the first contact hole 200, the etching of the first contact hole 200 that originally passed through the semiconductor layer 12 is changed to stay on the dummy gate covering layer 23, thereby reducing the corresponding etching window and enhancing the design flexibility of the etching window.

[0121] Example 2

[0122] In the first embodiment of the present invention, Figure 21 As shown, the etching of the first contact hole 200 stops on the dummy gate cover layer 23, that is, the first contact hole 200 does not pass through the dummy gate cover layer 23, but the etching of the corresponding third contact hole 500 is over-etched; Figure 24As shown, the second contact hole 400 and the third contact hole 500 are formed by etching simultaneously. After etching through the fourth dielectric layer 26 , the high selectivity of the semiconductor layer 12 to the first dielectric layer 20 filled in the first contact hole 200 is required to achieve this.

[0123] However, this has requirements on the materials of the semiconductor layer 12 and the first dielectric layer 20 filled in the first contact hole 200 , and the corresponding etching depth of the second contact hole 400 is relatively deep, and the process conditions are relatively harsh.

[0124] Based on this, in this embodiment, the etching of the first contact hole 200 passes through the dummy gate covering layer 23 and stops at the bottom of the through hole 100 filled with the first dielectric layer 20, that is, the first contact hole 200 passes through the dummy gate covering layer 23, and correspondingly, the etching of the third contact hole 500 does not need to be over-etched.

[0125] In detail, in step S8, as Figure 27 As shown, when etching to form the first contact hole 200, the etching of the first contact hole 200 stops at the bottom of the filled through hole 100, that is, the first contact hole 200 passes through the dummy gate covering layer 23; then, in step S9, as shown Figure 28 As shown, the first contact hole 200 is filled to form a first metal plug 401 .

[0126] Among them, steps S1 to S10 in this embodiment are the same as those in the first embodiment of the present invention and are not described again here.

[0127] Corresponding to step S8, in step S11 of this embodiment, as shown in FIG. Figure 29 As shown, the fourth dielectric layer 26 is etched to form a second contact hole 400 in the area of the fourth dielectric layer 26 located on the array area 102, and a third contact hole 500 is formed in the area of the fourth dielectric layer 26 located on the edge areas 101 and 103. The third contact hole 500 is aligned with the through hole 100, and the third contact hole 500 exposes the first metal plug 401. However, the third contact hole 500 does not pass through the dummy gate cover layer 23. The etching of the third contact hole 500 stays in the first dielectric layer 20 filled in the through hole 100. In this way, the over-etching process of the third contact hole 500 can be avoided, thereby reducing the difficulty of the etching process.

[0128] In addition, in this embodiment, Figure 30 As shown, the manufacturing method of the three-dimensional memory further includes:

[0129] S12: Fill the second contact hole 400 to form a source contact structure 601; fill the third contact hole 500 to form a metal connection structure 602. It is understood that in this embodiment, the method for manufacturing a three-dimensional memory device further includes steps S13 and S14, which are identical to those in the first embodiment of the present invention. For details, please refer to the first embodiment of the present invention and will not be repeated here.

[0130] Finally, in the embodiment of the present invention, a three-dimensional memory is obtained, such as Figure 31 As shown, it includes:

[0131] The bottom dielectric layer (i.e., the fourth dielectric layer 26 ) includes an array region 102 and edge regions 101 and 103 . The array region 102 includes a core region 1022 and step regions 1021 and 1023 .

[0132] The semiconductor layer 12 is disposed on the bottom dielectric layer 26;

[0133] The middle dielectric layer (i.e., the first dielectric layer 20 ) is located in a local area on the edge regions 101 and 103 and penetrates the semiconductor layer 12 ;

[0134] A dummy gate covering layer 23 is provided at least on the middle dielectric layer;

[0135] The stacked structure 2 ′ is disposed on the semiconductor layer 12 on the array region 102 ;

[0136] The step structure 2 is provided in the stacked structure 2' on the step regions 1021 and 1023, and includes a plurality of steps 2a, each step 2a including a gate layer 25 and a dielectric layer (ie, a second dielectric layer 21);

[0137] The top dielectric layer (ie, the third dielectric layer 24 ) is disposed on the stepped structure 2 and the dummy gate capping layer 23 .

[0138] In detail, such as Figure 31 As shown, the three-dimensional memory further includes:

[0139] The first metal plug 401 penetrates the top dielectric layer, the dummy gate cap layer 23 and the middle dielectric layer to the bottom dielectric layer, and its projection on the bottom dielectric layer (or semiconductor layer 12) is located within the through hole 100;

[0140] The second metal plug 402 penetrates the top dielectric layer, corresponds to the steps 2a one by one, and contacts the gate layer 25 of the corresponding step;

[0141] The source contact structure 601 penetrates the bottom dielectric layer and extends into the semiconductor layer 12 to electrically lead out the well region (or common source structure);

[0142] The metal connection structure 602 penetrates the bottom dielectric layer and extends into the middle dielectric layer, and is in electrical contact with the first metal plug 401 .

[0143] In summary, in the manufacturing method of the three-dimensional memory and the three-dimensional memory provided by the present invention, after depositing an additional dummy gate covering layer on the step structure, only the dummy gate covering layer on the sidewall of the step is removed, and the dummy gate covering layer remaining on the semiconductor layer is not removed. Instead, a dielectric layer is directly formed on the remaining dummy gate covering layer and etched to fill it to form a metal plug, which simplifies the etching process and saves masks, thereby improving production efficiency and reducing production costs. At the same time, when etching to form contact holes, the etching of the contact holes that originally passed through the semiconductor layer is changed to staying in the dummy gate covering layer, thereby reducing the corresponding etching window and enhancing its design flexibility.

[0144] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A three-dimensional memory, characterized in that: include: a semiconductor layer comprising an array region and an edge region; a stacked structure disposed in the array region on the semiconductor layer, the stacked structure comprising alternately stacked second dielectric layers and gate layers, wherein an end of the stacked structure near the edge region comprises a plurality of steps, the plurality of steps extending in a direction from the array region to the edge region, each step comprising the second dielectric layer and the gate layer stacked sequentially in a direction away from the semiconductor layer; A first dielectric layer is located in an edge region of the semiconductor layer and penetrates the semiconductor layer; and A dummy gate covering layer is provided in an edge region on the semiconductor layer and covers at least a surface of the first dielectric layer close to the stacking structure; in a vertical direction, the dummy gate covering layer is higher than a bottom surface of the stacking structure.

2. The three-dimensional memory according to claim 1, wherein: The three-dimensional memory further includes: a third dielectric layer, covering the multiple steps and the dummy gate covering layer; and A fourth dielectric layer covers a surface of the semiconductor layer away from the stacked structure and a surface of the first dielectric layer away from the stacked structure.

3. The three-dimensional memory according to claim 2, wherein: The three-dimensional memory further includes: A first metal plug extends through the third dielectric layer to the dummy gate capping layer, and an orthographic projection of the first metal plug on the semiconductor layer is located in the first dielectric layer; and A metal connection structure penetrates the fourth dielectric layer, the first dielectric layer, and the dummy gate capping layer, and contacts the first metal plug.

4. The three-dimensional memory according to claim 2, wherein: The three-dimensional memory further includes: a first metal plug, passing through the third dielectric layer, the dummy gate capping layer and the first dielectric layer to the fourth dielectric layer; and The metal connection structure penetrates the fourth dielectric layer and contacts the first metal plug.

5. The three-dimensional memory according to claim 2, wherein: The portion of the gate layer located within the step includes a protrusion protruding away from the surface of the semiconductor layer.

6. The three-dimensional memory according to claim 5, characterized in that A gap is provided between the side wall of the protrusion and the adjacent side wall of the step; The third dielectric layer fills the gap.

7. The three-dimensional memory according to claim 2, wherein: A well region is provided in the array region of the semiconductor layer; The three-dimensional memory further includes a source contact structure, wherein the source contact structure penetrates the fourth dielectric layer in the array region and extends into the well region.

8. The three-dimensional memory according to claim 2, wherein: The stacking structure includes a core area and a step area, and the step area is located between the core area and the edge area; The multiple steps are located in the step area of the stacked structure; The three-dimensional memory further includes: a plurality of second metal plugs penetrating the third dielectric layer, each of the second metal plugs being in contact with the gate layer of the corresponding step; as well as, A storage array structure is located in the array region of the stacked structure, and the storage array structure includes a plurality of conductive channel structures penetrating the stacked structure.

9. The three-dimensional memory according to claim 1, wherein: The semiconductor layer includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer stacked in sequence, wherein the third semiconductor layer is located between the second semiconductor layer and the stacked structure.

10. The three-dimensional memory according to claim 9, wherein: The material of the first semiconductor layer includes polysilicon; and / or, The material of the second semiconductor layer includes doped polysilicon; and / or, The material of the third semiconductor layer includes polysilicon.

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