Semiconductor memory device including multiple memory blocks and method of manufacturing the same

Abstract

This disclosure provides a semiconductor memory device comprising a plurality of memory blocks and a method for manufacturing the same. A semiconductor memory device may include a plurality of memory blocks and at least one insulating bridge. The plurality of memory blocks may be defined by a plurality of parallel slits. The at least one insulating bridge may be formed in at least one slit on at least one side of a memory block among the plurality of memory blocks to support adjacent memory blocks.

Description

Technical Field

[0001] The various embodiments generally relate to a semiconductor memory device and a method of manufacturing the same, and more specifically, to a semiconductor memory device comprising a plurality of memory blocks and a method of manufacturing the semiconductor memory device. Background Technology

[0002] To meet customer demands for high performance and low cost, it may be necessary to increase the integration density of semiconductor memory devices. Since the integration density of semiconductor memory devices can be a significant factor in determining their price, increasing the integration density may be necessary.

[0003] In conventional two-dimensional or planar semiconductor memory devices, the integration density can be determined by the area of ​​a unit memory cell, making it highly susceptible to the technology used to form intricate patterns. However, forming intricate patterns may require expensive equipment. Therefore, although the integration density of two-dimensional semiconductor memory devices can be increased, it may still be limited.

[0004] To overcome this limitation, a three-dimensional semiconductor memory device comprising memory cells arranged in three dimensions can be proposed.

[0005] Three-dimensional semiconductor devices can include stacked memory cells. Therefore, the integration density of memory cells can be closely related to the height of the structure, which can potentially increase the aspect ratio due to the high integration density. Summary of the Invention

[0006] In an exemplary embodiment of this disclosure, a semiconductor memory device may include a plurality of memory blocks and insulating bridges. The plurality of memory blocks may be defined by a plurality of slits parallel to each other. Insulating bridges may be formed in the slits on both sides of the memory blocks to support adjacent memory blocks.

[0007] In an exemplary embodiment of this disclosure, a semiconductor memory device may include a plurality of memory blocks and at least one bridge portion. Each memory block may include a stacked structure. The stacked structure may include alternately stacked insulating and conductive layers. The at least one bridge portion may include the insulating layer of the memory block. The at least one bridge portion may be placed between adjacent memory blocks.

[0008] In the example implementation, the bridge portions placed on both sides of a memory block may face each other. Alternatively, the bridge portions placed on both sides of a memory block may not face each other.

[0009] In the example implementation, the number of bridges in the space between storage blocks (i.e., slits) can be equal or different for each slit.

[0010] In an exemplary embodiment of this disclosure, a method of manufacturing a semiconductor memory device may include the steps of: alternately stacking a first insulating layer and a second insulating layer to form a stacked structure. Slits may be formed at the stacked structure to divide the stacked structure into a plurality of memory blocks. Initial bridge portions may be formed simultaneously in each slit to partially connect the memory blocks of the stacked structure to each other. The second insulating layer of the initial bridge portions and memory blocks exposed through the slits may be selectively removed to form spaces. Conductive layers for word lines may be formed in the spaces between the memory blocks and the initial bridge portions. The conductive layers for word lines remaining in the spaces of the initial bridge portions may be removed to form insulating bridge portions.

[0011] In the example implementation, the step of removing the conductive layer for word lines in the space of the initial bridge can be performed simultaneously with the step of removing the conductive layer for word lines retained on the sidewalls and bottom surface of the slit.

[0012] In an example implementation, the step of removing the conductive layer for word lines retained on the sidewalls and bottom surface of the slit may include the following steps: over-etching the conductive layer for word lines retained on the sidewalls of the slit with a width (thickness) greater than the width of the conductive layer for word lines retained on the sidewalls of the slit.

[0013] In an example implementation, the width of the insulating bridge can be determined based on the amount of over-etching of the conductive layer used for word lines.

[0014] In an example implementation, the width of the insulating bridge portion may be twice the width of the over-etched conductive layer for word lines in the initial bridge portion, or twice the width of the conductive layer for word lines retained on the sidewall of the slit. Attached Figure Description

[0015] The above and other aspects, features, and advantages of the subject matter of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an example embodiment;

[0017] Figure 2 This is an equivalent circuit diagram showing a memory block according to an example implementation.

[0018] Figure 3 This is a plan view illustrating a semiconductor memory device according to an example embodiment;

[0019] Figures 4 to 6 This is a plan view showing the memory blocks of a memory cell array according to an example embodiment;

[0020] Figures 7 to 10 It is shown that the definition has along Figure 5 A cross-sectional view of a semiconductor memory block with an insulating bridge section cut by line A-A';

[0021] Figures 11 to 14 It is shown that the definition has along Figure 5 A cross-sectional view of a semiconductor memory block with an insulating bridge section cut by line B-B';

[0022] Figure 15 This is a plan view showing the bridge portion after the formation of the conductive layer for word lines, according to an exemplary embodiment;

[0023] Figure 16 This is a block diagram illustrating a memory system according to an example embodiment;

[0024] Figure 17 This is a block diagram illustrating another memory system according to an example implementation;

[0025] Figure 18 This is a block diagram illustrating a computing system according to an example implementation; and

[0026] Figure 19 This is a block diagram illustrating another computing system according to an example implementation. Detailed Implementation

[0027] Various embodiments of the invention will be described in more detail with reference to the accompanying drawings. The drawings are schematic illustrations of various embodiments (and intermediate structures). Therefore, variations in the configuration and shape of the illustrations can be expected due to, for example, manufacturing techniques and / or tolerances. Consequently, the described embodiments should not be construed as limited to the specific constructions and shapes shown herein, but may include deviations in configuration and shape without departing from the spirit and scope of the invention as defined by the appended claims.

[0028] The invention is described herein with reference to cross-sectional and / or plan views of preferred embodiments. However, the embodiments of the invention should not be construed as limiting the inventive concept. Although some embodiments of the invention will be shown and described, those skilled in the art will understand that changes can be made to these embodiments without departing from the principles and spirit of the invention.

[0029] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an example embodiment.

[0030] Reference Figure 1 The semiconductor memory device 100 in the example implementation may include a memory cell array 110, a row decoder 120, a page buffer circuit 130, and peripheral circuitry 140.

[0031] The memory cell array 110 may include multiple memory blocks BLK1 to BLKn. Each of the memory blocks BLK1 to BLKn may include multiple strings and multiple memory cells. Memory cells may be accessed via word lines and bit lines. For example, a memory cell may include a non-volatile memory cell configured to retain stored data regardless of power supply. However, the memory cell is not limited to non-volatile memory cells.

[0032] In the following description, the semiconductor memory device of the example implementation may include vertical NAND flash memory, and may not be limited to a specific memory type.

[0033] Semiconductor memory device 100 may include a plurality of first line structures L1 and a plurality of second line structures L2. Each first line structure L1 may include stacked word lines. Each second line structure L2 may include bit lines. The first line structure L1 may be part of a memory cell array 110. The first line structure L1 may be electrically connected to a row decoder (X-DEC) 120. The second line structure L2 may be another part of the memory cell array 110. The second line structure L2 may be electrically connected to a page buffer circuit 130 including a plurality of page buffers PB.

[0034] Each first line structure L1 may include at least one drain select line, multiple word lines, and at least one source select line. For example, a first line structure L1 may form a memory block BLK. The row decoder 120 may select any one of the memory blocks BLK1 to BLKn of the memory cell array 110 based on the address information ADD provided from the controller.

[0035] The line decoder 120 can receive the operating voltage Vop generated from the peripheral circuitry 140. The line decoder 120 can transmit the operating voltage Vop to the selected memory block BLK via the first line structure L1. For example, the operating voltage Vop can include programming voltage, pass voltage, and read voltage. Although not shown in the figures, the line decoder 120 may include a pass switch element configured to provide the operating voltage Vop to the selected memory blocks BLK1 to BLKn.

[0036] Page buffer circuit 130 may include multiple page buffers PB connected to the second line structure L2. Page buffer circuit 130 may receive page buffer control signal PB_C from peripheral circuit 140. In addition, data DATA may be transferred between page buffer circuit 130 and peripheral circuit 140.

[0037] Page buffer circuit 130 can control the second line structure L2, i.e., bit lines, of memory cell array 110 in response to page buffer control signal PB_C. For example, page buffer circuit 130 can sense the voltage level of the bit lines in memory cell array 110 in response to page buffer control signal PB_C to detect data stored in memory cells. Furthermore, page buffer circuit 130 can send the detected data to peripheral circuitry 140. Page buffer circuit 130 can apply a voltage corresponding to the data to the bit lines based on page buffer control signal PB_C and data DATA to perform a programming operation. Page buffer circuit 130 can program data into or read data from memory cells connected to word lines that can be activated by row decoder 120.

[0038] Peripheral circuitry 140 can receive command signals CMD, address information ADD, and control signals CTRL from an external device, such as a controller, of the semiconductor memory device 100. Furthermore, data DATA can be transferred between peripheral circuitry 140 and an external device, such as a controller, of the semiconductor memory device 100. Peripheral circuitry 140 can output signals (e.g., row address X-add and page buffer control signal PB_C) based on command signals CMD, address signals ADD, and control signals CTRL for programming data DATA into selected memory cells of the memory cell array 110 or for reading data from those memory cells. Peripheral circuitry 140 can generate various voltages required by the semiconductor memory device 100 (e.g., operating voltage Vop).

[0039] Figure 2 This is an equivalent circuit diagram showing a memory module according to an example implementation.

[0040] Reference Figure 2 The storage block BLKi may include multiple second line structures L2 (i.e., bit lines) and multiple cell strings CSTRs connected between the bit lines BL and the source selection line SSL.

[0041] The second line structure L2 can extend parallel in the y-direction. The unit string CSTR can be connected in parallel between each second line structure L2 and the source selection line SSL.

[0042] Each cell string (CSTR) may include a drain-select transistor (DST), a source-select transistor (SST), and multiple memory cells (MCs). The drain-select transistor (DST) may be connected to the second line structure L2 (i.e., the bit line BL). The source-select transistor (SST) may be connected to a common source line. The memory cells (MCs) may be connected between the drain-select transistor (DST) and the source-select transistor (SST). The drain-select transistor (DST), the memory cells (MCs), and the source-select transistor (SST) may be connected in series with each other in the z-direction.

[0043] The drain select line DSL, multiple word lines WL, and source select line SSL can be stacked between the second line structure L2 and the common source line. The drain select line DSL, word lines WL, and source select line SSL can extend in the x-direction. The drain select line DSL can be connected to the gate of the drain select transistor DST. The source select line SSL can be connected to the gate of the source select transistor SST. The reference numeral CSL can represent a common source line connected to the source of the source select transistor SST.

[0044] Figure 3 This is a plan view illustrating a semiconductor memory device according to an example embodiment.

[0045] Reference Figure 3 Four memory cell arrays 110-1 to 110-4 can be arranged in a matrix shape on a semiconductor substrate along the x and y directions. The memory cell arrays 110-1 to 110-4 can correspond to the plane of a non-volatile memory device.

[0046] The row decoders 120-1 to 120-4 can be arranged at one edge of the memory cell array 110-1 to 110-4. For example, the row decoders 120-1 to 120-4 can be placed at the edge of the memory cell array 110-1 to 110-4 that is parallel to the y-direction.

[0047] Page buffer circuits 130-1 to 130-4 can be arranged at other edge portions of memory cell arrays 110-1 to 110-4. For example, page buffer circuits 130-1 to 130-4 can be placed at the edge portion of other edge portions of memory cell arrays 110-1 to 110-4 that is parallel to the x-direction.

[0048] The memory cell arrays 110-1 to 110-4 can be arranged between the page buffer circuits 130-1 to 130-4 and the peripheral circuits 140.

[0049] exist Figure 3In this configuration, the memory cell arrays 110-1 to 110-4, the row decoders 120-1 to 120-4, the page buffer circuits 130-1 to 130-4, and the peripheral circuits 140 can be placed on substantially the same plane. Alternatively, the memory cell arrays 110-1 to 110-4, the row decoders 120-1 to 120-4, the page buffer circuits 130-1 to 130-4, and the peripheral circuits 140 can be placed on different planes. That is, the memory cell arrays 110-1 to 110-4, the row decoders 120-1 to 120-4, the page buffer circuits 130-1 to 130-4, and the peripheral circuits 140 can have different heights from the surface of the semiconductor substrate. For example, the row decoders 120-1 to 120-4, the page buffer circuits 130-1 to 130-4, and the peripheral circuits 140 can be located below the memory cell arrays 110-1 to 110-4.

[0050] The memory blocks BLK1 to BLKn in the memory cell arrays 110-1 to 110-4 can be divided by slits. The length of each of the memory blocks BLK1 to BLKn can correspond to the length of the memory cell arrays 110-1 to 110-4 in the x-direction. Conversely, for the number n of memory blocks BLK1 to BLKn, the width of the memory blocks BLK1 to BLKn can correspond to the length of the memory cell arrays 110-1 to 110-4 in the y-direction.

[0051] Furthermore, when the number of memory cells in a memory block BLKi can be increased, the height of the memory block BLKi can also be increased. Therefore, memory blocks BLK1 to BLKn, divided by narrow slits, can have very high aspect ratios. Consequently, memory blocks BLK1 to BLKn can have a thin and long rectangular parallelepiped shape to create curvature.

[0052] Figures 4 to 6 This is a plan view showing the memory blocks of a memory cell array according to an example embodiment. Figures 4 to 6 The diagram shows storage blocks BLKi to BLKi+n among multiple storage blocks.

[0053] Reference Figures 4 to 6 Storage blocks BLKi to BLKi+n can be divided by slits S. Multiple channel contact portions CT can be formed within the storage blocks BLKi to BLKi+n. In an example embodiment, the channel contact portions CT can be arranged in a four-row shape. Alternatively, the channel contact portions CT can be arranged in a zigzag pattern, a honeycomb shape, etc.

[0054] In the example implementation, the slit S can be a narrow deep valley. The width of the slit S can be much narrower than the width of the storage blocks BLKi to BLKi+n.

[0055] At least one insulating bridge portion IBR may be formed at the slit S to prevent deformation such as bending at the storage blocks BLKi to BLKi+n. For example, the insulating bridge portion IBR may include multiple insulating layers of the storage blocks BLKi to BLKi+n. The insulating bridge portion IBR may extend from the insulating layers of adjacent storage blocks BLKi to BLKi+n. The insulating bridge portion IBR may be configured to support adjacent storage blocks BLKi to BLKi+n without electrical influence between adjacent storage blocks BLKi to BLKi+n, thereby preventing bending of the storage blocks BLKi to BLKi+n.

[0056] like Figure 4 As shown, the insulating bridges IBRs for each slit S can be arranged such that the corresponding insulating bridges IBRs correspond to each other. Therefore, the number of insulating bridges IBRs for each slit can be equal.

[0057] In addition, such as Figure 5 As shown, the insulating bridge sections (IBRs) for each slit S do not need to face each other, so that adjacent memory blocks BLKi to BLKi+n can be supported by insulating bridge sections (IBRs) at different locations. The insulating bridge sections (IBRs) formed at a slit S can be spaced apart by uniform gaps. The number of insulating bridge sections (IBRs) for each slit S can be equal or different.

[0058] like Figure 6 As shown, the number of insulating bridge sections (IBRs) for each slit S can differ from one another. At slits S where bending is likely to occur relatively frequently, a relatively large number of insulating bridge sections (IBRs) can be arranged with uniform gaps. Conversely, at slits S where bending is likely to occur relatively infrequently, a relatively small number of insulating bridge sections (IBRs) can be arranged with uniform gaps. Therefore, the number of insulating bridge sections (IBRs) for each slit S can differ from one another.

[0059] The insulating bridge section (IBR) can have a width w or less to facilitate its formation using only an insulating layer (without a conductive layer). The width w of the insulating bridge section (IBR) will be described later.

[0060] Figures 7 to 10 It is shown that the definition has along Figure 5 A cross-sectional view of a semiconductor memory block with an insulating bridge section cut by line A-A'. Figures 11 to 14 It is shown that the definition has along Figure 5 A cross-sectional view of the method for taking the insulating bridge portion of the semiconductor memory block by line B-B', and Figure 15 This is a plan view showing the bridge portion after the formation of the conductive layer for word lines, according to an example embodiment.

[0061] Reference Figure 5 , Figure 7 and Figure 11 You can prepare a base layer of 200.

[0062] In an example implementation, the base layer 200 may include a semiconductor substrate (not shown) and a control circuit layer (not shown) formed on the semiconductor substrate. Figure 1 As shown, the control circuit layer may include a line decoder 120, a page buffer circuit 130, and a peripheral circuit 140.

[0063] Alternatively, the base layer 200 may consist only of a semiconductor substrate. The control circuit layer may be arranged on a substrate composed of, for example, a semiconductor substrate. Figure 1 The memory cell array 110 shown defines one side of the base layer 200.

[0064] The base layer 200, which can later form the memory cell array 110, can be divided into a first region MA1, which can later form memory blocks, and a second region MA2, which can later form slits.

[0065] The first insulating layer 210 and the second insulating layer 220 may be alternately stacked on the base layer 200 where a memory cell array can be formed later, to form a stacked structure ST.

[0066] The first insulating layer 210 may include a material that is etch-selective relative to the material of the second insulating layer 220. For example, the first insulating layer 210 may include a silicon oxide layer, and the second insulating layer 220 may include a silicon nitride layer. Figure 7 In this structure, the first insulating layer 210 and the second insulating layer 220 may be stacked alternately four times, but are not limited to a specific number of times. For example, the first insulating layer 210 and the second insulating layer 220 may be stacked alternately dozens or hundreds of times. Furthermore, for example, the first insulating layer may be formed on top of the stacked structure ST.

[0067] The channel contact portion CT can be formed at the laminated structure ST corresponding to the first region MA1. For example, the channel contact portion CT can include a channel hole H formed in the laminated structure ST. The channel contact portion CT can include a channel post P configured to fill the channel hole H. The channel post P can include a buried insulating layer 225a configured to fill the channel hole H, and a cover pattern 225b formed on the buried insulating layer 225a. The cover pattern 225b can be electrically connected to Figure 2The conductive pattern of the bit lines in the diagram. For example, overlay pattern 225b may include a polysilicon layer doped with conductive impurities.

[0068] The channel contact portion CT may further include: a memory layer ML formed on the surface of the channel hole H, and a channel layer CH interposed between the memory layer ML and the channel pillar P. For example, the memory layer ML may include a data storage layer. The data storage layer may include a charge trapping layer such as a silicon nitride layer, a silicon layer, a phase change layer, a nanodot layer, and a variable resistance layer including a metal oxide. The memory layer ML may include a tunnel insulating layer, a data storage layer, and a barrier insulating layer stacked sequentially. The channel layer CH may be formed on the surface of the memory layer ML to fill the channel hole H. The channel layer CH may include a polycrystalline silicon layer doped with conductive impurities.

[0069] In an example implementation, the first region MA1 may be a region where memory cells can be placed. Alternatively, the first region MA1 may be a contact region electrically connected between the memory block BLK and the line decoder. When the first region MA1 is a contact region, a plurality of contact plugs replacing the channel contact portions CT may be formed in the stacked structure ST.

[0070] The laminated structure ST in the second region MA2 can be partially removed to form a slit S and an initial bridge portion BR in the second region MA2. The initial bridge portion BR may include a first insulating layer 210 and a second insulating layer 220 of the laminated structure ST.

[0071] Reference Figure 5 , Figure 8 and Figure 12 The second insulating layer 220 can be selectively removed. For example, the second insulating layer 220 can be selectively removed by a wet etching process. When the second insulating layer 220 may include a silicon nitride layer, the second insulating layer 220 can be selectively removed using a phosphoric acid solution. Therefore, a space 230 can be formed in the stacked structure ST and the initial bridge portion BR.

[0072] Reference Figure 5 , Figure 9 , Figure 13 and Figure 15 The space 230 of the stacked structure ST and the initial bridge portion BR can be filled with a conductive layer 240 for word lines. The conductive layer 240 for word lines may include tungsten, which has excellent gap-filling properties and excellent conductivity. Alternatively, the conductive layer 240 for word lines may include other conductive materials besides tungsten. When the space 230 can be filled with the conductive layer 240 for word lines, the conductive layer 240 for word lines can be formed on the sidewalls and bottom surfaces of the slit S and in the space 230. Here, reference numeral 240S denotes the sidewall conductive layer, and reference numeral 240b denotes the bottom conductive layer.

[0073] To target the conductive layer 240 in each layer isolation stack ST, the conductive layers 240S and 240b for word lines on the sidewalls and bottom surface of the slit S can be anisotropically etched. Because the width of the slit S can be very narrow, it may be necessary to over-etch the conductive layers 240S and 240b for word lines to completely remove them from the sidewalls and bottom surface of the slit S.

[0074] For example, such as Figure 13 As shown, when the sidewall conductive layer 240S can have a width or thickness "a", the actual etching target width can be "a+b" in order to completely remove the retained conductive layer 240S. Therefore, when the width w of the initial bridge portion BR can be set to be equal to or less than "2b", the conductive layer 240 in the initial bridge portion BR can be removed along with the retained conductive layers 240S and 240b. The width w of the initial bridge portion BR can be in a direction parallel to the length direction of the memory block (i.e., Figure 6 The width in the x-direction.

[0075] Reference Figure 5 , Figure 10 and Figure 14 Multiple word lines 240a and the first insulating layer 210 can be alternately stacked in the laminated structure ST in the first region MA1. An insulating bridge portion IBR including the first insulating layer 210 can be formed in the slit S.

[0076] In the example implementation, the isolated conductive layer 240a may be referred to as a word line. Alternatively, the isolated conductive layer 240a located in the upper and lower regions of the stacked structure ST may be understood as a source select line and a drain select line, etc.

[0077] According to an example embodiment, a semiconductor memory device may include insulating bridge portions on both sides of a memory block. Therefore, at least one insulating bridge portion on both sides of the memory block can support the memory block to prevent it from tilting or bending.

[0078] Furthermore, the bridge between adjacent memory blocks may consist of only an insulating layer, so that control of the memory blocks can be performed without electrical impact on the memory blocks.

[0079] Figure 16 This is a block diagram of the configuration of a memory system 1000 according to an embodiment of the present disclosure.

[0080] like Figure 16 As shown, the memory system 1000 may include a memory device 1200 and a controller 1100.

[0081] Memory device 1200 can be used to store various data types such as text, graphics, and software code. Memory device 1200 can be non-volatile memory. Memory device 1200 can be as described above. Figures 1 to 15 The semiconductor device described.

[0082] The controller 1100 can be connected to the host and the memory device 1200, and can access the memory device 1200 in response to requests from the host. For example, the controller 1100 can control reading, writing and erasing, and can communicate with the background operations of the memory device 1200.

[0083] The controller 1100 may include random access memory (RAM) 1110, central processing unit (CPU) 1120, host interface 1130, error correction code (ECC) circuitry 1140 and memory interface 1150.

[0084] RAM 1110 can be used as operating memory for CPU 1120, cache memory between memory device 1200 and host, and buffer memory between memory device 1200 and host. RAM 1110 can be replaced by static random access memory (SRAM) or read-only memory (ROM).

[0085] Host interface 1130 can be connected to a host interface. For example, controller 1100 can communicate with the host via one of various interface protocols, including Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, and proprietary protocols.

[0086] ECC circuit 1140 can detect and correct errors included in data read from memory device 1200 by using error correction codes (ECC).

[0087] The memory interface 1150 can be interfaced with the memory device 1200. For example, the memory interface 1150 may include a NAND interface or a NOR interface.

[0088] For example, controller 1100 may also include a buffer memory (not shown) configured to temporarily store data. The buffer memory may temporarily store data transferred from an external source via host interface 1130, or temporarily store data transferred from memory device 1200 via memory interface 1150. Additionally, controller 1100 may also include ROM for storing code data for connection to the host interface.

[0089] As described above, since the memory system 1000 according to the embodiments of the present disclosure can be reliably manufactured and includes a memory device 1200 having a stable structure and improved characteristics, the characteristics of the memory system 1000 can also be improved.

[0090] Figure 17 This is a block diagram of the configuration of a memory system 1000' according to an embodiment of the present disclosure. In the following, descriptions of content common to the previously described embodiments are omitted.

[0091] like Figure 17 As shown, the memory system 1000' may include a memory device 1200' and a controller 1100. In addition, the controller 1100 may include RAM 1110, CPU 1120, host interface 1130, ECC circuit 1140 and memory interface 1150.

[0092] Memory device 1200' may be a non-volatile memory device. Memory device 1200' may be as described above. Figures 1 to 15 The semiconductor device described. Since the memory device 1200' can be formed and manufactured in the manner described above, its detailed description will be omitted.

[0093] Additionally, the memory device 1200' can be a multi-chip package consisting of multiple memory chips. The multiple memory chips can be divided into multiple groups. Multiple groups can communicate with the controller 1100 via first channels CH1 to the k-th channels CHk. Furthermore, memory chips included in a single group can be adapted to communicate with the controller 1100 via a common channel. The memory system 1000' can be modified to allow individual memory chips to be coupled to a single channel.

[0094] As described above, since the memory system 1000' according to the embodiments of this disclosure can be reliably manufactured and can include a memory device 1200' with a stable structure and improved characteristics, the characteristics of the memory system 1000' can also be improved. Furthermore, by using a multi-chip package to form the memory device 1200', the data storage capacity of the memory system 1000' can be further increased.

[0095] Figure 18This is a block diagram of the configuration of a computing system 2000 according to an embodiment of the present disclosure. In the following text, descriptions of content common to the previously described embodiments are omitted.

[0096] like Figure 18 As shown, the computing system 2000 may include a memory device 2100, a CPU 2200, a random access memory (RAM) 2300, a user interface 2400, a power supply 2500, and a system bus 2600.

[0097] The memory device 2100 can store data input through the user interface 2400 and data processed by the CPU 2200. Additionally, the memory device 2100 can be electrically connected to the CPU 2200, RAM 2300, user interface 2400, and power supply 2500. For example, the memory device 2100 can be connected to the system bus 2600 via a controller (not shown), or it can be directly connected to the system bus 2600. When the memory device 2100 is directly connected to the system bus 2600, the functions of the controller can be executed by the CPU 2200 and RAM 2300.

[0098] The memory device 2100 may be a non-volatile memory. Alternatively, the memory device 2100 may be as described above. Figures 1 to 19 The semiconductor memory device described. Additionally, as referenced above... Figure 17 The memory device 2100 may be a multi-chip package consisting of multiple memory chips.

[0099] The computing system 2000 with the above configuration may be one of the components of an electronic device such as a computer, an ultra-portable PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet computer, a cordless phone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a three-dimensional (3D) television, a digital recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device for sending / receiving information in a wireless environment, one of various electronic devices for a home network, one of various electronic devices for a computer network, one of various electronic devices for a telematics network, an RFID device, and / or one of various devices for a computing system.

[0100] As described above, since the computing system 2000 according to the embodiments of this disclosure can be reliably manufactured and can include a memory device 2100 having a stable structure and improved characteristics, the characteristics of the computing system 2000 can also be improved.

[0101] Figure 19 This is a block diagram of a computing system 3000 according to an embodiment of the present disclosure.

[0102] like Figure 19 As shown, the computing system 3000 may include an application 3100, an operating system 3200, a file system 3300, and a translation layer 3400. Additionally, the computing system 3000 may include a hardware layer such as a memory device 3500.

[0103] Operating system 3200 manages the software and hardware resources of computing system 3000. Operating system 3200 can control program execution of the central processing unit. Application 3100 may include various application programs executed by computing system 3000. Application 3100 may be an entity executed by operating system 3200.

[0104] File system 3300 can refer to a logical structure configured to manage data and files existing in computing system 3000. File system 3300 can organize files or data to be stored in storage device 3500 according to rules. File system 3300 can be determined based on the operating system 3100 used in computing system 3000. For example, when operating system 3100 is a Microsoft Windows-based system, file system 3300 can be a File Allocation Table (FAT) or NT File System (NTFS). Alternatively, when operating system 3100 is a Unix / Linux-based system, file system 3300 can be an Extended File System (EXT), a Unix File System (UFS), or a Journaling File System (JFS).

[0105] Translation layer 3400 can translate addresses suitable for memory device 3500 in response to requests from file system 3300. For example, translation layer 3400 can translate logical addresses generated by file system 3300 into physical addresses of memory device 3500. The mapping information between logical and physical addresses can be stored in an address translation table. For example, translation layer 3400 can be a flash translation layer (FTL) or a universal flash link layer (ULL), etc.

[0106] Memory device 3500 may be non-volatile memory. Memory device 3500 may be as described above. Figures 1 to 15 The semiconductor memory device described. The computing system 3000 having the above configuration can be divided into an operating system layer operating in an upper region and a controller layer operating in a lower region. The operating system 3100, application 3200, and file system 3300 can be included in the operating system layer and driven by the operating memory. Additionally, a translation layer 3400 can be included in either the operating system layer or the controller layer.

[0107] In one embodiment, the semiconductor device may include: a plurality of memory blocks; and at least one insulating bridge portion connecting adjacent memory blocks among the plurality of memory blocks.

[0108] The embodiments described above in this teaching are intended to illustrate, not limit, the teaching. Various alternatives and equivalents are possible. This teaching is not limited to the embodiments described herein. This teaching is also not limited to any particular type of semiconductor device. Other additions, reductions, or modifications based on this disclosure are possible and are intended to fall within the scope of the appended claims.

[0109] Cross-references to related applications

[0110] This application claims priority to Korean Application No. 10-2020-0117386, filed on September 14, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: a plurality of memory blocks divided by a plurality of slits arranged in parallel to each other by uniform gaps; and at least one insulating bridge formed in each of the slits on both sides of each of the plurality of memory blocks to support adjacent memory blocks, wherein each of the plurality of memory blocks comprises: a stacked structure comprising insulating layers and conductive layers alternately stacked, wherein the conductive layers are over-etched with respect to the insulating layers at side surfaces of the slits, and wherein a width of the insulating bridge in a length direction of the slit is equal to or less than twice an over-etching amount of the conductive layers.

2. The semiconductor memory device according to claim 1, wherein, each of the plurality of memory blocks further comprises: a plurality of channel structures formed through the stacked structure.

3. The semiconductor memory device of claim 1, wherein, the at least one insulating bridge comprises an insulating layer extending from the insulating layers of the adjacent memory blocks.

4. The semiconductor memory device according to claim 1, wherein, the at least one insulating bridge formed in each of the slits on both sides of the memory blocks is arranged to face each other.

5. The semiconductor memory device of claim 1, wherein, the insulating bridges on the both sides of the memory blocks are arranged at positions where the insulating bridges do not face each other.

6. The semiconductor memory device of claim 1, wherein, a number of the insulating bridges arranged at each slit is the same.

7. The semiconductor memory device of claim 1, wherein, a number of the insulating bridges formed in each slit is different. 8.A semiconductor memory device, comprising: a plurality of memory blocks comprising a stacked structure comprising insulating layers and conductive layers alternately stacked; and at least one bridge comprising the insulating layers of the memory blocks placed in at least one space between the memory blocks, wherein the conductive layers are over-etched with respect to the insulating layers at side surfaces of the space, wherein a width of the bridge in a length direction of the space is equal to or less than twice an over-etching amount of the conductive layers, and wherein the bridges on both sides of one memory block are arranged at positions where the bridges do not correspond to each other.

9. The semiconductor memory device of claim 8, wherein, a number of the bridges formed in each space is equal to each other.

10. The semiconductor memory device of claim 8, wherein, a number of the bridges in each space is different from each other. 11.A method of manufacturing a semiconductor memory device, comprising the steps of: alternately stacking first and second insulating layers at least once to form a stacked structure; forming a plurality of slits in the stacked structure to divide the stacked structure into a plurality of memory blocks; forming an initial bridge in a slit to partially connect the stacked structure to the initial bridge; selectively removing the second insulating layer of the initial bridge exposed through the slit and the second insulating layer of the plurality of memory blocks exposed through the slit to form a space; forming a conductive layer for a word line in the memory blocks and the space of the initial bridge; and removing the conductive layer for the word line remaining in the space of the initial bridge to form an insulating bridge. ​ wherein the step of removing the conductive layer for the word line remaining in the space of the initial bridge portion includes a step of over-etching the conductive layer for the word line remaining on the sidewall of the slit with a thickness greater than a width of the conductive layer for the word line remaining on the sidewall of the slit, wherein a width of the insulating bridge portion is not more than twice a width of the conductive layer for the word line that is over-etched in the initial bridge portion.

12. The method of claim 11, wherein, The step of removing the conductive layer for the word line remaining in the space of the initial bridge portion includes a step of simultaneously performing a process of removing the conductive layer for the word line remaining on the sidewall and the bottom surface of the slit.

13. The method of claim 12, wherein, The step of removing the conductive layer for the word line remaining on the sidewall and the bottom surface of the slit includes a step of over-etching the conductive layer for the word line remaining on the sidewall of the slit with the thickness greater than the width of the conductive layer for the word line remaining on the sidewall of the slit.

14. A semiconductor memory device, comprising: a plurality of memory blocks divided by a plurality of slits; and at least one insulating bridge portion connecting adjacent memory blocks among the plurality of memory blocks, wherein each of the plurality of memory blocks includes: a stacked structure including insulating layers and conductive layers alternately stacked, wherein the conductive layers are over-etched with respect to the insulating layers at a side surface of the slit, and wherein a width of the insulating bridge portion in a length direction of the slit is equal to or less than twice an over-etching amount of the conductive layers.

15. The semiconductor memory device of claim 14, wherein, The at least one insulating bridge portion extends from insulating layers constituting the plurality of memory blocks.

16. The semiconductor memory device of claim 14, wherein, The at least one insulating bridge portion is located in a slit for defining the plurality of memory blocks.

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