Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

The present disclosure provides a semiconductor storage device with low contact resistance of a trench and a manufacturing method thereof. The semiconductor storage device of an embodiment includes a plurality of first wiring layers, a first pillar, a second wiring layer, a semiconductor-containing layer, and a first insulating layer. The plurality of first wiring layers are stacked in a first direction. The first pillar extends inside the plurality of first wiring layers along the first direction and includes a first semiconductor layer. The second wiring layer is disposed above an upper end of the first semiconductor layer and extends along a second direction intersecting the first direction. The semiconductor-containing layer has a first portion, a second portion, and a third portion. The first portion is disposed between the upper end of the first semiconductor layer and a bottom surface of the second wiring layer. The second portion is continuous with the first portion and is disposed along a side surface of the second wiring layer. The third portion is continuous with an upper end of the second portion and extends along a direction intersecting the first direction. The first insulating layer is disposed between the first portion and the second wiring layer and between the second portion and the second wiring layer. At least an upper surface of the third portion contains a metal.

Description

[0001] This application claims priority from Japanese Patent Application No. 2020-153733 (filing date: September 14, 2020), the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the semiconductor memory device. Background Art

[0003] A NAND flash memory in which memory cells are three-dimensionally stacked is known. Summary of the Invention

[0004] An object of the present invention is to provide a semiconductor memory device having low channel contact resistance.

[0005] A semiconductor memory device according to an embodiment includes a plurality of first wiring layers, a first pillar, a second wiring layer, a semiconductor-containing layer, and a first insulating layer. The plurality of first wiring layers are stacked in a first direction. The first pillar extends along the first direction within the plurality of first wiring layers and includes the first semiconductor layer. The second wiring layer is arranged above the upper end of the first semiconductor layer and extends along a second direction intersecting the first direction. The semiconductor-containing layer includes a first portion, a second portion, and a third portion. The first portion is arranged between the upper end of the first semiconductor layer and the bottom surface of the second wiring layer. The second portion is in contact with the first portion and is provided along a side surface of the second wiring layer. The third portion is in contact with the upper end of the second portion and extends in a direction intersecting the first direction. The first insulating layer is arranged between the first portion and the second wiring layer and between the second portion and the second wiring layer. At least the upper surface of the third portion contains metal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 This is a block diagram showing a circuit configuration of a semiconductor memory device according to the first embodiment.

[0007] Figure 2 This is a circuit diagram of a memory cell array of the semiconductor memory device according to the first embodiment.

[0008] Figure 3 It is a plan view of a memory cell array of the semiconductor memory device according to the first embodiment.

[0009] Figure 4 It is a cross-sectional view of a memory cell array of the semiconductor memory device according to the first embodiment.

[0010] Figure 5 It is a cross-sectional view of a characteristic portion of the memory cell array of the semiconductor memory device according to the first embodiment.

[0011] Figure 6 It is a perspective view of the vicinity of a selection transistor in a memory cell array of the semiconductor memory device according to the first embodiment.

[0012] Figures 7 to 18 It is a diagram for explaining an example of a method for manufacturing the semiconductor memory device according to the first embodiment.

[0013] Figure 19 It is a cross-sectional view of a characteristic portion of a memory cell array of a semiconductor memory device according to the first modification.

[0014] Figure 20 It is a cross-sectional view of a characteristic portion of a memory cell array of a semiconductor memory device according to a second modification.

[0015] Figure 21 It is a cross-sectional view of a characteristic portion of a memory cell array of a semiconductor memory device according to a third modification.

[0016] Description of labels

[0017] 1 semiconductor memory device; 24, 35 wiring layers; 29 semiconductor layer; 33 semiconductor containing layer; 33cA, 33dA upper surface; 33cB, 33dB lower surface; 33a first layer; 33b second layer; 33c third layer; 34 insulating layer; 37 conductor; 50 metal layer; MP memory pillar DETAILED DESCRIPTION

[0018] Hereinafter, a semiconductor storage device according to an embodiment will be described with reference to the accompanying drawings. In the following description, components having the same or similar functions are denoted by the same reference numerals. In addition, repeated descriptions of those components are sometimes omitted. The accompanying drawings are schematic or conceptual diagrams, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily limited to the same as in reality. In this specification, "connection" is not limited to the case of physical connection, but also includes the case of electrical connection. In this specification, "extending in direction A" means, for example, that the dimension in direction A is larger than the smallest dimension of each dimension in the X direction, Y direction, and Z direction described later. "Direction A" is an arbitrary direction.

[0019] The X direction, the Y direction, and the Z direction are defined. The X direction and the Y direction are directions substantially parallel to the surface of the semiconductor substrate 20 described later (see Figure 4). The Y direction is the direction in which the slit SLT described later extends. The X direction is a direction intersecting (e.g., substantially perpendicular to) the Y direction. The Z direction is a direction intersecting (e.g., substantially perpendicular to) the X and Y directions and moving away from the semiconductor substrate 20. However, these expressions are for convenience only and do not specify the direction of gravity. In this embodiment, the Z direction is an example of a "first direction."

[0020] (First embodiment)

[0021] Figure 1 This is a block diagram showing the system configuration of a semiconductor memory device 1. Semiconductor memory device 1 is a nonvolatile semiconductor memory device, such as a NAND flash memory. Semiconductor memory device 1 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0022] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer greater than or equal to 1). The block BLK is a nonvolatile memory cell transistor MC0 to MC7 (see Figure 2 ). Memory cell array 10 includes multiple bit lines and multiple word lines. Each memory cell transistor MC0-MC7 is connected to a bit line and a word line, respectively. When the memory cell transistors MC0-MC7 are not distinguished from each other, they are sometimes referred to as memory cell transistors MC. The detailed structure of memory cell array 10 will be described later.

[0023] The command register 11 holds the command CMD received by the semiconductor memory device 1 from the memory controller 2. The command CMD includes, for example, a command for causing the sequencer 13 to execute a read operation, a write operation, an erase operation, and the like.

[0024] The address register 12 holds address information ADD received by the semiconductor memory device 1 from the memory controller 2. The address information ADD includes, for example, a block address BA, a page address PA, and a column address CA. For example, the block address BA, the page address PA, and the column address CA are used to select a block BLK, a word line, and a bit line, respectively.

[0025] The sequencer 13 controls the overall operation of the semiconductor memory device 1. For example, based on the command CMD held in the command register 11, the sequencer 13 controls the driver module 14, the row decoder module 15, and the sense amplifier module 16 to execute read operations, write operations, and erase operations.

[0026] The driver module 14 generates voltages used in read operations, write operations, and erase operations, etc. The driver module 14 applies the generated voltages to signal lines corresponding to selected word lines based on, for example, the page address PA held in the address register 12 .

[0027] The row decoder module 15 selects a block BLK in the corresponding memory cell array 10 based on the block address BA held in the address register 12. The row decoder module 15 then transfers, for example, a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0028] During a write operation, the sense amplifier module 16 applies a voltage to each bit line based on write data DAT received from the memory controller 2. Furthermore, during a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line and transmits the determination result to the memory controller 2 as read data DAT.

[0029] The communication between the semiconductor memory device 1 and the memory controller 2 supports, for example, the NAND interface standard. For example, the communication between the semiconductor memory device 1 and the memory controller 2 uses a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, a ready / busy signal RBn, and input / output signals I / O.

[0030] The input / output signal I / O is, for example, an 8-bit signal and may include a command CMD, address information ADD, data DAT, and the like.

[0031] The command latch enable signal CLE is a signal indicating that the input / output signal I / O received by the semiconductor memory device 1 is a command CMD.

[0032] The address latch enable signal ALE is a signal indicating that the signal I / O received by the semiconductor memory device 1 is the address information ADD.

[0033] The write enable signal WEn is a signal that instructs the semiconductor memory device 1 to input an input signal I / O.

[0034] The read enable signal REn is a signal that instructs the semiconductor memory device 1 to output the input / output signal I / O.

[0035] The ready / busy signal RBn is a signal that notifies the memory controller 2 whether the semiconductor memory device 1 is in a ready state to accept a command from the memory controller 2 or in a busy state to not accept a command.

[0036] The semiconductor memory device 1 and memory controller 2 described above may be combined to form a single semiconductor device. Examples of such semiconductor devices include memory cards such as SDTM cards and SSDs (solid state drives).

[0037] Next, the electrical structure of the memory cell array 10 will be described.

[0038] Figure 2 1 is a diagram showing an equivalent circuit of the memory cell array 10, and illustrates one block BLK extracted from the memory cell array 10. The block BLK includes a plurality of (eg, four) string units SU0 to SU3.

[0039] A plurality of NAND strings NS are respectively associated with bit lines BL0 to BLm (m is an integer greater than or equal to 1). Each NAND string NS includes, for example, memory cell transistors MC0 to MC7 and select transistors ST1 and ST2.

[0040] The memory cell transistor MC includes a control gate and a charge storage layer, and stores data in a nonvolatile manner. The selection transistors ST1 and ST2 are used to select the string unit SU during various operations.

[0041] The memory cell transistor MC may be a MONOS type using an insulating film as a charge storage layer, or an FG type using a conductive layer as a charge storage layer. In the following, in this embodiment, the MONOS type is described as an example.

[0042] In each NAND string NS, the drain of select transistor ST1 is connected to the associated bit line BL, and the source of select transistor ST1 is connected to one end of the series-connected memory cell transistors MC0-MC7. In the same block BLK, the gates of select transistors ST1 in string units SU0-SU3 are commonly connected to select gate lines SGD0-SGD3, respectively. Select gate lines SGD0-SGD3 are connected to row decoder module 15.

[0043] In each NAND string NS, the drain of select transistor ST2 is connected to the other end of the series-connected memory cell transistors MC0-MC7. Within the same block BLK, the sources of select transistors ST2 are commonly connected to source line SL, and the gates of select transistors ST2 are commonly connected to select gate line SGS. Select gate line SGS is connected to row decoder module 15.

[0044] The bit line BL is commonly connected to one NAND string NS included in each of the string units SU0 to SU3 in each block BLK. The source line SL is commonly connected among, for example, a plurality of blocks BLK.

[0045] A collection of multiple memory cell transistors MC connected to a common word line WL within a string unit SU is referred to as a cell unit CU. For example, the storage capacity of a cell unit CU, which includes memory cell transistors MC each storing one bit of data, is defined as "one page of data." Depending on the number of bits of data stored by the memory cell transistors MC, a cell unit CU may have a storage capacity of two or more pages of data.

[0046] Furthermore, the circuit configuration of the memory cell array 10 included in the semiconductor memory device 1 according to the first embodiment is not limited to the configuration described above. For example, the number of memory cell transistors MC and select transistors ST1 and ST2 included in each NAND string NS can be designed to be any number. The number of string units SU included in each block BLK can also be designed to be any number.

[0047] Figure 3 It is a plan view of the memory cell array 10 included in the semiconductor memory device 1 according to the first embodiment. Figure 3 An example of a top view of one block BLK is shown. In this embodiment, a case where one block BLK includes eight string units SU0 to SU7 is described. In addition, for simplicity of description, a portion of the insulating layer is omitted.

[0048] like Figure 3 As shown, the two sides of the word line WL in the Y direction each have a slit SLT. The slit SLT extends in the X direction. In this embodiment, the select gate line SGS and the word lines WL0 to WL7 (see FIG. 1 ) are sequentially stacked on the semiconductor substrate 20. Figure 4 ). Furthermore, the slit SLT separates the selection gate line SGS and the word line WL by, for example, block BLK.

[0049] like Figure 3 As shown, the string units SU0 to SU7 are arranged in the Y direction, for example. Each string unit SU has a plurality of memory pillars MP. When the string units SU0 to SU7 are not distinguished, they are referred to as a string unit SU.

[0050] The memory column MP corresponds to the NAND string NS. The memory column MP includes memory cell transistors MC0-MC7 and a select transistor ST2 within the NAND string NS. The memory column MP extends in the Z direction, passing through the select gate line SGS and word lines WL0-WL7. The structure of the memory column MP will be described in detail later.

[0051] For example, each string unit SU has two memory pillar groups arranged in the Y direction. In each string unit SU, multiple memory pillars MP are arranged in a zigzag pattern in the X direction. One block BLK has 16 memory pillar groups extending in the X direction and arranged in the Y direction.

[0052] For example, the storage column MP1 of the string unit SU1 and the storage column MP2 of the string unit SU2 are adjacent in the Y direction. The storage column MP3 of the string unit SU2 and the storage column MP4 of the string unit SU3 are adjacent in the Y direction. The storage column MP5 of the string unit SU1 and the storage column MP6 of the string unit SU2 are adjacent in the Y direction. The storage column MP1 and the storage column MP5 are adjacent in the X direction, and the storage column MP2 and the storage column MP6 are adjacent in the X direction. In the X direction, the storage columns MP3 and MP4 are arranged between the storage column MP1 (and MP2) and the storage column MP5 (and MP6). In the Y direction, the storage column MP3 is arranged between the storage column MP1 (and MP5) and the storage column MP2 (and MP6). In addition, in the Y direction, the storage columns MP2 and MP6 are arranged between the storage column MP3 and the storage column MP4. In addition, the arrangement of the storage columns MP can be set arbitrarily.

[0053] Each memory column MP has a selection transistor ST1. The gates of the multiple selection transistors ST1 of each string unit SU are commonly connected to the selection gate line SGD. When the selection gate lines SGD0 to SGD7 are not distinguished, they are referred to as the selection gate line SGD. Figure 3 In the example, the select gate line SGD is located between adjacent memory pillars MP in the Y direction and extends in the X direction. For example, in the string unit SU2, a select gate line SGD2 extending in the X direction is provided between the select transistor ST1 on the memory pillar MP3 and the select transistor ST1 on the memory pillar MP2 (and MP6).

[0054] In the following description, for example, in an XY plane generally parallel to the semiconductor substrate, the direction connecting the center of memory pillar MP1 and the center of memory pillar MP2 is referred to as direction A, and the direction connecting the center of memory pillar MP6 and the center of memory pillar MP4 is referred to as direction B. Direction A is a direction generally parallel to the semiconductor substrate and different from the X and Y directions. Direction B is a direction generally parallel to the semiconductor substrate and intersecting direction A.

[0055] In this embodiment, in two adjacent string units SU, the select transistors ST1 of two memory columns MP adjacent in the A direction or the B direction are commonly connected to a single bit line BL via contact plugs CP1 and CP2. In other words, the two select transistors ST1 disposed between two select gate lines SGD and adjacent in the A direction or the B direction are commonly connected to a single contact plug CP1. The contact plug CP1 is an example of a "first conductor."

[0056] For example, the semiconductor containing layer 33 of the memory pillar MP1 of the string unit SU1 and the semiconductor containing layer 33 of the memory pillar MP3 of the string unit SU2 adjacent in the A direction are connected to one contact plug CP1. Similarly, for example, the semiconductor containing layer 33 of the memory pillar MP6 of the string unit SU2 and the semiconductor containing layer 33 of the memory pillar MP4 of the string unit SU3 adjacent in the B direction are connected to one contact plug CP1.

[0057] A contact plug CP2 is provided on the contact plug CP1. The contact plug CP2 connects one of a plurality of bit lines BL extending in the Y direction to the contact plug CP1.

[0058] Figure 4 It is a cross-sectional view of a memory cell array 10 included in the semiconductor memory device 1 according to the first embodiment. Figure 4 It is along Figure 3 Cross-sectional view of line A1-A2.

[0059] like Figure 4 As shown, an insulating layer 21 is provided on a semiconductor substrate 20. For example, a silicon oxide film (SiO2) is used for the insulating layer 21. Furthermore, circuits such as a row decoder module 15 or a sense amplifier module 16 may be provided in the region where the insulating layer 21 is formed, that is, between the semiconductor substrate 20 and the wiring layer 22.

[0060] A wiring layer 22 extending in the X direction and functioning as a source line SL is provided on the insulating layer 21. The wiring layer 22 is formed of a conductive material, for example, an n-type semiconductor, a p-type semiconductor, or a metal material.

[0061] An insulating layer 23 is provided on the wiring layer 22. The insulating layer 23 is made of SiO2, for example.

[0062] Nine wiring layers 24 and nine insulating layers 25, functioning as select gate lines SGS and word lines WL0 to WL7, are alternately stacked on insulating layer 23 from the bottom. Insulating layer 25 is located between adjacent wiring layers 24. Wiring layer 24 is an example of a "first wiring layer."

[0063] Wiring layer 24 is formed from a conductive material, such as an n-type semiconductor, a p-type semiconductor, or a metal material. The following describes a case where a stacked structure of titanium nitride (TiN) and tungsten (W) is used as wiring layer 24. TiN functions as a barrier layer to prevent the reaction between W and SiO2 during W film formation using CVD (chemical vapor deposition), or as an adhesion layer to improve the adhesion of W. Furthermore, SiO2, for example, can be used for insulating layer 25.

[0064] A memory pillar MP is provided within the stack of wiring layers 24 and insulating layers 25. The memory pillar MP is an example of a "first pillar" and a "second pillar." The memory pillar MP penetrates the nine wiring layers 24, with its bottom surface reaching the wiring layer 22. The memory pillar MP includes a bulk insulating film 26, a charge storage layer 27, a tunnel insulating film 28, a semiconductor layer 29, a core layer 30, and a cap layer 31. The semiconductor layer 29 is an example of a "first semiconductor layer."

[0065] The memory column MP is located in the hole. The hole passes through multiple wiring layers 24 and multiple insulating layers 25, and the bottom surface reaches the wiring layer 22. The block insulating film 26, the charge storage layer 27, and the tunnel insulating film 28 are stacked in this order from the inner circumference of the hole to the inside. The side surface of the semiconductor layer 29 is in contact with the tunnel insulating film 28, and the bottom surface is in contact with the wiring layer 22. The semiconductor layer 29 is a region where the channels of the selection transistor ST2 and the memory cell transistor MC are formed. The semiconductor layer 29 functions as a signal line that connects the current path of the selection transistor ST2 and the memory cell transistors MC0 to MC7. The core layer 30 is located inside the semiconductor layer 29. A cap layer 31 is provided on the semiconductor layer 29 and the core layer 30, the side surface of which is in contact with the tunnel insulating film 28. The memory column MP includes the semiconductor layer 29 that passes through the interior of the multiple wiring layers 24 and extends in the Z direction.

[0066] The bulk insulating film 26, the tunnel insulating film 28, and the core layer 30 are, for example, SiO2. The charge storage layer 27 is, for example, a silicon nitride film (SiN). The semiconductor layer 29 and the cap layer 31 are, for example, polysilicon.

[0067] Memory cell transistors MC0 to MC7 are each composed of a memory pillar MP and eight wiring layers 24 functioning as word lines WL0 to WL7. Similarly, select transistor ST2 is composed of a memory pillar MP and a wiring layer 24 functioning as select gate line SGS.

[0068] Above the memory pillar MP, a selection transistor ST1 is formed by a semiconductor containing layer 33, an insulating layer 34, and a wiring layer 35. The channel region of the selection transistor ST1 is formed by the first layer 33a and the second layer 33b of the semiconductor containing layer 33 along the side and bottom surfaces of the wiring layer 35.

[0069] The semiconductor-containing layer 33 includes a first layer 33a, a second layer 33b, and a third layer 33c. The first layer 33a is an example of the "first portion" and the "fourth portion." The second layer 33b is an example of the "second portion" and the "fifth portion." The third layer 33c is an example of the "third portion." The semiconductor-containing layer 33 electrically connects the conductor 37 (described later) to the semiconductor layer 29.

[0070] The first layer 33a extends in a certain direction in the XY plane. For example, the first layer 33a extends in the Y direction. The first layer 33a is located between the upper end of the semiconductor layer 29 and the bottom surface of the wiring layer 35. Figure 4 As shown, a cap layer 31 may also be provided between the semiconductor layer 29 and the first layer 33a. The second layer 33b connects the first layer 33a and the third layer 33c. The second layer 33b extends approximately in the Z direction from the first layer 33a. The second layer 33b is formed along the side of the wiring layer 35. The third layer 33c is connected to the upper end of the second layer 33b and extends in a certain direction within the XY plane. The third layer 33c extends, for example, in the A direction or the B direction. The third layer 33c is located above the upper surface of the wiring layer 35. The third layer 33c connects the two second layers 33b connected to the two adjacent storage pillars MP in the A direction or the B direction. The third layer 33c connects the two adjacent selection transistors ST1. The first layer 33a and the second layer 33b are, for example, polycrystalline silicon or amorphous silicon.

[0071] Figure 5 It is a cross-sectional view of a characteristic portion of the memory cell array 10 included in the semiconductor memory device 1 according to the first embodiment. Figure 5 It will Figure 4 The enlarged view of the semiconductor containing layer 33. The upper surface 33cA of the third layer 33c also contains metal on the basis of semiconductor. The surface 33cA of the third layer 33c is, for example, silicide. Silicide is a compound of silicon and metal. Metals that form silicide are, for example, nickel and cobalt. Figure 5 As shown, the third layer 33c includes, for example, a first region 33c1 and a second region 33c2. The second region 33c2 is located above the first region 33c1 in the Z direction. The first region 33c1 is polycrystalline silicon or amorphous silicon, and the second region 33c2 is silicide.

[0072] The thickness of the third layer 33c is, for example, thicker than that of the second layer 33b. The thickness is the thickness in a direction perpendicular to the surface of the layer extension. In addition, the perimeter of the upper surface 33cA of the third layer 33c is, for example, greater than the perimeter of the lower surface 33cB. When the thickness of the third layer 33c is thick, when an opening is formed to form the conductor 37, the third layer 33c can be prevented from being penetrated. When a semiconductor is combined with a metal (for example, silicided), its volume expands. The thickness of the third layer 33c becomes thicker than that of the second layer 33b by combining with the metal. The thickness of the third layer 33c can also be formed to be thicker than that of the second layer 33b by selectively growing a semiconductor on the third layer 33c.

[0073] The insulating layer 34 is located between the semiconductor containing layer 33 and the wiring layer 35. The insulating layer 34 is an example of a "first insulating layer". The insulating layer 34 is located along the semiconductor containing layer 33. The insulating layer 34 functions as a gate insulating film of the selection transistor ST1. The insulating layer 34 includes, for example, a first portion located on the first layer 33a and a second portion located on the second layer 33b. That is, the insulating layer 34 includes, for example, a first portion extending in the Y direction and a second portion extending approximately in the Z direction. The insulating layer 34 is, for example, SiO2. In addition, the insulating layer 34 may be a stacked structure or a MONOS structure (more specifically, a stacked structure of an insulating layer, a charge storage layer, and an insulating layer) that enables threshold control.

[0074] The wiring layer 35 is located above the storage column MP. The wiring layer 35 functions as a selection gate line SGD. The wiring layer 35 extends, for example, in the X direction. For example, the center position of the wiring layer 35 in the Y direction is different from the center position of the storage column MP. The wiring layer 35 is arranged above the upper end of the semiconductor layer 29 in the Y direction. The wiring layer 35 is formed of a conductive material, for example, an n-type semiconductor, a p-type semiconductor, or a metal material. The wiring layer 35 is, for example, a single-layer structure of W or a stacked structure of TiN / W. The wiring layer 35 can also be a silicide.

[0075] Above the storage column MP, there is an insulating layer 32 extending in the X direction and the Y direction between the insulating layer 25. The insulating layer 32 functions as an etching stop layer when processing the trench TR (i.e., the groove pattern) described later. The insulating layer 32 is an insulating material that can obtain an etching selectivity ratio with the insulating layer 25, such as SiN. In addition, the insulating layer 32 can also be omitted. The trench TR passes through the insulating layer 25 and the insulating layer 32, and the bottom surface reaches the storage column MP and extends in the X direction. A wiring layer 35 is formed in the trench TR.

[0076] A semiconductor containing layer 33 and an insulating layer 34 are stacked on the side and bottom of the trench TR above the storage column MP. An insulating layer 36 is provided on the side and bottom of the trench TR except for the area where the semiconductor containing layer 33 and the insulating layer 34 are provided, and in the area between the upper surfaces of two adjacent trenches TR in the Y direction. The insulating layer 36 is, for example, SiO2. The height position of the upper surface of the wiring layer 35 in the Z direction is lower than that of the upper surface of the trench TR (close to the semiconductor substrate 20). That is, the height position of the upper surface of the wiring layer 35 in the Z direction is lower than that of the upper surface of the semiconductor containing layer 33 and the insulating layer 34. In addition, the insulating layer 36 provided in the area between the upper surfaces of two adjacent trenches TR in the Y direction may also be omitted.

[0077] On the third layer 33c, there is a conductor 37 that functions as a contact plug CP1. Conductor 37 is an example of a "first conductor." On conductor 37, there is a conductor 38 that functions as a contact plug CP2. On conductor 38, there is a wiring layer 39 that functions as a bit line BL and extends in the Y direction. Conductor 37, conductor 38, and wiring layer 39 are formed of a conductive material, such as a metal material.

[0078] Next, use Figure 6 An example of the arrangement of the selection transistor ST1 and the selection gate line SGD will be described. Figure 6 1 is a perspective view showing the arrangement of the upper portion of the memory column MP, the selection transistor ST1, the selection gate line SGD, the contact plugs CP1 and CP2, and the bit line BL. Figure 6 In the example of FIG, a portion of the insulating layer is omitted for simplicity of illustration. In addition, the selection transistor ST1 is simplified.

[0079] like Figure 6 As shown, for example, two storage columns MP1 and MP3 are arranged at positions inclined relative to the X direction and the Y direction. The wiring layer 35 (selection gate line SGD1) extends in the X direction by passing over a portion of the area of ​​the storage column MP1. Similarly, the wiring layer 35 (selection gate line SGD2) extends in the X direction by passing over a portion of the area of ​​the storage column MP3. The wiring layer 35 is not provided between the storage column MP1 and the storage column MP3. A semiconductor containing layer 33 and an insulating layer 34 are provided on the storage columns MP1 and MP3, and between the storage columns MP1 and MP3. The semiconductor containing layer 33 is connected to the wiring layer 39 via conductors 37 and 38. In addition, in Figure 6 In the example shown in FIG. 1 , the insulating layer 25 between the memory pillar MP1 and the memory pillar MP3 is omitted in order to illustrate the connection between the semiconductor containing layer 33 and the conductor 37 .

[0080] Next, a method for manufacturing the semiconductor memory device 1 according to the first embodiment will be described. Figures 7 to 18 A plan view of the memory cell array 10 during the manufacturing process and a cross section along line B1 - B2 (B1 - B2 cross section) are shown.

[0081] Hereinafter, a method of forming the wiring layer 24 by forming a structure corresponding to the wiring layer 24 with a sacrificial layer and then removing the sacrificial layer and replacing it with a conductive material (wiring layer 24) (hereinafter referred to as "replacement") will be described.

[0082] like Figure 7 As shown, an insulating layer 21, a wiring layer 22, and an insulating layer 23 are sequentially formed on a semiconductor substrate 20. Next, nine sacrificial layers 40 corresponding to the wiring layers 24 and nine insulating layers 25 are alternately stacked. The sacrificial layers 40 can be made of a material that provides a wet etching selectivity with the insulating layers 25. For example, the sacrificial layers 40 are SiN.

[0083] Next, a storage column MP is formed. First, a hole is formed that penetrates the 9 insulating layers 25, the 9 sacrificial layers 40, and the insulating layer 23, and whose bottom reaches the wiring layer 22. Next, the block insulating film 26, the charge storage layer 27, and the tunnel insulating film 28 are stacked in sequence. Then, the block insulating film 26, the charge storage layer 27, and the tunnel insulating film 28 at the bottom of the hole are removed, exposing the wiring layer 22 at the bottom of the hole. Next, a semiconductor layer 29 and a core layer 30 are formed and filled into the hole. Next, the semiconductor layer 29 and the core layer 30 on the topmost insulating layer 25 are removed. At this time, the semiconductor layer 29 and the core layer 30 on the upper part of the hole are also removed. Next, a cap layer 31 is formed in such a manner as to fill the upper part of the hole.

[0084] like Figure 8 As shown, after the insulating layer 25 is formed, the insulating layer 32 is formed so as to cover the upper surface of the memory pillar MP. At this time, the insulating layer 32 in the region where the slit SLT will be formed is removed. Next, the insulating layer 25 is formed on the insulating layer 32.

[0085] like Figure 9 As shown, a trench TR is formed whose bottom reaches the memory pillars MP. At this point, for example, by using the insulating layer 32 as an etch stop, the trench TR can be processed in two stages, thereby reducing processing damage to the upper surfaces of the memory pillars MP. At the bottom of the trench TR, a portion of the upper surfaces of the memory pillars MP arranged in two rows in a zigzag pattern are exposed.

[0086] Next, the semiconductor-containing layer 33, the insulating layer 34A, and the insulating layer 41 are stacked in this order. The insulating layer 41 functions as a protective layer for the insulating layer 34A, for example. For example, a material that can achieve a wet etching selectivity with the insulating layer 34A can be used for the insulating layer 41. For example, the insulating layer 41 is SiN.

[0087] Then, if Figure 10 As shown, a mask pattern covering upper portions of two adjacent memory pillars MP is formed between the two trenches TR.

[0088] like Figure 11 As shown, the insulating layer 34A and the insulating layer 41 in the region not covered by the resist 42 are removed by, for example, CDE (chemical dry etching).

[0089] like Figure 12 As shown, after resist 42 is removed, a portion of semiconductor-containing layer 33 is oxidized to form insulating layer 36. At this time, the region of semiconductor-containing layer 33 whose surface is covered by insulating layer 34A and insulating layer 41 is not oxidized. Furthermore, the end regions of semiconductor-containing layer 33 whose surface is covered by insulating layer 34A and insulating layer 41 may also be oxidized. Then, insulating layer 41 is removed, for example, by wet etching.

[0090] like Figure 13 As shown, insulating layer 34B and insulating layer 34C are sequentially stacked on insulating layer 34A and insulating layer 36. Insulating layer 34B is made of, for example, silicon nitride, and insulating layer 34C is made of, for example, silicon oxide. Furthermore, after a conductive layer is stacked within trench TR, unnecessary portions are etched back to form wiring layer 35.

[0091] like Figure 14 As shown, insulating layers 34A, 34B, and 34C stacked on the upper surface of semiconductor-containing layer 33 are removed to expose the upper surface of semiconductor-containing layer 33. Parts of insulating layers 34A, 34B, and 34C are removed, for example, by chemical mechanical polishing (CMP). Alternatively, a semiconductor may be selectively grown on the exposed semiconductor-containing layer 33 to increase the thickness of semiconductor-containing layer 33.

[0092] like Figure 15 As shown, a metal layer 43 is laminated on the upper surface of the laminate. Metal layer 43 is, for example, nickel. After laminating metal layer 43, the laminate is heated, causing the semiconductor and metal to combine on the upper surface of semiconductor-containing layer 33. For example, the exposed surface of semiconductor-containing layer 33 is silicided. This process is known as self-aligned silicidation. If wiring layer 35 is formed of a semiconductor, wiring layer 35 is also silicided simultaneously. The unsilicided metal layer 43 is then removed.

[0093] like Figure 16 As shown, the insulating layer 25 is formed on the upper surface 33cA of the semiconductor containing layer 33. The insulating layers 34A, 34B, and 34C constitute the insulating layer 34.

[0094] like Figure 17 As shown, after the slit SLT is processed, the sacrificial layer 40 is removed from the side of the slit SLT by wet etching to form a gap AG.

[0095] like Figure 18 As shown, after TiN and W are formed to fill the gaps, the TiN and W formed in the gaps SLT and on the uppermost insulating layer 25 are removed to form the wiring layer 24.

[0096] like Figure 18 As shown, the gap SLT is then filled with an insulating layer 44. Then, a conductor 37 is formed whose bottom surface is in contact with the semiconductor containing layer 33. After the insulating layer 25 is formed, the conductor 38 and the wiring layer 39 are formed.

[0097] The semiconductor memory device 1 according to this embodiment is manufactured through the above steps. The manufacturing steps shown here are just an example, and other steps may be inserted between the steps. In addition, the example of silicide of the wiring layer 35 and the semiconductor containing layer 33 has been described so far, but the wiring layer 35 may also be a stacked film of W, W and TiN, for example. In this case, after becoming Figure 13 After the state, an insulating layer is stacked on the wiring layer 35 to fill the trench TR. Figure 14 Similarly, the insulating layers 34A, 34B, and 34C stacked on the upper surface of the semiconductor containing layer 33 are removed to expose the upper surface of the semiconductor containing layer 33 , and the semiconductor and the metal are chemically combined on the upper surface of the semiconductor containing layer 33 .

[0098] In the semiconductor memory device 1 according to this embodiment, upper surface 33cA of third layer 33c of semiconductor-containing layer 33 contains a metal, such as a silicide. The metal-containing region (e.g., silicide) on upper surface 33cA of third layer 33c prevents the opening from penetrating third layer 33c when forming an opening for forming conductor 37. Furthermore, by pre-combining upper surface 33cA of third layer 33c with the metal (forming a self-aligned silicide), the contact resistance between third layer 33c and conductor 37 is reduced.

[0099] (First Modification)

[0100] A first modification of the semiconductor memory device 1 according to the first embodiment will be described. Figure 19 It is a cross-sectional view of a characteristic portion of a memory cell array 10 included in a semiconductor memory device 1 according to a first modification. Figure 19This is an enlarged view of the vicinity of the semiconductor containing layer 33. The semiconductor memory device according to the first modification has the same configuration as the semiconductor memory device 1 according to the first embodiment except for the configuration described below.

[0101] The semiconductor-containing layer 33 includes a first layer 33a, a second layer 33b, and a third layer 33d. The structure of the third layer 33d differs from that of the third layer 33c of the semiconductor-containing layer 33 according to the first embodiment. The entire thickness direction of the third layer 33d contains metal. For example, the entire thickness direction of the third layer 33d is chemically bonded with the metal, for example, forming a fully silicided layer. The thickness of the third layer 33d is, for example, greater than the thickness 33b of the second layer, and the perimeter of the upper surface 33dA of the third layer 33d is, for example, greater than the perimeter of the lower surface 33dB.

[0102] The configuration according to the first modification example can also produce the same effects as those of the first embodiment.

[0103] (Second Modification)

[0104] A second modification of the semiconductor memory device 1 according to the first embodiment will be described. Figure 20 It is a cross-sectional view of a characteristic portion of a memory cell array 10 included in a semiconductor memory device 1 according to a second modification. Figure 20 This is an enlarged view of the vicinity of the semiconductor containing layer 33. The semiconductor memory device according to the second modification has the same configuration as that of the semiconductor memory device 1 according to the first embodiment except for the configuration described below.

[0105] The semiconductor storage device according to the second modification further includes a metal layer 50 on the upper surface 33cA of the third layer 33c of the semiconductor containing layer 33. The metal layer 50 includes, for example, titanium, tantalum, or tungsten. Figure 14 As shown, the metal layer 50 is formed by selectively growing the metal layer 50 on the exposed conductive surface after exposing the upper surface 33cA of the third layer 33c. The selective growth of the metal layer 50 can be performed by, for example, area selective atomic layer deposition (ALD) or electroless plating.

[0106] The configuration of the second modified example also achieves the same effects as those of the first embodiment. Furthermore, the presence of the metal layer 50 further prevents the third layer 33c from being penetrated by the openings for forming the conductors 37. Furthermore, titanium, tantalum, and tungsten used in the metal layer 50 are less likely to cause contamination in subsequent processes than nickel and cobalt used for silicide formation. For example, nickel and cobalt are difficult to remove if they enter the etching equipment for the insulating layer used in subsequent processes, but titanium, tantalum, and tungsten are easier to remove than nickel and cobalt.

[0107] (Third Modification)

[0108] A third modification of the semiconductor memory device 1 according to the first embodiment will be described. Figure 21 It is a cross-sectional view of a characteristic portion of a memory cell array 10 included in a semiconductor memory device 1 according to a third modification. Figure 21 This is an enlarged view of the vicinity of the semiconductor containing layer 33. The configuration of the semiconductor memory device according to the first modification example, except for the configuration described below, is the same as that of the semiconductor memory device 1 according to the first embodiment.

[0109] The semiconductor device according to the third modification further includes a metal layer 50 on the upper surface 33dA of the third layer 33d according to the first modification. The metal layer 50 is the same as that of the second modification.

[0110] The configuration according to the third modification can also produce the same effects as those of the first embodiment.

[0111] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments may be implemented in various other ways and may be omitted, replaced, or modified without departing from the spirit of the invention. These embodiments and / or their variations are intended to be within the scope and spirit of the invention and are also intended to be within the scope of the invention as set forth in the claims and their equivalents.

Claims

1. A semiconductor memory device comprising: a plurality of first wiring layers stacked in a first direction; a first pillar extending along the first direction within the plurality of first wiring layers and comprising a first semiconductor layer; a second wiring layer disposed above an upper end of the first semiconductor layer and extending along a second direction intersecting the first direction; a semiconductor-containing layer having a first portion, a second portion, and a third portion, wherein the first portion is disposed between an upper end of the first semiconductor layer and a bottom surface of the second wiring layer, the second portion is in contact with the first portion and is disposed along a side surface of the second wiring layer, and the third portion is in contact with an upper end of the second portion and extends in a direction intersecting the first direction; as well as a first insulating layer disposed between the first portion and the second wiring layer and between the second portion and the second wiring layer; At least the upper surface of the third portion contains metal, Said Part 3 has: a first layer comprising polycrystalline silicon or amorphous silicon; and The second layer, located above the first layer, includes silicide.

2. The semiconductor memory device according to claim 1, A metal layer is further provided, and the metal layer is laminated on the upper surface of the third portion.

3. The semiconductor memory device according to claim 1, The thickness of the third portion is thicker than the thickness of the second portion.

4. The semiconductor memory device according to claim 1, The circumference of the upper surface of the third portion is greater than or equal to the circumference of the lower surface of the third portion.

5. The semiconductor memory device according to claim 1, further comprising a first conductor electrically connected to the third portion and extending above the third portion along the first direction; The circumference of the upper surface of the third portion is longer than the circumference of the first conductor.

6. The semiconductor memory device according to claim 1, further comprising: a second pillar extending along the first direction within the plurality of first wiring layers and including a second semiconductor layer; and a third wiring layer disposed above the upper end of the second semiconductor layer and extending along the second direction; The semiconductor containing layer further includes a fourth portion and a fifth portion. The fourth portion is arranged between the upper end of the second semiconductor layer and the bottom surface of the third wiring layer. The fifth portion extends from the fourth portion toward the third portion along the side surface of the second wiring layer.

7. A method for manufacturing a semiconductor memory device, comprising: a step of alternately stacking conductive layers or sacrificial layers and insulating layers in a first direction; forming a hole extending in a first direction in the stacked layer, and forming a first pillar including a first semiconductor layer inside the hole; a step of laminating a first insulating layer on the first pillar and forming a groove in the first insulating layer; a step of forming a semiconductor-containing layer on the first semiconductor layer by oxidizing a portion of the second semiconductor layer after forming the second semiconductor layer in the groove; forming a second wiring layer in the groove; as well as A step of exposing a portion of the semiconductor-containing layer and combining the semiconductor in the exposed portion with a metal.

8. The method for manufacturing a semiconductor memory device according to claim 7, The second wiring layer and the semiconductor containing layer are simultaneously combined with metal.

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