Semiconductor device and method of manufacturing the same

Abstract

An object is to provide a reverse-conducting IGBT that improves the trade-off relationship between the recovery loss and the forward voltage drop during the operation of a diode. The first composite region is provided at least on the second main surface side of the seventh semiconductor layer in the sixth semiconductor layer and in a region that overlaps the seventh semiconductor layer when viewed from above.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Generally, there are various requirements for power devices, such as the ability to withstand voltage and the guarantee of a safe operating range that does not damage the components during operation. One of the most important requirements is low loss. Low loss in power devices has the effect of miniaturization and lightness of the device. In a broad sense, it has the effect of caring about the global environment by reducing energy consumption. Moreover, it is required to achieve these characteristics at the lowest possible cost.

[0003] As a method for solving the above-mentioned problem, a reverse-conducting IGBT (RC-IGBT) having characteristics of an IGBT (Insulated Gate Bipolar Transistor) and a diode in one structure has been proposed.

[0004] The reverse conducting IGBT has several technical problems, one of which is that the recovery loss during diode operation is large. Patent document 1 discloses that in order to improve the recovery loss during diode operation, the diode region p + A structure in which the area ratio of the type contact layer is reduced.

[0005] Patent Document 1: Japanese Patent No. 5924420

[0006] However, if the diode region p + The method of reducing the area ratio of the type contact layer to reduce the recovery loss during diode operation will result in a problem that although the recovery loss is reduced, the forward voltage drop is deteriorated. In improving the performance of the reverse conducting IGBT, it is important to improve the trade-off relationship between the recovery loss during diode operation and the forward voltage drop. Summary of the invention

[0007] The present invention has been made in order to improve such a problem, and an object of the present invention is to provide a reverse conducting IGBT having an improved trade-off relationship between the recovery loss and the forward voltage drop during diode operation.

[0008] In a semiconductor device according to one embodiment of the present invention, a transistor and a diode are formed on a common semiconductor substrate. In this semiconductor device, the semiconductor substrate has: a first main surface and a second main surface as one main surface and the other main surface; a transistor region in which a transistor is formed; and a diode region in which a diode is formed. The transistor region has: a first semiconductor layer of a first conductivity type provided on the second main surface side of the semiconductor substrate; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer; a third semiconductor layer of the first conductivity type provided closer to the first main surface side of the semiconductor substrate than the second semiconductor layer; a fourth semiconductor layer of the second conductivity type provided on the third semiconductor layer; a second electrode electrically connected to the fourth semiconductor layer; and a first electrode electrically connected to the first semiconductor layer. The diode region has: a fifth semiconductor layer of the second conductivity type provided on the second main surface side of the semiconductor substrate; the second semiconductor layer provided on the fifth semiconductor layer; a sixth semiconductor layer of the first conductivity type provided closer to the first main surface side of the semiconductor substrate than the second semiconductor layer; a seventh semiconductor layer of the first conductivity type provided on the sixth semiconductor layer, the impurity concentration of the first conductivity type being higher than that of the sixth semiconductor layer; a second electrode electrically connected to the seventh semiconductor layer; and a first electrode electrically connected to the fifth semiconductor layer. The first composite region is provided at least on the second main surface side of the seventh semiconductor layer in the sixth semiconductor layer and in a region overlapping the seventh semiconductor layer in a plan view.

[0009] Effects of the Invention

[0010] In a semiconductor device according to one embodiment of the present invention, the first composite region is provided at least on the second main surface side of the seventh semiconductor layer in the sixth semiconductor layer and in a region overlapping the seventh semiconductor layer in a plan view. Thereby, the trade-off relationship between the recovery loss and the forward voltage drop during the operation of the diode is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is an overall plan view of the strip-shaped semiconductor device of Embodiment 1.

[0012] Figure 2 is an overall plan view of the island-shaped semiconductor device of Embodiment 1.

[0013] Figure 3 is a plan view of a boundary portion between the IGBT region and the diode region of the semiconductor device of Embodiment 1.

[0014] Figure 4 is a cross-sectional view of a boundary portion between the IGBT region and the diode region of the semiconductor device of Embodiment 1.

[0015] Figure 5It is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the semiconductor device of Embodiment 1.

[0016] Figure 6 It is a cross-sectional view of the boundary portion between the IGBT region and the outer peripheral region of the semiconductor device of Embodiment 1.

[0017] Figure 7 It is a cross-sectional view of the boundary portion between the diode region and the outer peripheral region of the semiconductor device of Embodiment 1.

[0018] Figure 8 It is a cross-sectional view for explaining the manufacturing method of the semiconductor device of Embodiment 1.

[0019] Figure 9 It is a cross-sectional view for explaining the manufacturing method of the semiconductor device of Embodiment 1.

[0020] Figure 10 It is a cross-sectional view for explaining the manufacturing method of the semiconductor device of Embodiment 1.

[0021] Figure 11 It is a cross-sectional view for explaining the manufacturing method of the semiconductor device of Embodiment 1.

[0022] Figure 12 It is a cross-sectional view for explaining the manufacturing method of the semiconductor device of Embodiment 1.

[0023] Figure 13 It is a cross-sectional view for explaining the manufacturing method of the semiconductor device of Embodiment 1.

[0024] Figure 14 It is a cross-sectional view for explaining the manufacturing method of the semiconductor device of Embodiment 1.

[0025] Figure 15 It is a cross-sectional view for explaining the manufacturing method of the semiconductor device of Embodiment 1.

[0026] Figure 16 It is a cross-sectional view for explaining the manufacturing method of the semiconductor device of Embodiment 1.

[0027] Figure 17 It is a cross-sectional view for explaining the manufacturing method of the semiconductor device of Embodiment 1.

[0028] Figure 18 It is a cross-sectional view for explaining the manufacturing method of the semiconductor device of Embodiment 1.

[0029] Figure 19 It is a cross-sectional view for explaining the manufacturing method of the semiconductor device of Embodiment 1.

[0030] Figure 20 It is a cross-sectional view for explaining the manufacturing method of the semiconductor device of Embodiment 1.

[0031] Figure 21 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1.

[0032] Figure 22 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1.

[0033] Figure 23 It is a graph showing the relationship between the area ratio of the defective region and the peak recovery current of the semiconductor device according to Embodiment 1.

[0034] Figure 24 It is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the semiconductor device according to Embodiment 2.

[0035] Figure 25 It is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the semiconductor device according to Embodiment 2.

[0036] Figure 26 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 2.

[0037] Figure 27 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 2.

[0038] Figure 28 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 2.

[0039] Figure 29 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 2.

[0040] Figure 30 It is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the semiconductor device according to Embodiment 3.

[0041] Figure 31 It is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the semiconductor device according to Embodiment 3.

[0042] Figure 32 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 3.

[0043] Figure 33 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 3.

[0044] Figure 34 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 3.

[0045] Figure 35 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 3.

[0046] Figure 36 It is a cross-sectional view showing a method of manufacturing a semiconductor device according to Embodiment 3.

[0047] Figure 37 It is a cross-sectional view showing a method of manufacturing a semiconductor device according to Embodiment 3.

[0048] Figure 38 It is a cross-sectional view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to Embodiment 4.

[0049] Figure 39 It is a cross-sectional view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to Embodiment 4.

[0050] Figure 40 It is a cross-sectional view showing a method of manufacturing a semiconductor device according to Embodiment 4.

[0051] Figure 41 It is a cross-sectional view showing a method of manufacturing a semiconductor device according to Embodiment 4.

[0052] Figure 42 It is a cross-sectional view showing a method of manufacturing a semiconductor device according to Embodiment 4.

[0053] Figure 43 It is a cross-sectional view showing a method of manufacturing a semiconductor device according to Embodiment 4.

[0054] Figure 44 It is a cross-sectional view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to Embodiment 5.

[0055] Figure 45 It is a cross-sectional view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to Embodiment 5.

[0056] Figure 46 It is a cross-sectional view showing a method of manufacturing a semiconductor device according to Embodiment 5.

[0057] Figure 47 It is a cross-sectional view showing a method of manufacturing a semiconductor device according to Embodiment 5.

[0058] Figure 48 It is a cross-sectional view showing a method of manufacturing a semiconductor device according to Embodiment 5.

[0059] Figure 49 It is a cross-sectional view showing a method of manufacturing a semiconductor device according to Embodiment 5.

[0060] Figure 50 It is a top view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to Embodiment 6.

[0061] Figure 51 It is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the semiconductor device of Embodiment 6.

[0062] Figure 52 It is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the semiconductor device of Embodiment 6.

[0063] Figure 53 It is a top view of the boundary portion between the IGBT region and the diode region of the semiconductor device of Embodiment 7.

[0064] Figure 54 It is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the semiconductor device of Embodiment 7.

[0065] Figure 55 It is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the semiconductor device of Embodiment 7.

[0066] Figure 56 It is a top view of the boundary portion between the IGBT region and the diode region of the semiconductor device of Embodiment 8.

[0067] Figure 57 It is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the semiconductor device of Embodiment 8.

[0068] Figure 58 It is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the semiconductor device of Embodiment 8.

[0069] Figure 59 It is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the semiconductor device of Embodiment 9.

[0070] Figure 60 It is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the semiconductor device of Embodiment 9.

[0071] Figure 61 It is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the semiconductor device of Embodiment 10.

[0072] Figure 62 It is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the semiconductor device of Embodiment 10.

[0073] Figure 63 It is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the semiconductor device of Embodiment 11.

[0074] Figure 64It is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the semiconductor device of Embodiment 11.

[0075] Figure 65 It is a top view of the boundary portion between the IGBT region and the diode region of the semiconductor device of Embodiment 12.

[0076] Figure 66 It is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the semiconductor device of Embodiment 12.

[0077] Figure 67 It is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the semiconductor device of Embodiment 12.

[0078] Figure 68 It is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the semiconductor device of Embodiment 13.

[0079] Figure 69 It is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the semiconductor device of the comparative example. Detailed Embodiments

[0080] <Preface>

[0081] In the following description, n-type and p-type represent the conductivity types of semiconductors. In the present invention, the first conductivity type is p-type and the second conductivity type is n-type for description, but it is also possible that the first conductivity type is n-type and the second conductivity type is p-type. Additionally, n - -type represents a concentration lower than that of the n-type, and n + +-type represents a concentration higher than that of the n-type. Similarly, p - -type represents a concentration lower than that of the p-type, and p + +-type represents a concentration higher than that of the p-type.

[0082] In addition, the drawings are only schematic, and the mutual relationships of the sizes and positions of the images shown in different drawings are not necessarily accurately recorded and can be appropriately changed. Also, in the following description, the same reference numerals are used to label the same structural elements in the drawings, and their names and functions are also the same. Therefore, the detailed description of them may sometimes be omitted.

[0083] In addition, in the following description, terms such as "upper", "lower", "side", "front", and "back" indicating specific positions and directions are sometimes used. These terms are only used for the convenience of understanding the content of the embodiments and are used for convenience, and have nothing to do with the direction in actual implementation.

[0084] <Comparative Example>

[0085] Before describing the embodiments, Figure 69 a comparative example is shown. The semiconductor device 1000 of this comparative example is different in the arrangement of the p Figure 1 - Figure 2 type contact layer 6 from the semiconductor device 200 or the semiconductor device 201 shown in Figure 4 p + In addition, compared with the semiconductor device 200 or the semiconductor device 201, the semiconductor device 1000 does not have a defective region 15. Other aspects of the semiconductor device 1000 are the same as those of the semiconductor device 200 or the semiconductor device 201, and the description thereof is omitted here.

[0086] The purpose of the structure of the semiconductor device 1000 is to suppress the deterioration of the forward voltage drop by providing the p + type contact layer 6 in the diode region 102, and to reduce the area ratio of the p + type contact layer 6, thereby reducing the effective concentration of p-type impurities in the anode region composed of the p-type anode layer 5 and the p + type contact layer 6 in the diode region 102 and suppressing the recovery loss of the diode.

[0087] However, if the area ratio of the p + type contact layer 6 is too high, the recovery loss of the diode cannot be sufficiently reduced. When the area ratio of the p + type contact layer 6 is reduced, as the area ratio becomes lower, the ohmic resistance with the emitter electrode 13 increases, and thus the forward voltage drop (Vf) becomes larger. Thus, there is a trade-off relationship between Vf and the recovery loss.

[0088] In addition, even when the area ratio of the p + type contact layer 6 is set low, the recovery loss cannot be reduced to the state where the area ratio is zero. Therefore, there is a limit to reducing the recovery loss, and other methods need to be used to further improve the recovery loss.

[0089] <A. Embodiment 1>

[0090] <A-1. Structure>

[0091] Figure 1 FIG. is a top view showing the RC-IGBT, i.e., the semiconductor device 200, according to Embodiment 1. In addition, Figure 2 FIG. is a top view showing the RC-IGBT, i.e., the semiconductor device 201, having other structures according to Embodiment 1. For the Figure 1 shown semiconductor device 200, IGBT regions 101 and diode regions 102 are arranged in a strip shape and can be simply referred to as "strip type". For the Figure 2For the semiconductor device 201 shown, a plurality of diode regions 102 are provided longitudinally and transversely, and an IGBT region 101 is provided around the diode regions 102, which can be simply referred to as "island type". The detailed planar structures of the strip type and the island type will be described later.

[0092] As Figure 1 shown, the strip type semiconductor device 200 has an IGBT region 101 and a diode region 102 within one semiconductor device. The IGBT region 101 and the diode region 102 extend from one end side of the semiconductor device 200 to the other end side, and are alternately arranged in a strip shape in a direction orthogonal to the extending direction of the IGBT region 101 and the diode region 102. In Figure 1 , there are shown 3 IGBT regions 101 and 2 diode regions 102, and a structure in which all the diode regions 102 are sandwiched by the IGBT regions 101. However, the numbers of the IGBT region 101 and the diode region 102 are not limited to this. The number of the IGBT regions 101 can be greater than or equal to 3, or less than or equal to 3, and the number of the diode regions 102 can be greater than or equal to 2, or less than or equal to 2. Additionally, it can be a structure in which the Figure 1 positions of the IGBT region 101 and the diode region 102 are exchanged, or a structure in which all the IGBT regions 101 are sandwiched by the diode regions 102. Further, the IGBT region 101 and the diode region 102 can also be arranged such that each one is adjacent to each other one by one.

[0093] As Figure 2 shown, the island type semiconductor device 201 has an IGBT region 101 and a diode region 102 within one semiconductor device. When viewed from above, a plurality of diode regions 102 are arranged and configured longitudinally and transversely within the semiconductor device 201, and the periphery of the diode regions 102 is surrounded by the IGBT region 101. That is, a plurality of diode regions 102 are arranged in an island shape within the IGBT region 101. In Figure 2 , there is shown a structure in which the diode regions 102 have 4 columns in the left - right direction of the paper surface and 2 rows in the up - down direction of the paper surface and are arranged in a matrix shape. However, the number and configuration of the diode regions 102 are not limited to this, as long as one or more diode regions 102 are dispersedly arranged within the IGBT region 101 and the periphery of each diode region 102 is surrounded by the IGBT region 101.

[0094] As Figure 1 or Figure 2As shown, in semiconductor device 200 or semiconductor device 201, gate pad region 104 is provided adjacent to IGBT region 101. Gate pad region 104 is a region where a gate pad (hereinafter, referred to as gate pad 104a) is provided. Gate pad 104a is a control pad to which a gate drive voltage for controlling the on / off of semiconductor device 200 or semiconductor device 201 is applied. Gate pad 104a is electrically connected to the buried gate electrode 8 of IGBT region 101 described later. In addition, in semiconductor device 200 or semiconductor device 201, in addition to gate pad 104a, a control pad for detecting the current flowing in the cell region of semiconductor device 200 or semiconductor device 201, that is, a current sense pad, a Kelvin emitter pad for electrically connecting to the p-type channel doping layer 2 of IGBT region 101 described later and applying a gate drive voltage for controlling the on / off of semiconductor device 200 or semiconductor device 201, a temperature sense diode pad for measuring the temperature of semiconductor device 200 or semiconductor device 201, etc. may be provided.

[0095] In semiconductor device 200 or semiconductor device 201, IGBT region 101 and diode region 102 are collectively referred to as the cell region. For the breakdown voltage retention of semiconductor device 200 or semiconductor device 201, a peripheral region 103 is provided around the region where the cell region and gate pad region 104 are combined. A known breakdown voltage retention structure can be appropriately and selectively provided in peripheral region 103. Regarding the breakdown voltage retention structure, for example, it can be configured such that on the surface side, i.e., the first main surface side, of semiconductor device 200 or semiconductor device 201, an FLR (Field Limitting Ring) that surrounds the cell region with a p-type end well layer of p-type semiconductor, and a VLD (Variation of Lateral Doping) that surrounds the cell region with a p-type well layer having a concentration gradient are provided. The number of circular p-type end well layers used for FLR and the concentration distribution used for VLD can be appropriately selected according to the breakdown voltage design of semiconductor device 200 or semiconductor device 201. The first main surface side of semiconductor device 200 or semiconductor device 201 is Figure 4 、 5 the direction indicated by arrow C in, and the second main surface side is Figure 4 、 5 the direction indicated by arrow D in.

[0096] <A-1-1. Local planar structure>

[0097] Figure 3 is an enlarged top view showing the structures of IGBT region 101 and diode region 102 of the RC-IGBT, i.e., the semiconductor device of the present embodiment, and is an enlarged view showing Figure 1The figure of the region surrounded by the dashed line 82 in the semiconductor device 200 or Figure 2 the semiconductor device 201 shown. Additionally, Figure 3 The structure in the first main surface of the semiconductor substrate 120 is shown.

[0098] As Figure 3 shown, trench gates 50 are disposed in a strip shape in the IGBT region 101 and the diode region 102. In the semiconductor device 200, the trench gates 50 extend in the length direction of the IGBT region 101 and the diode region 102, and the length direction of the IGBT region 101 and the diode region 102 is the length direction of the trench gates 50. On the other hand, in the semiconductor device 201, the length direction and the width direction of the IGBT region 101 and the diode region 102 are not particularly distinguished, and in Figure 2 it, the left - right direction of the paper surface can be set as the length direction of the trench gates 50, or the up - down direction of the paper surface can be set as the length direction of the trench gates 50, but hereinafter, the trench gates 50 are set to extend in a direction perpendicular to the line E - E.

[0099] The trench gate 50 is configured such that a buried gate electrode 8 is disposed in a trench formed in the semiconductor substrate with a gate insulating film 7 interposed therebetween. The buried gate electrode 8 of the trench gate 50 is electrically connected to the gate pad 104a.

[0100] In the IGBT region 101, an n + -type emitter layer 3 and a p + -type contact layer 4 are disposed in the region between two adjacent trench gates 50. The n + -type emitter layer 3 and the p + -type contact layer 4 are each disposed to extend in the same direction as the extension direction of the trench gate 50. The n + -type emitter layer 3 contacts the gate insulating film 7 of the trench gate 50, and the p + -type contact layer 4 is disposed to be separated from the gate insulating film 7 of the trench gate 50. The n + -type emitter layer 3 is a semiconductor layer having, for example, As (arsenic) or P (phosphorus) as an n-type impurity, and the concentration of the n-type impurity is 1.0E + 17 / cm 3 to 1.0E + 20 / cm 3 . The p + -type contact layer 4 is a semiconductor layer having, for example, B (boron) or Al (aluminum) as a p-type impurity, and the concentration of the p-type impurity is 5.0E + 18 / cm 3 to 1.0E + 20 / cm 3 .

[0101] In the diode region 102, a p-type anode layer 5 and a p +p-type contact layer 6. The p-type anode layer 5 and the p + -type contact layer 6 are alternately arranged in the longitudinal direction of the trench gate 50. The p-type anode layer 5 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+12 / cm 3 ~5.0E+18 / cm 3 。p + -type contact layer 6 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 5.0E+18 / cm 3 ~1.0E+20 / cm 3 。

[0102] <A-1-2. Cross-sectional structure>

[0103] Figure 4 This is a cross-sectional view taken along line A-A shown in the semiconductor device 200 or the semiconductor device 201. Figure 3 This is a cross-sectional view taken along line B-B shown in the semiconductor device 200 or the semiconductor device 201. Figure 5 This is a cross-sectional view taken along line B-B shown in the semiconductor device 200 or the semiconductor device 201. Figure 3 This is a cross-sectional view taken along line B-B shown in the semiconductor device 200 or the semiconductor device 201.

[0104] The semiconductor device 200 or the semiconductor device 201 has an n - -type drift layer 1 (the second semiconductor layer). The n - -type drift layer 1 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+12 / cm 3 ~1.0E+15 / cm 3 。The n - -type drift layer 1 in the diode region 102 and the n - -type drift layer 1 in the IGBT region 101 are continuously formed as a single body and are formed of the same semiconductor substrate.

[0105] The semiconductor substrate 120 is within the range from the n Figure 4 and Figure 5 in the IGBT region 101 from the n + -type emitter layer 3 (the fourth semiconductor layer) and the p + -type contact layer 4 (the ninth semiconductor layer) to the p-type collector layer 11 (the first semiconductor layer), within the range from the p Figure 4 in the diode region 102 from the p + -type contact layer 6 (the seventh semiconductor layer) to the n + -type cathode layer 12 (the fifth semiconductor layer), and within the range from the p-type anode layer 5 (the sixth semiconductor layer) to the n Figure 5 in the diode region 102 from the p-type anode layer 5 (the sixth semiconductor layer) to the n +A p-type or n-type semiconductor layer in the range up to the type cathode layer 12, which is formed by introducing impurity ions into a semiconductor substrate and then diffusing them in the semiconductor substrate through heat treatment.

[0106] In Figure 4 the n + -type emitter layer 3 and the p + -type contact layer 4 and the p + -type contact layer 6, the end portion on the emitter electrode 13 side is referred to as the first main surface of the semiconductor substrate 120, and the end portion on the collector electrode 14 side of the p-type collector layer 11 and the n + -type cathode layer 12 is referred to as the second main surface of the semiconductor substrate 120. In Figure 5 the n + -type emitter layer 3 and the p + -type contact layer 4 and the p-type anode layer 5, the end portion on the emitter electrode 13 side is referred to as the first main surface of the semiconductor substrate 120, and the end portion on the collector electrode 14 side of the p-type collector layer 11 and the n + -type cathode layer 12 is referred to as the second main surface of the semiconductor substrate 120. The first main surface of the semiconductor substrate 120 is the main surface on the surface side of the semiconductor device 200 or the semiconductor device 201, and the second main surface of the semiconductor substrate 120 is the main surface on the back side of the semiconductor device 200 or the semiconductor device 201. In the description of the manufacturing method or from the perspective of the manufacturing method, for the semiconductor substrate used in forming the semiconductor substrate 120, the main surface of the semiconductor substrate corresponding to the first main surface side of the semiconductor substrate 120 is also referred to as the first main surface of the semiconductor substrate, and the main surface of the semiconductor substrate corresponding to the second main surface side of the semiconductor substrate 120 is referred to as the second main surface of the semiconductor substrate. The semiconductor device 200 or the semiconductor device 201 has an n - -type drift layer 1 between the first main surface and the second main surface opposite to the first main surface in the IGBT region 101 and the diode region 102.

[0107] <A-1-2-1. Cross-sectional structure of the IGBT region>

[0108] As Figure 4 and Figure 5 shown, in the IGBT region 101, a p-type channel doping layer 2 (the third semiconductor layer) is provided on the first main surface side of the n - -type drift layer 1. The p-type channel doping layer 2 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+12 / cm 3 ~5.0E+18 / cm 3 . The p-type channel doping layer 2 is in contact with the gate insulating film 7 of the trench gate 50. An n+ type emitter layer 3 is provided with p in the remaining area + type contact layer 4. n + type emitter layer 3 and p + type contact layer 4 form a part of the first main surface of the semiconductor substrate 120.

[0109] As Figure 4 and Figure 5 shown, in the IGBT region 101 of the semiconductor device 200 or the semiconductor device 201, on the second main surface side of the n - type drift layer 1, an n-type buffer layer 10 with a higher concentration of n-type impurities than that of the n - type drift layer 1 is provided. The n-type buffer layer 10 is provided to suppress the breakdown of the depletion layer extending from the p-type channel doping layer 2 to the second main surface side when the semiconductor device 200 or the semiconductor device 201 is in the off state. The n-type buffer layer 10 can be formed, for example, by implanting phosphorus or protons, or by implanting both phosphorus and protons. The concentration of n-type impurities in the n-type buffer layer 10 is 1.0E+12 / cm 3 ~1.0E+18 / cm 3 .

[0110] In addition, the semiconductor device 200 or the semiconductor device 201 may also be configured without the n-type buffer layer 10, and in the region of the n-type buffer layer 10 as shown in Figure 4 and Figure 5 , an n - type drift layer 1 is also provided. The n-type buffer layer 10 and the n - type drift layer 1 can also be collectively referred to as a drift layer (second semiconductor layer).

[0111] In the IGBT region 101 of the semiconductor device 200 or the semiconductor device 201, a p-type collector layer 11 is provided on the second main surface side of the n-type buffer layer 10. That is, a p-type collector layer 11 is provided between the n - type drift layer 1 and the second main surface. The p-type collector layer 11 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+16 / cm 3 ~1.0E+20 / cm 3 . The p-type collector layer 11 forms a part of the second main surface of the semiconductor substrate 120. The p-type collector layer 11 is provided not only in the IGBT region 101 but also in the peripheral region 103, and the portion of the p-type collector layer 11 provided in the peripheral region 103 constitutes a p-type end collector layer 11a (see Figure 6 , Figure 7 ). In addition, a part of the p-type collector layer 11 can also be provided to extend from the IGBT region 101 to the diode region 102.

[0112] As Figure 4 and Figure 5 shown, in the IGBT region 101 of the semiconductor device 200 or the semiconductor device 201, trenches are formed that penetrate the p-type channel doping layer 2 from the first main surface of the semiconductor substrate 120 and reach the n - -type drift layer 1. A trench gate 50 is formed by disposing a buried gate electrode 8 in the trench with a gate insulating film 7 interposed therebetween. The buried gate electrode 8 faces the n - -type drift layer 1 with the gate insulating film 7 interposed therebetween. The gate insulating film 7 of the trench gate 50 in the IGBT region 101 is in contact with the p-type channel doping layer 2 and the n + -type emitter layer 3. When a gate drive voltage is applied to the buried gate electrode 8, a channel is formed in the p-type channel doping layer 2 in contact with the gate insulating film 7 of the trench gate 50.

[0113] As Figure 4 and Figure 5 shown, an interlayer insulating film 9 is provided above the buried gate electrode 8 of the trench gate 50 in the IGBT region 101. An emitter electrode 13 is provided above the region of the first main surface of the semiconductor substrate 120 where the interlayer insulating film 9 is not provided and above the interlayer insulating film 9. The emitter electrode 13 makes an ohmic contact with the n + -type emitter layer 3 and the p + -type contact layer 4 in the IGBT region 101, and is electrically connected to the n + -type emitter layer 3 and the p + -type contact layer 4. The emitter electrode 13 can be formed of an aluminum alloy such as an aluminum-silicon alloy (Al-Si alloy), or can be an electrode composed of a multi-layer metal film in which a coating film is formed by electroless plating or electroplating on an electrode formed of an aluminum alloy. The coating film formed by electroless plating or electroplating can be, for example, a nickel (Ni) coating film. In addition, in a case where there is a minute region such as between adjacent interlayer insulating films 9 where the emitter electrode 13 cannot be well buried, tungsten having better burying property than the emitter electrode 13 can be disposed in the minute region, and the emitter electrode 13 can be provided above the tungsten.

[0114] A barrier metal can also be formed above the region of the first main surface of the semiconductor substrate 120 where the interlayer insulating film 9 is not provided and above the interlayer insulating film 9, and the emitter electrode 13 is provided above the barrier metal (hereinafter, the barrier metal is referred to as the barrier metal 27). The barrier metal 27 can be, for example, a conductor containing titanium (Ti), such as titanium nitride, or TiSi obtained by alloying titanium and silicon (Si). In addition, when the barrier metal 27 is formed, the barrier metal 27 makes an ohmic contact with the n + -type emitter layer 3 and the p + -type contact layer 4, and is in contact with the n+ type emitter layer 3 and p + type contact layer 4 are electrically connected. The blocking metal 27 and the emitter electrode 13 can be combined and referred to as the emitter electrode. Additionally, the blocking metal 27 can be provided only on the n + type emitter layer 3 and other n-type semiconductor layers.

[0115] A collector electrode 14 is provided on the second main surface side of the p-type collector layer 11. The collector electrode 14 can also be composed of aluminum alloy, or aluminum alloy and a coating film, similar to the emitter electrode 13. Additionally, the collector electrode 14 can have a structure different from that of the emitter electrode 13. The collector electrode 14 makes an ohmic contact with the p-type collector layer 11 and is electrically connected to the p-type collector layer 11.

[0116] <A-1-2-2. Cross-sectional Structure of Diode Region>

[0117] As Figure 4 and Figure 5 shown, in the diode region 102, similar to the IGBT region 101, an n - type buffer layer 10 is provided on the second main surface side of the n-type drift layer 1. The n-type buffer layer 10 provided in the diode region 102 has the same structure as the n-type buffer layer 10 provided in the IGBT region 101. Additionally, similar to the IGBT region 101, the n - type drift layer 1 and the n-type buffer layer 10 can be combined and referred to as the drift layer.

[0118] In the diode region 102, a p-type anode layer 5 is provided on the first main surface side of the n - type drift layer 1. The p-type anode layer 5 is provided between the n - type drift layer 1 and the first main surface. The concentration of the p-type impurities in the p-type anode layer 5 can be set to the same concentration as that of the p-type channel doping layer 2 in the IGBT region 101, and the p-type anode layer 5 and the p-type channel doping layer 2 can be formed simultaneously. Additionally, it can be configured such that the concentration of the p-type impurities in the p-type anode layer 5 is set lower than the concentration of the p-type impurities in the p-type channel doping layer 2 in the IGBT region 101, so as to reduce the amount of holes flowing into the n - type drift layer 1 during diode operation. By reducing the amount of holes flowing into the n - type drift layer 1 during diode operation, the recovery loss during diode operation can be reduced.

[0119] In Figure 4 the cross-section of the diode region 102 shown, a p + type contact layer 6 is provided on the first main surface side of the p-type anode layer 5. The concentration of the p-type impurities in the p + type contact layer 6 can be set to the same as that of the p in the IGBT region 101+ The p-type impurities in the p-type contact layer 4 may have the same concentration or different concentrations. p + type contact layer 6 forms a part of the first main surface of the semiconductor substrate 120. In addition, p + type contact layer 6 is a region where the concentration of p-type impurities is higher than that of the p-type anode layer 5, and is a region where the concentration of p-type impurities in the anode region is greater than or equal to 5.0E+18 / cm 3 . Additionally, the p-type anode layer 5 is a region where the concentration of p-type impurities is less than 5.0E+18 / cm 3 .

[0120] As Figure 4 shown, a defective region 15 (first crystal defect region) is formed in the p-type anode layer 5. The defective region 15 is provided at least on the second main surface side of the p-type anode layer 5 and overlaps with the p + type contact layer 6 in a plan view. The defective region 15 may be provided in a region that is in surface contact with the second main surface side of the p-type contact layer 6 in the p-type anode layer 5, or may be provided across the p + type anode layer 5 and the p + type contact layer 6 on the surface of the second main surface side of the type contact layer 6, including the surface in contact with the p-type anode layer 5. The defective region 15 may also be provided separately from the p + type contact layer 6, but by providing it in a region in surface contact with the second main surface side of the p + type contact layer 6, or by providing it to also span the p + type contact layer 6, the amount of holes flowing into the n + type drift layer 1 can be more effectively suppressed. In the present embodiment, in particular, a case where the defective region 15 and the p + type contact layer 6 are formed by ion implantation using the same mask and are formed in the same region in a plan view will be described. However, the defective region 15 and the p - type contact layer 6 being formed in the same region in a plan view means the same degree as achieved by ion implantation using the same mask and subsequent heat treatment as described later in <A-2. Manufacturing method>, and even in the case where there is a normal offset due to these treatments, the defective region 15 and the p + type contact layer 6 are considered to be formed in the same region in a plan view. + type contact layer 6 are considered to be formed in the same region in a plan view. + type contact layer 6 are formed in the same region in a plan view.

[0121] In the diode region 102, an n + type cathode layer 12 is provided on the second main surface side of the n-type buffer layer 10. n + type cathode layer 12 is provided between the n - type drift layer 1 and the second main surface. n+ The cathode layer 12 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+16 / cm 3 ~1.0E+21 / cm 3 .like Figure 4 , Figure 5 As shown, n + The cathode layer 12 is provided in a part or the whole of the diode region 102. + The p-type cathode layer 12 constitutes a portion of the second main surface of the semiconductor substrate 120. Although not shown in the figure, p-type impurities may be further selectively implanted into the n-type cathode layer 12 formed as described above. + The area of the type cathode layer 12 will form an n + A part of the region of the p-type cathode layer 12 is provided as a p-type semiconductor.

[0122] exist Figure 4 , Figure 5 In the diode region 102 of the semiconductor device 200 or the semiconductor device 201, a first main surface of the semiconductor substrate 120 is formed through the p-type anode layer 5 to reach the n-type anode layer 5. - The trench of the n type drift layer 1. In the diode region 102, similarly to the IGBT region 101, a buried gate electrode 8 is provided in the trench via the gate insulating film 7 to form a trench gate 50. The buried gate electrode 8 of the diode region 102 is connected to the n type drift layer 1 via the gate insulating film 7. - type drift layer 1 is opposite.

[0123] like Figure 4 As shown, an interlayer insulating film 9 is provided on the buried gate electrode 8 of the trench gate 50 in the diode region 102. An emitter electrode 13 is provided on the region of the first main surface of the semiconductor substrate 120 where the interlayer insulating film 9 is not provided and on the interlayer insulating film 9. The emitter electrode 13 is connected to the p + The type contact layer 6 makes ohmic contact with the p + The buried gate electrode 8 and the emitter electrode 13 of the trench gate 50 of the diode region 102 are electrically connected to each other. Figure 4 The different cross sections shown are electrically connected. The emitter electrode 13 provided in the diode region 102 is formed continuously with the emitter electrode 13 provided in the IGBT region 101. Figure 4 , the interlayer insulating film 9 is also shown provided on the buried gate electrode 8 of the trench gate 50 in the diode region 102 , but the interlayer insulating film 9 may not be provided on the buried gate electrode 8 of the trench gate 50 in the diode region 102 .

[0124] In the diode region 102 as well as in the IGBT region 101, a barrier metal 27 can be formed over the region of the first main surface of the semiconductor substrate 120 where the interlayer insulating film 9 is not provided and over the interlayer insulating film 9, and an emitter electrode 13 is provided over the barrier metal 27. When the barrier metal 27 is provided in the diode region 102, the barrier metal 27 can have the same structure as the barrier metal 27 that can be provided in the IGBT region 101. When the barrier metal 27 is provided in the diode region 102, the barrier metal 27 makes an ohmic contact with the p + -type contact layer 6 and is electrically connected to the p + -type contact layer 6. The barrier metal 27 and the emitter electrode 13 can be collectively referred to as the emitter electrode.

[0125] A collector electrode 14 is provided on the second main surface side of the n + -type cathode layer 12. Similar to the emitter electrode 13, the collector electrode 14 in the diode region 102 is formed continuously with the collector electrode 14 provided in the IGBT region 101. The collector electrode 14 makes an ohmic contact with the n + -type cathode layer 12 and is electrically connected to the n + -type cathode layer 12.

[0126] Figure 5 The diode region 102 of Figure 4 is different from the diode region 102 of + in that the p Figure 4 -type contact layer 6 is not provided, and the p-type anode layer 5 constitutes a part of the first main surface of the semiconductor substrate 120. That is, + the p Figure 5 -type contact layer 6 shown is selectively provided on the first main surface side of the p-type anode layer 5. In other respects, Figure 4 the cross-section of

[0127] <A-1-3. Structure of the Peripheral Region>

[0128] Figure 6 and Figure 7 are cross-sectional views showing the structure of the peripheral region of the RC-IGBT, i.e., the semiconductor device of the present embodiment. Figure 6 is Figure 1 or Figure 2 the cross-sectional view of the single-dot chain line E-E in Figure 7 and is a cross-sectional view from the IGBT region 101 to the peripheral region 103. Further, Figure 1 the cross-sectional view of the single-dot chain line F-F in

[0129] As shown in Figure 6 and Figure 7As shown, the outer peripheral region 103 of the semiconductor device 200 or the semiconductor device 201 has an n-type drift layer 1 between the first main surface and the second main surface of the semiconductor substrate 120. - The first main surface and the second main surface of the outer peripheral region 103 are the same as the first main surface and the second main surface of the IGBT region 101 and the diode region 102, respectively. In addition, the n-type drift layer 1 of the outer peripheral region 103 is the same structure as the n-type drift layer 1 of the IGBT region 101 and the diode region 102, and is continuously formed as a single body. - type drift layer 1 respectively and the IGBT region 101 and the diode region 102 of the n - type drift layer 1 is the same structure, and is continuously formed as one body.

[0130] In the first main surface side of the n - type drift layer 1, that is, between the first main surface of the semiconductor substrate 120 and the n - type drift layer 1, a p-type end well layer 31 is provided. The p-type end well layer 31 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+14 / cm 3 ~1.0E+19 / cm 3 . The p-type end well layer 31 is provided to surround the cell region including the IGBT region 101 and the diode region 102. The p-type end well layer 31 is provided in a plurality of rings, and the number of the p-type end well layers 31 provided is appropriately selected according to the breakdown voltage design of the semiconductor device 200 or the semiconductor device 201. In addition, an n + type channel cutoff layer 32 is provided on the more edge side of the p-type end well layer 31, and the n + type channel cutoff layer 32 surrounds the p-type end well layer 31.

[0131] In the n - type drift layer 1 and the second main surface of the semiconductor substrate 120, a p-type end collector layer 11a is provided. The p-type end collector layer 11a is continuously formed as a single body with the p-type collector layer 11 provided in the cell region. Therefore, it may also be referred to as the p-type collector layer 11 including the p-type end collector layer 11a. In addition, in the structure where the diode region 102 is adjacent to the outer peripheral region 103 as in the semiconductor device 200 shown in Figure 1 , as shown in Figure 7 , the end portion of the p-type end collector layer 11a on the diode region 102 side extends toward the diode region 102 by a distance U2. In this way, by setting the p-type end collector layer 11a to extend into the diode region 102, the distance between the n + type cathode layer 12 of the diode region 102 and the p-type end well layer 31 can be increased, and the p-type end well layer 31 can be prevented from acting as the anode of the diode. The distance U2 can be, for example, 100 μm.

[0132] On the second main surface of the semiconductor substrate 120, a collector electrode 14 is provided. The collector electrode 14 is continuously formed integrally from the cell region including the IGBT region 101 and the diode region 102 to the outer peripheral region 103. On the other hand, an emitter electrode 13 continuous from the cell region and a terminal electrode 13a separated from the emitter electrode 13 are provided on the first main surface of the semiconductor substrate 120 in the outer peripheral region 103.

[0133] The emitter electrode 13 and the terminal electrode 13a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 can be, for example, sinSiN (semi-insulating Silicon Nitride). The terminal electrode 13a and the p-type terminal well layer 31 and n + type channel cut-off layer 32 are electrically connected via a contact hole formed in an interlayer insulating film 9 provided on the first main surface of the outer peripheral region 103. In addition, in the outer peripheral region 103, a terminal protective film 34 is provided so as to cover the emitter electrode 13, the terminal electrode 13a, and the semi-insulating film 33. The terminal protective film 34 can be formed of, for example, polyimide.

[0134] <A-1-4. Summary of the structure>

[0135] The semiconductor device 200 or the semiconductor device 201 is a semiconductor device in which an IGBT and a diode are formed on a common semiconductor substrate 120. The semiconductor substrate 120 has a first main surface and a second main surface as one main surface and the other main surface, an IGBT region 101 in which an IGBT is formed, and a diode region 102 in which a diode is formed. The IGBT region 101 has: a p-type collector layer 11 provided on the second main surface side of the semiconductor substrate 120; n - type drift layer 1 provided on the p-type collector layer 11; a p-type channel doping layer 2 provided closer to the first main surface side of the semiconductor substrate 120 than the n - type drift layer 1; an n + type emitter layer 3 provided on the p-type channel doping layer 2; an emitter electrode 13 electrically connected to the n + type emitter layer 3; and a collector electrode 14 electrically connected to the p-type collector layer 11. The diode region 102 has: an n + type cathode layer 12 provided on the second main surface side of the semiconductor substrate 120; an n - type drift layer 1 provided on the n + type cathode layer 12; a p-type anode layer 5 provided closer to the first main surface side of the semiconductor substrate 120 than the n - type drift layer 1; p +The p-type contact layer 6 is disposed on the p-type anode layer 5 and has a higher impurity concentration than the p-type anode layer 5; the emitter electrode 13 is electrically connected to the p- + type contact layer 6; and the collector electrode 14 is electrically connected to the n- + type cathode layer 12. In addition, the defect region 15 is disposed at least on the second main surface side of the p-type contact layer 6 in the p-type anode layer 5 and in a region overlapping the p- + type contact layer 6 when viewed from above. + The region that overlaps the p-type contact layer 6.

[0136] In the semiconductor device 200 or the semiconductor device 201, in the IGBT region 101, an n-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure formed by an n- - type drift layer 1, a p-type channel doping layer 2, an n- + type emitter layer 3, a gate insulating film 7, and a buried gate electrode 8 is formed. Moreover, the MOSFET includes a p-type collector layer 11 to form an IGBT structure.

[0137] In the semiconductor device 200 or the semiconductor device 201, in the diode region 102, a diode structure is formed by the p-type anode layer 5 and the p- + type contact layer 6, the n- - type drift layer 1, and the n- + type cathode layer 12.

[0138] In addition, the semiconductor device 200 or the semiconductor device 201 has the following characteristics.

[0139] The first characteristic is that the defect region 15 is disposed on the second main surface side of the p-type contact layer 6 in the region of the p-type anode layer 5 formed in the diode region 102 and in a region overlapping the p- + type contact layer 6 when viewed from above. Moreover, the defect region 15 and the p- + type contact layer 6 are formed in the same region when viewed from above. The presence of the defect region 15 can be confirmed by the cathodoluminescence method, which is a method for evaluating physical properties by cathodoluminescence, i.e., luminescence generated when accelerated electrons are irradiated onto a sample. + The region that overlaps the p-type contact layer 6.

[0140] The second characteristic is that the defect region 15 contains any light ions of Ar (argon), N (nitrogen), H (hydrogen), and He (helium) and is a crystal defect region formed by ion implantation of any of argon, nitrogen, helium, and hydrogen.

[0141] The third characteristic is that the defect region 15 is formed when the p- +The type contact layer 6 is formed using the same mask in the process of selectively forming on the surface.

[0142] The fourth feature is that the defect region 15 is formed in the p + type impurity concentration in the type contact layer 6 or the p-type anode layer 5 is greater than or equal to 1.0E+16 / cm 3 of the region.

[0143] The fifth feature is that in the first main surface, the p-type anode layer 5 and the p + type contact layer 6 are alternately formed in the length direction of the trench gate 50, and the area of the p + type contact layer 6 (i.e., the area of the defect region 15) when viewed from above relative to the area of the region where the p-type anode layer 5 and the p + type contact layer 6 are combined when viewed from above is set to be greater than or equal to 20%.

[0144] The sixth feature is that the defect region 15 is formed to at least include the region in the diode region 102 that contacts the IGBT region 101. For example, the defect region 15 is at least formed in the region in the diode region 102 where the distance from the IGBT region 101 when viewed from above is smaller than the thickness of the semiconductor substrate 120.

[0145] <A-2. Manufacturing method>

[0146] An example of the manufacturing method of the semiconductor device 200 or the semiconductor device 201 will be described. Hereinafter, it is assumed that Figure 3 the cross-section at the A-A line shown ([[]] Figure 4 ) is described. Except that the defect region 15 and the p Figures 15 to 17 type contact layer 6 are not formed in the cross-section in the process up to + , the structure of the cross-section at the B-B line shown in Figure 3 is formed in the same manner as the cross-section at the A-A line shown in Figure 3 .

[0147] First, as Figure 8 shown, prepare to constitute n -Semiconductor substrate of the type drift layer 1. Although the case where the semiconductor substrate is a silicon substrate is described, it may also be a SiC substrate or the like. For example, the semiconductor substrate may be a so-called FZ wafer manufactured by the FZ (Floating Zone) method or a so-called MCZ wafer manufactured by the MCZ (Magnetic field applied Czochralski) method. The semiconductor substrate may be an n-type wafer containing n-type impurities. The concentration of the n-type impurities contained in the semiconductor substrate is appropriately selected according to the breakdown voltage of the manufactured semiconductor device. For example, in a semiconductor device with a breakdown voltage of 1200V, the concentration of the n-type impurities is adjusted so that the n - type drift layer 1 has a relative resistance of about 40 to 120 Ω·cm. As Figure 8 shown, in the process of preparing the semiconductor substrate, the entire semiconductor substrate is the n - type drift layer 1. However, by injecting p-type or n-type impurity ions from the first main surface side or the second main surface side of such a semiconductor substrate and diffusing them into the semiconductor substrate through subsequent heat treatment or the like, a p-type or n-type semiconductor layer is formed, and the semiconductor device 200 or the semiconductor device 201 is manufactured.

[0148] As Figure 8 shown, the semiconductor substrate constituting the n - type drift layer 1 has regions that become the IGBT region 101 and the diode region 102. In addition, although not shown, there is a region that becomes the outer peripheral region 103 around the regions that become the IGBT region 101 and the diode region 102. Hereinafter, mainly the manufacturing method of the structures of the IGBT region 101 and the diode region 102 of the semiconductor device 200 or the semiconductor device 201 will be described, but the outer peripheral region 103 of the semiconductor device 200 or the semiconductor device 201 can be manufactured by a known manufacturing method. For example, in the case where an FLR having a p-type end well layer 31 is formed in the outer peripheral region 103 as a breakdown voltage holding structure, it can be formed by injecting p-type impurity ions before processing the IGBT region 101 and the diode region 102 of the semiconductor device 200 or the semiconductor device 201, or it can be formed by injecting p-type impurity ions simultaneously when injecting p-type impurity ions into the IGBT region 101 or the diode region 102 of the semiconductor device 200 or the semiconductor device 201.

[0149] Next, as Figure 9As shown, p-type impurities such as boron are implanted from the first main surface side of the semiconductor substrate to form a p-type channel doping layer 2 and a p-type anode layer 5. The p-type channel doping layer 2 and the p-type anode layer 5 are formed by diffusing impurity ions through heat treatment after implanting the impurity ions into the semiconductor substrate. Since the p-type impurities are ion-implanted after applying a mask treatment on the first main surface of the semiconductor substrate, the p-type channel doping layer 2 and the p-type anode layer 5 are selectively formed on the first main surface side of the semiconductor substrate. The p-type channel doping layer 2 and the p-type anode layer 5 are formed in the IGBT region 101 and the diode region 102, and are connected to the p-type end well layer 31 in the peripheral region 103. In addition, the mask treatment refers to a process of coating a resist on the semiconductor substrate, forming an opening in a specified region of the resist using photolithography technology, and forming a mask on the semiconductor substrate in order to perform ion implantation or etching on a specified region of the semiconductor substrate through the opening.

[0150] It is also possible to simultaneously implant p-type impurities to form the p-type channel doping layer 2 and the p-type anode layer 5. In this case, the depths and p-type impurity concentrations of the p-type channel doping layer 2 and the p-type anode layer 5 are the same and have the same structure. Additionally, it is also possible to separately implant p-type impurity ions into the p-type channel doping layer 2 and the p-type anode layer 5 through a mask treatment, so that the depths and p-type impurity concentrations of the p-type channel doping layer 2 and the p-type anode layer 5 are different.

[0151] Furthermore, it is also possible to simultaneously implant p-type impurities with the p-type anode layer 5 to form the p-type end well layer 31 formed at other cross-sections. In this case, the depths and p-type impurity concentrations of the p-type end well layer 31 and the p-type anode layer 5 can be made the same and have the same structure. Additionally, it is also possible to simultaneously implant p-type impurities to form the p-type end well layer 31 and the p-type anode layer 5, and set the p-type impurity concentrations of the p-type end well layer 31 and the p-type anode layer 5 to different concentrations. In this case, set the mask of either one or both to a grid-shaped mask and change the aperture ratio.

[0152] Moreover, it is also possible to separately implant p-type impurity ions into the p-type end well layer 31 and the p-type anode layer 5 through a mask treatment, so that the depths and p-type impurity concentrations of the p-type end well layer 31 and the p-type anode layer 5 are different.

[0153] It is also possible to simultaneously implant p-type impurities to form the p-type end well layer 31, the p-type channel doping layer 2, and the p-type anode layer 5.

[0154] Next, as Figure 10 shown, n-type impurities are selectively implanted into the first main surface side of the p-type channel doping layer 2 in the IGBT region 101 through a mask treatment to form n +The n-type emitter layer 3. The implanted n-type impurities may be, for example, arsenic or phosphorus.

[0155] Then, if Figure 11 As shown, a first main surface side of the semiconductor substrate is formed to penetrate n + type emitter layer 3 and p-type anode layer 5 to reach n - The trench 51 of the type drift layer 1. In the IGBT region 101, the trench 51 penetrates the n + The sidewalls of the trench 51 of the type emitter layer 3 constitute n + A part of the emitter layer 3 of the type. After depositing an oxide film such as SiO2 on the semiconductor substrate, an opening can be formed in the oxide film of the portion where the groove 51 is formed by masking, and the semiconductor substrate can be etched using the oxide film with the opening as a mask, thereby forming the groove 51. Figure 11 In the embodiment, the pitch of the trenches 51 is formed to be the same in the IGBT region 101 and the diode region 102, but the pitch of the trenches 51 may be different in the IGBT region 101 and the diode region 102. The pitch of the trenches 51 and the pattern when viewed from above can be appropriately changed according to the mask pattern of the mask process.

[0156] Then, if Figure 12 As shown, the semiconductor substrate is heated in an oxygen-containing atmosphere to form an oxide film on the inner wall of the trench 51 and the first main surface of the semiconductor substrate. Here, the oxide film formed on the inner wall of the trench 51 is the gate insulating film 7 of the trench gate 50, and the oxide film formed on the first main surface of the semiconductor substrate is the oxide film 90. The oxide film 90 is removed by the subsequent process.

[0157] Then, if Figure 13 As shown, in the trench 51 having the gate insulating film 7 formed on the inner wall, polysilicon doped with n-type or p-type impurities is deposited by CVD (chemical vapor deposition) or the like to form the buried gate electrode 8.

[0158] Next, the oxide film 90 formed on the first main surface of the semiconductor substrate is removed.

[0159] Then, if Figure 14 As shown, impurity ions are selectively implanted into the IGBT region 101, and the impurity ions are diffused by heat treatment to form p + When the impurity ions are injected, the p-type contact layer 4 is removed by masking in advance. + A mask is formed in the area corresponding to the type contact layer 4.

[0160] Next, after removing the p + After the mask is used when forming the type contact layer 4, the p-type contact layer 102 is formed by mask processing except for the diode region 102. +The photoresist 16 covers the area outside the area corresponding to the type contact layer 6.

[0161] Then, if Figure 15 As shown, the photoresist 16 is used as a mask to perform ion implantation, and p-type impurities are introduced into the p-type region of the diode region 102. + A p-type impurity introduction region 17 is formed in a region corresponding to the p-type contact layer 6 .

[0162] Then, if Figure 16 As shown, using the same photoresist 16 as that used when forming the p-type impurity introduction region 17, any element among argon, nitrogen, helium, and hydrogen is introduced to a position deeper than the p-type impurity introduction region 17 to form a crystal defect introduction region 18. Nitrogen is used to form an n-type semiconductor layer using materials such as SiC, but here it is used to form a crystal defect layer for a semiconductor substrate of an assumed silicon material.

[0163] Then, if Figure 17 As shown, the photoresist 16 is removed and the structure of the anode region of the diode region 102 can be formed by heat treatment.

[0164] In this embodiment, any of argon, nitrogen, helium, and hydrogen is used to form the defect region 15. These elements can be implanted by a common ion implanter, and by using these elements, the defect region 15 can be formed at low cost.

[0165] Then, if Figure 18 As shown, an interlayer insulating film 9 is formed on the buried gate electrode 8 of the trench gate 50. The interlayer insulating film 9 can be, for example, SiO2. In addition, after the interlayer insulating film 9 is deposited on the surface of the semiconductor substrate except for the buried gate electrode 8, the unnecessary part is removed by masking to form a contact hole.

[0166] Then, if Figure 19 As shown in FIG. 1 , an emitter electrode 13 is formed on the first main surface of the semiconductor substrate and the interlayer insulating film 9. Alternatively, a barrier metal may be formed on the first main surface of the semiconductor substrate and the interlayer insulating film 9, and the emitter electrode 13 may be formed on the barrier metal. The barrier metal is formed by forming a film of titanium nitride by PDV (physical vapor deposition) or CVD.

[0167] For example, an aluminum-silicon alloy (Al-Si-based alloy) can be deposited on the first main surface of the semiconductor substrate and on the interlayer insulating film 9 by PVD such as sputtering or evaporation to form the emitter electrode 13. Additionally, a nickel alloy (Ni alloy) can be further formed on the formed aluminum-silicon alloy by electroless plating or electroplating as the emitter electrode 13. If the emitter electrode 13 is formed by electroplating, a thick metal film can be easily formed as the emitter electrode 13, so that the heat capacity of the emitter electrode 13 can be increased and the heat resistance can be improved. Further, in the case where a nickel alloy is further formed by electroplating treatment after the emitter electrode 13 made of an aluminum-silicon alloy is formed by PVD, the electroplating treatment for forming the nickel alloy can also be performed after the processing on the second main surface side of the semiconductor substrate is carried out.

[0168] Next, as Figure 20 shown, the second main surface side of the semiconductor substrate is polished to thin the semiconductor substrate to a designed thickness. In Figure 20 , the n - -type drift layer 1 constituting the semiconductor substrate is thinned. The thickness of the polished semiconductor substrate can be, for example, 80 μm to 200 μm.

[0169] Next, as Figure 21 shown, an n-type impurity is implanted from the second main surface side of the semiconductor substrate to form an n-type buffer layer 10. Further, a p-type impurity is implanted from the second main surface side of the semiconductor substrate to form a p-type collector layer 11. The n-type buffer layer 10 can be formed in the IGBT region 101, the diode region 102, and the peripheral region 103, or can be formed only in the IGBT region 101 or the diode region 102.

[0170] The n-type buffer layer 10 can be formed, for example, by implanting phosphorus ions. Additionally, it can be formed by implanting protons. Moreover, it can be formed by implanting both protons and phosphorus. Protons can be implanted from the second main surface of the semiconductor substrate to a deep position with relatively low acceleration energy. Additionally, the depth of the implanted protons can be changed relatively easily by changing the acceleration energy. Therefore, if the n-type buffer layer 10 is formed by protons and multiple implantations are performed while changing the acceleration energy, a wider n-type buffer layer 10 can be formed in the thickness direction of the semiconductor substrate compared to the case of forming by phosphorus.

[0171] Further, since the activation rate of phosphorus as an n-type impurity can be set higher than that of protons, by forming the n-type buffer layer 10 with phosphorus, even for the thinned semiconductor substrate, the breakdown of the depletion layer can be more reliably suppressed. In order to further thin the semiconductor substrate, it is preferable to form the n-type buffer layer 10 by implanting both protons and phosphorus. At this time, protons are implanted from the second main surface to a deeper position than phosphorus.

[0172] The p-type collector layer 11 can be formed, for example, by implanting boron. The p-type collector layer 11 is also formed in the outer peripheral region 103, and the p-type collector layer 11 in the outer peripheral region 103 becomes the p-type end collector layer 11a. After ion implantation from the second main surface side of the semiconductor substrate, laser annealing is performed by irradiating the second main surface with a laser, thereby activating the implanted boron to form the p-type collector layer 11. At this time, the phosphorus in the n-type buffer layer 10, which is implanted to a relatively shallow position from the second main surface of the semiconductor substrate, is also activated simultaneously. On the other hand, since protons are activated at a relatively low annealing temperature of 380 °C to 420 °C, care needs to be taken not to make the entire semiconductor substrate a temperature higher than 380 °C to 420 °C except for the process for activating protons after proton implantation. Since laser annealing can make only the vicinity of the second main surface of the semiconductor substrate a high temperature, it can also be used for activating n-type impurities and p-type impurities after proton implantation.

[0173] Next, as Figure 22 shown, an n + -type cathode layer 12 is formed in the diode region 102. The n + -type cathode layer 12 can be formed, for example, by implanting phosphorus. The implantation amount of the n-type impurity for forming the n + -type cathode layer 12 is larger than the implantation amount of the p-type impurity for forming the p-type collector layer 11. In Figure 22 , it is shown that the depths of the p-type collector layer 11 and the n + -type cathode layer 12 from the second main surface are the same, but the depth of the n + -type cathode layer 12 is greater than or equal to the depth of the p-type collector layer 11. Since the region for forming the n + -type cathode layer 12 needs to implant n-type impurities into the region where p-type impurities are implanted to become an n-type semiconductor, the concentration of the n-type impurities implanted in the entire region for forming the n + -type cathode layer 12 is made higher than the concentration of the p-type impurities.

[0174] Next, as Figure 4 shown, a collector electrode 14 is formed on the second main surface of the semiconductor substrate. The collector electrode 14 is formed over the entire surfaces of the IGBT region 101, the diode region 102, and the outer peripheral region 103 of the second main surface. In addition, the collector electrode 14 can be formed over the entire surface of the second main surface of the semiconductor substrate, that is, the n-type wafer. The collector electrode 14 can be formed by depositing an aluminum-silicon alloy (Al-Si-based alloy), titanium (Ti), etc. by PVD such as sputtering or evaporation, or can be formed by laminating multiple metals such as an aluminum-silicon alloy, titanium, nickel, or gold. Moreover, it can also be formed as the collector electrode 14 by performing electroless plating or electroplating on the metal film formed by PVD to further form a metal film.

[0175] The semiconductor device 200 or the semiconductor device 201 is fabricated through the above-described process. Regarding the semiconductor device 200 or the semiconductor device 201, since a plurality of them are fabricated in a matrix form on a single n-type wafer, they are cut into individual semiconductor devices 200 or semiconductor devices 201 by using laser cutting or blade cutting, thereby completing the semiconductor device 200 or the semiconductor device 201.

[0176] <A-3. Operation>

[0177] In the semiconductor device 200 or the semiconductor device 201 of the present embodiment, a diode is formed by a p-type anode layer 5, a p + -type contact layer 6, an n - -type drift layer 1, and an n + -type cathode layer 12. The on-state of the diode is a state in which the paired IGBTs are turned off, and the potential of the emitter electrode 13 is higher than that of the collector electrode 14. In the on-state of the diode, since holes flow into the n + -type drift layer 1 from the anode region composed of the p-type anode layer 5 and the p - -type contact layer 6, and electrons flow into the n + -type drift layer 1 from the cathode region composed of the n - -type cathode layer 12, conductivity modulation occurs and the diode becomes conductive.

[0178] In the present embodiment, a defect region 15 is formed in a portion of the p-type anode layer 5 below the p + -type contact layer 6, and the holes flowing into the n + -type drift layer 1 from the p - -type contact layer 6 pass through the defect region 15. Since the holes recombine through the defect region 15, the number of holes flowing into the n - -type drift layer 1 becomes smaller. Therefore, the degree of conductivity modulation decreases, and the carrier concentration near the anode region in the conductive state of the diode is lower than that in the case without the defect region 15.

[0179] Next, the operation when the diode transitions from this state through the recovery state to the cutoff state will be described. If the potential of the emitter electrode 13 becomes lower than that of the collector electrode 14 and the paired IGBTs become on when the diode is turned on, then the holes in the n - -type drift layer 1 flow into the emitter electrode 13 from the p-type anode layer 5 and the p + -type contact layer 6, and electrons flow into the collector electrode 14 from the n + -type cathode layer 12. In order for the diode to enter the cutoff state, it is necessary to release excess carriers. If there are many excess carriers, the reverse recovery current increases, the amount of excess carriers released increases, and the reverse recovery peak current (Irr) and the recovery loss (Err) become larger.

[0180] In the present embodiment, as described above, compared with the case where there is no defective region 15, the carrier concentration near the anode region is low in the on-state of the diode. Therefore, compared with the prior art, the reverse recovery peak current (Irr) and the recovery loss (Err) during the operation of the diode can be reduced.

[0181] Next, the operation of the IGBT will be described. Regarding the on-state of the IGBT, the buried gate electrode 8 and the collector electrode 14 are at a higher potential than the emitter electrode 13, and the paired diodes are in the cut-off state. In the on-state of the IGBT, holes flow from the p-type collector layer 11 into the n - -type drift layer 1, and electrons flow from the n + -type emitter layer 3 into the n - -type drift layer 1, causing conductivity modulation. If the collector electrode 14 remains at a higher potential than the emitter electrode 13 and the buried gate electrode 8 becomes at a lower potential than the emitter electrode 13, the MOS channel formed by the n + -type emitter layer 3, the p-type channel doping layer 2, and the n - -type drift layer 1 is closed. Regarding the excess carriers in the n - -type drift layer 1, holes are released from the emitter electrode 13 and electrons are released from the collector electrode 14, thereby transitioning to the off-state of the IGBT.

[0182] In the RC-IGBT, that is, in the semiconductor device 200 or the semiconductor device 201 of the present embodiment, the IGBT region 101 and the diode region 102 are formed adjacent to each other. Therefore, the current from the p-type collector layer 11 corresponding to the IGBT region 101 formed near the diode region 102, in addition to the component flowing through the n - -type drift layer 1 of the IGBT region 101 to the emitter electrode 13, also includes a part that flows through the n - -type drift layer 1 inside the diode region 102 to the emitter electrode 13, resulting in a state where there are excess carriers inside the diode region 102 in the state of causing conductivity modulation during the operation of the IGBT.

[0183] If the excess carriers inside the diode region 102 are not released, the transition to the off-state of the IGBT cannot be achieved. Therefore, the excess carriers inside the diode region 102 cause problems such as deterioration of the turn-off loss during the operation of the IGBT and deterioration of the reverse bias safe operating area (Reverse Bias Safe Operating Area, RBSOA) due to current concentration in the part near the diode region 102 in the IGBT region 101.

[0184] In the present embodiment, as described above <a-1-4>As in the sixth feature, since a defective region 15 is formed in the region of the diode region 102 that contacts the IGBT region 101, excess carriers become likely to flow into the diode region 102, enabling current dispersion, thereby suppressing current concentration in the portion near the diode region 102 in the IGBT region 101, and suppressing problems such as deterioration of turn-off loss and RBSOA deterioration during IGBT operation.

[0185] In the p-type anode layer 5 and the p + -type contact layer 6, it is effective to form the defective region 15 in a portion where the p-type impurity concentration is approximately greater than or equal to 1.0E+16 / cm 3 .

[0186] Preferably, the defective region 15 is formed on the current path for becoming a minority carrier recombination center, but if the depletion layer reaches the defective region 15 when the diode is turned off (during withstand voltage holding), the problem of increased leakage current occurs. Therefore, it is effective to form the defective region 15 in a region where the depletion layer does not reach during withstand voltage holding. The region where the depletion layer does not reach during withstand voltage holding depends on the depth and concentration distribution of the anode region, but by forming the defective region 15 in a manner that does not include a region where the p-type impurity concentration is less than or equal to 1.0E+16 / cm 3 , it is possible to suppress the depletion layer from reaching the defective region 15 during withstand voltage holding. Thereby, it is possible to suppress the leakage current during withstand voltage holding and effectively reduce the recovery current.

[0187] In Figure 23 , the results of verifying the relationship between the area ratio of the p + -type contact layer 6 in the diode region 102 of the present embodiment and the recovery peak current (Irr) during diode operation are shown by simulation. The area ratio of the p + -type contact layer 6 in the diode region 102 is the ratio of the area of the p + -type contact layer 6 of the diode region 102 when viewed from above to the area of the region when the p-type anode layer 5 and the p + -type contact layer 6 of the diode region 102 are combined and viewed from above.

[0188] Figure 23 In Conditions 1 and 2, the defect density of the defective region 15 is changed in the present embodiment. The defect density of Condition 2 is higher than that of Condition 1, and the probability of recombination through the defective region 15 is higher than that of Condition 1. In Conditions 1 and 2, the defective region 15 is not provided in the p + -type contact layer 6, but on the second main surface side of the p-type anode layer 5 and in the p + -type contact layer 6 and is in contact with the p + The same region as the p-type contact layer 6 when viewed from above is in contact with the side surface on the second main surface side of the p-type contact layer 6. In addition, + the defective region 15 is removed from Condition 1 or Condition 2 in the comparative example shown in Figure 23 . That is, for the Condition 1, Condition 2, and the comparative example shown in Figure 23 , if the area ratio of the p-type contact layer 6 is the same, the structures are the same except for the defective region 15. In particular, the p-type anode layer 5 and the p + -type contact layer 6 are arranged in the same way. In the simulation shown in + , the p Figure 23 -type contact layer 6 is configured to extend in the extending direction of the trench gate 50. For Condition 1 and Condition 2 as well as the comparative example shown in + , the area ratio of the p Figure 69 -type contact layer 6 is changed by changing the width of the p + -type contact layer 6 in the direction perpendicular to the extending direction of the trench gate 50, but it is considered that the same result is obtained even if the width in the extending direction of the trench gate 50 is changed. + As described above, in the present embodiment, the defective region 15 is formed in the same region as the p

[0189] -type contact layer 6 when viewed from above. That is, ideally, the defective region 15 is formed only in the region overlapping with the p + -type contact layer 6 when viewed from above. Therefore, it is possible to effectively suppress the inflow of holes from the part with high inflow efficiency. Since the defective region 15 is not formed in the part that does not overlap with the p + -type contact layer 6 but only overlaps with the p-type anode layer 5 when viewed from above, it is possible to suppress an increase in the forward voltage drop Vf and improve the in-plane uniformity of the ease of current flow. + As can be seen from

[0190] , regardless of the differences between Condition 1 and Condition 2, if it is the structure of the present embodiment, through the defective region 15, compared with the comparative example with the same area ratio as the p Figure 23 -type contact layer 6, the recovery peak current (Irr) can be reduced, and thus the recovery loss can be reduced. If the area ratio of the p + -type contact layer 6 (the area ratio of the defective region 15) is greater than or equal to 20%, it can be seen that compared with the prior art with a substantially same area ratio, the effect is such that the recovery peak current (Irr) can be reduced by greater than or equal to 5%. + Moreover, Condition 2 can obtain p

[0191] -type contact layer 6 and + The higher the area ratio of the p-type contact layer 6 (area ratio of the defective region 15), the more the recovery peak current (Irr) and recovery loss (Err) can be reduced. It can be seen that in Condition 2, compared with the minimum loss that can be achieved when there is no defective region 15 (the loss when the area ratio of the p-type contact layer 6 in Figure 23 is p + type contact layer 6 is 0%), the loss can be reduced.

[0192] That is, when there is no defective region 15, if the area of the p + type contact layer 6 is reduced to reduce the recovery loss, as a side effect, the forward voltage drop increases due to the increase in the ohmic resistance. However, in this embodiment, the defective region 15 does not increase the ohmic resistance and the recovery loss can be reduced, so the trade-off relationship between the recovery loss and the forward voltage drop can be improved.

[0193] Moreover, if the defect density of the defective region 15 is set high as in Condition 2, by increasing the area ratio of the p + type contact layer 6 and the defective region 15, the ohmic resistance can be reduced, and the recovery current and recovery loss can be reduced.

[0194] <A-4. Effects>

[0195] As described above, in the semiconductor device 200 or semiconductor device 201 of this embodiment, a defective region 15 is formed in a portion of the p-type anode layer 5 that overlaps with the p + type contact layer 6 when viewed from above. Since the region where the defective region 15 is formed contacts the conduction path in the on state of the diode and the defective region 15 is formed, the amount of holes flowing from the p + type contact layer 6 into the n - type drift layer 1 in the on state of the diode can be reduced, so the recovery current and recovery loss of the diode can be reduced.

[0196] The defective region 15 contains any one of argon, nitrogen, helium, and hydrogen, and the semiconductor device 200 or semiconductor device 201 can be manufactured inexpensively using a common ion implanter.

[0197] Moreover, in the ion implantation for forming the defective region 15, since the same mask as the mask used in the ion implantation for forming the p + type contact layer 6 can be used, the increase in the number of processes can be limited to the minimum, and the defective region 15 can be formed.

[0198] The defective region 15 is such that the concentration of p-type impurities in the p-type anode layer 5 is less than or equal to 1.0E+16 / cm 3 It is formed in such a manner as to be in a region. Since a defect region 15 is formed in the current path in the diode conduction state and in the region where the depletion layer does not reach in the diode cutoff state, an increase in the leakage current in the diode cutoff state can be suppressed, and the recovery loss can be reduced.

[0199] Moreover, the ratio of the area of the p + -type contact layer 6 and the defect region 15 when viewed from above to the area of the region when the p-type anode layer 5 and the p + -type contact layer 6 are combined and viewed from above is set to be greater than or equal to 20%, which can reduce the ohmic resistance between the anode region and the emitter electrode 13 and reduce the recovery loss of the diode as compared with the case where there is no defect region 15.

[0200] <B. Embodiment 2>

[0201] <B-1. Structure>

[0202] In Figure 1 is shown a plan view of the strip-shaped RC-IGBT, i.e., the semiconductor device 200b, of the present embodiment. In Figure 2 is shown a plan view of the island-shaped RC-IGBT, i.e., the semiconductor device 201b, of the present embodiment. In Figure 3 is shown an enlarged plan view of the region surrounded by the dashed line 82 in the semiconductor device 200b shown in Figure 1 or the semiconductor device 201b shown in Figure 2 magnified.

[0203] Figure 24 is a cross-sectional view taken along the line A-A shown in Figure 3 of the semiconductor device 200b or the semiconductor device 201b. Figure 25 is a cross-sectional view taken along the line B-B shown in Figure 3 of the semiconductor device 200b or the semiconductor device 201b.

[0204] In the present embodiment, compared with the semiconductor device 200 or the semiconductor device 201 of Embodiment 1, there is no defect region 15. Instead, as Figure 24 shown, an n-type semiconductor layer 19 (the eighth semiconductor layer) is formed on the second main surface side of the p + -type contact layer 6. That is, the n-type semiconductor layer 19 is selectively formed on the surface on the first main surface side of the p-type anode layer 5, and the p + -type contact layer 6 is formed on the surface on the first main surface side of the n-type semiconductor layer 19. The n-type semiconductor layer 19 and the p + The type contact layer 6 is formed in the same area when viewed from above. Except for these aspects, the structures of the semiconductor device 200b or the semiconductor device 201b are the same as those of the semiconductor device 200 or the semiconductor device 201, respectively. However, in the present embodiment, if the p-type impurity concentration in the region on the first main surface side of the n-type semiconductor layer 19 in the anode region is higher than that in the region on the second main surface side of the n-type semiconductor layer 19, the region on the first main surface side of the n-type semiconductor layer 19 can be regarded as p + type contact layer 6, and the region on the second main surface side of the n-type semiconductor layer 19 can be regarded as a p-type anode layer 5.

[0205] In the present embodiment, as described in <B-2. Manufacturing method>, the n-type semiconductor layer 19 introduces n-type impurities into the p-type region and is formed as an n-type region as a whole. Whether the n-type semiconductor layer 19 is n-type as a whole can be determined by a scanning capacitance microscopy method (SCM) or a spreading resistance profiler (SRP).

[0206] <B-2. Manufacturing method>

[0207] In Figures 26 to 29 an example of the manufacturing method of the present embodiment is shown.

[0208] Figure 26 is a manufacturing process diagram of a cross section corresponding to Figure 24 and is the same as that of Embodiment 1. Figure 14 Same.

[0209] From Figure 26 this state, except for a part of the diode region 102, it is covered with a photoresist 16 through a mask process, and n-type impurities are introduced into this part of the diode region 102 ( Figure 27 ). In the present embodiment, by introducing phosphorus or arsenic, an n-type impurity introduction region 20 is formed.

[0210] Moreover, in the next process, in a state where the semiconductor substrate is locally covered with the same photoresist 16, p-type impurities are introduced to a position shallower than the n-type impurity introduction region 20 to form a p-type impurity introduction region 17 ( Figure 28 ).

[0211] In the next process, by removing the photoresist 16 and performing heat treatment, the p-type impurity introduction region 17 can be set as p + type contact layer 6, the n-type impurity introduction region 20 is set as the n-type semiconductor layer 19, and the structure of the diode region 102 is formed ( Figure 29 ).

[0212] In the method of manufacturing the semiconductor device according to this embodiment, the formation of the p-type impurity introduction region 17 and the n-type impurity introduction region 20 can be performed by ion implantation using a general ion implanter, and the p-type impurity introduction region 17 and the n-type impurity introduction region 20 can be formed at low cost.

[0213] In addition, since the same mask can be used when forming the p-type impurity introduction region 17 and when forming the n-type impurity introduction region 20, an increase in cost caused by forming the n-type impurity introduction region 20 is suppressed.

[0214] Since Figure 29 the subsequent processes are the same as those in Embodiment 1 Figure 17 the subsequent processes will be omitted from description.

[0215] <B-3. Operation>

[0216] In the semiconductor device 200b or the semiconductor device 201b according to this embodiment, a diode structure is formed by the p-type anode layer 5 and the p + type contact layer 6, the n - type drift layer 1 and the n + type cathode layer 12. In the diode conduction state, holes flow from the p-type anode layer 5 and the p + type contact layer 6 into the n - type drift layer 1.

[0217] The n-type semiconductor layer 19 is formed above the path of the current flowing from the p + type contact layer 6 to the n - type drift layer 1. The n-type semiconductor layer 19 acts as a potential barrier layer for holes flowing from the p + type contact layer 6 to the n - type drift layer 1. In addition, holes are recombined through the n-type semiconductor layer 19, so that the number of holes flowing into the n - type drift layer 1 becomes smaller. Therefore, the degree of conductivity modulation is reduced, and the carrier concentration near the anode region in the diode conduction state becomes lower than that in the case without the n-type semiconductor layer 19.

[0218] In this embodiment, as described above, the carrier concentration near the anode region in the diode conduction state is designed to be lower than that in the case without the n-type semiconductor layer 19. Therefore, compared with the case without the n-type semiconductor layer 19, the area ratio of the p + type contact layer 6 is not reduced, and the effects of reducing the recovery peak current and the recovery loss during the recovery operation can be obtained. As described above, through the n-type semiconductor layer 19, the trade-off relationship between the recovery loss and the forward voltage drop can be improved.

[0219] In order to prevent an increase in the leakage current in the cut-off state of the diode, it is preferable that the n-type semiconductor layer 19 is in a region where the depletion layer does not reach during withstand voltage retention. The n-type semiconductor layer 19 is formed in such a manner that it does not include a region where the p-type impurity concentration in the p-type anode layer 5 is less than or equal to 1.0E+16 / cm 3 is sufficient.

[0220] In addition, by setting the ratio of the area of the p + -type contact layer 6 (i.e., the area of the n-type semiconductor layer 19) in a plan view to be greater than or equal to 20%, the recovery loss can be sufficiently reduced.

[0221] <C. Embodiment 3>

[0222] <C-1. Structure>

[0223] In Figure 1 is shown a plan view of the strip-shaped RC-IGBT, i.e., the semiconductor device 200c, of the present embodiment. In Figure 2 is shown a plan view of the island-shaped RC-IGBT, i.e., the semiconductor device 201c, of the present embodiment. In Figure 3 is shown an enlarged plan view in which the region surrounded by the dashed line 82 in the semiconductor device 200c shown in Figure 1 or the semiconductor device 201c shown in Figure 2 is enlarged and shown.

[0224] Figure 30 is a cross-sectional view taken along the line A-A shown in Figure 3 of the semiconductor device 200c or the semiconductor device 201c. Figure 31 is a cross-sectional view taken along the line B-B shown in Figure 3 of the semiconductor device 200c or the semiconductor device 201c.

[0225] In the semiconductor device 200c or the semiconductor device 201c of the present embodiment, in addition to forming the defect region 15 in the anode region in a portion that overlaps with the p + -type contact layer 6 in a plan view, a defect region 21 is also formed in a portion that does not overlap with the p + -type contact layer 6 in a plan view. Except for the aspect of forming the defect region 21, the structures of the semiconductor device 200c or the semiconductor device 201c are the same as those of the semiconductor device 200 or the semiconductor device 201, respectively.

[0226] Next, it is described that the region (the first crystal defect region) combining the defect region 15 and the defect region 21 occupies the whole of the p-type anode layer 5 in a plan view, but may also occupy a partial region of the p-type anode layer 5 in a plan view. For example, the defect region 21 only occupies, in a plan view, in the anode region, the part that overlaps with the p + A part of the non-overlapping portion of the p-type contact layer 6 when viewed from above.

[0227] <C-2. Manufacturing Method>

[0228] Refer to Figures 32 to 37 An example of the manufacturing method of the semiconductor device of this embodiment will be described.

[0229] Regarding Figures 32 to 34 the A-A cross-section and the B-B cross-section are common.

[0230] To Figure 32 the manufacturing process up to Figure 14 is different from that of Embodiment 1 up to Figure 14 in that the p-type anode layer 5 is not formed. This difference can be achieved by mask processing. The rest is the same as that of Embodiment 1 up to

[0231] From Figure 32 the state, except for a part of the diode region 102 is covered with the photoresist 16 through mask processing, and p-type impurities are introduced into this part of the diode region 102 to form a p-type impurity introduction region 22 ( Figure 33 ).

[0232] Next, in a state where the semiconductor substrate is locally covered with the same photoresist 16, any element among argon, nitrogen, helium, and hydrogen is introduced to a position deeper than the p-type impurity introduction region 22 to form a crystal defect introduction region 18 ( Figure 34 ).

[0233] In the next process, the photoresist 16 is removed, and through heat treatment, the impurities in the p-type impurity introduction region 22 diffuse to form a p-type anode layer 5 (A-A cross-section: Figure 35 , B-B cross-section: Figure 36 ).

[0234] After that, using ordinary mask processing, ion implantation technology, and diffusion technology, a p + type contact layer 6 is selectively formed in the diode region 102. Thus, the A-A cross-section becomes the state shown in Figure 37 . The B-B cross-section remains in the state of Figure 36 .

[0235] Since Figure 36 the subsequent processes are the same as those of Embodiment 1 Figure 17 after that, the description is omitted.

[0236] <C-3. Operation>

[0237] The operation of the semiconductor device 200c or the semiconductor device 201c in this embodiment is the same as that of the semiconductor device 200 or the semiconductor device 201 in Embodiment 1. That is, in the semiconductor device 200c or the semiconductor device 201c, when the diode is in the on state, the amount of holes flowing into the n - -type drift layer 1 is reduced through the defect region 15 and the defect region 21, whereby the reverse recovery peak current (Irr) and the recovery loss in the diode operation can be reduced without increasing the ohmic resistance, and the trade-off relationship between the recovery loss and the forward voltage drop can be improved.

[0238] In this embodiment, since all the current paths between the emitter electrode 13 of the diode region 102 and the n - -type drift layer 1 pass through the defect region 15 or the defect region 21, compared with Embodiment 1, although the forward voltage drop (Vf) in the diode on state becomes higher, the recovery loss is reduced. Embodiment 1 and this embodiment can be used differently according to the application.

[0239] By forming the defect regions 15 and 21 in such a way that they do not include regions where the impurity concentration of p-type is less than or equal to 1.0E+16 / cm 3 , it is possible to suppress the depletion layer from reaching the defect regions 15 and 21 during breakdown voltage retention and reduce the recovery current.

[0240] In addition, compared with Embodiment 1, a defect region 21 is newly formed in this embodiment, and all the current paths between the emitter electrode 13 of the diode region 102 and the n - -type drift layer 1 pass through the defect region 15 or the defect region 21. Therefore, if the defect density of the defect region 15 is set to the defect density of the defect region 15 under Condition 1 or Condition 2 in Figure 23 , and the area ratio of the p + -type contact layer 6 is set to be greater than or equal to 20%, then compared with the case where there are no defect regions 15 and 21, the recovery loss can be reduced by greater than or equal to 5%. Moreover, by appropriately setting the area ratio of the p + -type contact layer 6, an increase in the ohmic resistance of the anode region of the diode region 102 can be prevented.

[0241] <D. Embodiment 4>

[0242] <D-1. Structure>

[0243] In Figure 1 shows a top view of the strip-shaped RC-IGBT, i.e., the semiconductor device 200d, of this embodiment. In Figure 2 shows a top view of the island-shaped RC-IGBT, i.e., the semiconductor device 201d, of this embodiment. In Figure 3 shown in the Figure 1 The semiconductor device 200d or Figure 2 The enlarged plan view of the semiconductor device 201d shown is an enlarged view of the region surrounded by the dotted line 82.

[0244] Figure 38 The semiconductor device 200d or the semiconductor device 201d Figure 3 A cross-sectional view taken along line AA is shown. Figure 39 The semiconductor device 200d or the semiconductor device 201d Figure 3 A cross-sectional view at line BB is shown.

[0245] This embodiment is different from the embodiment 1 in that the p-type channel doping layer 2 in the IGBT region 101 is + A defect region 23 (second crystal defect region) is formed on the second main surface side of the type contact layer 4. Other aspects of this embodiment are the same as those of Embodiment 1. For example, the arrangement of the defect region 15 in this embodiment is the same as that of the defect region 15 in Embodiment 1.

[0246] The defect region 23 is formed at least in the p-type channel doping layer 2. + The second main surface side of the type contact layer 4 and the p + The defect region 23 may be disposed in a portion of the p-type channel doping layer 2 and overlapped with the p-type contact layer 4. + The p-type contact layer 4 may be separated from the p-type channel doping layer 2. + The surface contact area of the second main surface side of the type contact layer 4 may also be in the p + The surface of the second main surface side of the p-type contact layer 4 includes a surface in contact with the p-type channel doping layer 2, and spans the p-type channel doping layer 2 and the p-type contact layer 4. + In this embodiment, the defect region 23 and the p + The type contact layer 4 is formed in the same region when viewed from above.

[0247] <D-2.制造方法>

[0248] An example of a method for manufacturing a semiconductor device according to this embodiment will be described.

[0249] Figure 40 AA is a manufacturing process diagram of the IGBT region 101 and the diode region 102. Figure 13 The process to this point removes the oxide film 90 and obtains Figure 40 status.

[0250] from Figure 40 state, through mask processing, remove the regions of the p-type contact layer 4 formed in the IGBT region 101 and the regions of the p-type contact layer 6 formed in the diode region 102, cover them with the photoresist 16, introduce p-type impurities into a part of the IGBT region 101 and the diode region 102, and form a p-type impurity introduction region 17( + type contact layer 4, and the regions of the p + type contact layer 6 are covered with the photoresist 16, p-type impurities are introduced into a part of the IGBT region 101 and the diode region 102, and a p-type impurity introduction region 17 is formed( Figure 41 ).

[0251] Next, in a state where the semiconductor substrate is locally covered with the same photoresist 16, any element among argon, nitrogen, helium, and hydrogen is introduced to a position deeper than the p-type impurity introduction region 17 to form a crystal defect introduction region 18( Figure 42 ).

[0252] In the next process, the photoresist 16 is removed, and through heat treatment, the p-type impurity introduction region 17 is made into a p + type contact layer 4 or p + type contact layer 6, and the structure of the anode region of the IGBT region 101 and the diode region 102 is formed( Figure 43 ).

[0253] Since Figure 43 the subsequent processes are the same as those of Embodiment 1 Figure 17 the subsequent processes are the same, so the description is omitted.

[0254] In this embodiment, any one of argon, nitrogen, helium, and hydrogen is used for the formation of the defect region 15 and the defect region 23. These elements can be implanted by an ion implanter, and the defect regions can be formed at low cost.

[0255] Moreover, in this embodiment, the p + type contact layer 4 and the p + type contact layer 6 are formed by the same ion implantation process, and moreover, the defect region 15 and the defect region 23 are formed by the same ion implantation process. In addition, the same photoresist 16 is used in the ion implantation for forming the p + type contact layer 4 and the p + type contact layer 6 and the ion implantation for forming the defect region 15 and the defect region 23. Thus, in this embodiment, an increase in cost can be suppressed and the required functions can be achieved.

[0256] <D-3. Operation>

[0257] Since the structure of the diode region 102 in this embodiment is the same as that in Embodiment 1, the description of the operation related to the diode region 102 is omitted, and the operation related to the IGBT region 101 is described.

[0258] Since the IGBT region 101 is connected to the emitter electrode 13 and the collector electrode 14, a parasitic diode is formed through the p-type channel doping layer 2, the p + -type contact layer 4, the n - -type drift layer 1, and the n + -type cathode layer 12. Therefore, holes flowing into the n + -type drift layer 1 from the p-type channel doping layer 2 and the p - -type contact layer 4 may become a factor increasing the recovery loss of the entire device during the operation of the diode.

[0259] In the present embodiment, the defect region 23 is formed at least on the second main surface side of the p-type channel doping layer 2 in the p + -type contact layer 4 and in a region overlapping the p + -type contact layer 4 when viewed from above. Since the defect region 23 is located on the path where holes flow from the high-concentration impurity layer, i.e., the p + -type contact layer 4, into the n - -type drift layer 1, there is an effect that the carrier concentration of the n - -type drift layer 1 near the p-type channel doping layer 2 of the IGBT region 101 is reduced in the on-state during the operation of the diode. Therefore, similar to the case where it was explained in Embodiment 1 that the recovery loss during the operation of the diode can be reduced, the recovery loss of the parasitic diode formed through the p-type channel doping layer 2, the p + -type contact layer 4, the n - -type drift layer 1, and the n + -type cathode layer 12 can be reduced, and the recovery loss of the diode operation of the entire semiconductor device 200d or semiconductor device 201d can be comprehensively reduced.

[0260] In order to suppress the leakage current, similar to the case of Embodiment 1, it is effective to form the defect region 15 and the defect region 23 in such a way that they do not include a region where the impurity concentration of p is less than or equal to 1.0E+16 / cm 3 .

[0261] In addition, regarding the relationship between the area ratio of the p + -type contact layer 6 and the defect region 15 and the reduction of the recovery loss, since the same or better effects as those in Embodiment 1 are obtained under the same conditions as in Embodiment 1, the details are omitted.

[0262] As described above, in the present embodiment, in the diode region 102, the defect region 15 is provided on the second main surface side of the p-type anode layer 5 in the p + -type contact layer 6 and overlaps with the p + Region where the type - contact layer 6 overlaps in a plan view. Thus, by forming the defect region 15, it is possible to reduce the holes flowing into the n - type drift layer 1 without accompanying an increase in the ohmic resistance between the anode region and the emitter electrode 13. Thereby, the recovery loss can be reduced. In addition, it is possible to improve the trade - off relationship between the recovery loss and the forward voltage drop during diode operation. - Type - holes in the drift layer 1, thereby reducing the recovery loss. In addition, it is possible to improve the trade - off relationship between the recovery loss and the forward voltage drop during diode operation.

[0263] Moreover, similarly, since a defect region 23 is formed in a portion on the second main surface side of the p - type contact layer 4 in the p - type channel doping layer 2, it is possible to suppress the recovery loss caused by the parasitic diode formed across the IGBT region 101 and the diode region 102, and it is possible to improve the trade - off relationship between the recovery loss and the forward voltage drop during diode operation. In order to more effectively suppress the recovery loss caused by the parasitic diode, it is preferable that the defect region 23 is formed in a region where the distance from the diode region 102 in a plan view is smaller than the thickness of the semiconductor substrate. + Moreover, similarly, since a defect region 23 is formed in a portion on the second main surface side of the p - type contact layer 4 in the p - type channel doping layer 2, it is possible to suppress the recovery loss caused by the parasitic diode formed across the IGBT region 101 and the diode region 102, and it is possible to improve the trade - off relationship between the recovery loss and the forward voltage drop during diode operation. In order to more effectively suppress the recovery loss caused by the parasitic diode, it is preferable that the defect region 23 is formed in a region where the distance from the diode region 102 in a plan view is smaller than the thickness of the semiconductor substrate.

[0264] In addition, if the defect region 23 is formed only in the region that overlaps with the p - type contact layer 4 in a plan view, it is possible to suppress the influence on the on - state characteristics of the IGBT while suppressing the recovery loss caused by the parasitic diode. + In addition, if the defect region 23 is formed only in the region that overlaps with the p - type contact layer 4 in a plan view, it is possible to suppress the influence on the on - state characteristics of the IGBT while suppressing the recovery loss caused by the parasitic diode.

[0265] <E. Embodiment 5>

[0266] <E - 1. Structure>

[0267] In Figure 1 shows a plan view of the strip - type RC - IGBT, i.e., the semiconductor device 200e, of this embodiment. In Figure 2 shows a plan view of the island - type RC - IGBT, i.e., the semiconductor device 201e, of this embodiment. In Figure 3 shows an enlarged plan view of the region surrounded by the dashed line 82 in the semiconductor device 200e shown in Figure 1 or the semiconductor device 201e shown in Figure 2 magnified.

[0268] Figure 44 is a cross - sectional view taken along line A - A of the semiconductor device 200e or the semiconductor device 201e shown in Figure 3 . Figure 45 is a cross - sectional view taken along line B - B of the semiconductor device 200e or the semiconductor device 201e shown in Figure 3 .

[0269] In the semiconductor device 200e or the semiconductor device 201e of this embodiment, the region in the p - type channel doping layer 2 of the IGBT region 101 where the defect region 23 is formed extends over the region that overlaps with the p - + The entire overlapping region of the p-type contact layer 4 and the n + -type emitter layer 3 when viewed from above, that is, the entire in-plane direction of the p-type channel doping layer 2. Further, the defect region 23 is on the surface on the second main surface side of the p + -type contact layer 4, including the surface in contact with the p-type channel doping layer 2, and is formed across the p-type channel doping layer 2 and the p + -type contact layer 4. In other respects, it is the same as the semiconductor device 200c or the semiconductor device 201c of Embodiment 3. That is, in the present embodiment, when viewed from above, the region combining the defect region 23, the defect region 15, and the defect region 21 overlaps with the entire p-type channel doping layer 2 and the entire p-type anode layer 5.

[0270] <E-2. Manufacturing method>

[0271] An example of the manufacturing method of the semiconductor device of the present embodiment will be described.

[0272] Figure 46 It is a manufacturing process diagram of the A-A cross section of the IGBT region 101 and the diode region 102. Figure 47 It is a manufacturing process diagram of the B-B cross section of the IGBT region 101 and the diode region 102. By performing the Figure 13 processes up to the same as those in Embodiment 1, while forming the p + -type contact layer 4, the p + -type contact layer 6 of the A-A cross section is formed, thereby obtaining the Figure 46 and Figure 47 states.

[0273] Next, a photoresist 16 covering the trench gate 50 is formed by a mask process, and any element among argon, nitrogen, helium, and hydrogen is introduced by ion implantation to form the defect region 23, the defect region 15, and the defect region 21 (A-A cross section: Figure 48 , B-B cross section: Figure 49 ).

[0274] Since Figure 48 , Figure 49 the processes after Figure 17 are the same as those in Embodiment 1, the description thereof is omitted.

[0275] <E-3. Operation>

[0276] The structure of the semiconductor device 200e or semiconductor device 201e according to this embodiment is a structure obtained by combining Embodiments 1, 3, and 4. During diode operation, the current path of the diode in the diode region 102 and the current path of the parasitic diode existing across the IGBT region 101 and the diode region 102 pass through any one of the defect region 23, the defect region 15, and the defect region 21. Therefore, the recovery loss during diode operation can be reduced without an increase in the ohmic resistance. In addition, thereby, the trade-off relationship between the forward voltage drop Vf and the recovery loss can be improved.

[0277] <F. Embodiment 6>

[0278] <F-1. Structure>

[0279] In Figure 1 is shown a top view of the strip-shaped RC-IGBT, i.e., the semiconductor device 200f, according to this embodiment. In Figure 2 is shown a top view of the island-shaped RC-IGBT, i.e., the semiconductor device 201f, according to this embodiment. In Figure 50 is shown an enlarged top view showing an enlarged view of the region surrounded by the dashed line 82 in the semiconductor device 200f shown in Figure 1 or the semiconductor device 201f shown in Figure 2

[0280] Figure 51 is a cross-sectional view of the semiconductor device 200f or semiconductor device 201f at the Figure 50 shown G-G line. Figure 52 is a cross-sectional view of the semiconductor device 200f or semiconductor device 201f at the Figure 50 shown H-H line.

[0281] In Figure 50 , Figure 51 , Figure 52 the boundary cell region 105 is the unit cell region of the portion of the diode region 102 in contact with the IGBT region 101. The reference cell region 106 refers to the region of the diode region 102 other than the boundary cell region 105. A unit cell refers to each region divided by the trench gate 50.

[0282] In this embodiment, in the same region as the p + -type contact layer 4 when viewed from above, a defect region 23 is formed across the p + -type contact layer 4 and the p-type channel doping layer 2. In addition, in the same region as the p + -type contact layer 6 when viewed from above, a defect region 15 is formed across the p + -type contact layer 6 and the p-type anode layer 5.

[0283] In the present embodiment, as Figure 50 shown, the area ratio of the p + -type contact layer 6 in the boundary cell region 105 is higher than the area ratio of the p + -type contact layer 6 in the reference cell region 106.

[0284] The area ratio of the p + -type contact layer 6 in a certain region in the diode region is the ratio of the area of the p + -type contact layer 6 in the top view of this region to the area of the region obtained by combining the p-type anode layer 5 and the p + -type contact layer 6 in the top view of this region. Similarly, the area ratio of the defect region 15 in a certain region in the diode region is the ratio of the area of the defect region 15 in the top view of this region to the area of the region obtained by combining the p-type anode layer 5 and the p + -type contact layer 6 in the top view of this region.

[0285] In the present embodiment, since it is assumed that the defect region 15 is formed in the same region as the p + -type contact layer 6 in the top view, the area ratio of the p + -type contact layer 6 in a certain region in the diode region can be regarded as the area ratio of the defect region 15 in this certain region. That is, in the present embodiment, as Figure 50 shown, the area ratio of the defect region 15 in the boundary cell region 105 is higher than the area ratio of the defect region 15 in the reference cell region 106.

[0286] Moreover, the defect region 15 in the boundary cell region 105 is set to a condition such that the recovery peak current decreases as the areas of the p Figure 23 -type contact layer 6 and the defect region 15 increase, as in the case of Condition 2 of Embodiment 1 shown in + . For example, the defect densities of the defect regions 15 in both the boundary cell region 105 and the reference cell region 106 are set as in Figure 23 Condition 2 shown. Additionally, for example, the defect density of the defect region 15 in the boundary cell region 105 is set as in Figure 23 Condition 2 shown, while the defect density of the defect region 15 in the reference cell region 106 is set as in Figure 23 Condition 1 shown, and the defect density of the defect region 15 in the boundary cell region 105 is higher than the defect density of the defect region 15 in the reference cell region 106.

[0287] In addition to the p + In terms of the layout of the p-type contact layer 6 and the defect region 15 in a plan view and aspects other than the conditions of the defect concentration in the defect region 15, the structures of the semiconductor device 200f or the semiconductor device 201f in this embodiment are the same as those of the semiconductor device 200d or the semiconductor device 201d in Embodiment 4.

[0288] <F-2. Manufacturing Method>

[0289] The manufacturing method of the semiconductor device 200f or the semiconductor device 201f is the same as that of the semiconductor device 200d or the semiconductor device 201d. The layout of the p + -type contact layer 6 and the defect region 15 can be achieved by changing the patterning position during photolithography of the mask process.

[0290] <F-3. Operation>

[0291] The boundary cell region 105 is set such that the area ratio of the defect region 15 is higher and the recovery loss of the diode is lower than that of the adjacent reference cell region 106.

[0292] Moreover, compared with the reference cell region 106, in the IGBT region 101 near the boundary cell region 105 and its vicinity, there are fewer excess carriers near the p-type anode layer 5 in the diode-on state. Therefore, it is possible to suppress the recovery current flowing in the path of the parasitic diode that spans the IGBT region 101 and the diode region 102. The excess carriers are not limited to being injected by the parasitic diode, but only the loss caused by the recovery current flowing in the path of the parasitic diode is referred to as the recovery loss of the parasitic diode. Since the path of the parasitic diode is long and the loss is large, by suppressing the recovery loss of the parasitic diode, it is possible to effectively suppress the recovery loss of the entire device.

[0293] In this embodiment, the boundary cell region 105 is formed in one unit cell, but the boundary cell region 105 can also be formed in a plurality of unit cells on the side close to the IGBT region 101 to increase the area ratio of the defect region 15 in the boundary cell region 105. In this case, it is possible to more effectively suppress the recovery current flowing in the path of the parasitic diode and reduce the recovery loss.

[0294] <G. Embodiment 7>

[0295] <G-1. Structure>

[0296] In Figure 1 shows a plan view of the strip-type RC-IGBT, i.e., the semiconductor device 200g, of this embodiment. In Figure 2 shows a plan view of the island-type RC-IGBT, i.e., the semiconductor device 201g, of this embodiment. In Figure 53 shows the Figure 1 region surrounded by the dashed line 82 in the semiconductor device 200g or Figure 2 the semiconductor device 201g shown, in an enlarged plan view.

[0297] Figure 54 is a cross-sectional view taken along the line I-I of the semiconductor device 200g or the semiconductor device 201g. Figure 53 shown. Figure 55 is a cross-sectional view taken along the line J-J of the semiconductor device 200g or the semiconductor device 201g. Figure 53 shown.

[0298] In Figure 53 , Figure 54 , Figure 55 , the boundary cell region 107 is the region of the unit cell in the IGBT region 101 that is at the boundary with the diode region 102. In addition, the reference cell region 108 is the region in the IGBT region 101 other than the boundary cell region 107.

[0299] In the present embodiment, in the same region as the p + -type contact layer 4 when viewed from above, a defective region 23 is formed across the p + -type contact layer 4 and the p-type channel doping layer 2. In addition, in the same region as the p + -type contact layer 6 when viewed from above, a defective region 15 is formed across the p + -type contact layer 6 and the p-type anode layer 5.

[0300] In the IGBT region 101 of the semiconductor device 200g or the semiconductor device 201g, as Figure 53 shown, in the first main surface, the n + -type emitter layer 3 and the p + -type contact layer 4 are alternately arranged in the extending direction of the trench gate 50. In the present embodiment, the n + -type emitter layer 3 and the p + -type contact layer 4 are arranged in the same manner as in Embodiments 1 to 6. That is, it can also be set such that the n + -type emitter layer 3 and the p + -type contact layer 4 each extend in the extending direction of the trench gate 50, the n + -type emitter layer 3 contacts the gate insulating film 7 of the trench gate 50, and the p + -type contact layer 4 is separated from the gate insulating film 7 of the trench gate 50. In addition, in Embodiments 1 to 6, it can also be as in the present embodiment, the n + -type emitter layer 3 and the p + The p-type contact layer 4 is alternately arranged in the extending direction of the trench gate 50.

[0301] The semiconductor device 200g or the semiconductor device 201g of the present embodiment is as Figure shown, and the area ratio of the p-type contact layer 4 in the boundary cell region 107 is higher than that of the p-type contact layer 4 in the reference cell region 108. In addition, the area ratio of the defect region 23 in the boundary cell region 107 is higher than that of the defect region 23 in the reference cell region 108. + type contact layer 4 is higher than the area ratio of the p-type contact layer 4 in the reference cell region 108. + type contact layer 4 is higher than the area ratio of the defect region 23 in the reference cell region 108.

[0302] In a certain region of the IGBT region, the area ratio of the p + type contact layer 4 is the area of the p-type contact layer 4 in a plan view of this region relative to the area of the region obtained by combining the n + type contact layer 4 and the p + type emitter layer 3 and the p + type contact layer 4 in a plan view of the combined region.

[0303] In addition, in a certain region of the IGBT region, the area ratio of the defect region 23 is the area of the defect region 23 in a plan view of this region relative to the area of the region obtained by combining the p-type channel doping layer 2 and the n + type emitter layer 3 and the p + type contact layer 4 in a plan view of the combined region.

[0304] <G-2. Manufacturing method>

[0305] The semiconductor device 200g or the semiconductor device 201g can be manufactured in the same manner as the semiconductor device 200f or the semiconductor device 201f of Embodiment 6. Since the difference from Embodiment 6 can be achieved by changing the patterning position during photolithography of the mask process, detailed description is omitted.

[0306] <G-3. Operation>

[0307] Since the parasitic diode formed inside the boundary cell region 107 is close to the n + type cathode layer 12, the influence on the deterioration of the recovery loss of the entire element is greater than that of the parasitic diode formed inside the reference cell region 108.

[0308] In the present embodiment, the boundary cell region 107 having a great influence on the deterioration of the recovery loss is set such that the area ratio of the defect region 23 is higher than that of the reference cell region 108, and it is easy to suppress the recovery loss. Therefore, the recovery loss caused by the parasitic diode is effectively suppressed, and as a result, the recovery loss of the entire element can be effectively reduced.

[0309] In this embodiment, the boundary cell region 107 is formed by one unit cell, but it may also be formed in a plurality of unit cells on the side closer to the diode region 102 to increase the area ratio of the defective region 23 of the boundary cell region 107. In this case, the recovery loss caused by the parasitic diode can be more effectively reduced.

[0310] <H. Embodiment 8>

[0311] <H-1. Structure>

[0312] In ​ is shown a top view of the strip-shaped RC-IGBT, i.e., the semiconductor device 200h, of this embodiment. In ​ is shown a top view of the island-shaped RC-IGBT, i.e., the semiconductor device 201h, of this embodiment. In ​ is shown an enlarged top view of the region surrounded by the dashed line 82 in the semiconductor device 200h shown in ​ or the semiconductor device 201h shown in ​ is shown enlarged.

[0313] ​ is a cross-sectional view of the semiconductor device 200h or the semiconductor device 201h at the K-K line shown in ​ is shown. ​ is a cross-sectional view of the semiconductor device 200h or the semiconductor device 201h at the L-L line shown in ​ is shown.

[0314] One of the features of this embodiment is that Embodiment 6 and Embodiment 7 are combined, the area ratio of the defective region 15 of the boundary cell region 105 is higher than the configured area ratio of the defective region 15 of the reference cell region 106, and the area ratio of the defective region 23 of the boundary cell region 107 is higher than the area ratio of the defective region 23 of the reference cell region 108.

[0315] Another feature of the features of this embodiment is that as shown in ​ or ​ is shown, the boundary between the p-type collector layer 11 and the n + type cathode layer 12 is offset by a distance U1 toward the diode region 102 side compared with the boundary between the IGBT region 101 and the diode region 102. Thus, by setting the p-type collector layer 11 to extend into the diode region 102, the n of the diode region 102 can be increased + The distance between the trench gate 50 of the p-type cathode layer 12 and the IGBT region 101. Thus, even when a gate drive voltage is applied to the buried gate electrode 8 of the IGBT region 101 during the diode turn-on operation, it is possible to suppress the current from flowing through the channel formed adjacent to the trench gate 50 of the IGBT region 101 to the n + type cathode layer 12. The distance U1 can be, for example, 100 μm. Further, depending on the use of the RC-IGBT, i.e., the semiconductor device 200h or the semiconductor device 201h, the distance U1 can also be zero or a distance smaller than 100 μm. Additionally, in other embodiments as well, the distance U1 can be set corresponding to the use.

[0316] <H-2. Manufacturing method>

[0317] The semiconductor device 200h or the semiconductor device 201h can be manufactured in the same manner as the semiconductor device 200f or the semiconductor device 201f of Embodiment 6 or the semiconductor device 200g or the semiconductor device 201g of Embodiment 7. Since the difference from Embodiment 6 or Embodiment 7 can be achieved by changing the patterning position during photolithography when forming the front and back surfaces, detailed description is omitted.

[0318] <H-3. Operation>

[0319] In the present embodiment, it is set such that the area ratio of the defective region 15 in the boundary cell region 105 is higher than the area ratio of the defective region 15 in the reference cell region 106, and the area ratio of the defective region 23 in the boundary cell region 107 is higher than the area ratio of the defective region 23 in the reference cell region 108. During the diode operation of the element, the excess carrier density in the entire boundary cell regions 105 and 107 is significantly reduced. As a result, the recovery loss of the parasitic diode formed across the IGBT region 101 and the diode region 102, particularly across the boundary cell region 105 and the diode region 102, is reduced. Therefore, the recovery loss of the entire element can be reduced.

[0320] Moreover, in the present embodiment, since the boundary between the p-type collector layer 11 and the n + type cathode layer 12 is arranged to be biased toward the diode region 102 side compared to the boundary between the IGBT region 101 and the diode region 102, the distance between the anode region (p-type channel doping layer 2) of the parasitic diode in the IGBT region 101 and the n + type cathode layer 12 becomes larger. This actually has the same effect as thickening the n - type drift layer 1, and the excess carrier concentration in the vicinity of the region of the parasitic diode formed across the IGBT region 101 and the diode region 102 is reduced. Therefore, the recovery loss of the parasitic diode is further reduced.

[0321] <I. Embodiment 9>

[0322] In ​ a top view of the bar-shaped RC-IGBT, i.e., semiconductor device 200i, of the present embodiment is shown. In ​ a top view of the island-shaped RC-IGBT, i.e., semiconductor device 201i, of the present embodiment is shown. In ​ In ​ a magnified top view showing an enlarged view of the region surrounded by the dashed line 82 in the semiconductor device 200i shown in ​ or the semiconductor device 201i shown in

[0323] ​ is a cross-sectional view taken along line A-A shown in ​ of the semiconductor device 200i or the semiconductor device 201i. ​ is a cross-sectional view taken along line B-B shown in ​ of the semiconductor device 200i or the semiconductor device 201i.

[0324] The semiconductor device 200i or the semiconductor device 201i is the same as the semiconductor device 200 or the semiconductor device 201 of Embodiment 1 in the following aspects, that is, the defect region 15 is provided on the second main surface side of the p-type anode layer 5 in the p + -type contact layer 6 and in a region overlapping with the p + -type contact layer 6 when viewed from above. On the other hand, in the semiconductor device 200i or the semiconductor device 201i, the region where the defect region 15 is provided is not the whole but a part of the region overlapping with the p + -type contact layer 6 when viewed from above. In addition, the defect region 15 is only formed in the region overlapping with the p + -type contact layer 6 when viewed from above. In other aspects, the semiconductor device 200i or the semiconductor device 201i is the same as the semiconductor device 200 or the semiconductor device 201.

[0325] In the semiconductor device 200i or the semiconductor device 201i, since holes are recombined through the defect region 15, the number of holes flowing into the n - -type drift layer 1 in the on-state during diode operation is also smaller than in the case where there is no defect region 15, and the recovery loss can be reduced.

[0326] <J. Embodiment 10>

[0327] In ​ a top view of the bar-shaped RC-IGBT, i.e., semiconductor device 200j, of the present embodiment is shown. In ​ The top view of the island-type RC-IGBT, i.e., the semiconductor device 201j, of the present embodiment is shown. In ​ is shown ​ the enlarged top view which magnifies the region surrounded by the dashed line 82 in the semiconductor device 200j shown in ​ or the semiconductor device 201j shown in

[0328] ​ is the cross-sectional view taken along the line A-A of the semiconductor device 200j or the semiconductor device 201j ​ shown in ​ is the cross-sectional view taken along the line B-B of the semiconductor device 200j or the semiconductor device 201j ​ shown in

[0329] The present embodiment is obtained by combining the structure of Embodiment 1 with a device called CSTBT (registered trademark, Carrier Stored Trench-Gate Bipolar Transistor).

[0330] In CSTBT, an n-type carrier storage layer 25 is formed between the second main surface side of the p-type channel doping layer 2 and the p-type channel doping layer 2 and the n - type drift layer 1. CSTBT is a device that can reduce the steady-state loss in the IGBT on-state by having the structure of the n-type carrier storage layer 25.

[0331] Except for having the n-type carrier storage layer 25, the semiconductor device 200j or the semiconductor device 201j has the same structure as the semiconductor device 200 or the semiconductor device 201 of Embodiment 1.

[0332] In the present embodiment, the defect region 15 is provided at least on the second main surface side of the p-type contact layer 6 in the p-type anode layer 5 and in the region that overlaps the p + type contact layer 6 when viewed from above. Therefore, similar to Embodiment 1, the reverse recovery characteristics of the diode can be improved. Since the reverse recovery loss can be reduced without increasing the ohmic resistance, the trade-off relationship between the reverse recovery loss and the forward voltage drop can be improved. + type contact layer 6 when viewed from above. Therefore, similar to Embodiment 1, the reverse recovery characteristics of the diode can be improved. Since the reverse recovery loss can be reduced without increasing the ohmic resistance, the trade-off relationship between the reverse recovery loss and the forward voltage drop can be improved.

[0333] <K. Embodiment 11>

[0334] In ​ is shown the top view of the strip-type RC-IGBT, i.e., the semiconductor device 200k, of the present embodiment. In ​ is shown the top view of the island-type RC-IGBT, i.e., the semiconductor device 201k, of the present embodiment. In ​ is shown ​ The enlarged top view showing the region surrounded by the dashed line 82 in the semiconductor device 200k or ​ the semiconductor device 201k shown.

[0335] ​ It is a cross-sectional view taken along line A-A of the semiconductor device 200k or the semiconductor device 201k. ​ shown. ​ It is a cross-sectional view taken along line B-B of the semiconductor device 200k or the semiconductor device 201k. ​ shown.

[0336] In the present embodiment, as ​ , ​ shown, compared with Embodiment 1, the gate insulating film 7 is a thick film gate insulating film 26. Correspondingly, the shape of the buried gate electrode 8 changes. Regarding the thick film gate insulating film 26, the portion on the second main surface side is thicker than the portion on the first main surface side. By making the portion on the second main surface side thick, the gate capacitance can be reduced and high-speed operation can be achieved. By combining the effect of such a thick film gate insulating film 26 and the effect of reducing the excess carriers during the diode operation in the defect region 15 to reduce the recovery loss, further high-speed operation can be realized.

[0337] <L. Embodiment 12>

[0338] In ​ is shown the top view of the strip-shaped RC-IGBT, i.e., the semiconductor device 200l, of the present embodiment. In ​ is shown the top view of the island-shaped RC-IGBT, i.e., the semiconductor device 201l, of the present embodiment. In ​ is shown the enlarged top view showing the region surrounded by the dashed line 82 in the semiconductor device 200l or ​ the semiconductor device 201l shown. ​ shown.

[0339] ​ It is a cross-sectional view taken along line M-M of the semiconductor device 200l or the semiconductor device 201l. ​ shown. ​ It is a cross-sectional view taken along line N-N of the semiconductor device 200l or the semiconductor device 201l. ​ shown.

[0340] In the present embodiment, a pseudo trench gate 50b is provided in the IGBT region 101. In ​ , ​ In the cross-section shown, an interlayer insulating film 9 is provided over the pseudo trench gate 50b, but the pseudo trench gate 50b is electrically connected to the emitter electrode 13 in other cross-sections. The interlayer insulating film 9 may not be provided over the pseudo trench gate 50b. As ​ , ​ , ​ shown, in the region sandwiched by the pseudo trench gate 50b, a p + -type contact layer 4 is provided on the first main surface side. In the present embodiment, the structure of the diode region 102 is the same as that of the diode region 102 in the first embodiment. In the present embodiment as well, the trade-off relationship between the recovery loss and the forward voltage drop during diode operation is improved by the defect region 15.

[0341] <M. Embodiment 13>

[0342] In ​ is shown a plan view of the bar-shaped RC-IGBT, i.e., the semiconductor device 200m, of the present embodiment. In ​ is shown a plan view of the island-shaped RC-IGBT, i.e., the semiconductor device 201m, of the present embodiment. In ​ is shown an enlarged plan view of the region surrounded by the dashed line 82 in the semiconductor device 200m shown in ​ or the semiconductor device 201m shown in ​ .

[0343] ​ is a cross-sectional view taken along the line A-A shown in ​ of the semiconductor device 200m or the semiconductor device 201m. In ​ is shown a cross-sectional view taken along the line B-B shown in ​ of the semiconductor device 200m or the semiconductor device 201m.

[0344] In the present embodiment, compared with the fourth embodiment, the difference is that the defect region 15 of the diode region 102 is not formed. Other aspects are the same as those in the fourth embodiment. In the present embodiment as well, as described in the fourth embodiment, the recovery loss of the parasitic diode is reduced by the ​ shown defect region 23, and the recovery loss of the diode operation of the entire semiconductor device 200m or the semiconductor device 201m is comprehensively reduced, improving the trade-off relationship between the recovery loss and the forward voltage drop during diode operation. In order to more effectively suppress the recovery loss caused by the parasitic diode, it is preferable that the defect region 23 is formed to include the region in contact with the diode region 102. For example, it is preferably formed in a region where the distance from the diode region 102 in a plan view is smaller than the thickness of the semiconductor substrate.

[0345] <N. Embodiment 14>

[0346] In Embodiments 1, 3 to 12, as long as the defective region 15 or the defective region 21 or both are recombination regions (first recombination regions) where holes have a high degree of recombination, the same effects as those described in the respective embodiments can be obtained. In addition, the n-type semiconductor layer 19 of Embodiment 2 can also be regarded as a recombination region. Embodiment 2 can be combined with any one of Embodiments 6 to 9, and the defective region 15 of any one of Embodiments 6 to 9 can be replaced with the n-type semiconductor layer 19.

[0347] In addition, in Embodiments 4 to 8 and 13, as long as the defective region 23 is a recombination region (second recombination region) where holes have a high degree of recombination, the same effects as those described in the respective embodiments can be obtained. Instead of the defective region 23, an n-type semiconductor layer 28 (eleventh semiconductor layer) can be provided between the second main surface sides of the p-type channel doping layer 2 and the p + type contact layer 4. The region where the n-type semiconductor layer 28 is provided is, for example, a partial region of the p + type contact layer 4 when viewed from above, and is provided in a partial region of the boundary between the p-type channel doping layer 2 and the p + type contact layer 4. As a result, the holes flowing from the p + type contact layer 4 into the n - type drift layer 1 are reduced, the recovery loss of the parasitic diode is reduced, and the recovery loss of the diode operation of the entire semiconductor device is reduced.

[0348] The RC-IGBT has been described in each embodiment, but each embodiment can also be combined with a MOSFET or the like.

[0349] In addition, as an example of the manufacturing method, a manufacturing method using a Si substrate has been described, but a semiconductor substrate made of a different material such as SiC can also be used.

[0350] As a cell structure near the emitter electrode 13 of the IGBT region 101, a strip-shaped cell structure in which the trench gate 50 extends in one direction is illustrated, but it can be combined with a cell structure called a mesh type in which the trench gate extends vertically and horizontally, and can also be combined with a cell structure other than the trench type (a structure called a planar type).

[0351] In addition, the respective embodiments can be freely combined, and the respective embodiments can be appropriately deformed or omitted.

[0352] Description of reference numerals

[0353] 1 n - type drift layer, 2 p-type channel doping layer, 3 n + type emitter layer, 4 p + type contact layer, 5 p-type anode layer, 6 p + Type contact layer, 7 gate insulating film, 8 buried gate electrode, 9 interlayer insulating film, 10 n-type buffer layer, 11 p-type collector layer, 11a p-type end collector layer, 12 n + Type cathode layer, 13 emitter electrode, 13a end electrode, 14 collector electrode, 15, 21, 23 defect regions, 16 photoresist, 17, 22 p-type impurity introduction regions, 18 crystal defect introduction region, 19, 28 n-type semiconductor layers, 20 n-type impurity introduction region, 25 n-type carrier storage layer, 26 thick film gate insulating film, 31 p-type end well layer, 32 n + Type channel cut-off layer, 33 semi-insulating film, 34 end protective film, 50 trench gate, 50b pseudo-trench gate, 51 trench, 101 IGBT region, 102 diode region, 103 peripheral region, 104 gate pad region, 104a gate pad, 105, 107 boundary cell regions, 106, 108 reference cell regions, 120 semiconductor substrate, 200, 200b, 200c, 200d, 200e, 200f, 200g, 200h, 200i, 200j, 200k, 200l, 200m, 201, 201b, 201c, 201d, 201e, 201f, 201g, 201h, 201i, 201j, 201k, 201l, 201m, 1000 semiconductor device.

Claims

1. A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate, In this semiconductor device, The semiconductor substrate has: A first main surface and a second main surface as one main surface and the other main surface; A transistor region in which the transistor is formed; and A diode region in which the diode is formed, The transistor region has: A first semiconductor layer of a first conductivity type, which is provided on the second main surface side of the semiconductor substrate; A second semiconductor layer of a second conductivity type, which is provided on the first semiconductor layer; A third semiconductor layer of a first conductivity type, which is provided on the first main surface side of the semiconductor substrate compared with the second semiconductor layer; A fourth semiconductor layer of a second conductivity type, which is provided on the third semiconductor layer; A second electrode, which is electrically connected to the fourth semiconductor layer; and A first electrode, which is electrically connected to the first semiconductor layer, The diode region has: A fifth semiconductor layer of a second conductivity type, which is provided on the second main surface side of the semiconductor substrate; The second semiconductor layer, which is provided on the fifth semiconductor layer; A sixth semiconductor layer of a first conductivity type, which is provided on the first main surface side of the semiconductor substrate compared with the second semiconductor layer; A seventh semiconductor layer of a first conductivity type, which is provided on the sixth semiconductor layer, and the impurity concentration of the first conductivity type is higher than that of the sixth semiconductor layer; The second electrode, which is electrically connected to the seventh semiconductor layer; and The first electrode, which is electrically connected to the fifth semiconductor layer, A first composite region is provided at least in a region on the second main surface side of the seventh semiconductor layer in the sixth semiconductor layer and overlapping the seventh semiconductor layer in a plan view, The diode region is divided into a plurality of unit cell regions by a trench gate reaching the second semiconductor layer from the surface on the first main surface side of the semiconductor substrate, The ratio of the area of the first composite region in the unit cell region adjacent to the transistor region in the diode region in a plan view to the area of the region obtained by combining the sixth semiconductor layer and the seventh semiconductor layer in a plan view is higher than the ratio of the area of the first composite region in the unit cell region not adjacent to the transistor region in the diode region in a plan view to the area of the region obtained by combining the sixth semiconductor layer and the seventh semiconductor layer in a plan view.

2. The semiconductor device according to claim 1, wherein The first composite region is provided at least in a region in contact with the surface on the second main surface side of the seventh semiconductor layer in the sixth semiconductor layer.

3. The semiconductor device according to claim 1, wherein The first composite region is provided across the sixth semiconductor layer and the seventh semiconductor layer on the surface on the second main surface side of the seventh semiconductor layer, including the surface in contact with the sixth semiconductor layer.

4. The semiconductor device according to claim 2 or 3, wherein The first composite region is formed at least in a region in the diode region where the distance from the transistor region is smaller than the thickness of the semiconductor substrate when viewed from above.

5. The semiconductor device according to any one of claims 1 to 3, wherein the first composite region is formed only in a region that overlaps with the seventh semiconductor layer when viewed from above.

6. The semiconductor device according to any one of claims 1 to 3, wherein the first composite region and the seventh semiconductor layer are formed in the same region when viewed from above.

7. The semiconductor device according to any one of claims 1 to 3, wherein the area of the first composite region when viewed from above is greater than or equal to 20% of the area of the region obtained by combining the sixth semiconductor layer and the seventh semiconductor layer when viewed from above.

8. The semiconductor device according to any one of claims 1 to 3, wherein The sixth semiconductor layer has a region where the impurity concentration of the first conductivity type is greater than 1.0E+16 / cm 3 and a region where the impurity concentration of the first conductivity type in the sixth semiconductor layer is less than or equal to 1.0E+16 / cm 3 does not form the first recombination region.

9. The semiconductor device according to any one of claims 1 to 3, wherein the transistor region has a ninth semiconductor layer of a first conductivity type, the ninth semiconductor layer of the first conductivity type is provided in a remaining region of the third semiconductor layer other than the region where the fourth semiconductor layer is provided, and the impurity concentration of the ninth semiconductor layer of the first conductivity type is higher than that of the third semiconductor layer, the second electrode is electrically connected to the ninth semiconductor layer, a second composite region is provided at least on the second main surface side of the ninth semiconductor layer in the third semiconductor layer and in a region that overlaps with the ninth semiconductor layer when viewed from above.

10. The semiconductor device according to any one of claims 1 to 3, wherein the transistor region has a ninth semiconductor layer of a first conductivity type, the ninth semiconductor layer of the first conductivity type is provided in a remaining region of the third semiconductor layer other than the region where the fourth semiconductor layer is provided, and the impurity concentration of the first conductivity type is higher than that of the third semiconductor layer, the second electrode is electrically connected to the ninth semiconductor layer, a second crystal defect region is provided at least on the second main surface side of the ninth semiconductor layer in the third semiconductor layer and in a region that overlaps with the ninth semiconductor layer when viewed from above.

11. The semiconductor device according to any one of claims 1 to 3, wherein the transistor region has: a ninth semiconductor layer of a first conductivity type, which is provided in a remaining region of the third semiconductor layer other than the region where the fourth semiconductor layer is provided, and the impurity concentration of the first conductivity type is higher than that of the third semiconductor layer; and an eleventh semiconductor layer of a second conductivity type, which is provided in the third semiconductor layer below the ninth semiconductor layer, the second electrode is electrically connected to the ninth semiconductor layer.

12. A semiconductor device that forms a transistor and a diode in a common semiconductor substrate, in this semiconductor device, the semiconductor substrate has: a first main surface and a second main surface as one main surface and the other main surface; a transistor region in which the transistor is formed; and a diode region in which the diode is formed, the transistor region has: A first semiconductor layer of a first conductivity type, which is provided on the second main surface side of the semiconductor substrate; A second semiconductor layer of a second conductivity type, which is provided on the first semiconductor layer; A third semiconductor layer of a first conductivity type, which is provided on the first main surface side of the semiconductor substrate as compared with the second semiconductor layer; A fourth semiconductor layer of a second conductivity type, which is provided on the third semiconductor layer; A second electrode, which is electrically connected to the fourth semiconductor layer; and A first electrode, which is electrically connected to the first semiconductor layer, The diode region has: A fifth semiconductor layer of a second conductivity type, which is provided on the second main surface side of the semiconductor substrate; The second semiconductor layer, which is provided on the fifth semiconductor layer; A sixth semiconductor layer of a first conductivity type, which is provided on the first main surface side of the semiconductor substrate as compared with the second semiconductor layer; A seventh semiconductor layer of a first conductivity type, which is provided on the sixth semiconductor layer, and the impurity concentration of the first conductivity type is higher than that of the sixth semiconductor layer; The second electrode, which is electrically connected to the seventh semiconductor layer; and The first electrode, which is electrically connected to the fifth semiconductor layer, A first crystal defect region is provided at least on the second main surface side of the seventh semiconductor layer in the sixth semiconductor layer and in a region overlapping the seventh semiconductor layer when viewed from above; The diode region is divided into a plurality of unit cell regions by a trench gate reaching the second semiconductor layer from the surface on the first main surface side of the semiconductor substrate; The ratio of the area of the first crystal defect region in the unit cell region adjacent to the transistor region in the diode region when viewed from above to the area of the region obtained by combining the sixth semiconductor layer and the seventh semiconductor layer when viewed from above is higher than the ratio of the area of the first crystal defect region in the unit cell region not adjacent to the transistor region in the diode region when viewed from above to the area of the region obtained by combining the sixth semiconductor layer and the seventh semiconductor layer when viewed from above.

13. The semiconductor device according to claim 12, wherein, The first crystal defect region is provided at least in a region in contact with the surface on the second main surface side of the seventh semiconductor layer in the sixth semiconductor layer.

14. The semiconductor device according to claim 12, wherein, The first crystal defect region is provided across the sixth semiconductor layer and the seventh semiconductor layer on the surface on the second main surface side of the seventh semiconductor layer, including the surface in contact with the sixth semiconductor layer.

15. The semiconductor device according to any one of claims 12 to 14, wherein, The first crystal defect region contains Ar, i.e., argon.

16. The semiconductor device according to any one of claims 12 to 14, wherein, The first crystal defect region contains N, i.e., nitrogen.

17. The semiconductor device according to any one of claims 12 to 14, wherein, The first crystal defect region contains He, i.e., helium.

18. The semiconductor device according to any one of claims 12 to 14, wherein, the first crystal defect region contains H, i.e., hydrogen.

19. The semiconductor device according to claim 13 or 14, wherein, the first crystal defect region is formed at least in a region of the diode region where the distance from the transistor region is smaller than the thickness of the semiconductor substrate when viewed from above.

20. The semiconductor device according to any one of claims 12 to 14, wherein, the first crystal defect region is formed only in a region that overlaps with the seventh semiconductor layer when viewed from above.

21. The semiconductor device according to any one of claims 12 to 14, wherein, the first crystal defect region and the seventh semiconductor layer are formed in the same region when viewed from above.

22. The semiconductor device according to any one of claims 12 to 14, wherein, the area of the first crystal defect region when viewed from above is greater than or equal to 20% of the area of the region obtained by combining the sixth semiconductor layer and the seventh semiconductor layer when viewed from above.

23. The semiconductor device according to any one of claims 12 to 14, wherein, The 6th semiconductor layer has a region where the impurity concentration of the first conductivity type is greater than 1.0E+16 / cm 3 and in the region where the impurity concentration of the first conductivity type in the 6th semiconductor layer is less than or equal to 1.0E+16 / cm 3 the first crystal defect region is not formed.

24. The semiconductor device according to any one of claims 12 to 14, wherein, the transistor region has a ninth semiconductor layer of a first conductivity type, the ninth semiconductor layer of the first conductivity type is provided in a remaining region of the third semiconductor layer other than the region where the fourth semiconductor layer is provided, and the impurity concentration of the ninth semiconductor layer of the first conductivity type is higher than that of the third semiconductor layer, the second electrode is electrically connected to the ninth semiconductor layer, a second recombination region is provided at least on the second main surface side of the ninth semiconductor layer in the third semiconductor layer and in a region that overlaps with the ninth semiconductor layer when viewed from above.

25. The semiconductor device according to any one of claims 12 to 14, wherein, the transistor region has a ninth semiconductor layer of a first conductivity type, the ninth semiconductor layer of the first conductivity type is provided in a remaining region of the third semiconductor layer other than the region where the fourth semiconductor layer is provided, and the impurity concentration of the first conductivity type is higher than that of the third semiconductor layer, the second electrode is electrically connected to the ninth semiconductor layer, a second crystal defect region is provided at least on the second main surface side of the ninth semiconductor layer in the third semiconductor layer and in a region that overlaps with the ninth semiconductor layer when viewed from above.

26. The semiconductor device according to any one of claims 12 to 14, wherein, the transistor region has: a ninth semiconductor layer of a first conductivity type, which is provided in a remaining region of the third semiconductor layer other than the region where the fourth semiconductor layer is provided, and the impurity concentration of the first conductivity type is higher than that of the third semiconductor layer; and an eleventh semiconductor layer of a second conductivity type, which is provided in the third semiconductor layer below the ninth semiconductor layer, the second electrode is electrically connected to the ninth semiconductor layer.

27. A method for manufacturing a semiconductor device, which is a method for manufacturing the semiconductor device according to any one of claims 1 to 9, In this method for manufacturing a semiconductor device, The first composite region is formed by a first ion implantation, The seventh semiconductor layer is formed by a second ion implantation, The same mask is used in the first ion implantation and the second ion implantation.

28. A method for manufacturing a semiconductor device, which is a method for manufacturing the semiconductor device according to any one of claims 12 to 23, In this method for manufacturing a semiconductor device, The first crystal defect region is formed by a first ion implantation.

29. The method for manufacturing a semiconductor device according to claim 28, wherein, The seventh semiconductor layer is formed by a second ion implantation, The same mask is used in the first ion implantation and the second ion implantation.

30. The method for manufacturing a semiconductor device according to claim 28 or 29, wherein, Ion implantation of Ar, that is, argon, is performed in the first ion implantation.

31. The method for manufacturing a semiconductor device according to claim 28 or 29, wherein, Ion implantation of N, that is, nitrogen, is performed in the first ion implantation.

32. The method for manufacturing a semiconductor device according to claim 28 or 29, wherein, Ion implantation of He, that is, helium, is performed in the first ion implantation.

33. The method for manufacturing a semiconductor device according to claim 28 or 29, wherein, Ion implantation of H, that is, hydrogen, is performed in the first ion implantation.

Images