Semiconductor devices

Abstract

A semiconductor device with small output capacitance is provided, comprising, from bottom to top: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer with a larger band gap; a first source electrode; a second source electrode, and further comprising: a first gate electrode disposed on the second nitride semiconductor layer between the first source electrode and the second source electrode; a second gate electrode disposed on the second nitride semiconductor layer between the second source electrode and the first gate electrode; a drain electrode disposed on the second nitride semiconductor layer between the first gate electrode and the second gate electrode, and having a first wiring, a second wiring disposed between the second gate electrode and the first wiring, an element separation region of the second nitride semiconductor layer disposed below the first wiring and the second wiring, and a fourth wiring disposed above the first wiring, the second wiring, and the element separation region and electrically connected to the first wiring and the second wiring; and an insulating film disposed between the element separation region and the fourth wiring.

Description

[0001] Related Applications

[0002] This application claims the priority of Japanese Patent Application No. 2020-155011 (filing date: September 15, 2020) as a basic application, and the present application incorporates all the contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device. Background Art

[0004] As a material for the next generation of power semiconductor devices, III-nitrides such as GaN (gallium nitride) semiconductors are highly anticipated. GaN semiconductors have a larger band gap than Si (silicon). Therefore, GaN semiconductor devices can achieve small and high-voltage power semiconductor devices compared to Si (silicon) semiconductor devices. Summary of the invention

[0005] Embodiments of the present invention provide a semiconductor device having a small output capacitance.

[0006] A semiconductor device in an embodiment comprises: a substrate; a first nitride semiconductor layer provided on the substrate; a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer; a first source electrode provided on the second nitride semiconductor layer; a second source electrode provided on the second nitride semiconductor layer; a first gate electrode provided on the second nitride semiconductor layer between the first source electrode and the second source electrode; a second gate electrode provided on the second nitride semiconductor layer between the second source electrode and the first gate electrode; a drain electrode provided on the second nitride semiconductor layer between the first gate electrode and the second gate electrode, having a first wiring, a second wiring provided between the second gate electrode and the first wiring, an element separation region of the second nitride semiconductor layer provided below between the first wiring and the second wiring, and a fourth wiring provided on the first wiring, the second wiring and the element separation region and electrically connected to the first wiring and the second wiring; and an insulating film provided between the element separation region and the fourth wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a schematic plan view of the semiconductor device according to the first embodiment.

[0008] Figure 2 (a) and (b) are schematic diagrams of the semiconductor device according to the first embodiment.

[0009] Figure 3 It is a schematic plan view of the semiconductor device according to the first embodiment.

[0010] Figure 4 (a) and (b) are schematic diagrams of the semiconductor device according to the first embodiment.

[0011] Figure 5 (a) to (d) are schematic cross-sectional views of semiconductor devices according to other forms of the first embodiment.

[0012] Figure 6 This is a schematic cross-sectional view of a semiconductor device serving as a comparative example to the semiconductor device of the first embodiment.

[0013] Figure 7 It is a schematic plan view of a semiconductor device according to a second embodiment.

[0014] Figure 8 (a) and (b) are schematic cross-sectional views of a semiconductor device according to a second embodiment.

[0015] Fig. 9 It is a schematic plan view of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION

[0016] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same or similar components may be denoted by the same reference numerals. In addition, the description of components that have been described once may be appropriately omitted.

[0017] In this specification, in order to indicate the positional relationship of components, the upper direction of the drawings is described as "up", and the lower direction of the drawings is described as "down". In this specification, the concepts of "up" and "down" are not necessarily words that indicate the relationship with the direction of gravity.

[0018] (First Embodiment)

[0019] The semiconductor device of this embodiment comprises: a substrate; a first nitride semiconductor layer provided on the substrate; a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer; a first source electrode provided on the second nitride semiconductor layer; a second source electrode provided on the second nitride semiconductor layer; a first gate electrode provided on the second nitride semiconductor layer between the first source electrode and the second source electrode; a second gate electrode provided on the second nitride semiconductor layer between the second source electrode and the first gate electrode; a drain electrode provided on the second nitride semiconductor layer between the first gate electrode and the second gate electrode, having a first wiring, a second wiring provided between the second gate electrode and the first wiring, an element separation region of the second nitride semiconductor layer provided below between the first wiring and the second wiring, and a fourth wiring provided on the first wiring, the second wiring and the element separation region and electrically connected to the first wiring and the second wiring; and an insulating film provided between the element separation region and the fourth wiring.

[0020] Figure 1 1 is a schematic plan view of the semiconductor device 100 according to the present embodiment. Figure 2 It is a schematic diagram of a semiconductor device 100 according to this embodiment. Figure 2 (a) is a schematic plan view of a main part of the semiconductor device 100 according to the present embodiment. Figure 2 (b) is Figure 2 (a) is a schematic cross-sectional view of the semiconductor device 100 of this embodiment along a plane P. Figure 2 In (a), the Figure 1 Schematic diagram of source wiring 50 shown in FIG.

[0021] The semiconductor device 100 of the present embodiment is a HEMT (High Electron Mobility Transistor) using a nitride semiconductor such as GaN (gallium nitride), AlGaN (aluminum gallium nitride), or InGaN (indium gallium nitride). In addition, the electrode structure of the semiconductor device 100 of the present embodiment is, for example, a multi-finger touch structure.

[0022] For example, a Si (silicon) substrate or a sapphire substrate is used as the substrate 2. In particular, a Si (silicon) substrate is preferably used as the substrate 2. The substrate 2 has a substrate surface 2a.

[0023] The first nitride semiconductor layer 6 is, for example, non-doped Al X Ga 1－XN (0≤X<1). More specifically, the first nitride semiconductor layer 6 is, for example, non-doped GaN. The first nitride semiconductor layer 6 functions as a channel layer. The film thickness of the first nitride semiconductor layer 6 is, for example, not less than 0.2 μm and not more than 3 μm.

[0024] The second nitride semiconductor layer 8 is provided on the first nitride semiconductor layer 6. The band gap of the second nitride semiconductor layer 8 is larger than the band gap of the first nitride semiconductor layer 6. The second nitride semiconductor layer 8 is, for example, non-doped Al Y Ga 1－Y N (0<Y≤1, X<Y). More specifically, the second nitride semiconductor layer 8 is, for example, non-doped Al 0.2 Ga 0.8 N. The second nitride semiconductor layer 8 functions as a barrier layer. The film thickness of the second nitride semiconductor layer 8 is, for example, not less than 15 nm and not more than 50 nm.

[0025] The third nitride semiconductor layer 4 is provided between the substrate 2 and the first nitride semiconductor layer 6. The third nitride semiconductor layer 4 functions as a buffer layer for alleviating the lattice mismatch between the third nitride semiconductor layer 4 and the substrate 2. The third nitride semiconductor layer 4 is made of, for example, aluminum gallium nitride (AlGaN). W Ga 1－W N(0<W<1)) is formed.

[0026] In the present embodiment, an X direction, a Y direction perpendicularly intersecting the X direction, and a Z direction perpendicularly intersecting the X direction and the Y direction are defined. The Z direction is the direction in which the substrate 2, the third nitride semiconductor layer 4, the first nitride semiconductor layer 6, and the second nitride semiconductor layer 8 are stacked. The substrate 2, the substrate surface 2a, the third nitride semiconductor layer 4, the first nitride semiconductor layer 6, and the second nitride semiconductor layer 8 are arranged in parallel with respect to a plane including an X axis parallel to the X direction and a Y axis parallel to the Y direction, that is, an XY plane. In addition, the interface between the substrate 2 and the third nitride semiconductor layer 4, the interface between the third nitride semiconductor layer 4 and the first nitride semiconductor layer 6, and the interface between the first nitride semiconductor layer 6 and the second nitride semiconductor layer 8 are arranged in parallel with respect to the XY plane. In addition, the X direction is an example of a first direction, and the Y direction is an example of a second direction. Figure 2 The plane P shown in (a) is a plane parallel to the YZ plane.

[0027] A heterojunction interface is provided between the first nitride semiconductor layer 6 and the second nitride semiconductor layer 8. When the semiconductor device 100 is turned on, a two-dimensional electron gas (2DEG) is formed at the heterojunction interface and becomes a carrier.

[0028] The plurality of source electrodes 10 are separately provided on the second nitride semiconductor layer 8 . Figure 1 Plural source electrodes 10 a , 10 b , 10 c , and 10 d are shown as the source electrodes 10 . Figure 2 , a plurality of source electrodes 10a (an example of a first source electrode) and 10b (an example of a second source electrode) are shown as a plurality of source electrodes. The plurality of source electrodes 10 extend in the X direction. The plurality of source electrodes 10 have, for example, a stacked structure of titanium (Ti) and aluminum (Al) or a stacked structure of nickel (Ni) and gold (Au).

[0029] The plurality of gate electrodes 12 are provided on the second nitride semiconductor layer 8 between the source electrodes 10 . Figure 1 Plural gate electrodes 12 a , 12 b , 12 c , 12 d , 12 e , and 12 f are shown as the plurality of gate electrodes 12 . Figure 2 , a plurality of gate electrodes 12a (an example of a first gate electrode) and 12b (an example of a second gate electrode) are shown as the plurality of gate electrodes 12. The gate electrode 12a is provided between the source electrode 10a and the source electrode 10b. The gate electrode 12b is provided between the gate electrode 12a and the source electrode 10b. The plurality of gate electrodes 12 have, for example, a stacked structure of titanium (Ti) and aluminum (Al) or a stacked structure of nickel (Ni) and gold (Au).

[0030] The drain electrode 20 is provided on the second nitride semiconductor layer 8 between the gate electrodes 12 . Figure 2 The drain electrode 20 is shown in FIG. Figure 1 4 , fourth wirings 28 a , 28 b , and 28 c are shown as the fourth wirings 28 respectively included in the plurality of drain electrodes 20 .

[0031] Each drain electrode 20 includes a first wiring 22 a , a second wiring 22 b , a fifth wiring 24 a , a sixth wiring 24 b , a fourth wiring 28 a , an insulating film 26 , and an element isolation region 40 .

[0032] The first wiring 22 a extends in the X direction.

[0033] The second wiring 22b is provided between the gate electrode 12b and the first wiring 22a. The second wiring 22b extends in the X direction.

[0034] The element isolation region 40 is provided in the second nitride semiconductor layer 8 below between the first wiring 22a and the second wiring 22b. Figure 2In (b), the element isolation region 40 is provided between the second nitride semiconductor layer 8a below the source electrode 10a and the gate electrode 12a and the second nitride semiconductor layer 8b below the source electrode 10b and the gate electrode 12b. Moreover, the lower portion of the element isolation region 40 is sunken into the upper portion of the first nitride semiconductor layer 6 and is provided in the first nitride semiconductor layer 6. The element isolation region 40 is formed, for example, by implanting Ar (argon) ions into the first nitride semiconductor layer 6 or the second nitride semiconductor layer 8. In addition, the element isolation region 40 can also be formed by burying an insulating material such as a polyimide film or a BCB (benzocyclobutene) film having a relatively low dielectric constant in the first nitride semiconductor layer 6 or the second nitride semiconductor layer 8.

[0035] The fifth wiring 24a is provided on the first wiring 22a and is electrically connected to the first wiring 22a.

[0036] The sixth wiring 24b is provided on the second wiring 22b and is electrically connected to the second wiring 22b.

[0037] The fourth wiring 28a is provided on the fifth wiring 24a and the sixth wiring 24b and is electrically connected to the fifth wiring 24a and the sixth wiring 24b. In other words, the fifth wiring 24a is provided between the first wiring 22a and the fourth wiring 28a. In addition, the sixth wiring 24b is provided between the second wiring 22b and the fourth wiring 28a.

[0038] The insulating film 26a is Figure 2 In the cross section of the semiconductor device 100 shown in (b), the insulating film 26a is provided in a portion surrounded by the element isolation region 40, the first wiring 22a, the fifth wiring 24a, the fourth wiring 28a, and the sixth wiring 24b. For example, the insulating film 26a is provided between the element isolation region 40 and the fourth wiring 28a.

[0039] A plurality of source wirings 50 are provided on each source electrode 10 and are electrically connected to each source electrode. Figure 1 , source wirings 50a, 50b, 50c, and 50d as a plurality of source wirings 50 are provided on source electrodes 10a, 10b, 10c, and 10d. The source wirings 50a, 50b, 50c, and 50d are connected to a wiring 54. The fourth wirings 28a, 28b, and 28c are electrically connected to a wiring 56. The gate electrodes 12a, 12b, 12c, 12d, 12e, and 12f are electrically connected to a wiring 52. The wiring 54, the wiring 56, and the wiring 52 are electrically connected to, for example, an external circuit not shown.

[0040] In addition, an interlayer insulating film (not shown) is provided on the second nitride semiconductor layer 8, on the multiple source electrodes 10, on the multiple gate electrodes 12, on the multiple drain electrodes 20, on the multiple source wirings 50, around the wiring 52, around the wiring 54, and around the wiring 56.

[0041] The substrate 2 of the semiconductor device 100 is mounted on a metal package 150 ( Figure 2 (b) above.

[0042] The first wiring 22a, the second wiring 22b, the fifth wiring 24a, the sixth wiring 24b, the fourth wiring 28a, the source wiring 50, the wiring 52, the wiring 54, and the wiring 56 have, for example, a stacked structure of titanium (Ti) and aluminum (Al) or a stacked structure of nickel (Ni) and gold (Au). The insulating film 26a includes, for example, an insulating material such as a polyimide film or a BCB (benzocyclobutene) film having a low relative dielectric constant.

[0043] Figure 3 1 is a schematic plan view of the semiconductor device 100 according to the present embodiment. Figure 1 and Figure 3 The difference is that in Figure 3 , a first area 61, a second area 62, a third area 63, a fourth area 64, a fifth area 65, a sixth area 66, and a seventh area 67 are shown. The third area 63 is provided between the first area 61 and the second area 62. The second area 62 is provided between the third area 63 and the fifth area 65. The fifth area 65 is provided between the second area 62 and the fourth area 64. The fourth area 64 is provided between the fifth area 65 and the seventh area 67. The seventh area 67 is provided between the fourth area 64 and the sixth area 66.

[0044] Figure 4 It is a schematic diagram of a semiconductor device 100 according to this embodiment. Figure 2 and Figure 4 The difference is that in Figure 4 1 and 2 show a first region 61, a second region 62, and a third region 63. In the third region 63, the insulating film 26a in the element isolation region 40a is arranged.

[0045] The semiconductor device of this embodiment comprises: a substrate; a first nitride semiconductor layer provided on the substrate; a second nitride semiconductor layer, having a first region, a second region and a third region between the first region and the second region, provided on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer; a first gate electrode provided in the first region and extending in a first direction parallel to the substrate surface of the substrate; a first source electrode provided on the first region and extending in the first direction; a second gate electrode provided on the second region and extending in the first direction; a second source electrode provided on the second region and extending in the first direction; a drain electrode connected to a first wiring provided on the first region and a second wiring provided on the second region; and an insulating film provided in the third region.

[0046] like Figure 4 As shown, the first wiring 22a in the first region 61 is provided at a position closer to the insulating film 26a of the third region 63 than the source electrode 10a and the gate electrode 12a, and the second wiring 22b in the second region 62 is provided at a position closer to the insulating film 26a in the third region than the source electrode 10b and the gate electrode 12b. That is, the first wiring 22a and the second wiring 22b are provided at a position closest to the insulating film 26a compared with other layers. The first wiring 22a is provided at the end of the first region 61, and the second wiring 22b is provided at the end of the second region 62. The first wiring 22a, the second wiring 22b, the fifth wiring 24a, and the sixth wiring 24b are in contact with the insulating film 26a. In this embodiment, for example, the bottom of the insulating film 26a is deeper than the second nitride semiconductor layer 8 and is provided on the first nitride semiconductor layer 6.

[0047] In addition, although the first region 61 , the second region 62 , and the third region 63 are described here, the same also applies to the fourth region 64 , the fifth region 65 , the sixth region 66 , and the seventh region 67 .

[0048] Figure 5 It is a schematic cross-sectional view of a semiconductor device 100 according to another form of the present embodiment.

[0049] The element isolation region 40 may be as follows Figure 5 As in (a), the device isolation region 40 is not sunken into the first nitride semiconductor layer 6 but is provided in the second nitride semiconductor layer 8. Figure 5 (b) Figure 5 (c) and Figure 5 As shown in (d) of FIG. 1 , the element isolation region 40 may be formed integrally with the insulating film 26a made of an insulating material such as a polyimide film or a BCB (benzocyclobutene) film. Figure 5As shown in (b), the first nitride semiconductor layer 6 is not sunken, but is provided in the second nitride semiconductor layer, and a portion of the second nitride semiconductor layer 8 is provided between the element isolation region 40 and the first nitride semiconductor layer 6. In addition, the element isolation region 40 may be as shown in FIG. Figure 5 As shown in (c) of FIG. 1 , the element isolation region 40 is in contact with the upper surface of the first nitride semiconductor layer 6. Figure 5 As shown in (d) , the lower portion of the element isolation region 40 is sunken into the upper portion of the first nitride semiconductor layer 6 , and is provided in the first nitride semiconductor layer 6 .

[0050] Next, the effects of the semiconductor device 100 according to the present embodiment will be described.

[0051] Figure 6 1 is a schematic cross-sectional view of a semiconductor device 800 serving as a comparative embodiment of the present embodiment. The element isolation region 40 and the insulating film 26a are not provided. In addition, a wiring 22 is provided in which a first wiring 22a and a second wiring 22b are integrated. In addition, a wiring 24 is provided in which a fifth wiring 24a and a sixth wiring 24b are integrated.

[0052] The semiconductor device of this embodiment is expected to be applied to high-frequency power semiconductor devices and the like. However, semiconductor devices generally have a large output capacitance C oss . Output capacitor C oss is the drain-source capacitance C ds and the gate-drain capacitance C gd Here, the capacitance component between the substrate 2 and the drain electrode 20, or the capacitance component between the package 150 provided under the substrate 2 and the drain electrode 20, is greater than the drain-source capacitance C ds In high frequency operation, the output capacitor C oss The switching loss caused by the charge and discharge becomes larger, and there is a problem that a semiconductor device with higher breakdown strength and higher electron mobility cannot be provided.

[0053] In addition, when a two-dimensional electron gas is formed at the heterojunction interface under the drain electrode 20, the drain electrode 20 is electrically connected to the two-dimensional electron gas. Therefore, the capacitance component between the substrate 2 and the two-dimensional electron gas, or the capacitance component between the package 150 provided under the substrate 2 and the two-dimensional electron gas, contributes to the output capacitance C oss The impact is great, and there is a problem that the switching loss increases.

[0054] By reducing the area of ​​the drain electrode 20 in a plane parallel to the substrate surface 2a, C oss However, there is a problem that the on-resistance of the semiconductor device becomes higher.

[0055] In the semiconductor device 100 of the present embodiment, the wiring 22 ( Figure 6 ) and the first wiring 22a and the second wiring 22b are provided separately from each other. Thus, the capacitance component between the substrate 2 and the drain electrode 20 or the capacitance component between the package 150 and the drain electrode 20 can be reduced.

[0056] In addition, by providing the element isolation region 40, the concentration of the two-dimensional electron gas formed at the heterojunction interface below the first wiring 22a and the second wiring 22b can be reduced. As a result, the capacitance component between the substrate 2 and the two-dimensional electron gas, or the capacitance component between the package 150 and the two-dimensional electron gas can be reduced. In addition, the concentration of the two-dimensional electron gas formed at the heterojunction interface below the first wiring 22a and the second wiring 22b is preferably zero.

[0057] As described above, a semiconductor device with a small output capacitance can be provided. In addition, since the fourth wiring 28a is provided, an increase in on-resistance is suppressed.

[0058] In addition, since the fifth wiring 24a and the sixth wiring 24b are provided, the distance between the substrate 2 or the package 150 and the fourth wiring 28a can be further increased. Thus, the capacitance component between the substrate 2 or the package 150 and the fourth wiring 28a can be reduced.

[0059] The semiconductor device 100 of this embodiment is particularly preferably applied to a case where the substrate 2 is a Si (silicon) substrate. This is because the Si (silicon) substrate has a higher conductivity than the sapphire substrate, and thus it is easy to generate an output capacitance C between the substrate 2 and the drain electrode 20. oss , the switching loss tends to become high.

[0060] The insulating film 26 a is a polyimide film, a benzocyclobutene film, or a silicon oxide film (SiOC film) containing carbon having a low relative dielectric constant, thereby further reducing the capacitance component between the fourth wiring 28 a and the substrate 2 .

[0061] According to the semiconductor device of this embodiment, it is possible to provide a semiconductor device having a small output capacitance.

[0062] (Second Embodiment)

[0063] The semiconductor device of this embodiment comprises: a substrate; a first nitride semiconductor layer provided on the substrate; a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer; a first source electrode provided on the second nitride semiconductor layer and extending in a first direction parallel to the substrate surface of the substrate; a second source electrode provided on the second nitride semiconductor layer and extending in the first direction; a first gate electrode provided on the second nitride semiconductor layer between the first source electrode and the second source electrode and extending in the first direction; a second gate electrode provided on the second nitride semiconductor layer between the second source electrode and the first gate electrode and extending in the first direction; a drain electrode A gate electrode is provided on a second nitride semiconductor layer between a first gate electrode and a second gate electrode, and comprises: a first wiring extending along a first direction, a second wiring provided between the second gate electrode and the first wiring and extending along the first direction, a plurality of element separation regions in the second nitride semiconductor layer below the first wiring and the second wiring which are separately provided along the first direction, a plurality of third wirings provided on the second nitride semiconductor layer between the plurality of element separation regions and electrically connecting the first wiring and the second wiring, and a fourth wiring provided on the first wiring, the second wiring, the plurality of element separation regions and the plurality of third wirings; and an insulating film provided between the plurality of element separation regions and the fourth wiring.

[0064] Here, description of contents overlapping with those of the first embodiment will be omitted.

[0065] Figure 7 1 is a schematic plan view of a semiconductor device 110 according to the present embodiment. Figure 8 is a plane P parallel to the YZ plane of the semiconductor device 110 of the embodiment. 1 Schematic cross-sectional diagram ( Figure 8 (b)) and the plane P parallel to the YZ plane 2 Schematic cross-sectional diagram ( Figure 8 Schematic cross-sectional view in (a)).

[0066] In the semiconductor device 110, as Figure 7 as well as Figure 8 As shown in (a) of FIG. 1 , the semiconductor device 100 of the first embodiment is different from the semiconductor device 100 of the first embodiment in that a plurality of element isolation regions 40 are provided in the second nitride semiconductor layer 8 between the first wiring 22 a and the second wiring 22 b so as to be separated from each other in the X direction. Figure 7 Element isolation regions 40 a , 40 b , and 40 c are shown as the plurality of element isolation regions 40 .

[0067] In addition, if Figure 8As shown in (b) of FIG. 1 , the semiconductor device 100 of the first embodiment is different from the semiconductor device 100 of the first embodiment in that a plurality of third wirings 30 electrically connecting the first wirings 22 a and the second wirings 22 b are provided on the second nitride semiconductor layer 8 between the plurality of element isolation regions 40 . Figure 7 4 , third wirings 30 a , 30 b , and 30 c are illustrated as the plurality of third wirings 30 .

[0068] Furthermore, the semiconductor device 100 of the first embodiment is different from that of the semiconductor device 100 in the first embodiment in that the fifth wiring 24 a and the sixth wiring 24 b are not provided and the plurality of third wirings 30 are electrically connected to the fourth wiring 28 a .

[0069] In addition, Figure 8 In the figure, the insulating film 26a is omitted.

[0070] The height h of the plurality of third wirings 30 is 2 It is preferable that the height h of the first wiring 22a is 1 and the height h of the second wiring 22b 1 This is because the distance between the fourth wiring 28a and the substrate 2 or the package 150 is lengthened to reduce the output capacitance C oss In addition, the height of the first wiring 22a and the height of the second wiring 22b may be different.

[0071] The semiconductor device of this embodiment can also provide a semiconductor device having a small output capacitance.

[0072] (Third Embodiment)

[0073] The semiconductor device of this embodiment comprises: a substrate; a first nitride semiconductor layer provided on the substrate; a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer; a first source electrode provided on the second nitride semiconductor layer and extending in a first direction parallel to a substrate surface of the substrate, and increasing in width in a second direction intersecting the first direction as it extends in the first direction; a second source electrode provided on the second nitride semiconductor layer and extending in the first direction, and increasing in width in the second direction as it extends in the first direction; a first gate electrode provided on the second nitride semiconductor layer between the first source electrode and the second source electrode and separated from the first source electrode and the second source electrode; and a first gate electrode provided on the second nitride semiconductor layer between the second source electrode and the first gate electrode. A second gate electrode arranged separately from the second source electrode and the first gate electrode; a drain electrode arranged on the second nitride semiconductor layer between the first gate electrode and the second gate electrode, having a fourth wiring extending in a first direction and decreasing in width in a second direction as it extends in the first direction, a first wiring arranged between the second nitride semiconductor layer and the fourth wiring and extending substantially parallel to the side of the first source electrode opposite to the first gate electrode, a second wiring arranged between the second nitride semiconductor layer between the first wiring and the second gate electrode and the fourth wiring and extending substantially parallel to the side of the second source electrode opposite to the second gate electrode, and an element separation region of the second nitride semiconductor layer arranged below between the first wiring and the second wiring; and an insulating film arranged between the element separation region and the fourth wiring.

[0074] Here, description of contents overlapping with those of the first embodiment and the second embodiment will be omitted.

[0075] Fig. 9 It is a schematic plan view of the semiconductor device 120 according to the present embodiment.

[0076] The width of the source electrode 10a and the source electrode 10b in the Y direction increases as they extend in the X direction. This is because it is considered that the farther away from the wiring 54 ( Figure 1 ), the amount of carriers flowing through the source electrode 10a and the source electrode 10b becomes smaller, so the width of the plurality of source electrodes 10 in the portion away from the wiring 54 is narrowed.

[0077] The fourth wiring 28 decreases in width in the Y direction as it extends in the X direction. This is because it is considered that the farther away from the wiring 56 ( Figure 1 ), as the amount of carriers flowing through the drain electrode 20 decreases, the width of the fourth wiring 28 in the portion away from the wiring 56 is narrowed.

[0078] Here, the source electrode 10a has a side surface 10a facing the gate electrode 12a. 2and side 10a 1 The source electrode 10b has a side surface 10b facing the gate electrode 12b. 1 and side 10b 2 The fourth wiring 28 has a side surface 28 whose distance from the gate electrode 12a is shorter than that from the gate electrode 12b. 1 , and the side surface 28 having a shorter distance from the gate electrode 12b than from the gate electrode 12a 2 .

[0079] For example, side 10a 2 With side 28 1 Furthermore, the gate electrode 12a is parallel to the side surface 10a. 2 and side 28 1 The gate electrode 12a may extend substantially parallel to the side surface 10a. 2 and side 28 1 Extend completely parallel.

[0080] For example, side 10b 1 With side 28 2 In addition, the gate electrode 12b is parallel to the side surface 10b. 1 and side 28 2 The gate electrode 12b may extend substantially parallel to the side surface 10b. 1 and side 28 2 Extend completely parallel.

[0081] The first wiring 22a is provided between the second nitride semiconductor layer 8 and the fourth wiring 28. 2 and side 28 1 The first wiring 22a may extend substantially parallel to the side surface 10a. 2 and side 28 1 Extend completely parallel.

[0082] The second wiring 22b is provided between the second nitride semiconductor layer 8 and the fourth wiring 28 between the first wiring 22a and the gate electrode 12b. 1 and side 28 2 The second wiring 22b may extend substantially parallel to the side surface 10b. 1 and side 28 2 Extend completely parallel.

[0083] The first wiring 22 a and the second wiring 22 b are connected to each other in, for example, a connection portion 23 .

[0084] The fifth wiring 24a is provided between the first wiring 22a and the fourth wiring 28, and electrically connects the first wiring 22a and the fourth wiring 28. For example, the fifth wiring 24a is connected to the side surface 10a. 2 And side 28 1 Extending substantially parallel.

[0085] The sixth wiring 24b is provided between the second wiring 22b and the fourth wiring 28, and electrically connects the second wiring 22b and the fourth wiring 28. For example, the sixth wiring 24b is connected to the side surface 10b. 1 and side 28 2 Extending substantially parallel.

[0086] The fifth wiring 24 a and the sixth wiring 24 b are connected to each other in, for example, a connection portion 25 .

[0087] The element isolation region 40 is provided in the second nitride semiconductor layer 8 below and between the first wiring 22 a and the second wiring 22 b .

[0088] In the semiconductor device 120 as in the present embodiment, in which the width of the source electrodes 10a and 10b in the Y direction increases as they extend in the X direction and the width of the fourth wiring 28 in the Y direction decreases as they extend in the X direction, a semiconductor device with small output capacitance can be provided.

[0089] Although several embodiments and examples of the present invention have been described, these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor device, It is characterized in that have: substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer, disposed on the first nitride semiconductor layer, having a larger band gap than the first nitride semiconductor layer; A first source electrode is provided on the second nitride semiconductor layer and extends along a first direction parallel to a substrate surface of the substrate; A second source electrode, disposed on the second nitride semiconductor layer and extending along the first direction; a first gate electrode, disposed on the second nitride semiconductor layer between the first source electrode and the second source electrode, and extending along the first direction; A second gate electrode, disposed on the second nitride semiconductor layer between the second source electrode and the first gate electrode, and extending along the first direction; A drain electrode is provided on the second nitride semiconductor layer between the first gate electrode and the second gate electrode, and has: a first wiring extending along the first direction; A second wiring is provided between the second gate electrode and the first wiring and extends along the first direction; a plurality of element isolation regions, which are separately provided in the second nitride semiconductor layer below the first wiring and the second wiring along the first direction; a plurality of third wirings, provided on the second nitride semiconductor layer between the plurality of element isolation regions, and electrically connecting the first wirings and the second wirings; as well as a fourth wiring disposed on the first wiring, the second wiring, the plurality of element isolation regions, and the plurality of third wirings; as well as An insulating film is provided between the plurality of element isolation regions and the fourth wiring.

2. The semiconductor device according to claim 1, It is characterized in that The heights of the plurality of third wirings are higher than the heights of the first wirings and the second wirings, and the plurality of third wirings are electrically connected to the fourth wiring.

3. The semiconductor device according to claim 1 or 2, It is characterized in that The substrate is a Si substrate, that is, a silicon substrate.

Images