Semiconductor device

Abstract

Embodiments provide a semiconductor device capable of improving electrical characteristics at current interruption. The semiconductor device according to the embodiments includes a first electrode, a plurality of first semiconductor regions of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, a third semiconductor region of the first conductivity type, a plurality of fourth semiconductor regions of the second conductivity type, a plurality of fifth semiconductor regions of the second conductivity type, and a second electrode. The first and second semiconductor regions are provided above the first electrode. The third semiconductor region is provided above the first and second semiconductor regions. The fourth semiconductor regions are provided above the third semiconductor region. The fifth semiconductor regions are provided above the third semiconductor region. The second electrode is provided above the fourth and fifth semiconductor regions. The second and fifth semiconductor regions extend in a third direction perpendicular to the first direction and the second direction. The plurality of fifth semiconductor regions are located directly above the respective plurality of second semiconductor regions.

Description

[0001] Related Application

[0002] This application claims priority based on Japanese Patent Application No. 2020-154929 (filing date: September 15, 2020). This application incorporates the entire contents of the base application by reference thereto. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices. Background Art

[0004] Semiconductor devices such as diodes are used for power conversion and other applications. Improvement in electrical characteristics at current interruption is required in semiconductor devices. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor device capable of achieving improvement in electrical characteristics at current interruption.

[0006] The semiconductor device of the embodiment includes a first electrode, a plurality of first semiconductor regions of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, a third semiconductor region of the first conductivity type, a plurality of fourth semiconductor regions of the second conductivity type, a plurality of fifth semiconductor regions of the second conductivity type, and a second electrode. The plurality of first semiconductor regions are provided above the first electrode. The plurality of second semiconductor regions are provided above the first electrode, are arranged side by side with the plurality of first semiconductor regions in a second direction perpendicular to a first direction from the first electrode toward the plurality of first semiconductor regions, and extend in a third direction perpendicular to the first direction and the second direction. The third semiconductor region is provided above the first semiconductor regions and the plurality of second semiconductor regions, and has a lower impurity concentration of the first conductivity type than the first semiconductor regions. The plurality of fourth semiconductor regions are provided above the third semiconductor region. The plurality of fifth semiconductor regions are provided above the third semiconductor region, are arranged side by side with the plurality of fourth semiconductor regions in the second direction, and have a higher impurity concentration of the second conductivity type than the plurality of fourth semiconductor regions. At least a part of the plurality of fifth semiconductor regions is located directly above each of the plurality of second semiconductor regions. The second electrode is provided above the plurality of fourth semiconductor regions and the plurality of fifth semiconductor regions. Brief Description of the Drawings

[0007] Figure 1 is a cross-sectional view showing a semiconductor device of the first embodiment.

[0008] Figure 2 (a) of Figure 2 and (b) of are top views showing the semiconductor device of the first embodiment.

[0009] Figure 3 (a) of Figure 3 and (b) of

[0010] Figure 4 are cross-sectional views showing a semiconductor device.

[0011] Figure 5 (a) of Figure 5 and (b) of

[0012] Figure 6 (a) to Figure 6 (d) of

[0013] Figure 7 are graphs showing simulation results of the semiconductor device according to the first embodiment.

[0014] Figure 8 (a) of Figure 8 and (b) of

[0015] Figure 9 are plan views showing a semiconductor device according to a modification of the first embodiment. Detailed Embodiments

[0016] Hereinafter, each embodiment of the present invention will be described with reference to the accompanying drawings.

[0017] The accompanying drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as the actual structure. Even when showing the same part, there are cases where the sizes or ratios are shown differently from each other in the accompanying drawings.

[0018] In the present application specification and each figure, the same reference numerals are given to the same elements as those already described, and the detailed description is appropriately omitted.

[0019] In the following description and drawings, n + , n, n － and p ++ , p +The markings of p indicate the relative levels of the impurity concentrations. That is, a marking with "++" indicates a relatively higher impurity concentration compared to a marking with "+", and a marking with "+" indicates a relatively higher impurity concentration compared to a marking with neither "+" nor "-". A marking with "-" indicates a relatively lower impurity concentration compared to a marking with no marking. When both p-type impurities and n-type impurities are included in each region, these markings indicate the relative levels of the net impurity concentration after compensation between these impurities.

[0020] (First Embodiment)

[0021] Figure 1 is a cross-sectional view showing the semiconductor device of the first embodiment.

[0022] Figure 1 The semiconductor device 100 of the first embodiment shown in is a diode.

[0023] The semiconductor device 100 includes a first electrode 11, a second electrode 12, a plurality of n + -type cathode regions 31 (a plurality of first semiconductor regions), a plurality of p + -type cathode regions 32 (a plurality of second semiconductor regions), an n － -type drift region 33 (a third semiconductor region), a plurality of p-type anode regions 34 (a plurality of fourth semiconductor regions), and a plurality of p + -type anode regions 35 (a plurality of fifth semiconductor regions). In this example, the semiconductor device 100 further includes a plurality of p ++ -type anode regions 36 (a plurality of sixth semiconductor regions) and an n-type buffer region 40.

[0024] Here, the direction from the first electrode 11 toward the plurality of n + -type cathode regions 31 is defined as the first direction D1. The first direction D1 is, for example, a direction perpendicular to the upper surface of the first electrode 11. Two directions perpendicular to and orthogonal to the first direction D1 are defined as the second direction D2 and the third direction D3. In addition, for the sake of explanation, the direction from the first electrode 11 toward the n + -type cathode regions 31 is called "up", and the opposite direction is called "down". These directions are based on the relative positional relationship between the first electrode 11 and the n + -type cathode regions 31 and are independent of the direction of gravity.

[0025] Figure 2 of (a) and Figure 2 of (b) are top views showing the semiconductor device of the first embodiment.

[0026] Figure 2 of (a) is from Figure 1The top view of the semiconductor device 100 is observed from the arrow AA1 shown. That is, Figure 2 (a) of Figure 2 shows the surface (upper surface) side of the semiconductor device 100. Figure 2 (b) of Figure 2 is Figure 1 the top view of the semiconductor device 100 observed from the arrow AA2 shown. That is, Figure 2 (b) of Figure 2 shows the back surface (lower surface) side of the semiconductor device 100. Figure 1 Corresponding to the A1 - A2 cross-sectional view of (a) of Figure 1 and corresponding to the B1 - B2 cross-sectional view of (b) of Figure 2 . In addition, Figure 2 the second electrode 12 and multiple P Figure 2 type anode regions 36 are omitted in (a) of Figure 2 . Figure 2 The first electrode 11 is omitted in (b) of Figure 2 . ++ type anode regions 36. Figure 2 The first electrode 11 is omitted in (b) of Figure 2 .

[0027] For example, as Figure 1 shown, the first electrode 11 is provided on the lower surface of the semiconductor device 100. Multiple n + type cathode regions 31 are disposed above the first electrode 11 and are electrically connected to the first electrode 11. Multiple p + type cathode regions 32 are disposed above the first electrode 11 and are arranged side by side with multiple n + type cathode regions 31 in the second direction D2 and are electrically connected to the first electrode 11.

[0028] An n-type buffer region 40 is disposed above multiple n + type cathode regions 31 and multiple p + type cathode regions 32. An n － type drift region 33 is disposed above the n-type buffer region 40 (that is, above multiple n + type cathode regions 31 and multiple p + type cathode regions 32). The n-type impurity concentration in the n-type buffer region 40 is lower than the n-type impurity concentration in the n + type cathode region 31. The n － type impurity concentration in the n-type drift region 33 is lower than the n-type impurity concentration in the n-type buffer region 40.

[0029] Multiple p-type anode regions 34 are disposed above the n － type drift region 33. Multiple p + type anode regions 35 are disposed above the n － type drift region 33. The upper parts of multiple p + type anode regions 35 are arranged side by side with multiple p-type anode regions 34 in the second direction D2. The p-type impurity concentration in multiple p + type anode regions 35 is higher than the p-type impurity concentration in multiple p-type anode regions 34. Multiple p+ The lower end of the type-anode region 35 is located at a position lower than that of the plurality of p-type anode regions 34. Each p + type-anode region 35 has a shape protruding downward more than the plurality of p-type anode regions 34. Each p + type-anode region 35 is arranged side by side with the n － type drift region 33 in the second direction and is surrounded by the n － type drift region 33.

[0030] A plurality of p ++ type-anode regions 36 are provided above the plurality of p + type-anode regions 35. The lower part and the side part of the plurality of p ++ type-anode regions 36 are surrounded by the plurality of p + type-anode regions 35. The p-type impurity concentration in the plurality of p ++ type-anode regions 36 is higher than the p-type impurity concentration in the plurality of p + type-anode regions 35.

[0031] The second electrode 12 is provided above the plurality of p-type anode regions 34, the plurality of p + type-anode regions 35, and the plurality of p ++ type-anode regions 36. The second electrode 12 is electrically connected to the plurality of p-type anode regions 34, the plurality of p + type-anode regions 35, and the plurality of p ++ type-anode regions 36. A Schottky contact is formed between the plurality of p-type anode regions 34 and the second electrode 12.

[0032] As Figure 2 shown in (a) of, the plurality of p-type anode regions 34 are arranged in the second direction D2 and extend in the third direction D3. For example, the plurality of p-type anode regions 34 are arranged periodically or at equal intervals in the second direction D2. The width (the length along the second direction D2) of each p-type anode region 34 may be the same as that of other p-type anode regions 34 or may be constant in the third direction D3.

[0033] A plurality of p + type-anode regions 35 are arranged in the second direction D2 and extend in the third direction D3. For example, the plurality of p + type-anode regions 35 are arranged periodically or at equal intervals in the second direction D2. The width of each p + type-anode region 35 may be the same as the width of other p + type-anode regions 35 or may be constant in the third direction D3. The number of p + type-anode regions 35 is, for example, 240 or more and 600 or less. Regarding the plurality of p ++ type-anode regions 36 (refer toFigure 1 ) is the same.

[0034] A plurality of p-type anode regions 34 and a plurality of p + -type anode regions 35 are alternately arranged in the second direction D2. That is, p + One of the p-type anode regions 35 is located between one of the p-type anode regions 34 and another of the p-type anode regions 34. In addition, one of the p-type anode regions 34 is located between + One of the p-type anode regions 35 and + Another of the p-type anode regions 35.

[0035] As Figure 2 (b) shows, a plurality of n + -type cathode regions 31 are arranged in the second direction D2 and extend in the third direction D3. For example, a plurality of n + -type cathode regions 31 are arranged periodically or at equal intervals in the second direction D2. The width of each n + -type cathode region 31 may be the same as the width of other n + -type cathode regions 31 or may be constant in the third direction D3.

[0036] A plurality of p + -type cathode regions 32 are arranged in the second direction D2 and extend in the third direction D3. For example, a plurality of p + -type cathode regions 32 are arranged periodically or at equal intervals in the second direction D2. The width of each p + -type cathode region 32 may be the same as the width of other p + -type cathode regions 32 or may be constant in the third direction D3. The number of p + -type cathode regions 32 is, for example, 18 or more and 180 or less.

[0037] A plurality of n + -type cathode regions 31 and a plurality of p + -type cathode regions 32 are alternately arranged in the second direction D2. That is, n + One of the cathode regions 31 is located between + One of the p-type cathode regions 32 and + Another of the p-type cathode regions 32. In addition, one of the p + -type cathode regions 32 is located between + One of the n-type cathode regions 31 and + Another of the n-type cathode regions 31.

[0038] For example, as Figure 1 shown, at least a part of the plurality of p + -type anode regions 35 is located in the plurality of p+ directly above each of the n-type cathode regions 32. For example, at least one p- + type anode region 35 is located directly above one p- + type cathode region 32. Two or more p- + type anode regions 35 may also be arranged directly above one p- + type cathode region 32.

[0039] In addition, "directly above" means on a straight line extending parallel to the first direction D1. For example, as Figure 1 shown, one of the p- + type cathode regions 32 and one of the p- + type anode regions 35 are located on a straight line L1 parallel to the first direction D1. In other words, at least a part of each p- + type cathode region 32 overlaps at least a part of one or more p- + type anode regions 35 in the first direction D1.

[0040] In this example, at least a part of the multiple p- + type anode regions 35 and at least a part of the multiple p- ++ type anode regions 36 are located directly above the centers 32c in the second direction D2 of each of the multiple p- + type cathode regions 32. In other words, at least a part of the center 32c of each p- + type cathode region 32 overlaps at least one or more p- + type anode regions 35 and at least one or more p- ++ type anode regions 36 in the first direction D1.

[0041] In addition, "at least a part of the multiple p- + type anode regions 35 (or p- ++ type anode regions 36) is located directly above each of the multiple p- + type cathode regions 32" means that the p- + type anode region 35 (or p- ++ type anode region 36) does not necessarily have to be strictly located directly above all of the p- + type cathode regions 32. For example, it is assumed that when observing a cross-section parallel to the first direction D1, the p- + type anode region 35 (or p- ++ type anode region 36) is located directly above one or more of the three p- + type cathode regions 32.

[0042] Similarly, "at least a part of the multiple p- + type anode regions 35 (or p- ++At least a part of the p-type anode region 36) is located directly above the center of each of the plurality of p-type cathode regions 32 + "Located directly above the center of each" means that the p-type anode region 35 (or the p-type anode region 36) may not be strictly located directly above the center of all of the p-type cathode regions 32. For example, when observing a cross-section parallel to the first direction D1, the p-type anode region 35 (or the p-type anode region 36) is located directly above the center of one or more of the three p-type cathode regions 32 + type anode region 35 (or p ++ type anode region 36) is sufficient + For example, when observing a cross-section parallel to the first direction D1, the p-type anode region 35 (or the p-type anode region 36) is located directly above the center of one or more of the three p-type cathode regions 32 + type anode region 35 (or p ++ type anode region 36) is located directly above the center of one or more of the three p-type cathode regions 32 + That is, it is sufficient

[0043] The pitch of the plurality of p-type cathode regions 32 in the second direction D2 is defined as pitch p32. In addition, "pitch" refers to the length of the unit of repeated positions. Pitch p32 corresponds to the position of "one of the plurality of p-type cathode regions 32" in the second direction D2 and the position of "another one of the plurality of p-type cathode regions 32" adjacent to the "one of the plurality of p-type cathode regions 32" in the second direction D2 along the second direction D2 + That is, it is sufficient + type cathode regions 32" in the second direction D2 and the position of "another one of the plurality of p-type cathode regions 32" adjacent to the "one of the plurality of p-type cathode regions 32" in the second direction D2 along the second direction D2 + type cathode regions 32" in the second direction D2 and the position of "another one of the plurality of p-type cathode regions 32" adjacent to the "one of the plurality of p-type cathode regions 32" in the second direction D2 along the second direction D2 + type cathode regions 32" in the second direction D2 and the position of "another one of the plurality of p-type cathode regions 32" adjacent to the "one of the plurality of p-type cathode regions 32" in the second direction D2 along the second direction D2

[0044] In addition, the pitch of the plurality of p-type anode regions 35 in the second direction D2 is defined as pitch p35. Pitch p35 corresponds to the position of "one of the plurality of p-type anode regions 35" in the second direction D2 and the position of "another one of the plurality of p-type anode regions 35" adjacent to the "one of the plurality of p-type anode regions 35" in the second direction D2 along the second direction D2 + That is, it is sufficient + type anode regions 35" in the second direction D2 and the position of "another one of the plurality of p-type anode regions 35" adjacent to the "one of the plurality of p-type anode regions 35" in the second direction D2 along the second direction D2 + type anode regions 35" in the second direction D2 and the position of "another one of the plurality of p-type anode regions 35" adjacent to the "one of the plurality of p-type anode regions 35" in the second direction D2 along the second direction D2 + type anode regions 35" in the second direction D2 and the position of "another one of the plurality of p-type anode regions 35" adjacent to the "one of the plurality of p-type anode regions 35" in the second direction D2 along the second direction D2

[0045] For example, pitch p32 is a natural number multiple of pitch p35. In the example shown, pitch p32 is 2 times pitch p35. In addition, the range of "natural number multiple" includes "substantially" being a natural number multiple. "Substantially" includes, for example, the range of manufacturing errors Figure 1 For example, pitch p32 is 2 times pitch p35. In addition, the range of "natural number multiple" includes "substantially" being a natural number multiple. "Substantially" includes, for example, the range of manufacturing errors

[0046] An example of the material of each component of the semiconductor device 100 will be described

[0047] The plurality of n-type cathode regions 31, the plurality of p-type cathode regions 32, the n-type buffer region 40, the n + type cathode regions 31, the plurality of p + type cathode regions 32, the n-type buffer region 40, the n －The n-type drift region 33, the plurality of p-type anode regions 34, the plurality of p + -type anode regions 35, and the plurality of p ++ -type anode regions 36 contain silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. In the case of using silicon as the semiconductor material, arsenic, phosphorus, or antimony can be used as an n-type impurity. Boron can be used as a p-type impurity.

[0048] The first electrode 11 and the second electrode 12 contain a metal such as aluminum. For example, when the second electrode 12 contains a material having a relatively large work function, in order to form an ohmic contact between the plurality of p + -type anode regions 35 and the second electrode 12, a plurality of p ++ -type anode regions 36 are provided. For example, the second electrode 12 contains aluminum and silicon. In addition, the second electrode 12 contains titanium or tungsten. In these cases, it is preferable to provide a plurality of p ++ -type anode regions 36.

[0049] The operation of the semiconductor device 100 will be described.

[0050] If a positive voltage is applied to the second electrode 12 with respect to the first electrode 11, then a forward voltage is applied across the pn junction surface between the n － -type drift region 33 and the plurality of p + -type anode regions 35 (carrier injection regions). Holes are injected from the plurality of p + -type anode regions 35 into the n － -type drift region 33, and electrons are injected from the plurality of n + -type cathode regions 31 into the n － -type drift region 33. A current flows from the second electrode 12 to the first electrode 11, and the semiconductor device 100 becomes a conducting state. In the conducting state, holes and electrons are accumulated in the n － -type drift region 33, and the resistance of the n － -type drift region 33 is significantly reduced. In addition, through the Schottky contact with the second electrode 12, carriers are not injected from the plurality of p-type anode regions 34.

[0051] Then, if a positive voltage is applied to the first electrode 11 with respect to the second electrode 12, the current flowing from the second electrode 12 to the first electrode 11 is interrupted, and the semiconductor device 100 becomes an off state. The holes accumulated in the n － -type drift region 33 are discharged to the second electrode 12 through the plurality of p + -type anode regions 35. The accumulated electrons are discharged to the first electrode 11 through the plurality of n + -type cathode regions 31. The depletion layer is formed from the n － -type drift region 33 and the plurality of p +The pn junction plane of the type-anode region 35 extends to the n － -type drift region 33 according to the voltage. By extending to the n － -type drift region 33, the breakdown voltage is maintained by the depletion layer.

[0052] The n-type impurity concentration in the n-type buffer region 40 is higher than that in the n － -type drift region 33. Therefore, the depletion layer extends in the first direction D1 throughout the n － -type drift region 33. When it reaches the n-type buffer region 40, the extension of the depletion layer is suppressed. Thus, it is possible to prevent the depletion layer from reaching the n + -type cathode region 31.

[0053] In addition, the lower ends of the plurality of p + -type anode regions 35 protrude downward more than the plurality of p-type anode regions 34. Thus, when the semiconductor device 100 is switched from the on state to the off state to cut off the current, punch-through to the surface of the plurality of p-type anode regions 34 is less likely to occur, and the breakdown tolerance of the semiconductor device 100 is improved.

[0054] If a plurality of p + -type cathode regions 32 are provided, when the semiconductor device 100 is turned off, holes are injected from the first electrode 11 into the n + -type drift region 33 through the plurality of p － -type cathode regions 32. Thus, for example, the potential difference between the first electrode 11 and the second electrode 12 is suppressed from increasing sharply when turned off. For example, the vibration of the potential of the first electrode 11 can be suppressed, and the noise generated by the vibration of the potential can be reduced.

[0055] Describe the effects of the first embodiment.

[0056] As already described, in the embodiment, at least a part of the plurality of p + -type anode regions 35 is located directly above each of the plurality of p + -type cathode regions 32. Thus, when the semiconductor device 100 is turned off, the vibration of the potential difference between the first electrode 11 and the second electrode 12 is suppressed. For example, the vibration of the potential of the first electrode 11 at the time of turning off and the vibration of the current flowing between the first electrode 11 and the second electrode can be suppressed. Therefore, the electrical characteristics at the time of current interruption (turning off) can be improved.

[0057] For example, when the semiconductor device 100 is in the on state, there are many carriers under the plurality of p + -type anode regions 35 which are carrier injection sites. Therefore, at the time of turning off, there are many carriers under the plurality of p +Many carriers also remain under the n-type anode region 35. That is, there are many holes in the n-type drift region 33 and the n-type buffer region 40. In this case, the potential barrier from the p + -type cathode region 32 to the n-type drift region 33 and the n-type buffer region 40 becomes lower. Therefore, by disposing a plurality of p + -type anode regions 35 directly above the plurality of p + -type cathode regions 32, for example, the PNP transport efficiency from the plurality of p + -type cathode regions 32 to the plurality of p + -type anode regions 35 is improved, and it is considered that holes are easily injected from the plurality of p + -type cathode regions 32 during recovery. Thus, it is considered that the oscillation of the potential and current during turn-off can be suppressed.

[0058] Figure 3 (a) and Figure 3 (b) are cross-sectional views showing a semiconductor device.

[0059] Figure 3 (a) shows the semiconductor device 101 of the first embodiment. Figure 3 (b) shows the semiconductor device 190 of the comparative example.

[0060] Figure 4 and Figure 5 are graphs showing the simulation results of the semiconductor device 101 and the semiconductor device 190.

[0061] As shown in Figure 3 (a), in the semiconductor device 101, the pitch p32 (see Figure 1 ) is 1 times the pitch p35 (see Figure 1 ). Other than this, the same description as that of the semiconductor device 100 can be applied to the semiconductor device 101.

[0062] As shown in Figure 3 (b), the semiconductor device 190 is different from the semiconductor device 101 in the positional relationship between the p + -type cathode region and the p + -type anode region. Other than this, the same description as that of the semiconductor device 101 can be applied to the semiconductor device 190. That is, the first electrode 11r, the n + -type cathode region 31r, the p + -type cathode region 32r, the n-type buffer region 40r, the n － -type drift region 33r, the p-type anode region 34r, the p + -type anode region 35r, and the p ++Type anode region 36r and the second electrode 12r. In the semiconductor device 190, p + type anode region 35r is not located directly above the p + type cathode region 32r. The p + type anode region 35r is located directly above the n + type cathode region 31r.

[0063] Figure 4 represents the relationship between the hole current density J (A / cm 2 ) and the position Y (μm) in the depth direction. The left side of the horizontal axis corresponds to the anode side, and the right side of the horizontal axis corresponds to the cathode side. The hole current density J101 is the hole current density along the cross-section C1 - C2 of the semiconductor device 101 (refer to Figure 3 (a)). The hole current density J190 is the hole current density along the cross-section D1 - D2 of the semiconductor device 190 (refer to Figure 3 (b)). The hole current density of the semiconductor device 101 is higher than that of the semiconductor device 190.

[0064] Figure 5 (a) and Figure 5 (b) represent the time variations of the current IF (A) and the voltage VR (V) between the first and second electrodes of the semiconductor device during turn-off. The voltage V101 and the current I101 represent the characteristics of the semiconductor device 101. The voltage V190 and the current I190 represent the characteristics of the semiconductor device 190. Figure 5 (b) is Figure 5 an enlarged view of a part of Figure 5 (a). As shown in Figure 5 (a), the vibration of the voltage V101 of the semiconductor device 101 is smaller than that of the voltage V190 of the semiconductor device 190. In addition, as shown in Figure 5 (b), the vibration of the current I101 of the semiconductor device 101 is smaller than that of the current I190 of the semiconductor device 190.

[0065] As described above, in the semiconductor device 101, compared with the semiconductor device 190, the hole current density is high, and the vibration of the current and potential during turn-off can be suppressed.

[0066] In addition, when the p + type anode region 35 (and the p ++ type anode region 36) is located directly above the center 32c of the second direction D2 of each of the plurality of p + type cathode regions 32 (refer to Figure 1 ), it is considered that holes are more easily injected during turn-off, and the vibration of the potential and current can be further suppressed.

[0067] In addition, a plurality of p + -type anode regions 35 are arranged periodically in the second direction D2, and a plurality of p + -type cathode regions 32 are arranged periodically in the second direction D2. With such a periodic pattern, for example, it is easy to control the carrier density. For example, by controlling the uniformity of the carrier density, the electrical characteristics can be made more stable.

[0068] Furthermore, the pitch p35 of the plurality of p + -type anode regions 35 in the second direction D2 is a natural number multiple of the pitch p32 of the plurality of p + -type cathode regions 32 in the second direction D2. By making the periodic pattern on the cathode side match the periodic pattern on the anode side in this way, the plurality of p + -type anode regions 35 are more reliably located directly above each p + -type cathode region 32.

[0069] Figure 6 (a) to Figure 6 (d) of FIG. are schematic cross-sectional views showing simulations of the semiconductor device of the first embodiment.

[0070] In Figure 6 the semiconductor device 102 shown in (a) of FIG., the pitch p32 is 1 times the pitch p35 (see Figure 1 ). The pitch p32 is 34 μm, and the p + -type cathode width W32 (the length of one of the plurality of p + -type cathode regions 32 in the second direction D2) is 10 μm.

[0071] In Figure 6 the semiconductor device 103 shown in (b) of FIG., the pitch p32 is 2 times the pitch p35 (see Figure 1 ). The pitch p32 is 68 μm, and the p + -type cathode width W32 is 20 μm.

[0072] In Figure 6 the semiconductor device 104 shown in (c) of FIG., the pitch p32 is 3 times the pitch p35 (see Figure 1 ). The pitch p32 is 102 μm, and the p + -type cathode width W32 is 30 μm.

[0073] In Figure 6 the semiconductor device 105 shown in (d) of FIG., the pitch p32 is 6 times the pitch p35 (see Figure 1 ). The pitch p32 is 204 μm, and the p + -type cathode width W32 is 60 μm.

[0074] In addition, the same description as that of the semiconductor device 100 can be applied to the semiconductor devices 102 to 105.

[0075] Figure 7 It is a graph showing the simulation results of the semiconductor device of the first embodiment.

[0076] Figure 7 Indicates regarding Figure 6 of (a) to Figure 6 of (d), the forward voltage VF (V) in the semiconductor devices 102 to 105. That is, the voltages V102 to V105 respectively represent the forward voltage VF of the semiconductor devices 102 to 105.

[0077] As Figure 7 shown, in the semiconductor device 104 where the pitch p32 is three times the pitch p35, the forward voltage VF becomes extremely small.

[0078] Compared with the semiconductor device 104, in the semiconductor device 105 where the pitch p32 and the p + -type cathode width W32 are wide, the forward voltage VF increases. It is considered that this is because in the semiconductor device 105, the carrier density becomes low in the region above the plurality of p + -type cathode regions 32.

[0079] On the other hand, compared with the semiconductor device 104, in the semiconductor devices 102 and 103 where the pitch p32 and the p + -type cathode width W32 are narrow, the forward voltage VF also increases. It is considered that this is because in the semiconductor devices 102 and 103, the amount of carrier injection from the cathode side decreases.

[0080] From the viewpoint of the forward voltage VF, the pitch p32 is preferably 1 time or more and 6 times or less of the pitch p35, more preferably 2 times or more. In addition, the p + -type cathode width W32 is preferably 10 μm or more and 120 μm or less, more preferably 20 μm or more and 60 μm or less. In addition, for example, as Figure 6 of (a) to Figure 6 of (d) shown, the p + -type cathode width W32 is narrower than the n + -type cathode width W31 (the length of one of the plurality of n + -type cathode regions 31 in the second direction D2). The n + -type cathode width W31 is preferably 24 μm or more and 144 μm or less. Thereby, an increase in the forward voltage VF can be suppressed.

[0081] For example, if a p +-type semiconductor region, the n-type semiconductor region of the cathode decreases, so there is a case where the characteristics during conduction deteriorate (for example, the conduction voltage VF increases). In contrast, in the embodiment, the p + -type anode region 35 is located directly above each of the plurality of p + -type cathode regions 32, whereby it is easier to suppress the vibration of the potential and current. Therefore, the plurality of p + -type cathode regions 32 can be made smaller. Thereby, it is possible to suppress the deterioration of characteristics caused by providing a p + -type semiconductor region in a part of the cathode, that is, it is possible to suppress the deterioration of characteristics caused by the reduction of the n + -type semiconductor region of the cathode. +

[0082] (Modification example)

[0083] Figure 8 (a) of Figure 8 and (b) of

[0084] Figure 8 (a) of Figure 8 and (b) of Figure 2 (a) of Figure 2 and (b) of

[0085] The semiconductor device 106 of the modification example is different from the semiconductor device 101 in the planar pattern of the semiconductor region on the anode side and the planar pattern of the semiconductor region on the cathode side. Other than this, the same description as that of the semiconductor device 101 can be applied to the semiconductor device 106.

[0086] As Figure 8 shown in (a) of + , the semiconductor device 106 is also provided with a plurality of p-type anode regions 34 and a plurality of p + -type anode regions 35. In this example, one of the plurality of p + -type anode regions 35 and another of the plurality of p + -type anode regions 35 are continuous in plan view and form a substantially rectangular ring. In other words, the plurality of p + -type anode regions 35 are a part of the p

[0087] -type semiconductor region that is ring-shaped in plan view (the part extending in the third direction D3). Similarly, in this example, one of the plurality of p-type anode regions 34 and another of the plurality of p-type anode regions 34 are continuous in plan view and form a substantially rectangular ring. In other words, the plurality of p-type anode regions 34 are a part of the p-type semiconductor region that is ring-shaped in plan view (the part extending in the third direction).

[0088] A ring-shaped p-type semiconductor region including a plurality of p-type anode regions 34 and a ring-shaped p + -type semiconductor region including a plurality of p + -type anode regions 35 are arranged concentrically and alternately.

[0089] As Figure 8 shown in (b) of [], a plurality of n + -type cathode regions 31 and a plurality of p + -type cathode regions 32 are also provided in the semiconductor device 106. In this example, one of the plurality of p + -type cathode regions 32 and another of the plurality of p + -type cathode regions 32 are continuous in a plan view and form a substantially rectangular ring. In other words, the plurality of p + -type cathode regions 32 are a part of a ring-shaped p + -type semiconductor region (a part extending in the third direction D3).

[0090] Similarly, in this example, one of the plurality of n + -type cathode regions 31 and another of the plurality of n + -type cathode regions 31 are continuous in a plan view and form a substantially rectangular ring. In other words, the plurality of n + -type cathode regions 31 are a part of a ring-shaped n + -type semiconductor region (a part extending in the third direction).

[0091] A p + -type semiconductor region including a plurality of p + -type cathode regions 32 and an n + -type semiconductor region including a plurality of n + -type cathode regions 31 are arranged concentrically and alternately.

[0092] In the semiconductor device 106, the p + -type anode region 35 is also located directly above each of the plurality of p + -type cathode regions 32. Thereby, vibration of the first electrode 11 at the time of turn-off and vibration of the current flowing between the first electrode 11 and the second electrode can be suppressed. Therefore, the electrical characteristics at the time of current interruption can be improved.

[0093] (Second Embodiment)

[0094] Figure 9 is a cross-sectional view showing a semiconductor device according to the second embodiment.

[0095] The semiconductor device 200 according to the second embodiment is an RC-IGBT. As Figure 9As shown, the semiconductor device 200 includes a plurality of n + -type cathode regions 31 (first semiconductor regions), a plurality of p + -type cathode regions 32 (second semiconductor regions), an n-type buffer region 40, an n － -type drift region 33 (third semiconductor region), a plurality of p-type anode regions 34 (fourth semiconductor regions), a plurality of p + -type anode regions 35 (fifth semiconductor regions), a first electrode 11, a second electrode 12, an insulating layer 15, a p + -type collector region 37 (seventh semiconductor region), a p-type base region 38 (eighth semiconductor region), an n + -type emitter region 39 (ninth semiconductor region), and a gate electrode 24.

[0096] The plurality of n + -type cathode regions 31, the plurality of p + -type cathode regions 32, and the p + -type collector region 37 are disposed above the first electrode 11 and are electrically connected to the first electrode 11. The p + -type collector region 37 is arranged side by side with the plurality of n + -type cathode regions 31 in a direction perpendicular to the first direction D1. In the illustrated example, the p + -type collector region 37 is arranged side by side with the plurality of n + -type cathode regions 31 in the second direction D2.

[0097] A part of the n-type buffer region 40 is disposed along a first surface perpendicular to the first direction D1 around the plurality of n + -type cathode regions 31, the plurality of p + -type cathode regions 32, and the p + -type collector region 37. Another part of the n-type buffer region 40 is disposed above the plurality of n + -type cathode regions 31, the plurality of p + -type cathode regions 32, and the p + -type collector region 37.

[0098] The plurality of p-type anode regions 34 are disposed above the n － -type drift region 33 and are located above the plurality of n + -type cathode regions 31 and the plurality of p + -type cathode regions 32. The p-type base region 38 is disposed above the n － -type drift region 33 and is located above the p +Above the p-type collector region 37. The p-type base region 38 is arranged side by side with a plurality of p-type anode regions 34 in a direction perpendicular to the first direction D1. In the illustrated example, the p-type base region 38 is arranged side by side with a plurality of p-type anode regions 34 in the second direction D2. The p-type base region 38 may be separated from or continuous with the plurality of p-type anode regions 34.

[0099] n + The n-type emitter region 39 is provided above the p-type base region 38. The second electrode 12 is electrically connected to the plurality of p-type anode regions 34, the plurality of p + -type anode regions 35, the p-type base region 38, and the n + -type emitter region 39. The gate electrode 24 faces the p-type base region 38 with a gate insulating layer 24a therebetween. In the illustrated example, the gate electrode 24 faces the p-type base region 38 in a direction perpendicular to the first direction D1. The gate electrode 24 may also be provided above the p-type base region 38 and face the p-type base region 38 with the gate insulating layer 24a therebetween in the first direction D1. The gate electrode 24 is electrically separated from the second electrode 12.

[0100] The semiconductor device 200 includes a diode region R1 and an IGBT region R2. A plurality of n + -type cathode regions 31, a plurality of p + -type cathode regions 32, a plurality of p-type anode regions 34, and a plurality of p + -type anode regions 35 are provided in the diode region R1. The p + -type collector region 37, the p-type base region 38, the n + -type emitter region 39, and the gate electrode 24 are provided in the IGBT region R2. In the semiconductor device 200, one diode region R1 and one IGBT region R2 are provided.

[0101] In the semiconductor device 200, the p + -type anode regions 35 are also located directly above the respective p + -type cathode regions 32. Thereby, vibration of the first electrode 11 during turn-off and vibration of the current flowing between the first electrode 11 and the second electrode can be suppressed. Therefore, the electrical characteristics during current interruption can be improved.

[0102] Regarding the relative magnitudes of the impurity concentrations between the respective semiconductor regions in the above-described embodiments, for example, SCM (Scanning Capacitance Microscopy) can be used to confirm. Additionally, the carrier concentration in each semiconductor region can be regarded as being equal to the impurity concentration activated in each semiconductor region. Thus, regarding the relative magnitudes of the carrier concentrations between the respective semiconductor regions, SCM can also be used to confirm. Furthermore, regarding the impurity concentration in each semiconductor region, for example, it can be measured by SIMS (Secondary Ion Mass Spectrometry).

[0103] As described above, several embodiments of the present invention have been illustrated, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other forms, and various omissions, substitutions, changes, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope or gist of the invention and are included in the invention described in the claims and its equivalent scope. Additionally, the above-described embodiments can be implemented in combination with each other.

Claims

1. A semiconductor device having: A first electrode; A plurality of first semiconductor regions of a first conductivity type, disposed above the first electrode; A plurality of second semiconductor regions of a second conductivity type, disposed above the first electrode, arranged side by side with the plurality of first semiconductor regions in a second direction perpendicular to a first direction from the first electrode toward the plurality of first semiconductor regions, and extending in a third direction perpendicular to the first direction and the second direction; A third semiconductor region of a first conductivity type, disposed above the first semiconductor region and the plurality of second semiconductor regions, having a first conductivity type impurity concentration lower than that of the first semiconductor region; A plurality of fourth semiconductor regions of a second conductivity type, disposed above the third semiconductor region; A plurality of fifth semiconductor regions of a second conductivity type, disposed above the third semiconductor region, arranged side by side with the plurality of fourth semiconductor regions in the second direction, and extending in the third direction, having a second conductivity type impurity concentration higher than that of the plurality of fourth semiconductor regions, and at least a part thereof is located directly above each of the plurality of second semiconductor regions; And A second electrode, disposed above the plurality of fourth semiconductor regions and the plurality of fifth semiconductor regions, The width of the fifth semiconductor region in the second direction is narrower than the width of the second semiconductor region in the second direction, The pitch of the plurality of second semiconductor regions in the second direction is a natural number multiple of the pitch of the plurality of fifth semiconductor regions in the second direction.

2. The semiconductor device according to claim 1, The fifth semiconductor region is located directly above the center of the second semiconductor region in the second direction.

3. The semiconductor device according to claim 1 or 2, The plurality of second semiconductor regions are periodically arranged in the second direction, The plurality of fifth semiconductor regions are periodically arranged in the second direction.

4. The semiconductor device according to claim 1, The pitch of the plurality of second semiconductor regions in the second direction is 1 times or more and 6 times or less the pitch of the plurality of fifth semiconductor regions in the second direction.

5. The semiconductor device according to claim 1 or 2, The length of one of the plurality of second semiconductor regions in the second direction is 20 μm or more and 120 μm or less.

6. The semiconductor device according to claim 1 or 2, The length of one of the plurality of first semiconductor regions in the second direction is 24 μm or more and 144 μm or less.

7. The semiconductor device according to claim 1 or 2, The lower ends of the plurality of fifth semiconductor regions are located at positions lower than those of the plurality of fourth semiconductor regions.

8. The semiconductor device according to claim 1 or 2, Further having a plurality of sixth semiconductor regions of a second conductivity type, the plurality of sixth semiconductor regions being disposed above the plurality of fifth semiconductor regions and having a second conductivity type impurity concentration higher than that of the plurality of fifth semiconductor regions, At least a part of the plurality of sixth semiconductor regions is located directly above each of the plurality of second semiconductor regions.

9. The semiconductor device according to claim 1 or 2, further comprising: a seventh semiconductor region of a second conductivity type, disposed above the first electrode and electrically connected to the first electrode, an eighth semiconductor region of a second conductivity type, disposed above the third semiconductor region, located above the seventh semiconductor region, and electrically connected to the second electrode, a ninth semiconductor region of a first conductivity type, disposed above the eighth semiconductor region; and a gate electrode, facing the eighth semiconductor region with a gate insulating layer therebetween.

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