Magnetic random access memory and method of forming the same

Abstract

A magnetic random access memory and a method for forming the same include: providing a substrate; forming a first dielectric layer on the substrate, wherein the first dielectric layer has a first opening; forming a first conductive structure and a second conductive structure in the first opening; and forming a magnetic tunnel junction on the first dielectric layer and the second conductive structure. By forming the first conductive structure and the second conductive structure in the first opening, the material of the second conductive structure is different from that of the first conductive structure. Since the first conductive structure can be formed at a relatively high height, the height of the correspondingly formed first dielectric layer is also relatively high, thereby avoiding etching from penetrating the first dielectric layer during the formation of the magnetic tunnel junction; and since the material hardness of the second conductive structure is relatively high, after being planarized, the top surface of the second conductive structure is relatively flat, thereby ensuring that the magnetic tunnel junction formed on the second conductive structure will not be deformed, thereby improving the performance of the magnetic random access memory finally formed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a magnetic random access memory and a forming method thereof. Background Art

[0002] Magnetic random access memory is a non-volatile memory technology that is being widely accepted by the industry as a mainstream data storage technology. It integrates a magnetoresistive device and a silicon-based selection matrix. Key attributes are non-volatility, low voltage operation, unlimited read and write endurance, fast read and write operations, and easy integration as a back-end technology. These characteristics make magnetic random access memory a potential replacement for many types of memory in various applications.

[0003] Magnetic random access memory stores "1" and "0" data through magnetic tunnel junction (MTJ) elements. The basic structure of a magnetic tunnel junction element is a structure in which an insulating layer (i.e., a tunnel barrier) is sandwiched between two strong magnetic layers. The data stored in the MTJ element is determined by whether the magnetization states of the two magnetic layers are parallel or antiparallel. In this case, parallel means that the magnetization directions of the two magnetic layers are the same, and antiparallel means that the magnetization directions of the two magnetic layers are opposite.

[0004] However, the performance of existing magnetic random access memory needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a magnetic random access memory and a method for forming the same, which can effectively improve the performance of the magnetic random access memory finally formed.

[0006] To solve the above problems, the present invention provides a magnetic random access memory, including a substrate; a first dielectric layer located on the substrate, the first dielectric layer having a first opening, the first opening including a first area and a second area located on the first area; a first conductive structure located in the first area; a second conductive structure located in the second area, the material of the second conductive structure being different from that of the first conductive structure; a magnetic tunnel junction located on the first dielectric layer and the second conductive structure; and a top electrode located on the magnetic tunnel junction.

[0007] Optionally, the material hardness of the second conductive structure is greater than the material hardness of the first conductive structure.

[0008] Optionally, the material of the first conductive structure includes: copper or cobalt.

[0009] Optionally, a material of the second conductive structure includes tantalum, tantalum nitride, titanium or titanium nitride.

[0010] Optionally, it further includes: a barrier layer located on the sidewalls and top surface of the first opening, and the first conductive structure and the second conductive structure are respectively located on the barrier layer.

[0011] Optionally, the material of the barrier layer includes: tantalum, tantalum nitride, titanium or titanium nitride.

[0012] Optionally, the aspect ratio of the second region of the first opening is 0.5:1 to 1.5:1.

[0013] Optionally, a portion of the top surface of the first dielectric layer is lower than a top surface of the second conductive structure.

[0014] Optionally, the magnetic tunnel junction includes: a buffer layer; a fixed layer located on the buffer layer; an insulating layer located on the fixed layer; a free layer located on the insulating layer; and a covering layer located on the free layer.

[0015] Optionally, it also includes: a stop layer located on the side wall surface of the magnetic tunnel junction, the top surface of the top electrode and the side wall surface.

[0016] Optionally, the method further includes: an isolation structure located on the surface of the stop layer; and a conductive plug located in the isolation structure, wherein the conductive plug is in contact with the top electrode.

[0017] Optionally, the substrate includes: a base and a device layer located on the base; the device layer includes a device structure and a second dielectric layer surrounding the device structure, the device structure includes a transistor, a resistor, an inductor, a capacitor or a conductive structure; the first conductive structure is electrically connected to the device structure.

[0018] Correspondingly, the present invention also provides a method for forming a magnetic random access memory, comprising: providing a substrate; forming a first dielectric layer on the substrate, wherein the first dielectric layer has a first opening, and the first opening includes a first region and a second region located on the first region; forming a first conductive structure in the first region; forming a second conductive structure in the second region, and the material of the second conductive structure is different from that of the first conductive structure; forming a magnetic tunnel junction on the first dielectric layer and the second conductive structure; and forming a top electrode on the magnetic tunnel junction.

[0019] Optionally, the material hardness of the second conductive structure is greater than the material hardness of the first conductive structure.

[0020] Optionally, the material of the first conductive structure includes: copper or cobalt.

[0021] Optionally, the material of the second conductive structure includes: tantalum, tantalum nitride, titanium or titanium nitride.

[0022] Optionally, after forming the top electrode, it also includes: forming a stop layer on the side wall surface of the magnetic tunnel junction, the top surface of the top electrode and the side wall surface; forming an isolation structure on the surface of the stop layer; forming a conductive plug in the isolation structure, wherein the conductive plug contacts the top electrode.

[0023] Optionally, before forming the first conductive structure, the method further includes: forming a barrier layer on a surface of the first opening, wherein the first conductive structure and the second conductive structure are respectively located on the barrier layer.

[0024] Optionally, the material of the barrier layer includes: tantalum, tantalum nitride, titanium or titanium nitride.

[0025] Optionally, the method for forming the barrier layer includes: forming an initial barrier layer on the surface of the first opening and the top surface of the first dielectric layer; and planarizing the barrier layer until the top surface of the first dielectric layer is exposed to form the barrier layer.

[0026] Optionally, the process for forming the initial barrier layer includes an atomic layer deposition process.

[0027] Optionally, the method for forming the first conductive structure includes: forming a first initial conductive structure on the surface of the initial barrier layer; and performing annealing and reflow treatment on the first initial conductive structure to form the first conductive structure, wherein the first conductive structure is located in the first region.

[0028] Optionally, the parameters of the annealing reflow treatment include: annealing time 20s to 200s; annealing temperature 200°C to 400°C.

[0029] Optionally, the method for forming the second conductive structure includes: forming a second initial conductive structure on the first conductive structure and on the surface of the initial barrier layer; planarizing the second initial conductive structure until the top surface of the first dielectric layer is exposed to form the second conductive structure, wherein the second conductive structure is located in the second region.

[0030] Optionally, the formation process of the second initial conductive structure includes a physical vapor deposition process.

[0031] Optionally, the aspect ratio of the second region of the first opening is 0.5:1 to 1.5:1.

[0032] Optionally, the process of planarizing the initial barrier layer includes a chemical mechanical polishing process; and the process of planarizing the second initial conductive structure includes a chemical mechanical polishing process.

[0033] Optionally, the method for forming the magnetic tunnel junction and the top electrode includes: forming a buffer material layer on the second conductive structure and the first dielectric layer; forming a fixed material layer on the buffer material layer; forming an insulating material layer on the fixed material layer; forming a free material layer on the insulating material layer; forming a covering material layer on the free material layer; forming a top electrode material layer on the covering material layer; forming a patterned mask layer on the top electrode material layer, wherein the patterned mask layer exposes a portion of the top surface of the top electrode material layer; and etching the top electrode material layer, the covering material layer, the free material layer, the insulating material layer, the fixed material layer and the buffer material layer using the patterned mask layer as a mask to form the magnetic tunnel junction and the top electrode.

[0034] Optionally, in the process of etching the top electrode material layer, the covering material layer, the free material layer, the insulating material layer, the fixed material layer and the buffer material layer using the patterned mask layer as a mask, it also includes: etching and removing a portion of the first dielectric layer, wherein a portion of the top surface of the first dielectric layer is lower than the top surface of the second conductive structure.

[0035] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0036] In the structure of the technical solution of the present invention, through the first conductive structure located in the first area, the second conductive structure located in the second area, the material of the second conductive structure is different from the material of the first conductive structure. Since the first conductive structure has good filling properties, the first conductive structure can be formed at a higher height, and the height of the corresponding first dielectric layer is also higher, thereby avoiding that etching will penetrate the first dielectric layer in the subsequent process of forming the magnetic tunnel junction, thereby damaging the device layer in the substrate; and the material hardness of the second conductive structure is relatively large. After the planarization treatment, the top surface of the second conductive structure is relatively flat, ensuring that the magnetic tunnel junction located on the second conductive structure will not be deformed, thereby improving the performance of the magnetic random access memory finally formed.

[0037] In the formation method of the technical solution of the present invention, a first conductive structure is formed in the first area, and a second conductive structure is formed in the second area, and the material of the second conductive structure is different from that of the first conductive structure. Since the first conductive structure has good filling properties, the first conductive structure can be formed at a higher height, and the height of the corresponding first dielectric layer is also higher, thereby avoiding that etching will penetrate the first dielectric layer in the subsequent formation of the magnetic tunnel junction, thereby damaging the device layer in the substrate; and the material hardness of the second conductive structure is relatively large. After the planarization treatment, the top surface of the second conductive structure is relatively flat, ensuring that the magnetic tunnel junction formed on the second conductive structure will not be deformed, thereby improving the performance of the magnetic random access memory finally formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of the structure of a magnetic random access memory;

[0039] Figure 2 is a schematic diagram of the structure of another magnetic random access memory;

[0040] Figures 3 to 11 It is a schematic structural diagram of each step of an embodiment of a method for forming a magnetic random access memory of the present invention. DETAILED DESCRIPTION

[0041] As described in the background art, the performance of existing magnetic random access memory still needs to be improved.

[0042] Please refer to Figure 1 , providing a substrate 100; forming a first dielectric layer 101 on the substrate 100, wherein the first dielectric layer 101 has a first opening (not shown); forming a first conductive structure 102 in the first opening; forming a magnetic tunnel junction 103 on the first dielectric layer 101 and the first conductive structure 102; and forming a top electrode 104 on the magnetic tunnel junction 103.

[0043] In this embodiment, the material of the first conductive structure 102 is copper. During the formation of the first conductive structure 102, a chemical mechanical polishing (CMP) process is required. Since the hardness of the copper material is relatively low, a concave (e.g., Figure 1 As shown in area A, since the thickness of the magnetic tunnel junction 103 is relatively small, the magnetic tunnel junction 103 formed on the first conductive structure 102 having a depression may also be deformed, thereby reducing the performance of the magnetic random access memory finally formed.

[0044] In order to solve the above problems, a magnetic random access memory is also provided, which will be described in detail below with reference to the accompanying drawings.

[0045] Please refer to Figure 2 , providing a substrate 200; forming a first dielectric layer 201 on the substrate 200, wherein the first dielectric layer 201 has a first opening (not shown); forming a second conductive structure 202 in the first opening; forming a magnetic tunnel junction 203 on the first dielectric layer 201 and the second conductive structure 202; and forming a top electrode 204 on the magnetic tunnel junction 203.

[0046] In this embodiment, the material of the second conductive structure 202 is tantalum, tantalum nitride, titanium or titanium nitride. These materials have high hardness. Therefore, after the second conductive structure 202 is subjected to chemical mechanical polishing (CMP) treatment, the top surface of the second conductive structure 202 is relatively flat, and the subsequently formed magnetic tunnel junction 203 will not be deformed, thereby improving the performance of the finally formed magnetic random access memory.

[0047] However, the process of forming the second conductive structure 202 in the first opening is a physical vapor deposition process (PVD), and the physical vapor deposition process has certain requirements for the depth-to-width ratio of the first opening. When the depth-to-width ratio of the first opening is large, it is difficult to fill the material of the second conductive structure 202 using the physical vapor deposition process. Therefore, in order to ensure that the material of the second conductive structure 202 can be filled into the first opening, it is necessary to reduce the height of the first opening, and the height direction is the direction perpendicular to the top surface of the substrate 200, so as to increase the depth-to-width ratio of the first opening. When the height of the first opening is reduced, the height of the corresponding second conductive structure 202 is also reduced. In the subsequent process of forming the magnetic tunnel junction, the magnetic tunnel junction needs to be etched. In the process of etching, the first dielectric layer 201 will be damaged. Since the height of the second conductive structure 202 is reduced, the corresponding height of the first dielectric layer 201 is also reduced. Therefore, in the process of etching the magnetic tunnel junction, it is easy to etch through the first dielectric layer 201, thereby damaging the device layer located in the substrate 200, so that the performance of the magnetic random access memory formed in the end is reduced.

[0048] On this basis, the present invention provides a magnetic random access memory and a method for forming the same, by forming a first conductive structure in the first region and a second conductive structure in the second region, wherein the material of the second conductive structure is different from that of the first conductive structure. Since the first conductive structure has good filling properties, the first conductive structure can be formed at a higher height, and the height of the corresponding first dielectric layer is also higher, thereby avoiding that etching will penetrate the first dielectric layer in the subsequent formation of the magnetic tunnel junction, thereby damaging the device layer in the substrate; and the material hardness of the second conductive structure is relatively high, and after the planarization treatment, the top surface of the second conductive structure is relatively flat, ensuring that the magnetic tunnel junction formed on the second conductive structure will not be deformed, thereby improving the performance of the magnetic random access memory finally formed.

[0049] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0050] Figures 3 to 11 It is a structural schematic diagram of a formation process of a magnetic random access memory according to an embodiment of the present invention.

[0051] Please refer to Figure 3 , providing a substrate.

[0052] In this embodiment, the substrate includes: a base 300 and a device layer located on the base 300; the device layer includes a device structure (not shown) and a second dielectric layer 301 surrounding the device structure, and the device structure includes a transistor, a resistor, an inductor, a capacitor or a conductive structure.

[0053] In this embodiment, the device structure includes a transistor.

[0054] The material of the substrate 300 includes silicon, silicon germanium, germanium, silicon on insulator or germanium on insulator. The material of the second dielectric layer 301 includes silicon oxide or silicon nitride.

[0055] In this embodiment, the material of the substrate 300 includes silicon. The material of the second dielectric layer 301 includes silicon oxide.

[0056] Please refer to Figure 4 A first dielectric layer 302 is formed on the substrate. The first dielectric layer 302 has a first opening 303 therein. The first opening 303 includes a first region I and a second region II located on the first region I.

[0057] In this embodiment, the method for forming the first opening 303 includes: forming a dielectric material layer (not shown) on the substrate; planarizing the dielectric material layer to form a first dielectric layer 302; forming a patterned layer (not shown) on the first dielectric layer 302, wherein the patterned layer exposes a portion of the surface of the first dielectric layer 302; etching the first dielectric layer 302 using the patterned layer as a mask until the substrate surface is exposed, thereby forming a first opening 303 in the first dielectric layer 302.

[0058] The material of the first dielectric layer 302 includes silicon oxide, silicon oxycarbide, carbon silicon oxyhydride, silicon nitride or silicon oxynitride; the process of forming the dielectric material layer includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process; the process of planarizing the dielectric material layer includes a chemical mechanical polishing process or a back etching process; the process of etching the first dielectric layer 302 includes a dry etching process or a wet etching process.

[0059] In this embodiment, the material of the first dielectric layer 302 includes silicon oxide; the process of forming the dielectric material layer includes a chemical vapor deposition process, and the chemical vapor deposition process can quickly form a dielectric material layer with a dense structure and a thick thickness; the process of planarizing the dielectric material layer includes a chemical mechanical polishing process; and the process of etching the first dielectric layer 302 includes a dry etching process.

[0060] In this embodiment, the first opening 303 is used to subsequently form a first conductive structure and a second conductive structure in the first opening 303 , wherein the first conductive structure is located in the first region I and the second conductive structure is located in the second region II. The first conductive structure is electrically connected to the substrate exposed by the first opening 303 .

[0061] Since the second conductive structure formed subsequently is formed by a physical vapor deposition process, the physical vapor deposition process has a certain range requirement for the aspect ratio of the first opening 303 .

[0062] In this embodiment, the aspect ratio of the second region II of the first opening 303 is 0.5:1 to 1.5:1.

[0063] After forming the first opening 303, the method further includes: forming a barrier layer on the surface of the first opening 303; forming a first conductive structure in the first region I; forming a second conductive structure in the second region II, wherein the material of the second conductive structure is different from that of the first conductive structure, and the first conductive structure and the second conductive structure are respectively located on the barrier layer. For the specific formation process of the barrier layer, the first conductive structure and the second conductive structure, please refer to Figures 5 to 7 .

[0064] Please refer to Figure 5 An initial blocking layer 304 is formed on a surface of the first opening 303 and a top surface of the first dielectric layer 302 .

[0065] In this embodiment, the formation process of the initial barrier layer 304 includes an atomic layer deposition process.

[0066] Please refer to Figure 6 , forming a first initial conductive structure (not shown) on the surface of the initial barrier layer 304; performing annealing and reflow treatment on the first initial conductive structure to form the first conductive structure 305, and the first conductive structure 305 is located in the first region I.

[0067] In this embodiment, the parameters of the annealing reflow treatment include: annealing time 20s-200s; annealing temperature 200°C-400°C.

[0068] In this embodiment, according to the depth of the first region I, the first conductive structure 305 may be formed by depositing the first initial conductive structure multiple times and performing annealing and reflow treatment until the first conductive structure 305 fills the first region I of the first opening 303 .

[0069] Please refer to Figure 7 , a second initial conductive structure (not shown) is formed on the first conductive structure 305 and the surface of the initial barrier layer 304; the second initial conductive structure is planarized until the top surface of the first dielectric layer 302 is exposed, to form the barrier layer 306 and the second conductive structure 307, and the second conductive structure 307 is located in the second region II.

[0070] The material of the second conductive structure 307 is different from that of the first conductive structure 305 , and the material hardness of the second conductive structure 307 is greater than the material hardness of the first conductive structure 305 .

[0071] In this embodiment, the material of the first conductive structure 305 is copper; in other embodiments, the material of the first conductive structure may also be cobalt.

[0072] In this embodiment, the material of the second conductive structure 307 is tantalum nitride; in other embodiments, the material of the second conductive structure may also be tantalum, titanium or titanium nitride.

[0073] In this embodiment, the second initial conductive structure is formed by a physical vapor deposition process.

[0074] In this embodiment, the material of the barrier layer 306 is tantalum nitride; in other embodiments, the material of the barrier layer may also be tantalum, titanium or titanium nitride.

[0075] In this embodiment, the process of planarizing the initial barrier layer 304 is a chemical mechanical polishing process; and the process of planarizing the second initial conductive structure is a chemical mechanical polishing process.

[0076] In this embodiment, the initial barrier layer 304 and the second initial conductive structure are planarized using the same chemical mechanical polishing process, which can effectively reduce the number of process steps and improve production efficiency.

[0077] The first conductive structure 305 is formed in the first region I, and the second conductive structure 307 is formed in the second region II, wherein the material of the second conductive structure 307 is different from that of the first conductive structure 305. Since the first conductive structure 305 is formed by a deposition and annealing reflow process, which has good filling properties, the first conductive structure 305 can be formed to a higher height, and the height of the correspondingly formed first dielectric layer 302 is also higher, thereby preventing etching from penetrating the first dielectric layer 302 in the subsequent process of forming the magnetic tunnel junction, thereby damaging the device layer in the substrate.

[0078] In addition, the material hardness of the second conductive structure 307 is relatively large. Since the chemical mechanical polishing process is a processing technology that combines chemical corrosion and mechanical removal, the material with a higher hardness has a weaker deformation ability. Therefore, after the planarization treatment using the chemical mechanical polishing process, the second conductive structure 307 will not produce a large deformation due to the application of mechanical force, thereby making the top surface of the second conductive structure 307 relatively flat, ensuring that the magnetic tunnel junction formed on the second conductive structure 307 will not be deformed, thereby improving the performance of the magnetic random access memory finally formed.

[0079] After forming the second conductive structure 307, the method further includes: forming a magnetic tunnel junction on the first dielectric layer 302 and the second conductive structure 307; and forming a top electrode on the magnetic tunnel junction. For details on the formation of the magnetic tunnel junction and the top electrode, please refer to Figures 8 to 9 .

[0080] Please refer to Figure 8, a buffer material layer 308 is formed on the second conductive structure 307 and the first dielectric layer 302; a fixed material layer 309 is formed on the buffer material layer 308; an insulating material layer 310 is formed on the fixed material layer 309; a free material layer 311 is formed on the insulating material layer 310; a covering material layer 312 is formed on the free material layer 311; a top electrode material layer 313 is formed on the covering material layer 312; a patterned mask layer 314 is formed on the top electrode material layer 313, and the patterned mask layer 314 exposes a portion of the top surface of the top electrode material layer 313.

[0081] The buffer material layer 308 provides a material layer for forming a buffer layer; the fixed material layer 309 provides a material layer for forming a fixed layer; the insulating material layer 310 provides a material layer for forming an insulating layer; the free material layer 311 provides a material layer for forming a free layer; the covering material layer 312 provides a material layer for forming a covering layer; and the top electrode material layer 313 provides a material layer for forming a top electrode.

[0082] The material of the buffer material layer 308 includes ruthenium, cobalt or platinum; the material of the fixed material layer 309 includes ferromagnetic material, and the ferromagnetic material includes cobalt iron boron, cobalt iron, nickel iron or cobalt iron nickel; the material of the insulating material layer 310 includes magnesium oxide or aluminum oxide; the material of the free material layer 311 includes ferromagnetic material, and the ferromagnetic material includes cobalt iron boron, cobalt iron, nickel iron or cobalt iron nickel; the material of the covering material layer 312 includes magnesium oxide, tantalum or tungsten; the material of the top electrode material layer 313 includes metal, and the metal includes tantalum nitride, titanium nitride, tantalum or titanium; the material of the patterned mask layer 314 includes photoresist or hard mask material, and the hard mask material includes silicon oxide or silicon nitride.

[0083] In this embodiment, the material of the buffer material layer 308 includes ruthenium; the material of the fixed material layer 309 includes cobalt iron boron; the material of the insulating material layer 310 includes magnesium oxide; the material of the free material layer 311 includes cobalt iron boron; the material of the covering material layer 312 includes magnesium oxide; the material of the top electrode material layer 313 includes tantalum nitride; and the material of the patterned mask layer 314 includes photoresist.

[0084] In this embodiment, the pattern of the second conductive structure 307 projected onto the substrate is within the range of the pattern of the patterned mask layer 314 projected onto the substrate, thereby ensuring that the top of the second conductive structure 307 will not be damaged during the subsequent etching of the buffer material layer 308, the fixed material layer 309, the insulating material layer 310, and the free material layer 311 including cobalt iron boron and the covering material layer 312.

[0085] Please refer to Fig. 9 , using the patterned mask layer 314 as a mask, the top electrode material layer 313 , the covering material layer 312 , the free material layer 311 , the insulating material layer 310 , the fixed material layer 309 and the buffer material layer 308 are etched to form the magnetic tunnel junction and the top electrode 315 .

[0086] In this embodiment, the magnetic tunnel junction includes: a buffer layer 316 ; a fixed layer 317 located on the buffer layer 316 ; an insulating layer 318 located on the fixed layer 317 ; a free layer 319 located on the insulating layer 318 ; and a capping layer 320 located on the free layer 319 .

[0087] At this time, since the top surface of the second conductive structure 307 is relatively flat, the magnetic tunnel junction formed on the second conductive structure 307 will not be deformed, which effectively improves the performance of the magnetic random access memory finally formed.

[0088] In this embodiment, during the process of etching to form the magnetic tunnel junction, the etching process also removes a portion of the first dielectric layer 302 , and a portion of the top surface of the first dielectric layer 302 is lower than the top surface of the second conductive structure 307 .

[0089] At this time, since the first conductive structure 305 has good filling properties, the first conductive structure can be formed at a higher height, and the height of the corresponding first dielectric layer 302 is also higher, thereby avoiding etching penetrating the first dielectric layer 302 during the formation of the magnetic tunnel junction, thereby damaging the device layer in the substrate.

[0090] The process of etching the top electrode material layer 313 , the cover material layer 312 , the free material layer 311 , the insulating material layer 310 , the fixed material layer 309 and the buffer material layer 308 includes a dry etching process or a wet etching process.

[0091] In this embodiment, the process of etching the top electrode material layer 313, the covering material layer 312, the free material layer 311, the insulating material layer 310, the fixed material layer 309 and the buffer material layer 308 adopts a dry etching process, and the dry etching process can form a magnetic tunnel junction with better sidewall morphology.

[0092] After forming the magnetic tunnel junction, the process of removing the patterned mask layer 314 includes an ashing process.

[0093] Please refer to Fig.10 After the magnetic tunnel junction is formed, a stop layer 321 is formed on the sidewall surface of the magnetic tunnel junction, the top surface of the top electrode 315, and the sidewall surface.

[0094] The stop layer 321 is also located on a portion of the surface extending to the first dielectric layer 302 .

[0095] The stop layer 321 is used as an etching stop layer when a conductive plug is subsequently formed on the top electrode 315. The formation process of the stop layer 321 includes an atomic layer deposition process or a chemical vapor deposition process; the material of the stop layer 321 includes silicon nitride, silicon carbide or silicon carbide nitride.

[0096] In this embodiment, the formation process of the stop layer 321 includes an atomic layer deposition process; the material of the stop layer 321 includes silicon nitride.

[0097] Please refer to Fig.11 , an isolation structure 322 is formed on the surface of the stop layer 321 ; a conductive plug 323 is formed in the isolation structure 322 , and the conductive plug 323 is electrically connected to the top electrode 315 .

[0098] The material of the isolation structure 322 includes silicon oxide, silicon oxycarbide, silicon oxycarbon hydride, silicon nitride or silicon oxynitride; the process of forming the isolation structure 322 includes chemical vapor deposition process, physical vapor deposition process or atomic layer deposition process.

[0099] In the present embodiment, the material of the isolation structure 322 includes silicon oxide; the process of forming the isolation structure 322 includes a chemical vapor deposition process, and the chemical vapor deposition process can quickly form an isolation structure 322 with a dense structure and a relatively thick thickness.

[0100] The method for forming the conductive plug 323 includes: forming a mask layer (not shown) on the surface of the isolation structure 322, wherein the mask layer exposes a portion of the surface of the isolation structure 322; etching the isolation structure 322 and the stop layer 321 using the mask layer as a mask until the surface of the top electrode 315 is exposed, thereby forming a second opening (not shown) in the isolation structure 322; forming a conductive plug material layer (not shown) in the second opening and on the surface of the isolation structure 322; and planarizing the conductive plug material layer until the surface of the isolation structure 322 is exposed, thereby forming the conductive plug 323.

[0101] The conductive plug 323 is used to electrically connect the magnetic random access memory to an external device or conductive structure. The material of the conductive plug 323 includes a combination of one or more of copper, tungsten, titanium and titanium nitride; the process of forming the conductive plug material layer includes a physical vapor deposition process, a chemical vapor deposition process or an electroplating process; the process of etching the isolation structure 322 and the stop layer 321 includes a dry etching process or a wet etching process; the process of planarizing the conductive plug material layer includes a chemical mechanical polishing process or a back etching process.

[0102] In this embodiment, the material of the conductive plug 323 includes copper; the process of forming the conductive plug material layer includes a physical vapor deposition process; the process of etching the isolation structure 322 and the stop layer 321 includes a dry etching process; and the process of planarizing the conductive plug material layer includes a chemical mechanical polishing process.

[0103] Accordingly, the embodiment of the present invention also provides a magnetic random access memory, please continue to refer to Fig.11 , including: a substrate; a first dielectric layer 302 located on the substrate, the first dielectric layer 302 having a first opening (not marked), the first opening including a first region I and a second region II located on the first region I; a first conductive structure 305 located in the first region I; a second conductive structure 307 located in the second region II, the material of the second conductive structure 307 being different from that of the first conductive structure 305; a magnetic tunnel junction located on the first dielectric layer 302 and the second conductive structure 307; and a top electrode 315 located on the magnetic tunnel junction.

[0104] In this embodiment, the material hardness of the second conductive structure 307 is greater than the material hardness of the first conductive structure 305 .

[0105] In this embodiment, the material of the first conductive structure 305 is copper; in other embodiments, the material of the first conductive structure may also be cobalt.

[0106] In this embodiment, the material of the second conductive structure 307 is tantalum nitride; in other embodiments, the material of the second conductive structure may also be tantalum, titanium or titanium nitride.

[0107] In this embodiment, the present invention further includes: a barrier layer 306 located on the sidewalls and top surface of the first opening, and the first conductive structure 305 and the second conductive structure 307 are respectively located on the barrier layer 306 .

[0108] In this embodiment, the material of the barrier layer 306 is tantalum nitride; in other embodiments, the material of the barrier layer may also be tantalum, titanium or titanium nitride.

[0109] In this embodiment, the aspect ratio of the second region II of the first opening is 0.5:1 to 1.5:1.

[0110] In this embodiment, a portion of the top surface of the first dielectric layer 302 is lower than the top surface of the second conductive structure 307 .

[0111] In this embodiment, the magnetic tunnel junction includes: a buffer layer 316 ; a fixed layer 317 located on the buffer layer 316 ; an insulating layer 318 located on the fixed layer 317 ; a free layer 319 located on the insulating layer 318 ; and a capping layer 320 located on the free layer 319 .

[0112] In this embodiment, it further includes: a stop layer 321 located on the side wall surface of the magnetic tunnel junction, the top surface and the side wall surface of the top electrode 315 .

[0113] In this embodiment, the structure further includes: an isolation structure 322 located on the surface of the stop layer 321 ; and a conductive plug 323 located in the isolation structure 322 , wherein the conductive plug 323 is in contact with the top electrode 315 .

[0114] In this embodiment, the substrate includes: a base 300 and a device layer located on the base 300; the device layer includes a device structure and a second dielectric layer 301 surrounding the device structure, the device structure includes a transistor, a resistor, an inductor, a capacitor or a conductive structure; the first conductive structure 305 is electrically connected to the device structure.

[0115] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A magnetic random access memory, characterized in that: include: substrate; A first dielectric layer located on the substrate, wherein the first dielectric layer has a first opening, and the first opening includes a first region and a second region located on the first region; a first conductive structure located in the first region; a second conductive structure located in the second region, wherein the material of the second conductive structure is different from the material of the first conductive structure, the material filling property of the first conductive structure is greater than the material filling property of the second conductive structure, the material hardness of the second conductive structure is greater than the material hardness of the first conductive structure, and the surface flatness of the second conductive structure after planarization by a chemical mechanical polishing process is greater than the surface flatness of the first conductive structure after planarization by a chemical mechanical polishing process; a magnetic tunnel junction located on the first dielectric layer and the second conductive structure, wherein a portion of the top surface of the first dielectric layer is lower than a top surface of the second conductive structure; A top electrode is located on the magnetic tunnel junction.

2. The magnetic random access memory according to claim 1, wherein: The material of the first conductive structure includes copper or cobalt.

3. The magnetic random access memory according to claim 1, wherein: The material of the second conductive structure includes: tantalum, tantalum nitride, titanium or titanium nitride.

4. The magnetic random access memory according to claim 1, wherein: Also includes: A barrier layer is located on the sidewalls and top surface of the first opening, and the first conductive structure and the second conductive structure are respectively located on the barrier layer.

5. The magnetic random access memory according to claim 4, characterized in that: The material of the barrier layer includes: tantalum, tantalum nitride, titanium or titanium nitride.

6. The magnetic random access memory according to claim 1, wherein: The second area of ​​the first opening has a depth-to-width ratio of 0.5:1 to 1.5:

1.

7. The magnetic random access memory according to claim 1, wherein: The magnetic tunnel junction includes: a buffer layer; a fixed layer located on the buffer layer; an insulating layer located on the fixed layer; a free layer located on the insulating layer; and a covering layer located on the free layer.

8. The magnetic random access memory according to claim 1, wherein: Also includes: A stop layer is located on the side wall surface of the magnetic tunnel junction, the top surface of the top electrode and the side wall surface.

9. The magnetic random access memory according to claim 8, characterized in that: Also includes: an isolation structure located on a surface of the stop layer; A conductive plug is located within the isolation structure, the conductive plug contacting the top electrode.

10. The magnetic random access memory according to claim 1, wherein: The substrate comprises: a base and a device layer located on the base; the device layer comprises a device structure and a second dielectric layer surrounding the device structure, the device structure comprises a transistor, a resistor, an inductor, a capacitor or a conductive structure; the first conductive structure is electrically connected to the device structure.

11. A method for forming a magnetic random access memory, characterized in that: include: providing a substrate; forming a first dielectric layer on the substrate, wherein the first dielectric layer has a first opening, and the first opening includes a first region and a second region located on the first region; forming a first conductive structure in the first region; A second conductive structure is formed in the second region, wherein the material of the second conductive structure is different from the material of the first conductive structure, the material filling property of the first conductive structure is greater than the material filling property of the second conductive structure, the material hardness of the second conductive structure is greater than the material hardness of the first conductive structure, and the surface flatness of the second conductive structure after planarization by a chemical mechanical polishing process is greater than the surface flatness of the first conductive structure after planarization by a chemical mechanical polishing process; forming a magnetic tunnel junction on the first dielectric layer and the second conductive structure, and etching and removing a portion of the first dielectric layer during the process of forming the magnetic tunnel junction, so that a portion of the top surface of the first dielectric layer is lower than a top surface of the second conductive structure; A top electrode is formed on the magnetic tunnel junction.

12. The method for forming a magnetic random access memory according to claim 11, wherein: The material of the first conductive structure includes copper or cobalt.

13. The method for forming a magnetic random access memory according to claim 11, wherein: The material of the second conductive structure includes: tantalum, tantalum nitride, titanium or titanium nitride.

14. The method for forming a magnetic random access memory according to claim 11, wherein: After forming the top electrode, the method further includes: forming a stop layer on the side wall surface of the magnetic tunnel junction, the top surface of the top electrode and the side wall surface; forming an isolation structure on the stop layer surface; and forming a conductive plug in the isolation structure, wherein the conductive plug contacts the top electrode.

15. The method for forming a magnetic random access memory according to claim 11, wherein: Before forming the first conductive structure, the method further includes: forming a barrier layer on a surface of the first opening, wherein the first conductive structure and the second conductive structure are respectively located on the barrier layer.

16. The method for forming a magnetic random access memory according to claim 15, wherein: The material of the barrier layer includes: tantalum, tantalum nitride, titanium or titanium nitride.

17. The method for forming a magnetic random access memory according to claim 15, wherein: The method for forming the barrier layer comprises: forming an initial barrier layer on the surface of the first opening and the top surface of the first dielectric layer; and flattening the barrier layer until the top surface of the first dielectric layer is exposed to form the barrier layer.

18. The method for forming a magnetic random access memory according to claim 17, wherein: The process of forming the initial barrier layer includes an atomic layer deposition process.

19. The method for forming a magnetic random access memory according to claim 17, wherein: The method for forming the first conductive structure includes: forming a first initial conductive structure on the surface of the initial barrier layer; performing annealing and reflow treatment on the first initial conductive structure to form the first conductive structure, wherein the first conductive structure is located in the first region.

20. The method for forming a magnetic random access memory according to claim 19, wherein: The parameters of the annealing reflow treatment include: annealing time 20s~200s; annealing temperature 200℃~400℃.

21. The method for forming a magnetic random access memory according to claim 19, wherein: The method for forming the second conductive structure includes: forming a second initial conductive structure on the first conductive structure and on the surface of the initial barrier layer; flattening the second initial conductive structure until the top surface of the first dielectric layer is exposed to form the second conductive structure, wherein the second conductive structure is located in the second region.

22. The method for forming a magnetic random access memory according to claim 21, wherein: The second initial conductive structure is formed by a process comprising a physical vapor deposition process.

23. The method for forming a magnetic random access memory according to claim 11, wherein: The second area of ​​the first opening has a depth-to-width ratio of 0.5:1 to 1.5:

1.

24. The method for forming a magnetic random access memory according to claim 21, wherein: The process of planarizing the initial barrier layer includes a chemical mechanical polishing process; and the process of planarizing the second initial conductive structure includes a chemical mechanical polishing process.

25. The method for forming a magnetic random access memory according to claim 11, wherein: The method for forming the magnetic tunnel junction and the top electrode includes: forming a buffer material layer on the second conductive structure and the first dielectric layer; forming a fixed material layer on the buffer material layer; forming an insulating material layer on the fixed material layer; forming a free material layer on the insulating material layer; forming a covering material layer on the free material layer; forming a top electrode material layer on the covering material layer; forming a patterned mask layer on the top electrode material layer, wherein the patterned mask layer exposes a portion of the top surface of the top electrode material layer; etching the top electrode material layer, the covering material layer, the free material layer, the insulating material layer, the fixed material layer and the buffer material layer using the patterned mask layer as a mask to form the magnetic tunnel junction and the top electrode.

26. The method for forming a magnetic random access memory according to claim 25, wherein: In the process of etching the top electrode material layer, the covering material layer, the free material layer, the insulating material layer, the fixed material layer and the buffer material layer using the patterned mask layer as a mask, it also includes: etching and removing part of the first dielectric layer, and part of the top surface of the first dielectric layer is lower than the top surface of the second conductive structure.

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