Integrated assembly and method of forming an integrated assembly

Abstract

This application relates to integrated assemblies and methods of forming integrated assemblies. Some embodiments include a method of forming an integrated assembly. A semiconductor material is patterned into a configuration including a set of first upwardly protruding structures spaced apart from each other by first gaps and second upwardly protruding structures spaced apart from the set by second gaps. The second gaps are larger than the first gaps. A conductive material is formed along the first and second upwardly protruding structures and within the first and second gaps. First and second segments of a protective material are formed over regions of the conductive material within the second gaps, and then the conductive material is patterned into first conductive structures within the first gaps and into second conductive structures within the second gaps using etching. Some embodiments include an integrated assembly.

Description

Technical Field

[0001] Integrated assemblies (e.g., integrated memory). Methods for forming integrated assemblies. Background Technology

[0002] The memory may use memory cells, which individually include access means (e.g., access transistors) combined with storage elements (e.g., capacitors, resistive memory devices, phase-change memory devices, etc.).

[0003] In some applications, it is necessary to form conductive interconnects that traverse the layers of the memory architecture. Difficulties arise when forming such conductive interconnects while maintaining the integrity of the structural components of the memory architecture (e.g., maintaining the integrity of word lines). It would be desirable to develop improved methods for manufacturing memory architectures and improved methods for forming conductive interconnects that traverse the layers of the memory architecture. Summary of the Invention

[0004] According to one aspect of this application, an integrated assembly is provided. The integrated assembly, along a cross-section, includes: an assembly of first upwardly projecting structures spaced apart from each other by a first gap; one of the first upwardly projecting structures being an edge upwardly projecting structure in the assembly; a second upwardly projecting structure spaced apart from the assembly of the first upwardly projecting structures by a second gap larger than the first gap; a first conductive structure within the first gap and adjacent to a sidewall of the first projecting structure; a second conductive structure within the second gap; one of the second conductive structures adjacent to a sidewall of the edge upwardly projecting structure, and the other of the second conductive structures adjacent to a sidewall of the second upwardly projecting structure; and along the cross-section, the shape of the second conductive structure differs from that of the first conductive structure.

[0005] According to another aspect of this application, a method for forming an integrated assembly is provided. The method includes: patterning a semiconductor material into a configuration comprising, along a cross-section, an assembly of first upwardly projecting structures spaced apart from each other by a first gap and second upwardly projecting structures spaced apart from the assembly by a second gap; one of the first upwardly projecting structures being an edge upwardly projecting structure in the assembly and adjacent to the second gap; the second gap being larger than the first gap; forming a conductive material along the first and second upwardly projecting structures and within the first and second gaps; forming a protective material across the first gap and within the second gap; removing the protective material over the first and second upwardly projecting structures while simultaneously removing the conductive material within the second gap. A segment of the protective material is left above the conductive material; one of the segments of the protective material is a first segment adjacent to the sidewall of the upwardly projecting edge structure, and another of the segments of the protective material is a second segment adjacent to the sidewall of the second upwardly projecting edge structure; and the conductive material is patterned by etching into a first conductive structure within the first gap and a second conductive structure within the second gap; one of the second conductive structures is adjacent to the sidewall of the upwardly projecting edge structure and is protected by the first segment of the protective material during the etching; the other of the second conductive structures is adjacent to the sidewall of the second upwardly projecting edge structure and is protected by the second segment of the protective material during the etching.

[0006] According to another aspect of this application, a method for forming an integrated assembly is provided. The method includes: forming a semiconductor material above a first series of first conductive lines; patterning the semiconductor material into a configuration that includes a set of first upwardly projecting structures, their cross-sections contained above one of the first conductive lines and spaced apart by a first gap, and a second upwardly projecting structure above the one of the first conductive lines and spaced apart from the set by a second gap; one of the first upwardly projecting structures being an edge upwardly projecting structure in the set and adjacent to the second gap; the second gap being larger than the first gap; forming a conductive material along the first and second upwardly projecting structures and within the first and second gaps; forming a protective material across the first gap and within the second gap; removing the protective material from above the first and second upwardly projecting structures, while leaving a fragment of the protective material above the conductive material within the second gap; the fragment of the protective material... One segment is a first segment adjacent to the sidewall of the upwardly projecting edge structure, and one of the segments of the protective material is a second segment adjacent to the sidewall of the second upwardly projecting edge structure; the conductive material is patterned into a second series of second conductive lines by etching; the second series includes a first set of second conductive lines within the first gap and a second set of second conductive lines within the second gap; one of the second conductive lines in the second set is adjacent to the sidewall of the upwardly projecting edge structure and is protected by the first segment of the protective material during etching; the other of the second conductive lines in the second set is adjacent to the sidewall of the second upwardly projecting edge structure and is protected by the second segment of the protective material during etching; and a memory element is formed above the first upwardly projecting edge structure and above the second upwardly projecting edge structure; each of the memory elements is uniquely addressed by the first conductive line and by a pair of second conductive lines. Attached Figure Description

[0007] Figure 1 A top-view diagram of the region of the instance integration assembly at the instance process phase of the instance method. Figure 1A and 1B To separate along Figure 1 A schematic cross-sectional side view of lines AA and BB.

[0008] Figure 2 and 2A They are respectively in Figure 1 and 1A The instance process phase after the instance process phase Figure 1 and 1AThe example integrates the region of the assembly with diagrammatic top view and diagrammatic cross-sectional side view. Figure 2A For along Figure 2 A schematic cross-sectional side view of line AA.

[0009] Figure 3 and 3A They are respectively in Figure 2 and 2A The instance process phase after the instance process phase Figure 1 and 1A The example integrates the region of the assembly with diagrammatic top view and diagrammatic cross-sectional side view. Figure 3A For along Figure 3 A schematic cross-sectional side view of line AA.

[0010] Figure 4 and 4A They are respectively in Figure 3 and 3A The instance process phase after the instance process phase Figure 1 and 1A The example integrates the region of the assembly with diagrammatic top view and diagrammatic cross-sectional side view. Figure 4A For along Figure 4 A schematic cross-sectional side view of line AA.

[0011] Figure 5 and 5A They are respectively in Figure 4 and 4A The instance process phase after the instance process phase Figure 1 and 1A The example integrates the region of the assembly with diagrammatic top view and diagrammatic cross-sectional side view. Figure 5A For along Figure 5 A schematic cross-sectional side view of line AA.

[0012] Figure 6 and 6A They are respectively in Figure 5 and 5A The instance process phase after the instance process phase Figure 1 and 1A The example integrates the region of the assembly with diagrammatic top view and diagrammatic cross-sectional side view. Figure 6A For along Figure 6 A schematic cross-sectional side view of line AA.

[0013] Figure 7 and 7A They are respectively in Figure 6 and 6A The instance process phase after the instance process phase Figure 1 and 1AThe example integrates the region of the assembly with diagrammatic top view and diagrammatic cross-sectional side view. Figure 7A For along Figure 7 A schematic cross-sectional side view of line AA.

[0014] Figure 8 and 8A They are respectively in Figure 7 and 7A The instance process phase after the instance process phase Figure 1 and 1A The example integrates the region of the assembly with diagrammatic top view and diagrammatic cross-sectional side view. Figure 8A For along Figure 8 A schematic cross-sectional side view of line AA.

[0015] Figure 8B For along Figure 8 A schematic cross-sectional side view of line BB.

[0016] Figure 9 This is a schematic diagram of the regions of an instance memory array. Detailed Implementation

[0017] Some embodiments include methods of forming integrated assemblies. Protective materials (e.g., silicon dioxide, alumina, hafnium oxide, etc.) can be used to protect segments of conductive material within wide gaps during etching, such that these segments are retained as conductive lines (e.g., word lines) in the finished architecture. Some embodiments include integrated assemblies in which the conductive lines (e.g., word lines) in the wide gaps have a different cross-sectional shape than similar conductive lines in narrow gaps. Reference Figures 1 to 9 Describe an example implementation.

[0018] refer to Figures 1 to 1B The integrated assembly 10 includes a series of conductive lines 12 extending along a first direction (the illustrated x-axis direction). The lines 12 are illustrated as straight, but in other embodiments, they may be curved, wavy, etc.

[0019] The conductive wires 12 are spaced apart from each other by insertion regions 14 comprising insulating material 16. The insulating material 16 may comprise any suitable composition; and in some embodiments, it may comprise silicon dioxide, be composed primarily of silicon dioxide, or be composed of silicon dioxide.

[0020] The conductive wire 12 includes a conductive material 18. The conductive material 18 may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.) and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.).

[0021] The conductive wire 12 and the insulating material 16 can be considered as being comprised of a first layer (layer) 20, wherein this layer is supported above the semiconductor substrate 22 (e.g., Figure 1A and 1B (As shown in the diagram). Semiconductor substrate 22 may include semiconductor materials; and may include, for example, monocrystalline silicon, consisting primarily of or composed of monocrystalline silicon. Substrate 22 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction including, but not limited to, semiconducting materials, such as: bulk semiconducting materials, for example, a semiconducting wafer (alone or in a combination of other materials); and (alone or in a combination of other materials) a layer of semiconducting materials. The term "substrate" refers to any support structure, including, but not limited to, the semiconductor substrate described above. In some applications, substrate 22 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit manufacturing. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulating materials, etc.

[0022] Layer 20 is shown as being vertically offset relative to base 22, and more precisely, as being offset from base 22 along the illustrated z-axis direction.

[0023] A gap is provided between layer 20 and substrate 22 to indicate that other materials and structures may be disposed between layer 20 and substrate 22. In some embodiments, circuitry (e.g., logic circuitry, such as CMOS) may be disposed along substrate 22. One or more conductive interconnects may ultimately be formed to extend through layer 20 to the circuitry associated with substrate 22.

[0024] Conductive wire 12 may be referred to as the first conductive wire, and may be considered as the first conductive wire configured as a first series.

[0025] refer to Figure 2 and 2A Semiconductor material 24 is formed on the first series of first conductive lines 12. Semiconductor material 24 may comprise any suitable composition; and in some embodiments, it may comprise one or more of, consist primarily of, or be composed of one or more of: silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides (e.g., InGaZnO, where the chemical formula indicates the major component rather than a specific stoichiometry), etc.; wherein the term III / V semiconductor material refers to semiconductor materials comprising elements selected from Groups III and V of the periodic table (where Groups III and V are older nomenclature and are now referred to as Groups 13 and 15). In some embodiments, semiconductor material 24 may comprise silicon, consisting primarily of, or be composed of silicon. Silicon may be in any suitable crystalline form (e.g., single crystal, amorphous, polycrystalline, etc.).

[0026] Semiconductor material 24 may include regions 15, 17, and 19. Regions 17 and 19 may be conductively doped to ultimately become source / drain regions of an access device (transistor), and region 15 may be appropriately doped to become the channel region of the access device. Dashed lines are provided to illustrate the approximate boundaries between regions 15, 17, and 19.

[0027] refer to Figure 3 and 3A The semiconductor material 24 is patterned into a configuration including upwardly projecting structures (features) 26 and 28. The upwardly projecting structures 26 and 28 may alternatively be referred to as pillars, columns, etc.

[0028] The upwardly projecting structure 26 may be referred to as the first upwardly projecting structure, and together they form assembly 30. The upwardly projecting structure 28 may be referred to as the second upwardly projecting structure. The upwardly projecting structures 26 and 28 are aligned with the conductive line 12. One of these conductive lines 12 is shown in... Figure 3A In the cross-section, and directly above such conductive lines, upward-projecting structures 26 and 28 are also shown. Figure 3A middle.

[0029] The first upwardly projecting structures 26 are spaced apart from each other by a first gap 32. The upwardly projecting features 26 may be on a gap P ranging from about 30 nanometers (nm) to about 60 nm. In some embodiments, the upper surface of the structure 26 may be along... Figure 3A The cross-section has a width W1 ranging from about 15 nm to about 30 nm, and the upper region of the gap 32 may have a width W2 ranging from about 15 nm to about 30 nm.

[0030] Along Figure 3A The second upwardly projecting structure 28 of the cross-section is spaced apart from the assembly 30 of the first upwardly projecting structures 26 by a second gap 34. The second gap 34 is along... Figure 3A The cross-section has a width W3. The width W3 of the second gap is greater than the width W2 of the first gap, and in some embodiments, it may be at least about twice the width of the first gap, at least about three times the width of the first gap, at least about four times the width of the first gap, etc.

[0031] exist Figure 3A In the illustrated embodiment, one of the first upwardly projecting structures 26 is adjacent to the second gap 34. This upwardly projecting structure may be referred to as the edge upwardly projecting structure of the assembly 30 and is designated as 26a, so that it can be distinguished from the other upwardly projecting structures 26.

[0032] Structure 26 has a sidewall surface 27 and a top surface 25, and structure 28 has a sidewall surface 31 and a top surface 29. In the illustrated embodiment, the sidewall surfaces (sidewalls) 27 and 31 gradually narrow along the vertical (z-axis) direction. In other embodiments, the sidewalls may be vertically straight rather than gradually narrowing.

[0033] In the illustrated embodiment, the semiconductor material 24 is held above the conductive line 12 within gaps 32 and 34. In other embodiments, the semiconductor material 24 may be completely removed from within the wide gap 34 and / or from the narrow gap 32.

[0034] refer to Figure 4 and 4A An insulating material 36 is provided along the bottom of gaps 32 and 34. The insulating material 36 may be provided to any suitable thickness. The insulating material 36 is offset relative to the bottom of the upwardly projecting structures 26 and 28 (formed in a later process stage) from the bottom of the transistor gate, and in some embodiments, may be formed to a thickness approximately equal to the thickness of the lower source / drain region 19 (as shown). The insulating material 36 may include any suitable composition; and in some embodiments, may include silicon dioxide, consisting primarily of silicon dioxide, or composed of silicon dioxide.

[0035] Dielectric material 38 is formed along surfaces 25, 27, 29, and 31 of the upwardly projecting structures 26 and 28. Dielectric material 38 may be formed after the formation of insulating material 36 (as shown), such that dielectric material 38 does not extend along the lower portions of the upwardly projecting structures 26 and 28. Alternatively, dielectric material 38 may be formed before the formation of insulating material 36 and may extend along the lower portions of structures 26 and 28.

[0036] The dielectric material 38 may comprise any suitable composition. In some embodiments, the dielectric material 38 may be formed from the semiconductor material 24. Thus, if the semiconductor material 24 comprises silicon, is primarily composed of silicon, or is composed of silicon, then the dielectric material 38 may comprise silicon dioxide, is primarily composed of silicon dioxide, or is composed of silicon dioxide. Alternatively, at least some of the dielectric materials 38 may be formed by deposition (e.g., atomic layer deposition, chemical vapor deposition, etc.). In such embodiments, in addition to silicon dioxide, or in lieu of silicon dioxide, the dielectric material 38 may also comprise one or more of, for example, alumina, hafnium oxide, zirconium oxide, etc.

[0037] The dielectric material 38 can be formed to any suitable thickness, and in some embodiments, it can be formed to be approximately [thickness missing]. To date Thickness within the specified range.

[0038] Conductive material 40 is formed on dielectric material 38; and in the illustrated embodiment, it is formed on the first upwardly projecting structure 26 and the second upwardly projecting structure 28, and within the first gap 32 and the second gap 34. Conductive material 40 may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.) and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, the conductive material 40 may include one or more metals (e.g., titanium, tungsten, etc.) and / or metal-containing compositions (e.g., titanium silicide, titanium carbide, titanium nitride, titanium boride, tungsten silicide, tungsten carbide, tungsten nitride, tungsten boride, etc.), and is mainly composed of one or more metals (e.g., titanium, tungsten, etc.) and / or metal-containing compositions (e.g., titanium silicide, titanium carbide, titanium nitride, titanium boride, tungsten silicide, tungsten carbide, tungsten nitride, tungsten boride, etc.) or is composed of one or more metals (e.g., titanium, tungsten, etc.) and / or metal-containing compositions (e.g., titanium silicide, titanium carbide, titanium nitride, titanium boride, tungsten silicide, tungsten carbide, tungsten nitride, tungsten boride, etc.).

[0039] The conductive material 40 can be formed to any suitable thickness, and in some embodiments, it can be formed to a thickness of approximately [missing information]. To date Thickness within the specified range.

[0040] refer to Figure 5 and 5A The protective material 42 extends across the first gap 32 and is formed within the second gap 34. It is noteworthy that the protective material 42 does not fill the first gap 32, but rather breaks across the first gap to leave a void 44 within it. However, the protective material 42 does extend into the second gap 34, and in the illustrated embodiment, conformally extends along the conductive material 40 within the second gap 34.

[0041] The protective material 42 can be formed to any suitable thickness to establish the illustrated configuration, wherein the material is clamped across the narrow gap 32 while conformally (or at least substantially conformally) extending along the conductive material 40 within the second gap 34. The term "at least substantially conformally" means conformally within reasonable manufacturing and measurement tolerances. In some embodiments, the protective material 42 can be formed to a thickness ranging from about 50 nm to about 100 nm.

[0042] Protective material 42 may comprise any suitable composition. In some embodiments, protective material 42 may comprise, consist primarily of, or be composed of, one or more of silicon dioxide and / or various high-k compositions. The term high-k means a dielectric constant greater than that of silicon dioxide (i.e., greater than about 3.9). Examples of high-k compositions include silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, etc. In some embodiments, protective material 42 may be electrically insulating. Alternatively, protective material 42 may be electrically conductive or semi-conductive.

[0043] refer to Figure 6 and 6A The protective material 42 is removed from above the first upward protruding structure 26 and the second upward protruding structure 28, while leaving a segment 46 of protective material above the conductive material 40 within the wide gap (second gap) 34. The segment 46 can be considered as a first segment 46a comprising a sidewall (or sidewall surface) 27 adjacent to the edge of the upward protruding structure 26a, and a second segment 46b adjacent to the sidewall (sidewall surface) 31 of the second upward protruding structure 28.

[0044] refer to Figure 7 and 7A The conductive material 40 is patterned into a first conductive structure 48 within a first gap 32 and a second conductive structure 50 within a second gap 34 using one or more suitable etching methods. Sections 46a and 46b of the protective material 42 are used to protect areas of the conductive material 40 within the second gap 34 so that such areas are not lost during etching of the conductive material 40. In contrast, conventional processing without the protective material 42 can result in the loss of all or almost all of the conductive material 40 from the second gap 34, resulting in the partial or substantial loss of conductive structures similar to the illustrated conductive structure 50. Therefore, the protective material 42 advantageously allows the conductive structure 50 to be formed to a suitable size and configuration for maintaining the integrity of the device manufactured within layer 20 of the integrated assembly 10.

[0045] In the illustrated embodiment, conductive structures 48 and 50 are incorporated into word lines 52 (WL1 to WL5), with a wide gap 34 between word lines WL4 and WL5. Pillars (upwardly extending structures) 26 and 28 are incorporated into the active region of the access device (transistor) 54. Each of the transistors includes a channel region 15 vertically disposed between a lower source / drain region 19 and an upper source / drain region 17. Source / drain regions 17 and 19 are coupled to each other in a gated manner through channel region 28. Specifically, an appropriate voltage on word line 52 (i.e., a voltage above a threshold voltage) can induce an electric field in the channel region near such word lines to create electrical coupling between the source / drain regions on opposite sides of the channel region.

[0046] The shape of the second conductive structure 50 is along... Figure 7A The first conductive structure 48 differs from the first conductive structure 48 in cross-section. Specifically, the first conductive structure 48 is shown as a generally straight structure (where the term "generally straight" means straight within reasonable manufacturing and measurement tolerances), and the conductive structure 50 is shown as an angled plate. The conductive structure 50 of the sidewall 27 adjacent to the edge support 26a is designated 50a, and the conductive structure 50 of the sidewall 31 adjacent to the support 28 is designated 50b. Conductive structures 50a and 50b may be referred to as the first angled plate and the second angled plate, respectively.

[0047] Each of the angle plates 50a and 50b includes a main portion 56 and a secondary portion 58 extending from the main portion 56 into the gap 34. In some embodiments, the secondary portion 58 may be considered configured as a flange. The flange 58 of the conductive structure 50a may be referred to as the first flange, and the flange 58 of the second conductive structure 50b may be referred to as the second flange. The remainder of the protective material 42 is supported by the flange 58. During etching of the conductive material 40, the protective material 42 protects the flange 58 and thus defines the length of the flange. In some embodiments, the protective material 42 may be thinned during etching used to pattern the conductive material 40, compared to the illustrated embodiment where the protective material 42 is not thinned, the etching reducing the length of the flange 58.

[0048] In the illustrated embodiment, during the patterning of the conductive material 40, the height of the conductive material 40 is reduced relative to the height of the protective material 42. Therefore, the angle plates 50a and 50b have an upper surface 51 that is vertically offset relative to the upper surface 53 of the segments 46a and 46b of the protective material 42.

[0049] The first angle plate 50a and the second angle plate 50b are substantially mirror images of each other, positioned across a vertical plane 60 centrally located between the first and second angle plates, as shown. In other embodiments (not shown), the first and second angle plates may not be substantially mirror images of each other. The term "substantially mirror image" means a mirror image within reasonable manufacturing and measurement tolerances.

[0050] refer to Figures 8 to 8B Storage element 62 is formed above pillars 26 and 28 and electrically coupled to the upper source / drain region 17. Storage element 62 can be any suitable device having at least two detectable states; and in some embodiments, it can be, for example, a capacitor, a resistive memory device, a conductive bridging device, a phase-change memory (PCM) device, a programmable metallization cell (PMC), etc. If the storage element is a capacitor, it can be a ferroelectric capacitor (i.e., it may include ferroelectric insulating material between a pair of capacitor electrodes) or a non-ferroelectric capacitor (i.e., it may only include non-ferroelectric insulating material between a pair of capacitor electrodes). Examples of ferroelectric insulating materials may include one or more of transition metal oxides, zirconium, zirconium oxide, niobium, niobium oxide, hafnium, hafnium oxide, lead zirconium titanate, and barium strontium titanate. Examples of non-ferroelectric insulating materials may include silicon dioxide, be primarily composed of silicon dioxide, or be composed of silicon dioxide.

[0051] In some embodiments, the storage element 62 above the pillar 26 may be referred to as the first storage element, and the storage element 62 above the pillar 28 may be referred to as the second storage element.

[0052] Insulating material 64 is formed within gaps 32 and 34. Figure 7 and 7A In some embodiments, protective material 42 may be considered to correspond to a first insulating material, and insulating material 64 may be considered to correspond to a second insulating material. The first insulating material 42 is not within the first gap 32, and the second insulating material 64 is within both the first gap 32 and the second gap 34 (where gaps 32 and 34 are shown in…). Figure 7 and 7A (In the middle). The first insulating material 42 and the second insulating material 64 may comprise compositions that are different from each other. For example, the first insulating material 42 may comprise one or more high-k dielectric compositions, while the second insulating material 64 may comprise silicon dioxide, consisting primarily of silicon dioxide or composed of silicon dioxide. In other embodiments, materials 42 and 64 may be identical in composition to each other and may be... Figures 8 to 8B The processing stages are combined. In addition, material 36 may be different in composition from one or both of materials 42 and 64, or may be the same in composition as both materials 42 and 64.

[0053] Although the protective material 42 is retained in Figures 8 to 8BIn the final structure, but it should be understood that in other embodiments, the protective material 42 may be removed after the patterned conductive structures 50a and 50b.

[0054] Storage element 62 and access device (transistor) 54 can be incorporated into memory array 66. Therefore, level 20 can be referred to as memory level.

[0055] In the illustrated embodiment, conductive interconnects 68 are formed to extend through memory layer 20 and to circuitry 70 associated with substrate 22. In some applications, circuitry 70 may be logic circuitry (e.g., CMOS).

[0056] Conductive interconnect 68 is formed in the wide gap 34 (marked in Figure 7 and 7A Within (the middle). Compared to forming similar interconnects within a narrower gap, a wider gap simplifies the formation of interconnect 68. Interconnect 68 can have any suitable shape and may or may not correspond to the illustrated cylindrical pillar. Interconnect 68 may include any suitable conductive material 72. For example, conductive material 72 may include one or more of the following: various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.).

[0057] The conductive interconnect 68 may be located between the first angle plate 50a and the second angle plate 50b, as can be seen by comparison. Figure 8 A top view (showing interconnect 68, but angle plates 50a and 50b are not visible) and Figure 7 The top view (which shows angle plates 50a and 50b) is understandable.

[0058] The memory array 66 can have any suitable configuration. Figure 9 The illustration shows an example configuration where storage element 62 is a capacitor. The capacitor can be a nonferroelectric capacitor, and therefore the memory array 66 can be a dynamic random access memory (DRAM) array. Alternatively, the capacitor can be a ferroelectric capacitor, and therefore the memory array 66 can be a ferroelectric random access memory (FeRAM) array.

[0059] The capacitor 62 described has an electrical node coupled to the access transistor 54, and each has another electrical node coupled to a reference 76. The reference 76 may correspond to any suitable reference voltage, including ground, VCC / 2, etc.

[0060] Word line 52 is shown coupled to word line driver circuitry 78, and digital line 12 is shown coupled to sense amplifier circuitry 80. Access transistor 54 and memory element 62 together form memory cell 82, wherein each memory cell is uniquely addressed by combining one of the digital lines 12 with one of the word lines 52.

[0061] The assemblies and structures discussed above can be utilized within integrated circuits (where the term "integrated circuit" refers to electronic circuits supported by a semiconductor substrate); and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and special-purpose modules, and can comprise multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0062] Unless otherwise specified, the various materials, substances, and compositions described herein may be formed by any suitable method now known or to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0063] The terms “dielectric” and “insulating” are used to describe materials having insulating electrical properties. These terms are considered synonymous in this disclosure. The use of the term “dielectric” in some instances and the term “insulating” (or “electrically insulating”) in others is a linguistic variation within this disclosure to simplify the premises of the appended claims, and not intended to indicate any significant chemical or electrical differences.

[0064] The terms "electrical connection" and "electrical coupling" are both used in this disclosure. The terms are considered synonymous. The use of one term in some cases and another in others provides linguistic variation within this disclosure to simplify the presuppositions in the appended claims.

[0065] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and in some applications the embodiments may be rotated relative to the shown orientation. The description provided herein and the appended claims relate to any structure having the described relationships between various features, whether the structure is in or rotated relative to the specific orientation of the drawings.

[0066] Unless otherwise specified, the accompanying cross-sectional drawings show only the features within the cross-sectional plane and not the material behind the cross-sectional plane in order to simplify the drawings.

[0067] When a structure is referred to as being “on,” “adjacent to,” or “against” another structure, the structure may be directly on the other structure or may also have an insert structure. In contrast, when a structure is referred to as being “directly” on, directly adjacent to, or directly against another structure, no insert structure is present. The terms “directly below,” “directly above,” etc., do not indicate direct physical contact (unless otherwise explicitly stated), but instead indicate upright alignment.

[0068] A structure (e.g., a layer, material, etc.) may be described as “vertically extending” to indicate that the structure extends generally upward from the underlying substrate (e.g., a base plate). A vertically extending structure may extend generally orthogonally relative to or not relative to the upper surface of the substrate.

[0069] Some embodiments include an integrated assembly having an assembly of first upwardly projecting structures spaced apart from each other by a first gap. One of the first upwardly projecting structures is an edge upwardly projecting structure in the assembly. A second upwardly projecting structure is spaced apart from the assembly of first upwardly projecting structures by a second gap larger than the first gap. A first conductive structure is located within the first gap and adjacent to the sidewall of the first projecting structure. A second conductive structure is located within the second gap. One of the second conductive structures is adjacent to the sidewall of the edge upwardly projecting structure, and the other of the second conductive structures is adjacent to the sidewall of the second upwardly projecting structure. Along the cross-section, the shape of the second conductive structure differs from that of the first conductive structure.

[0070] Some embodiments include a method of forming an integrated assembly. A semiconductor material is patterned into a configuration comprising, along a cross-section, an assembly of first upwardly projecting structures spaced apart from each other by a first gap and second upwardly projecting structures spaced apart from the assembly by a second gap. One of the first upwardly projecting structures is an edge upwardly projecting structure in the assembly and adjacent to the second gap. The second gap is larger than the first gap. Conductive material is formed along the first and second upwardly projecting structures and within the first and second gaps. Protective material is formed across the first gap and within the second gap. The protective material is removed from above the first and second upwardly projecting structures, leaving fragments of protective material above the conductive material within the second gap. One of the fragments of protective material is a first fragment adjacent to a sidewall of the edge upwardly projecting structure, and another of the fragments of protective material is a second fragment adjacent to a sidewall of the second upwardly projecting structure. The conductive material is patterned using etching to form the first conductive structure within the first gap and the second conductive structure within the second gap. One of the second conductive structures is adjacent to a sidewall of the edge upwardly projecting structure and is protected by the first fragment of protective material during etching. The other of the second conductive structures is adjacent to the sidewall of the second upwardly projecting structure and is protected by a second segment of protective material during etching.

[0071] Some embodiments include a method of forming an integrated assembly. Semiconductor material is formed above a first series of first conductive lines. The semiconductor material is patterned into a configuration that includes a set of first upwardly projecting structures, cross-sections of which are contained above one of the first conductive lines and spaced apart by a first gap, and a second upwardly projecting structure above the one of the first conductive lines and spaced apart by a second gap from the set. One of the first upwardly projecting structures is an edge upwardly projecting structure in the set and adjacent to the second gap. The second gap is larger than the first gap. Conductive material is formed along the first and second upwardly projecting structures and within the first and second gaps. Protective material is formed across the first gap and within the second gap. Protective material is removed from above the first and second upwardly projecting structures, leaving fragments of protective material above the conductive material within the second gap. One of the fragments of protective material is a first fragment adjacent to a sidewall of the edge upwardly projecting structure, and another fragment of protective material is a second fragment adjacent to a sidewall of the second upwardly projecting structure. The conductive material is patterned into a second series of second conductive lines using etching. The second series includes a first set of second conductive lines within the first gap and a second set of second conductive lines within the second gap. One of the second conductive lines in the second set is adjacent to the sidewall of the upwardly projecting structure and is protected by a first segment of protective material during etching. The other of the second conductive lines in the second set is adjacent to the sidewall of the second upwardly projecting structure and is protected by a second segment of protective material during etching. A memory element is formed above the first and second upwardly projecting structures. Each of the memory elements is uniquely addressed by said first conductive line and by a pair of second conductive lines.

[0072] As specified, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes exemplary embodiments. Therefore, the claims have the full scope as stated in the writing and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. An integrated assembly comprising, along its cross-section: A set of first upwardly projecting structures spaced apart from each other by a first gap; One of the first upward-protruding structures is the edge upward-protruding structure in the set; The second upward protruding structure is spaced apart from the assembly of the first upward protruding structures by a second gap larger than the first gap; Dielectric material is located on the sidewalls of the first upwardly projecting structure and the second upwardly projecting structure; A first conductive structure is located within the first gap, on the dielectric material, and adjacent to the sidewall of the first upwardly projecting structure. A second conductive structure is located within the second gap and on the dielectric material; one of the second conductive structures is adjacent to the sidewall of the upwardly projecting edge structure, and the other of the second conductive structures is adjacent to the sidewall of the upwardly projecting edge structure; and Along the cross-section, the shape of the second conductive structure differs from that of the first conductive structure. The second conductive structure is an angled plate along the cross-section, and The first upward protruding structure and the second upward protruding structure are formed of semiconductor material.

2. The integrated assembly of claim 1, comprising a conductive interconnect extending through the bottom of the second gap.

3. The integrated assembly according to claim 1, wherein the first conductive structure is substantially straight along the cross-section.

4. The integrated assembly of claim 1, wherein the second gap is at least twice the size of the first gap.

5. The integrated assembly of claim 1, wherein the second gap is at least three times larger than the first gap.

6. The integrated assembly of claim 1, wherein the second gap is at least four times larger than the first gap.

7. The integrated assembly of claim 1, wherein the first conductive structure and the second conductive structure are word lines and coupled to word line driver circuitry.

8. The integrated assembly of claim 7, wherein the first upward protruding structure and the second upward protruding structure are pillars of semiconductor material and are above the digital line; and wherein the digital line is coupled to a sense amplifier circuit.

9. The integrated assembly according to claim 8, wherein: The first upward protruding structure is the first pillar of the semiconductor material; The storage element is located above the first pillar of the semiconductor material and is part of the memory array; and Each of the memory elements is uniquely addressed by combining one of the digital lines and one of the word lines.

10. The integrated assembly of claim 9, wherein the storage element is a capacitor and the memory array is a DRAM array.

11. The integrated assembly of claim 9, wherein the storage element is a ferroelectric capacitor and the memory array is an FeRAM array.

12. The integrated assembly of claim 9, wherein the storage element is a first storage element, and wherein the second storage element is above the second upwardly projecting structure and electrically coupled to the second upwardly projecting structure.

13. An integrated assembly comprising, along its cross-section: A set of first upwardly projecting structures spaced apart from each other by a first gap; One of the first upward-protruding structures is the edge upward-protruding structure in the set; The second upward protruding structure is spaced apart from the assembly of the first upward protruding structures by a second gap larger than the first gap; A first conductive structure is located within the first gap and adjacent to the sidewall of the first upwardly projecting structure; A second conductive structure is located within the second gap; one of the second conductive structures is adjacent to the sidewall of the upwardly projecting edge structure, and the other of the second conductive structures is adjacent to the sidewall of the upwardly projecting edge structure; and Along the cross-section, the shape of the second conductive structure differs from that of the first conductive structure. The first conductive structure is substantially straight along the cross-section, and the second conductive structure is an angled plate along the cross-section. The first of the second conductive structures is the first of the angle plates, and the other of the second conductive structures is the second of the angle plates; and the first and second angle plates are mirror images of each other, positioned centrally across the vertical plane between the first and second angle plates.

14. The integrated assembly according to claim 13, wherein: One of the second conductive structures is the first of the angle plates, and the other of the second conductive structure is the second of the angle plates; The first angled plate includes a first main portion of the sidewall of the structure that protrudes upward along the edge, and includes a first secondary portion extending from the first main portion into the second gap; The first sub-part is configured as a first flange of the sidewall of the structure that protrudes upward adjacent to the edge; and The second angle plate includes a second main portion along the sidewall of the second upwardly projecting structure, and includes a second secondary portion extending from the second main portion into the second gap; The second sub-part is configured as a second flange adjacent to the sidewall of the second upwardly projecting structure.

15. The integrated assembly of claim 14, comprising: A first insulating material, which is supported by the first flange and the second flange and extends along the first main portion and the second main portion; A second insulating material is located within the first gap and the second gap; the second insulating material is above the first angle plate and the second angle plate, and above the first insulating material. and The first insulating material is different in composition from the second insulating material.

16. The integrated assembly of claim 15, wherein the first insulating material is not above the first conductive structure within the first gap.

17. The integrated assembly of claim 15, wherein the first angle plate and the second angle plate have upper surfaces that are vertically offset relative to the upper surface of the first insulating material supported by the first flange and the second flange, respectively.

18. The integrated assembly of claim 15, wherein the first insulating material comprises one or more high-k dielectric compositions, and wherein the second insulating material comprises silicon dioxide.

19. A method of forming an integrated assembly, comprising: A semiconductor material is patterned into a configuration comprising, along a cross section, a set of first upwardly projecting structures spaced apart from each other by a first gap and a second upwardly projecting structure spaced apart from the set by a second gap; One of the first upwardly protruding structures is an edge upwardly protruding structure in the set that is adjacent to the second gap; The second gap is larger than the first gap; Dielectric material is formed along the sidewalls of the first upwardly protruding structure and the second upwardly protruding structure; A conductive material is formed along the first upward protruding structure and the second upward protruding structure, on the dielectric material and within the first gap and the second gap; A protective material is formed across the first gap and within the second gap; The protective material is removed from above the first upward protruding structure and the second upward protruding structure, while leaving a fragment of the protective material above the conductive material in the second gap; one of the fragments of the protective material is a first fragment adjacent to the sidewall of the edge upward protruding structure, and one of the fragments of the protective material is a second fragment adjacent to the sidewall of the second upward protruding structure; and The conductive material is patterned into a first conductive structure within the first gap and a second conductive structure within the second gap by etching. One of the second conductive structures is adjacent to the sidewall of the upwardly projecting edge structure and is protected by the first segment of the protective material during the etching; the other of the second conductive structures is adjacent to the sidewall of the second upwardly projecting edge structure and is protected by the second segment of the protective material during the etching.

20. The method of claim 19, wherein the protective material comprises silicon dioxide.

21. The method of claim 19, wherein the protective material comprises one or more high-k compositions.

22. The method of claim 19, wherein the semiconductor material comprises silicon.

23. The method of claim 19, further comprising forming a conductive interconnect extending into the second gap and between one of the second conductive structures and the other of the second conductive structure.

24. The method of claim 19, wherein the shape of the second conductive structure is different from that of the first conductive structure along the cross-section.

25. The method of claim 24, wherein the first conductive structure is substantially straight along the cross-section, and wherein the second conductive structure is an angled plate along the cross-section.

26. A method of forming an integrated assembly, comprising: A semiconductor material is formed above the first conductive line of the first series; The semiconductor material is patterned into a configuration comprising a set of first upwardly projecting structures, the cross-section of which is contained above one of the first conductive lines and spaced apart from each other by a first gap, and a second upwardly projecting structure above the one of the first conductive lines and spaced apart from the set by a second gap; one of the first upwardly projecting structures is an edge upwardly projecting structure in the set and adjacent to the second gap. The second gap is larger than the first gap; Dielectric material is formed along the sidewalls of the first upwardly protruding structure and the second upwardly protruding structure; A conductive material is formed along the first upward protruding structure and the second upward protruding structure, on the dielectric material and within the first gap and the second gap; A protective material is formed across the first gap and within the second gap; The protective material is removed from above the first upward protruding structure and the second upward protruding structure, while leaving a fragment of the protective material above the conductive material in the second gap; one of the fragments of the protective material is a first fragment adjacent to the sidewall of the edge upward protruding structure, and one of the fragments of the protective material is a second fragment adjacent to the sidewall of the second upward protruding structure; The conductive material is patterned into a second series of second conductive lines using etching; the second series includes a first set of second conductive lines within the first gap and a second set of second conductive lines within the second gap; one of the second conductive lines in the second set is adjacent to the sidewall of the upwardly projecting edge structure and is protected by the first segment of the protective material during etching; the other of the second conductive lines in the second set is adjacent to the sidewall of the second upwardly projecting structure and is protected by the second segment of the protective material during etching; and A storage element is formed above the first upward protruding structure and above the second upward protruding structure; Each of the storage elements is uniquely addressed via one of the first conductive lines and via a pair of second conductive lines.

27. The method of claim 26, wherein the semiconductor material comprises one or more of silicon, germanium, III / V semiconductor materials, and semiconductor oxides.

28. The method of claim 26, wherein the semiconductor material comprises monocrystalline silicon.

29. The method of claim 26, wherein the storage element is a capacitor.

30. The method of claim 26, wherein the storage element is a ferroelectric capacitor.

31. The method of claim 26, wherein the shape of the second conductive wire is different from that of the first conductive wire along the cross-section.

32. The method of claim 31, wherein the first conductive line is substantially straight along the cross-section, and wherein the second conductive line is an angled plate along the cross-section.

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