Isolation circuit for isolating a transmitting end and a receiving end

Abstract

An isolation circuit for isolating a transmitting end and a receiving end is provided. The isolation circuit comprises: a clock end configured to receive a clock signal; a common mode signal end configured to receive a common mode signal; a transmitting end circuit configured to: perform signal processing on a plurality of data signals, the clock signal, and the common mode signal; and output a first signal comprising the plurality of data signals, the clock signal, and the common mode signal after signal processing; an isolation capacitor circuit configured to isolate a direct current component in the first signal to output a second signal; and a receiving end circuit configured to: demodulate the second signal to obtain a third signal corresponding to the plurality of data signals and a fourth signal corresponding to the clock signal; and demodulate and demultiplex the third signal based on the fourth signal.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of circuit, and in particular, to an isolation circuit for isolating a transmitting end and a receiving end. BACKGROUND

[0002] When data is transmitted between two circuits, an isolation circuit needs to be set between the transmitting end and the receiving end. This is because the transmitting end circuit and the receiving end circuit are usually in different voltage domains, and the voltage difference between them can reach several thousand volts. The direct current signal between them is likely to be interrupted or damaged, and the data transmitted between the circuits is likely to be interrupted or damaged. Therefore, a capacitive isolation circuit is usually used to isolate the direct current signal between the transmitting end and the receiving end, and to pass the alternating current signal. SUMMARY

[0003] The present disclosure provides an isolation circuit for isolating a transmitting end and a receiving end when data is transmitted between two circuits.

[0004] According to an aspect of the present disclosure, an isolation circuit for isolating a transmitting end and a receiving end is provided, comprising: a clock end configured to receive a clock signal; a common mode signal end configured to receive a common mode signal, the common mode signal indicating a disturbance of a power supply or a ground of the transmitting end; a transmitting end circuit configured to: perform signal processing on a plurality of data signals, the clock signal, and the common mode signal, wherein the signal processing comprises multiplexing and modulating the plurality of data signals; and output a first signal comprising the plurality of data signals after signal processing, the clock signal, and the common mode signal; an isolation capacitor circuit located between the transmitting end and the receiving end, and configured to isolate a direct current component in the first signal to output a second signal; and a receiving end circuit configured to: demodulate the second signal to obtain a third signal corresponding to the plurality of data signals and a fourth signal corresponding to the clock signal; and demodulate and demultiplex the third signal based on the fourth signal.

[0005] According to one or more embodiments of the present disclosure, by multiplexing and modulating the plurality of data signals, the suppression capability of the data signal to the common mode interference is improved, and the number of channels required for transmitting the plurality of data signals is reduced, thereby reducing the number of capacitors required for isolating the direct current signal, so that the circuit cost is greatly reduced. At the same time, the transmission of the common mode signal makes it possible to remove the influence of the disturbance of the power supply or the ground from the transmitting end at the receiving end, thereby improving the common mode transient immunity of the circuit.

[0006] These and other aspects of the present disclosure will become clear from the embodiments described below, and will be clarified with reference to the embodiments described below. Attached Figure Description

[0007] Further details, features, and advantages of this disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0008] Figure 1 This is a schematic block diagram illustrating an isolation circuit according to an exemplary embodiment of the present disclosure;

[0009] Figure 2 It is shown in the figure. Figure 1 A schematic block diagram of an example of an isolation circuit;

[0010] Figure 3 It is shown in the figure. Figure 2 A schematic block diagram of an example of a time-division multiplexed synchronous hybrid modulator;

[0011] Figure 4 This is a timing diagram illustrating the multiplexing of the data signal frame structure according to an exemplary embodiment of the present disclosure;

[0012] Figure 5 It is shown in the figure. Figure 2 A schematic block diagram of an example of the first demodulator in the diagram;

[0013] Figure 6 This is a schematic diagram illustrating the multiplexing and demultiplexing of data signals according to an exemplary embodiment of the present disclosure;

[0014] Figure 7 It is shown in the figure. Figure 1 A schematic block diagram of an example of an isolation circuit;

[0015] Figure 8 It is shown in the figure. Figure 7 A schematic block diagram of an example of a time-division multiplexed quasi-synchronous hybrid modulator; and

[0016] Figure 9 This is a schematic diagram illustrating the multiplexing and demultiplexing of data signals according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0017] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part without departing from the teachings of this disclosure.

[0018] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items and the phrase "at least one of A and B" includes only A, only B, and both A and B.

[0019] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the

[0020] In the related art, for the transmission of each data signal, an isolation capacitor is arranged between the sending end and the receiving end to isolate the direct current signal in the data signal. However, in such a scheme, the demand for isolation capacitors will increase with the increase in the number of data signals, and the transmitted data signal has weak suppression ability for the common mode signal, and the data signal received by the receiving end is prone to distortion.

[0021] To alleviate, mitigate or eliminate one or more of the above problems, embodiments of the present disclosure improve the suppression ability of the data signal for the common mode interference by multiplexing and modulating multiple data signals, reduce the number of channels required for transmitting multiple data signals, and thus reduce the number of isolation capacitors required for isolating direct current signals, greatly reducing the cost of the circuit. At the same time, the transmission of the common mode signal makes it possible to remove the disturbance of the power supply or ground from the sending end at the receiving end, improving the common mode transient immunity of the circuit.

[0022] Exemplary embodiments of the present disclosure will be described in detail below.

[0023] Figure 1 is a schematic block diagram illustrating an isolation circuit according to an exemplary embodiment of the present disclosure. As shown in FIG. 1, the isolation circuit includes a sending end 10 and a receiving end 20. The sending end 10 is configured to receive a plurality of data signals and a common mode signal, and the receiving end 20 is configured to receive the plurality of data signals and the common mode signal. Figure 1As shown, the isolation circuit 100 comprises: a clock terminal 101 configured to receive a clock signal; a common mode signal terminal 102 configured to receive a common mode signal, the common mode signal indicating a disturbance of a power supply or ground of the transmitting terminal; a transmitting terminal circuit 103 configured to: perform signal processing on a plurality of data signals, the clock signal and the common mode signal, wherein the signal processing comprises multiplexing and modulating the plurality of data signals; and output a first signal comprising the signal-processed plurality of data signals, clock signal and common mode signal; an isolation capacitor circuit 104 located between the transmitting terminal and the receiving terminal and configured to isolate a direct current component in the first signal to output a second signal; a receiving terminal circuit 105 configured to: demodulate the second signal to obtain a third signal corresponding to the plurality of data signals and a fourth signal corresponding to the clock signal; and demodulate and demultiplex the third signal based on the fourth signal.

[0024] At the transmitting terminal of the isolation circuit, the plurality of data signals are multiplexed based on the received clock signal to combine the plurality of data signals into one synchronous data packet and transmit the plurality of data signals through one channel, thereby reducing the number and cost of isolation capacitors required for isolating the direct current signal in the transmitted signal. In addition, the modulation of the data signal improves the suppression capability of the data signal to common mode interference. At the same time, in addition to transmitting the data signal at the transmitting terminal, the clock signal and the common mode signal are also transmitted, so that at the receiving terminal of the isolation circuit, the influence of the disturbance of the power supply or ground on the data signal can be removed based on the received common mode signal, thereby improving the common mode transient immunity of the circuit. Based on the received clock signal, the multiplexed data signal is demultiplexed to recover the plurality of data signals, thereby realizing the transmission of the data signal.

[0025] According to some embodiments, synchronous time division multiplexing can be used to modulate and demodulate the data signal, combine the plurality of data signals into one synchronous data packet, and transmit the signal through three channels at the transmitting terminal, respectively for transmitting the data signal, the common mode signal and the clock signal. The following embodiments will give a specific description of the isolation circuit using synchronous time division multiplexing.

[0026] Figure 2 is a schematic block diagram illustrating an example of the isolation circuit 100 of Figure 1 .

[0027] As shown in Figure 2As shown, in the isolation circuit employing synchronous time-division multiplexing, the transmitting circuit 103 includes: a time-division multiplexing synchronous hybrid modulator 201, which is used to multiplex and modulate the multiple data signals to output a fifth signal having one signal, and to modulate the clock signal to obtain a sixth signal; a first channel power amplifier 202, which is located in the first channel and is used to amplify the power of the fifth signal and output a seventh signal; a second channel power amplifier 203, which is located in the second channel and is used to amplify the power of the common-mode signal and output an eighth signal; and a third channel power amplifier 204, which is located in the third channel and is used to amplify the power of the sixth signal and output a ninth signal, wherein the seventh signal, the eighth signal, and the ninth signal are signal components of the first signal transmitted through different channels.

[0028] Inside the transmitting circuit 103, the data signal, common-mode signal, and clock signal are transmitted through three channels. A time-division multiplexing synchronous hybrid modulator 201 is used to multiplex and modulate the multiple data signals to output a fifth signal DATA0 with one channel, and to modulate the clock signal CLK to obtain a sixth signal CLK0. The modulated fifth signal DATA0, sixth signal CLK0, and common-mode signal VCM0 are then amplified by power amplifiers 203, 204, and 204 located in different channels to output amplified seventh signal DATA1, eighth signal VCM1, and ninth signal CLK1 in different channels. It can be understood that the seventh signal DATA1, eighth signal VCM1, and ninth signal CLK1 are the signal components transmitted through different channels in the first signal output by the transmitting circuit 103. Thus, multiple data signals can be transmitted through three channels.

[0029] Figure 3 It is shown in the figure. Figure 2 A schematic block diagram of an example of a time-division multiplexed synchronous hybrid modulator 201. (See attached diagram.) Figure 3 As shown, the time-division multiplexing synchronous hybrid modulator 201 includes: a first time-division multiplexer 301, which is used to time-division multiplex the multiple data signals based on the clock signal to merge the multiple data signals into one data signal; a first modulator 302, which is used to modulate the one data signal to obtain the fifth signal; and a second modulator 303, which is used to modulate the clock signal to obtain the sixth signal.

[0030] In operation, the first time division multiplexer 301 synchronously time-division multiplexes the plurality of data signals based on the clock signal CLK to combine the plurality of data signals into one data signal DATA. The first modulator 302 modulates the one data signal DATA to obtain a fifth signal DATA0. The second modulator 303 modulates the clock signal CLK to obtain a sixth signal CLK0. In the process of modulation, the first modulator 302 and the second modulator 303 can respectively perform various modulations, such as carrier modulation or edge modulation, on the one data signal DATA and the clock signal CLK based on a high-frequency carrier clock generated by a clock generator, and the disclosure does not limit the modulation mode of the signal. In one example, the first modulator 302 and the second modulator 303 can be On-Off Keying (OOK) modulators.

[0031] According to some embodiments, the first time division multiplexer 301 synchronously time-division multiplexes the plurality of data signals through a fixed frame structure, the plurality of data signals in the frame structure are synchronously coded and modulated by the clock signal, and then transmitted to the signal channel. Therefore, the data signal and the clock signal are completely symmetrical, so that the digital signal and the clock signal transmitted to the receiving end are also synchronous. Thus, the multiplexed data signal can be demultiplexed based on the clock signal recovered by the receiving end.

[0032] Figure 4 is a timing diagram illustrating a data signal frame structure multiplexing according to an exemplary embodiment of the disclosure. As shown in Figure 4 the data signal is sampled to obtain a plurality of data D0-DN and flag information in each high-level time slot of the clock signal CLK, wherein the flag information can include flag bits and check information. The sampled data D0-DN and flag information can be packaged into a synchronous data transmission package according to a fixed time slot. The synchronous transmission mechanism ensures that each data is in a fixed position. This greatly simplifies the process of multiplexing and demultiplexing, and at the same time, the small synchronous data transmission package can effectively improve the effective occupancy rate of the channel and improve the transmission speed of the signal.

[0033] According to some embodiments, the isolation capacitor circuit 104 includes: a first isolation capacitor for isolating a direct current component in the seventh signal to output a tenth signal; a second isolation capacitor for isolating a direct current component in the eighth signal to output an eleventh signal; and a third isolation capacitor for isolating a direct current component in the ninth signal to output a twelfth signal, wherein the tenth signal, the eleventh signal and the twelfth signal are signal components in the second signal transmitted through different channels.

[0034] In one example, each of the first isolation capacitor, the second isolation capacitor, and the third isolation capacitor is a single capacitor. In another example, each of the first isolation capacitor, the second isolation capacitor, and the third isolation capacitor is composed of a plurality of capacitors in series. It can be understood that the isolation capacitor needs to be able to withstand the maximum voltage difference between the two circuits, and when the voltage difference is large, two or more capacitors in series can be used to achieve this without affecting the analysis of signal transmission.

[0035] Thus, in Figure 2 the example, the three signal channels respectively correspond to an independent isolation capacitor circuit, and the entire circuit only needs three isolation capacitor circuits, so as to transmit multiple input signals, thereby reducing the cost of the circuit.

[0036] Corresponding to the transmitting end circuit 103 described above, in Figure 2 the example, the receiving end circuit 105 receives the tenth signal DATA2 corresponding to the data signal, the eleventh signal VCM2 corresponding to the common mode signal, and the twelfth signal CLK2 corresponding to the clock signal in the three channels respectively. As Figure 2 shown, the receiving end circuit 105 includes: a first filter 205 configured to filter the tenth signal to output a thirteenth signal; a second filter 206 configured to filter the eleventh signal to output a fourteenth signal; a third filter 207 configured to filter the twelfth signal to output a fifteenth signal; a first demodulator 208 configured to demodulate the thirteenth signal and the fifteenth signal based on the fourteenth signal to output the third signal corresponding to the thirteenth signal and the fourth signal corresponding to the fifteenth signal; and a first demultiplexer 209 configured to demultiplex the third signal based on the fourth signal.

[0037] Inside the receiving circuit 105, the tenth signal DATA2 corresponding to the data signal, the eleventh signal VCM2 corresponding to the common-mode signal, and the twelfth signal CLK2 corresponding to the clock signal are filtered in three channels by the first filter 205, the second filter 206, and the third filter 207, respectively, to output the thirteenth signal DATA3, the fourteenth signal VCM3, and the fifteenth signal CLK3 for demodulation. The first demodulator 208 demodulates the thirteenth signal DATA3 corresponding to the data signal and the fifteenth signal CLK3 corresponding to the clock signal based on the fourteenth signal VCM3 corresponding to the common-mode signal, to output the demodulated data signal (i.e., the third signal DATA4) and the demodulated clock signal (i.e., the fourth signal CLK4). Because the data signal path and the clock signal path are completely symmetrical, the third signal DATA4 and the fourth signal CLK4 are completely synchronized. The first demultiplexer 209 only needs to sample the fourth signal CLK4 in a fixed time slot to obtain the data signal of a fixed path, so as to output multiple data signals. Compared to asynchronous serial systems, synchronous time-division multiplexing and demultiplexing ensure the authenticity and interference resistance of data signals. Furthermore, using a single synchronous clock signal for synchronous modulation and demodulation of data signals can significantly reduce the bit error rate and improve the signal's noise immunity.

[0038] Figure 5 It is shown in the figure. Figure 2 A schematic block diagram of an example of the first demodulator 208. Figure 5 As shown, the first demodulator 208 includes: a first differential amplifier 501, which is used to differentially amplify the thirteenth signal and the fourteenth signal to obtain the sixteenth signal; a second differential amplifier 502, which is used to differentially amplify the fifteenth signal and the fourteenth signal to obtain the seventeenth signal; a first envelope detector 503, which is used to perform envelope detection on the sixteenth signal to output the third signal; and a second envelope detector 504, which is used to perform envelope detection on the seventeenth signal to output the fourth signal.

[0039] In operation, the first demodulator 208 receives the fourteenth signal VCM3 corresponding to the common mode signal, the thirteenth signal DATA3 corresponding to the data signal and the fifteenth signal CLK3 corresponding to the clock signal, and differentially amplifies the thirteenth signal DATA3 and the fourteenth signal VCM3 and the fifteenth signal CLK3 and the fourteenth signal VCM3 respectively to remove the effect of the differential mode signal on the data signal and the clock signal, and obtain the data signal (i.e. the sixteenth signal DATA5) and the clock signal (i.e. the seventeenth signal CLK5) removed of the effect of the common mode signal, thereby improving the anti-interference capability of the signals. The data signal (the sixteenth signal DATA5) and the clock signal (the seventeenth signal CLK5) removed of the effect of the common mode signal will be envelope detected by the first envelope detector 503 and the second envelope detector 504 respectively to obtain the demodulated data signal (the third signal DATA4) and the clock signal (the fourth signal CLK4). The two signals will be transmitted to the first demultiplexer 209 for demultiplexing of the data signal.

[0040] Figure 6 is a schematic diagram illustrating multiplexing and demultiplexing of data signals according to an exemplary embodiment of the present disclosure. The first time division multiplexer 301 synchronously time-division multiplexes multiple data signals by a fixed frame structure, so that the data signal of each channel corresponds to a fixed time slot, while ensuring that the data signal channel and the clock signal channel are completely symmetrical in the receiving end circuit before being transmitted to the first demultiplexer 209, and that the data signal of a fixed channel can be obtained by sampling based on the clock signal in the fixed time slot to output multiple data signals. This synchronous time-division multiplexing and synchronous demultiplexing process ensures the fidelity and anti-interference capability of the data signal.

[0041] According to some embodiments, quasi-synchronous time-division multiplexing can also be used to modulate multiple data signals and clock signals, and the modulated multiple data signals, clock signals and common mode signals are transmitted through a single channel, thereby further reducing the number of isolation capacitor circuits. The following embodiments will give a specific description of the quasi-synchronous time-division multiplexing isolation circuit.

[0042] Figure 7 is a schematic block diagram of a quasi-synchronous time-division multiplexing isolation circuit 700 as an example of the isolation circuit 100 in Figure 1 Figure 7 ​As shown, in the quasi-synchronous time-division multiplexing isolation circuit 700, the transmitting circuit 103 includes: a time-division multiplexing quasi-synchronous hybrid modulator 701, which is used to multiplex the multiple data signals to obtain a multiplexed data signal, and to mix and modulate the data signal with the clock signal to obtain an eighteenth signal; and a fourth-channel power amplifier 702, which is used to amplify the power of the eighteenth signal by using the common-mode signal as a reference level, so as to output the first signal in a single channel.

[0043] In the quasi-synchronous time-division multiplexing isolation circuit 700, the time-division multiplexing quasi-synchronous hybrid modulator 701 uses quasi-synchronous transmission (PDH) to modulate and demodulate the data signal, so that the data signal, clock signal, and common-mode signal are gradually combined in multiple modules to transmit the above three types of signals in a single channel. In the quasi-synchronous time-division multiplexing isolation circuit 700, only one path is needed to transmit multiple data signals, thus requiring a corresponding isolation capacitor circuit to isolate the DC component, further reducing the cost of the circuit.

[0044] Figure 8 It is shown in the figure. Figure 7 A schematic block diagram of an example of a time-division multiplexed quasi-synchronous hybrid modulator 701. (See attached diagram.) Figure 8 As shown, the time-division multiplexing quasi-synchronous hybrid modulator 701 includes: a second time-division multiplexer 801, which is used to time-division multiplex the multiple data signals based on the clock signal to obtain the single data signal; a time-division multiplexing mixer 802, which is used to mix the clock signal into the single data signal in a byte-interleaved multiplexing manner to output a nineteenth signal; and a third modulator 803, which is used to modulate the nineteenth signal to obtain the eighteenth signal.

[0045] In operation, the second time division multiplexer 801 synchronously time division multiplexes the multiple data signals based on the clock signal CLK to combine the multiple data signals into one data signal DATA9, and the time division multiplexing mixer 802 mixes the clock signal CLK into the one data signal DATA9 in a byte-interleaved multiplexing manner to obtain one signal DATA10 containing the data signal and the clock signal for transmission to the third modulator 803 for modulation. For example, the process of mixing the clock signal CLK into the DATA9 in a byte-interleaved multiplexing manner can be to insert the corresponding clock signal in front of the data signal of each multiplexed channel to obtain one data packet in which the data signal and the clock signal are interleaved. In the process of modulation, the one signal DATA10 can be subjected to various modulations such as carrier modulation or edge modulation based on the high-frequency carrier clock generated by the clock generator, and the modulation manner of the signal is not limited in the present disclosure. In one example, the third modulator 803 can be an On-Off Keying (OOK) modulator.

[0046] According to some embodiments, in the quasi-synchronous time division multiplexing isolation circuit 700, the isolation capacitor circuit 104 comprises a fourth isolation capacitor for isolating the direct current component in the first signal to output the second signal.

[0047] In one example, the fourth isolation capacitor is a single capacitor. In one example, the fourth isolation capacitor is composed of a plurality of capacitors connected in series. It can be understood that the isolation capacitor needs to be able to withstand the maximum voltage difference between the two circuits, and when the voltage difference is large, two or more capacitors can be connected in series to achieve without affecting the analysis of signal transmission.

[0048] Thus, in the quasi-synchronous time division multiplexing isolation circuit 700, the multiple data signals, the clock signal and the common mode signal are transmitted through only one channel, which corresponds to an independent isolation capacitor circuit, and the entire circuit only needs one isolation capacitor circuit to transmit the multiple input signals, thereby reducing the cost of the circuit.

[0049] Accordingly, in the quasi-synchronous time division multiplexing isolation circuit 700, the receiving end circuit 105 comprises: an active filter 703, configured to perform high-pass filtering on the second signal to output a twentieth signal, and configured to perform low-pass filtering on the second signal to output a twenty-first signal; a second demodulator 704, configured to demodulate the twentieth signal based on the twenty-first signal to output a twenty-second signal; a time division multiplexing frequency divider 705, configured to divide the frequency of the twenty-second signal to output the third signal and the fourth signal; and a second demultiplexer 706, configured to demultiplex the third signal based on the fourth signal.

[0050] Inside the receiving end circuit 105, the second signal output by the isolation capacitor circuit 104 is high-pass filtered and low-pass filtered by the active filter 703 to sort out the twentieth signal DATA6 corresponding to the data signal with high frequency and the twenty-first signal VCM4 corresponding to the common mode signal with low frequency, for demodulation by the second demodulator 704. Then, the influence of the common mode signal in the data signal is removed by differential amplification, and the corresponding data signal twenty-second signal DATA7 is detected by envelope detection. The time division multiplexing frequency divider 705 divides the frequency of the twenty-second signal DATA7 to distinguish the multiplexed data signal and clock signal, and outputs the third signal DATA8 and the fourth signal CLK6. The second demultiplexer 706 can demultiplex the multiplexed data signal (i.e., the third signal DATA8) based on the clock signal (i.e., the fourth signal CLK7) obtained by frequency division, to output the multipath data signal.

[0051] Figure 9 is a schematic diagram illustrating multiplexing and demultiplexing of data signals according to an exemplary embodiment of the present disclosure. The time division multiplexing quasi-synchronous hybrid modulator 701 first synchronously multiplexes the multipath data signal into one data signal based on the clock signal, and then packs the multiplexed data signal with the clock signal in the time division multiplexing frequency mixer 802 in the form of byte interleaving (i.e., inserting the clock signal corresponding to each data signal before the signal), while adding an identification code at the beginning or end of the packet to locate the frame header for frequency division of the mixed signal at the receiving end. The time division multiplexing frequency divider 705 can obtain the multiplexed data signal and clock signal by byte interleaving extraction after finding the frame header in the mixed data, and then demultiplex the multiplexed data signal by the second demultiplexer 706 to output the multipath data signal.

[0052] While the disclosure has been illustrated and described in detail in the drawings and foregoing description, such illustration and description is to be considered illustrative or exemplary and not restrictive; the disclosure is not limited to the disclosed embodiments. Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed subject matter, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, the word "a" or "an" does not exclude a plurality, the term "multiple" means two or more, and the term "based on" means "based at least in part on." The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. An isolation circuit for isolating a transmitting end and a receiving end, comprising: a clock end configured to receive a clock signal; a common mode signal end configured to receive a common mode signal, the common mode signal indicating a disturbance of a power supply or a ground of the transmitting end; a transmitting end circuit configured to: signal process one or more of a plurality of data signals, the clock signal, and the common mode signal, wherein the signal processing comprises multiplexing and modulating the plurality of data signals; and output a first signal, wherein the transmitting end circuit comprises: a time division multiplexing synchronous hybrid modulator for multiplexing and modulating the plurality of data signals to output a fifth signal having one signal, and modulating the clock signal to obtain a sixth signal; a first channel power amplifier located in a first channel and configured to power amplify the fifth signal and output a seventh signal; and a third channel power amplifier located in a third channel and configured to power amplify the sixth signal and output a ninth signal, wherein the seventh signal and the ninth signal are signal components of the first signal transmitted via different channels; an isolation capacitance circuit located between the transmitting end and the receiving end and configured to isolate a direct current component in the first signal to output a second signal; a receiving end circuit configured to: demodulate the second signal to obtain a third signal corresponding to the plurality of data signals and a fourth signal corresponding to the clock signal; and based on the fourth signal, demultiplex the third signal.

2. The isolation circuit of claim 1, wherein, The transmitting end circuit further comprises a second channel power amplifier located in a second channel and configured to power amplify the common mode signal and output an eighth signal, and wherein the eighth signal, the seventh signal and the ninth signal are signal components of the first signal transmitted via different channels.

3. The isolated circuit of claim 1 or 2, wherein, The time division multiplexing synchronous hybrid modulator comprises: a first time division multiplexer for time division multiplexing the plurality of data signals based on the clock signal to combine the plurality of data signals into one data signal; a first modulator for modulating the one data signal to obtain the fifth signal; and a second modulator for modulating the clock signal to obtain the sixth signal.

4. The isolation circuit of claim 3, wherein, The first time division multiplexer synchronously time division multiplexes the plurality of data signals by a fixed frame structure, and the plurality of data signals in the frame structure are synchronously coded modulated by the clock signal.

5. The isolation circuit of claim 3, wherein, The first time division multiplexer samples the plurality of data signals within a fixed level time slot of the clock signal, and packs the sampled data and flag information into a synchronous data transmission packet according to a fixed time slot.

6. The isolation circuit of claim 5, wherein, The flag information includes flag bits and check information.

7. The isolated circuit of claim 3, wherein, The first modulator and / or the second modulator is a binary on-off keying modulator.

8. The isolation circuit of claim 3, wherein, The modulation mode of the first modulator and / or the second modulator comprises carrier modulation and edge modulation.

9. The isolation circuit of claim 1, wherein, The isolation capacitor circuit comprises: a first isolation capacitor for isolating a direct current component in the seventh signal to output a tenth signal; and a third isolation capacitor for isolating a direct current component in the ninth signal to output a twelfth signal, wherein the tenth signal and the twelfth signal are signal components of the second signal transmitted through different channels.

10. The isolation circuit of claim 2, wherein, The isolation capacitor circuit comprises: a first isolation capacitor for isolating a direct current component in the seventh signal to output a tenth signal; a second isolation capacitor for isolating a direct current component in the eighth signal to output an eleventh signal; and a third isolation capacitor for isolating a direct current component in the ninth signal to output a twelfth signal, wherein the tenth signal, the eleventh signal and the twelfth signal are signal components of the second signal transmitted through different channels.

11. The isolation circuit of claim 10, wherein, One or more of the first isolation capacitor, the second isolation capacitor and the third isolation capacitor is a single capacitor or is composed of a plurality of capacitors in series.

12. The isolation circuit of claim 9, wherein, The receiving end circuit comprises: a first filter for filtering the tenth signal to output a thirteenth signal; a third filter for filtering the twelfth signal to output a fifteenth signal; a first demodulator for demodulating the thirteenth signal and the fifteenth signal to output the third signal corresponding to the thirteenth signal and the fourth signal corresponding to the fifteenth signal; and a first demultiplexer for demultiplexing the third signal based on the fourth signal.

13. The isolation circuit of claim 10, wherein, The receiving end circuit comprises: a first filter for filtering the tenth signal to output a thirteenth signal; a second filter for filtering the eleventh signal to output a fourteenth signal; a third filter for filtering the twelfth signal to output a fifteenth signal; a first demodulator for demodulating the thirteenth signal and the fifteenth signal based on the fourteenth signal to output the third signal corresponding to the thirteenth signal and the fourth signal corresponding to the fifteenth signal; and a first demultiplexer for demultiplexing the third signal based on the fourth signal.

14. The isolated circuit of claim 12 or 13, wherein, The first demultiplexer samples the fixed time slot based on the clock signal to obtain the fixed channel data signal and outputs the multi-channel data signal.

15. The isolated circuit of claim 12 or 13, wherein, The first demodulator comprises: a first differential amplifier for differentially amplifying the thirteenth signal and the fourteenth signal to obtain a sixteenth signal; a second differential amplifier configured to differentially amplify the fifteenth signal and the fourteenth signal to obtain a seventeenth signal; a first envelope detector configured to perform envelope detection on the sixteenth signal to output the third signal; and a second envelope detector configured to perform envelope detection on the seventeenth signal to output the fourth signal.

16. The isolation circuit of claim 1, wherein, The transmitting end circuit comprises: a time division multiplexing quasi-synchronous hybrid modulator configured to multiplex the multiple data signals to obtain one data signal, and to perform hybrid modulation on the one data signal and the clock signal to obtain an eighteenth signal; and a fourth channel power amplifier configured to perform power amplification on the eighteenth signal by taking the common mode signal as a reference level to output the first signal in a single channel.

17. The isolation circuit of claim 16, wherein, The time division multiplexing quasi-synchronous hybrid modulator comprises: a second time division multiplexer configured to time division multiplex the multiple data signals based on the clock signal to obtain the one data signal; a time division multiplexing frequency mixer configured to mix the clock signal into the one data signal in a byte interleaving multiplexing manner to output a nineteenth signal; and a third modulator configured to modulate the nineteenth signal to obtain the eighteenth signal.

18. The isolation circuit of claim 17, wherein, The byte interleaving multiplexing is to insert a corresponding clock signal in front of a data signal of each of the multiple data signals to obtain a data packet in which data signals and clock signals are interleaved and staggered.

19. The isolation circuit of claim 18, wherein, An identification code is added to a packet header or a packet tail of the data packet to locate a frame header.

20. The isolated circuit of claim 17, wherein, The third modulator is a binary on-off keying modulator.

21. The isolated circuit of claim 17, wherein, The modulation mode of the third modulator comprises carrier modulation and edge modulation.

22. The isolation circuit of claim 16, wherein, The isolation capacitor circuit comprises: a fourth isolation capacitor configured to isolate a direct current component in the first signal to output the second signal.

23. The isolation circuit of claim 22, wherein, The fourth isolation capacitor is a single capacitor or is composed of multiple capacitors in series.

24. The isolation circuit of claim 1, wherein, The receiving end circuit comprises: an active filter configured to perform high-pass filtering on the second signal to output a twentieth signal, and to perform low-pass filtering on the second signal to output a twenty-first signal; a second demodulator configured to demodulate the twentieth signal based on the twenty-first signal to output a twenty-second signal; a time division multiplexing frequency divider configured to divide the twenty-second signal to output the third signal and the fourth signal; and a second demultiplexer configured to demultiplex the third signal based on the fourth signal.

25. The isolated circuit of claim 24, wherein, The second demodulator removes the influence of the common mode signal in the twentieth signal by differential amplification, and detects the twenty-second signal corresponding to the twentieth signal by envelope detection.

26. The isolated circuit of claim 24, wherein, The time division multiplexing frequency divider obtains the third signal and the fourth signal by byte interleaving extraction.

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