Signal gain value judgment circuit and related method

Abstract

The present invention discloses a signal gain value judgment circuit and related methods. The signal gain value judgment circuit includes a digital comparator, a digital controller, and an arithmetic module. A first buffer is used to store a predetermined count value. A sensing integration circuit generates a first count value based on a first sensing signal within a first integration time. The digital comparator is used to compare the first count value with the predetermined count value to generate a comparison result. The digital controller is used to generate a control signal indicating a signal gain value based on the comparison result to provide to a signal amplifier of the sensing integration circuit; wherein the signal amplifier adjusts the first sensing signal based on the signal gain value to generate a second sensing signal, so that the sensing integration circuit generates a second count value corresponding to the second sensing signal within a second integration time. The arithmetic module is used to generate an output count value corresponding to the first sensing signal based on the second count value and the signal gain value.

Description

Technical Field

[0001] The present invention relates to a signal gain value judgment circuit and a related method, and in particular to a signal gain value judgment circuit and a related method for a sensing integration circuit. Background Art

[0002] In existing sensors (such as light, pressure, power, and temperature sensors), for example, when the integrated voltage value of the raw sensing signal increases to a predetermined reference voltage within a predetermined integration time, the integrator is reset. Simultaneously, a counter accumulates the number of times the integrated voltage value increases to the set reference voltage value. When the predetermined integration time expires, the counter value is read to obtain the count value corresponding to the raw sensing signal within the predetermined integration time.

[0003] Figure 1 A graph CN_1 is a diagram showing the count value versus signal-to-noise ratio (SNR) of a conventional sensing integration circuit. In practical applications, the applicant has noticed that the signal strength of the noise floor is usually within a certain range, and the noise floor is not proportional to the signal strength of the original sensing signal. In detail, Figure 1 As shown, when the conventional sensor operates in a range of relatively low sensing signal strength, the background noise intensity is high when the sensing signal strength is low, resulting in a poor signal-to-noise ratio. On the other hand, when the sensing signal strength is high, the background noise intensity is low when the sensing signal strength is high, resulting in a good signal-to-noise ratio.

[0004] Figure 2 A curve CS_1 is a schematic diagram showing the sensing signal versus count value of a conventional sensing integration circuit. When the sensing signal changes, the corresponding count value may change disproportionately, such as Figure 2 As shown, the slope of the curve CS_1 is not a constant value, so the linearity performance of the conventional sensing integration circuit may not be good enough and is therefore not suitable for products with strict requirements on linearity performance.

[0005] In short, because the noise floor and the signal strength of the original sensing signal do not scale proportionally, existing sensors experience uneven signal-to-noise ratios when operating in different sensing signal ranges. Furthermore, the count values ​​corresponding to changes in the sensing signal do not change proportionally in existing sensing integration circuits, making them unsuitable for products with stringent linearity requirements.

[0006] Therefore, how to improve the uniformity of the signal-to-noise ratio of the sensor when operating in different sensing signal ranges, and how to improve the linearity of existing sensors have become one of the important issues to be solved in this field. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a signal gain value judgment circuit to improve the uniformity and linearity of the signal-to-noise ratio of the sensor in response to the shortcomings of the prior art.

[0008] In addition, one of the technical solutions adopted by the present invention is to provide a signal gain value determination circuit for use in a sensing integration circuit. The signal gain value determination circuit includes a first buffer, a second buffer, a digital comparator, a digital controller, a third buffer, an arithmetic module, and a fourth buffer. The first buffer is used to store a predetermined count value. The second buffer is used to store a first count value. The sensing integration circuit generates the first count value based on a first sensing signal within a first integration time. The digital comparator is coupled to the first buffer and the second buffer and is used to compare the first count value with the predetermined count value after the first integration time to generate a comparison result. The digital controller is coupled to the digital comparator and is configured to determine a signal gain value based on the comparison result, thereby generating a control signal indicating the signal gain value to a signal amplifier of the sensing integration circuit. The signal amplifier adjusts the first sensing signal based on the signal gain value to generate a second sensing signal, causing the sensing integration circuit to generate a second count value corresponding to the second sensing signal within a second integration time. The second register stores the second count value after the second integration time. The third register is coupled to the digital controller and is configured to store the signal gain value. The arithmetic module is coupled to the third register and the second register and is configured to generate an output count value corresponding to the first sensing signal based on the second count value and the signal gain value after the second integration time. The fourth register is configured to store the output count value.

[0009] Preferably, when the comparison result indicates that the first count value is less than the predetermined count value, the signal gain value is greater than 1; and when the comparison result indicates that the first count value is not less than the predetermined count value, the signal gain value is equal to 1.

[0010] Preferably, when the signal gain value is greater than 1, the signal amplifier amplifies the first sensing signal according to the signal gain value to generate the second sensing signal, so that the second count value corresponding to the second sensing signal is greater than the first count value corresponding to the first sensing signal.

[0011] Preferably, the arithmetic module divides the second count value by the signal gain value after the second integration time to generate the output count value corresponding to the first sensing signal.

[0012] Preferably, when the second integration time is X times the first integration time, the arithmetic module multiplies the second count value by X times and divides it by the signal gain value after the second integration time to generate the output count value corresponding to the first sensing signal, where X is a value greater than 1.

[0013] Preferably, the first buffer is used to store N predetermined count values, and the N predetermined count values ​​correspond to N signal gain values ​​respectively.

[0014] Preferably, the M+1th predetermined count value among the N predetermined count values ​​is greater than the Mth predetermined count value; the M+1th signal gain value among the N signal gain values ​​is less than the Mth signal gain value; and N and M are positive integers, and 1≤M<N.

[0015] Preferably, the N predetermined count values ​​are predetermined according to at least a target signal-to-noise ratio of the sensing integration circuit.

[0016] Furthermore, one of the technical solutions employed by the present invention is a method for determining a signal gain value for a sensing integration circuit. The method includes configuring the sensing integration circuit to generate a first count value corresponding to a first sensing signal within a first integration time; after the first integration time, comparing the first count value with a predetermined count value to generate a comparison result; determining a signal gain value based on the comparison result to generate a control signal indicating the signal gain value; adjusting the first sensing signal based on the signal gain value to generate a second sensing signal; configuring the sensing integration circuit to generate a second count value corresponding to the second sensing signal within a second integration time; and after the second integration time, generating an output count value corresponding to the first sensing signal based on the second count value and the signal gain value.

[0017] Preferably, based on the comparison result, the step of determining the signal gain value includes: when the comparison result indicates that the first count value is less than the predetermined count value, the signal gain value is greater than 1; and when the comparison result indicates that the first count value is not less than the predetermined count value, the signal gain value is equal to 1.

[0018] Preferably, when the signal gain value is greater than 1, the signal amplifier amplifies the first sensing signal according to the signal gain value to generate the second sensing signal, so that the second count value corresponding to the second sensing signal is greater than the first count value corresponding to the first sensing signal.

[0019] Preferably, after the second integration time, the step of generating the output count value corresponding to the first sensing signal according to the second count value and the signal gain value includes dividing the second count value by the signal gain value to generate the output count value corresponding to the first sensing signal.

[0020] Preferably, when the second integration time is X times the first integration time, after the second integration time, the step of generating the output count value corresponding to the first sensing signal based on the second count value and the signal gain value includes multiplying the second count value by X times and dividing it by the signal gain value to generate the output count value corresponding to the first sensing signal, where X is a value greater than zero.

[0021] Preferably, the method further comprises configuring a first buffer to store the predetermined count value, wherein the predetermined count value comprises N predetermined count values.

[0022] Preferably, the M+1th predetermined count value among the N predetermined count values ​​is greater than the Mth predetermined count value; the N predetermined count values ​​correspond to N signal gain values ​​respectively, and the M+1th signal gain value among the N signal gain values ​​is less than the Mth signal gain value; and N and M are positive integers, and 1≤M<N.

[0023] Preferably, the method further comprises presetting the N predetermined count values ​​according to at least one predetermined signal-to-noise ratio.

[0024] One of the beneficial effects of the present invention is that the signal gain value determination circuit and related method provided by the present invention can achieve a more uniform signal-to-noise ratio distribution within the entire operating range of the sensor, while also improving the sensor's linearity, by employing the technical solution of "comparing a first count value corresponding to a first sensing signal with a predetermined count value within a first integration time to determine a signal gain value corresponding to the first sensing signal; adjusting the first sensing signal based on the signal gain value to generate a second sensing signal; generating a second count value corresponding to the second sensing signal within a second integration time; and, after the second integration time, generating an output count value corresponding to the first sensing signal based on the second count value and the signal gain value."

[0025] To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are only for reference and illustration and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 FIG. 4 is a diagram showing a curve of count value versus signal-to-noise ratio of a conventional sensing integration circuit.

[0027] Figure 2 FIG. 1 is a schematic diagram of a curve showing a sensing signal versus a count value of a conventional sensing integration circuit.

[0028] Figure 3 FIG. 1 is a functional block diagram of a sensing integration circuit and a signal gain value determination circuit according to a first embodiment of the present invention.

[0029] Figure 4 1 is a signal timing diagram of the integration time, calculation time, integration node voltage, first count value and predetermined count value according to the first embodiment of the present invention.

[0030] Figure 5 FIG. 4 is a schematic diagram of a curve showing count value versus signal-to-noise ratio according to the first embodiment of the present invention.

[0031] Figure 6 FIG. 4 is a flow chart of a method for determining a signal gain value according to a first embodiment of the present invention.

[0032] Figure 7 FIG. 1 is a signal timing diagram of the integration time, calculation time, integration node voltage, first count value, and predetermined count value according to the second embodiment of the present invention.

[0033] Figure 8 FIG. 4 is a schematic diagram of a curve of count value versus signal-to-noise ratio according to the second embodiment of the present invention.

[0034] Figure 9 FIG. 4 is a schematic diagram of a curve of count value versus signal-to-noise ratio according to the third embodiment of the present invention.

[0035] Figure 10 FIG. 1 is a graph showing a curve of sensing signals versus count values ​​according to a third embodiment of the present invention. DETAILED DESCRIPTION

[0036] The following content illustrates the implementation of the "signal gain value judgment circuit and related methods" disclosed in the present invention through specific specific embodiments. Those skilled in the art can understand the advantages and effects of the present invention from the contents disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not depicted according to actual dimensions. It is stated in advance. The following embodiments will further explain the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the scope of protection of the present invention. In addition, the term "or" used in this article may include any one or more combinations of the associated listed items depending on the actual situation.

[0037] [First embodiment]

[0038] Figure 3 FIG. 1 is a functional block diagram of a sensing integration circuit 10 and a signal gain value determination circuit 12 according to an embodiment of the present invention. The circuit structure of the sensing integration circuit 10 is as follows: Figure 3As shown, it includes a reset switch S1, a sensing unit SD, a signal amplifier CA, an operational amplifier OP, an integrating capacitor Cint, a comparator CP, and a counter CT. The sensing unit SD is, for example, a photodiode, used to generate a first sensing signal S11 (such as a light sensing current) to the signal amplifier CA. In other embodiments, the sensing unit SD can be a sensor for sensing pressure, temperature, or electricity, but is not limited thereto. During a first integration time T1 ( Figure 4 (shown), the gain of the signal amplifier CA is preset to 1, so the magnitude of the first sensing signal S11 is not adjusted. Furthermore, the first sensing signal S11 charges the integrating capacitor Cint, generating an integrated voltage Vint at the output of the operational amplifier OP and the first input of the comparator CP. The second input of the comparator CP is configured to receive a reference voltage Vref. Whenever the integrated voltage Vint increases to the reference voltage Vref, the output of the comparator CP generates a comparison voltage Vcomp, causing the reset switch S1 to reset the sensing unit SD based on the comparison voltage Vcomp (e.g., grounding the cathode of the sensing unit SD and the input of the signal amplifier CA to discharge the integrated voltage Vint on the integrating capacitor Cint back to zero). Simultaneously, whenever the integrated voltage Vint increases to the reference voltage Vref, the counter CT increments by 1 based on the comparison voltage Vcomp. When the first integration time T1 expires, the counter CT outputs the accumulated count value (i.e., the first count value D11) to the signal gain value determination circuit 12. In short, the sensing integration circuit 10 enables the counter CT to generate a first count value D11 to the signal gain value determination circuit 12 according to the first sensing signal S11 generated by the sensing unit SD within the first integration time T1 .

[0039] The signal gain value determination circuit 12 is coupled to the sensing integration circuit 10 and includes a first register REG1 , a second register REG2 , a third register REG3 , a fourth register REG4 , an arithmetic module MC, a digital comparator DCP, and a digital controller DC.

[0040] The first register REG1 is coupled to the digital comparator DCP and is configured to store a predetermined count value Dth. The second register REG2 is coupled to the counter CT, the digital comparator DCP, and the arithmetic module MC and is configured to store a first count value D11 within a first integration time T1. The digital comparator DCP is coupled to the first register REG1, the second register REG2, and the digital controller DC and is configured to compare the first count value D11 with the predetermined count value Dth after the first integration time T1 to generate a comparison result Dresult. The digital controller DC is coupled to the digital comparator DCP, the third register REG3, and the signal amplifier CA and is configured to determine a signal gain value GS11 based on the comparison result Dresult within a first calculation time Tset. The digital controller DC generates a control signal CTRL indicating the signal gain value GS11 to the signal amplifier CA. Simultaneously, the digital controller DC outputs the signal gain value GS11 to the third register REG3, causing the third register REG3 to store the signal gain value GS11. The signal amplifier CA adjusts the first sensing signal S11 according to the signal gain value GS11 to generate a second sensing signal S12, causing the sensing integration circuit 10 to generate a second count value D12 corresponding to the second sensing signal S12 within a second integration time T2. The second register REG2 stores the second count value D12 after the second integration time T2. The arithmetic module MC is coupled to the second register REG2, the third register, and the fourth register REG4. It is configured to generate an output count value Dout corresponding to the first sensing signal S11 based on the second count value D12 and the signal gain value GS11 within a second calculation time Tout after the second integration time T2. Simultaneously, the arithmetic module MC outputs the output count value Dout to the fourth register REG4, causing the fourth register REG4 to store the output count value Dout.

[0041] Figure 4 1 is a signal timing diagram of the integration time, calculation time, integration node voltage, first count value D11 and predetermined count value according to the first embodiment of the present invention. Figure 4 As shown, during the first integration time T1, the first sensing signal S11 charges and integrates the integrating capacitor Cint. Each time the integrated voltage Vint increases to the reference voltage Vref, the accumulated count value Dcount recorded by the counter CT is incremented by 1. Therefore, the curve of the accumulated count value Dcount increases as the first integration time T1 elapses. After the first integration time T1 ends, the accumulated count value Dcount is less than the predetermined count value Dth, indicating that the sensing integration circuit 10 is operating within a relatively small range of the first sensing signal S11. Therefore, there is a high probability that the first sensing signal S11 will be affected by noise, resulting in a poor signal-to-noise ratio.

[0042] Therefore, to reduce the probability of first sensing signal S11 being affected by noise, within a first calculation time Tset following first integration time T1, the digital controller DC determines, based on the comparison result Dresult (i.e., the first count value D11 being less than the predetermined count value Dth), that the first sensing signal S11 needs to be amplified (thereby increasing the proportion of the first sensing signal S11 in the noise floor). Accordingly, the digital controller DC outputs a control signal CTRL to set the gain of the signal amplifier CA, causing the signal amplifier CA to generate a second sensing signal S12 having a signal strength greater than that of the first sensing signal S11. In other words, when the signal gain is greater than 1, the signal amplifier CA amplifies the first sensing signal S11 according to the signal gain to generate the second sensing signal S12, such that the second count value D12 corresponding to the second sensing signal S12 is greater than the first count value D11 corresponding to the first sensing signal S11.

[0043] During the second integration time T2, the second sensing signal S12 charges and integrates the integrating capacitor Cint. The curve of the accumulated count value Dcount increases as the second integration time T2 elapses. After the second integration time T2 ends, the accumulated count value Dcount is greater than the predetermined count value Dth, indicating that the sensing integration circuit 10 operates within a relatively large range of the second sensing signal S12. Therefore, the probability of the second sensing signal S12 being affected by noise and resulting in a poor signal-to-noise ratio is low. However, to truly represent the actual count value corresponding to the first sensing signal S11, during the second calculation time Tout after the second integration time T2 ends, the arithmetic module MC divides the second count value D12 by the signal gain value GS11 to generate an output count value Dout corresponding to the first sensing signal S11, thereby restoring the output count value Dout corresponding to the first sensing signal S11.

[0044] Figure 5 Schematic diagrams of curves CN_1 and CN_2 showing count value versus signal-to-noise ratio according to a first embodiment of the present invention. In the first embodiment, when the comparison result Dresult indicates that the first count value D11 is less than the predetermined count value Dth, the signal gain value GS11 is greater than 1; and when the comparison result Dresult indicates that the first count value D11 is not less than the predetermined count value Dth, the signal gain value is equal to 1. In other words, when the signal gain value GS11 is greater than 1, the first sensing signal S11 is amplified into the second sensing signal S12 to generate a curve CN_2 with a larger rising slope, thereby improving the signal-to-noise ratio of the sensing signal with a smaller signal strength; and when the signal gain value GS11 is equal to 1, the first sensing signal S11 remains unchanged to generate a curve CN_1 with a smaller rising slope (this portion of the curve CN_1 is different from the curve CN_1). Figure 1The corresponding curves are the same), thus maintaining the operational performance of the sensing integrator circuit 10 when the sensing signal strength is relatively high. In other words, the signal gain value determination circuit 12 of the present invention can improve the signal-to-noise ratio when the sensing signal strength is relatively low, without affecting the operational performance of the sensing integrator circuit 10.

[0045] The operation of the signal gain value determination circuit 12 can be summarized as a signal gain value determination process, such as Figure 6 As shown, the process includes the following steps:

[0046] Step S10: Start.

[0047] Step S11 : configuring the sensing integration circuit to generate a first count value corresponding to a first sensing signal within a first integration time.

[0048] Step S12: After the first integration time, compare the first count value with the predetermined count value to generate a comparison result.

[0049] Step S13: Determine the signal gain value according to the comparison result to generate a control signal indicating the signal gain value.

[0050] Step S14: adjusting the first sensing signal according to the signal gain value to generate a second sensing signal.

[0051] Step S15 : configuring the sensing integration circuit to generate a second counting value corresponding to the second sensing signal within a second integration time.

[0052] Step S16 : After the second integration time, generate an output count value corresponding to the first sensing signal according to the second count value and the signal gain value.

[0053] Step S17: End.

[0054] exist Figure 6 In the embodiment, step S11 can be performed by the sensing integration circuit 10, step S12 can be performed by the digital comparator DCP, step S13 can be performed by the digital controller DC, step S14 can be performed by the signal amplifier CA, step S15 can be performed by the sensing integration circuit 10, and step S16 can be performed by the arithmetic module MC. Figure 6 For detailed description, please refer to Figures 1 to 5 The description is not repeated here.

[0055] [Second embodiment]

[0056] Figure 7The following is a timing diagram of the integration time, calculation time, integration node voltage, first count value, and predetermined count value according to a second embodiment of the present invention. Assuming the linearity of the sensing integration circuit 10 is within an allowable range, when the second integration time T2 is X times the first integration time T1', the arithmetic module MC multiplies the second count value by X times and divides it by the signal gain value GS11 during a second calculation time Tout following the second integration time, to generate an output count value Dout corresponding to the first sensing signal S11, where X is a value greater than 1. For example, when X is equal to 2, it means that the second integration time T2 is twice the first integration time T1', which is equivalent to the first integration time T1' being half the second integration time T2. Therefore, the first count value D11' generated by the first sensing signal S11 during the first integration time T1' is equivalent to half the first count value D11 during the first integration time T1. Accordingly, in order to truly represent the actual count value corresponding to the first sensing signal S11, within the second calculation time Tout after the second integration time T2, the arithmetic module MC multiplies the second count value D12 by X times (e.g., 2) and divides the result by the signal gain value GS11 to generate an output count value Dout corresponding to the first sensing signal S11, thereby restoring the output count value Dout corresponding to the first sensing signal S11.

[0057] From another perspective, the purpose of operating the sensing integration circuit 10 during the first integration time T1 is to determine whether the signal strength of the first sensing signal S11 falls within the small signal range or the large signal range. In the second embodiment, by shortening the first integration time T1, the time required to determine the range corresponding to the signal strength of the first sensing signal S11 can be reduced, thereby generating the output count value Dout corresponding to the first sensing signal S11 in a shorter time.

[0058] Furthermore, in the second embodiment, the first buffer REG1 ( Figure 7 (not shown) is used to store N predetermined count values, where the (M+1)th predetermined count value among the N predetermined count values ​​is greater than the Mth predetermined count value; the N predetermined count values ​​correspond to N signal gain values ​​respectively, where the (M+1)th signal gain value among the N signal gain values ​​is less than the Mth signal gain value; N and M are positive integers, and 1≤M<N. For example, Figure 7 A plurality of predetermined count values ​​Dth1, Dth2, Dth3, and Dth4 are shown, wherein Dth1<Dth2<Dth3<Dth4. The plurality of predetermined count values ​​Dth1, Dth2, Dth3, and Dth4 correspond to a plurality of signal gain values ​​G1, G2, G3, and G4, respectively, wherein G1>G2>G3>G4>1. In one embodiment, the magnitudes of the N predetermined count values ​​are the maximum count value divided by 2. NAssuming the maximum count value is 800, Dth1=800 / 2 4 =50, Dth2=800 / 2 3 =100, Dth3=800 / 2 2 =200, Dth4=2 1 =800 / 400, but not limited thereto. In one embodiment, the magnitudes of the N signal gain values ​​are respectively 2 N Descending values, for example, G1 = 2 4 =16, G2=2 3 =8, G3=2 2 =4, G4=2 1 =2, but not limited to this.

[0059] Figure 8 : is a curve diagram of count value versus signal-to-noise ratio according to the second embodiment of the present invention. When the first count value D11 corresponding to the first sensing signal S11 is less than or equal to the predetermined count value Dth1, the amplification factor corresponding to the first sensing signal S11 is the signal gain value G1 and the corresponding average signal-to-noise ratio is R1. When the first count value D11 corresponding to the first sensing signal S11 is greater than the predetermined count value Dth1 and less than or equal to the predetermined count value Dth2, the amplification factor corresponding to the first sensing signal S11 is the signal gain value G2 and the corresponding average signal-to-noise ratio is R2. When the first count value D11 corresponding to the first sensing signal S11 is greater than the predetermined count value Dth2 and less than or equal to the predetermined count value Dth3, the first The amplification factor corresponding to the sensing signal S11 is a signal gain value G3, and the corresponding average signal-to-noise ratio is R3. When the first count value D11 corresponding to the first sensing signal S11 is greater than the predetermined count value Dth3 and less than or equal to the predetermined count value Dth4, the amplification factor corresponding to the first sensing signal S11 is a signal gain value G4, and the corresponding average signal-to-noise ratio is R4. When the first count value D11 corresponding to the first sensing signal S11 is greater than the predetermined count value Dth4 and less than or equal to the maximum count value, the amplification factor corresponding to the first sensing signal S11 is a signal gain value G5 (where G5=1), and the corresponding average signal-to-noise ratio is R5. Thus, the second embodiment of the present invention can improve the signal-to-noise ratio of the sensing integration circuit 10 when operating in multiple different sensing signal ranges by setting multiple predetermined count values ​​and corresponding multiple signal gain values.

[0060] [Third embodiment]

[0061] Figure 9 Schematic diagram of a curve CN_3 and a curve CN_1 showing count values ​​versus signal-to-noise ratio according to a third embodiment of the present invention. In the third embodiment, a plurality of predetermined count values ​​are predetermined according to at least one target signal-to-noise ratio of the sensing integration circuit 10. Specifically, Figure 9In the example, assuming a maximum SNR of 266 and a corresponding maximum count value of 800, and a target SNR of 133 and a corresponding predetermined count value Dth2 of 400, the dashed portion of curve CN_1 illustrates that the SNR of the first sensing signal S11 during the first integration time T1 is lower than the target SNR of 133. Therefore, the first sensing signal S11 needs to be amplified to improve its SNR. In one embodiment, circuit designers can set multiple predetermined count values ​​Dth1 and Dth2 and their corresponding signal gain values ​​G1 and G2 (where the signal gain value G3 corresponding to the maximum SNR of 266 is 1) based on application requirements, assuming the SNR of the first sensing signal S11 is lower than the target SNR of 133. This allows for improved SNRs of the sensing integration circuit 10 when operating in multiple different sensing signal ranges.

[0062] Figure 10 FIG. 1 is a schematic diagram of a curve of sensing signals versus count values ​​according to a third embodiment of the present invention. Figure 10 In the figure, the dashed portion of curve CS_1 illustrates that when the sensing signal fluctuates, the corresponding count value may change disproportionally. That is, the slope of curve CS_1 is not constant. To address this issue, when the first count value D11 corresponding to the first sensing signal S11 is less than the predetermined count value Dth1, the amplification factor corresponding to the first sensing signal S11 is the signal gain value G1. When the first count value D11 corresponding to the first sensing signal S11 is less than the predetermined count value Dth2 and greater than or equal to the predetermined count value Dth1, the amplification factor corresponding to the first sensing signal S11 is the signal gain value G2. Thus, the solid curve CS_3 illustrates that when the sensing signal fluctuates, the corresponding count value changes more closely in proportion. That is, the slope of curve CS_3 is closer to a constant value, resulting in good linearity of the sensing integration circuit 10 over the entire operating range.

[0063] [Beneficial Effects of Embodiments]

[0064] One of the advantages of the present invention is that the signal gain value determination circuit and related method provided by the present invention can achieve a more uniform signal-to-noise ratio when the sensing integration circuit operates in different sensing signal ranges, and simultaneously improve the linearity of the sensor over the entire operating range by: "comparing a first count value corresponding to a first sensing signal with a predetermined count value during a first integration time to determine a signal gain value corresponding to the first sensing signal; adjusting the first sensing signal based on the signal gain value to generate a second sensing signal; generating a second count value corresponding to the second sensing signal during a second integration time; and, after the second integration time, generating an output count value corresponding to the first sensing signal based on the second count value and the signal gain value."

[0065] Another beneficial effect of the present invention is that the signal gain value judgment circuit and related method provided by the present invention can save time for judging the range corresponding to the signal strength of the first sensing signal through the technical solution of "when the second integration time is X times the first integration time, the arithmetic module multiplies the second count value by X times after the second integration time and divides it by the signal gain value to generate an output count value corresponding to the first sensing signal", so as to generate an output count value corresponding to the first sensing signal in a shorter time.

[0066] Another beneficial effect of the present invention is that the signal gain value determination circuit and related method provided by the present invention can, through the technical solutions of "predetermining N predetermined count values ​​and their corresponding N signal gain values" and "predetermining the N predetermined count values ​​based on at least one target signal-to-noise ratio of the sensing integration circuit," achieve a more uniform distribution of the signal-to-noise ratio of the sensing integration circuit when operating in different sensing signal ranges, while also improving the linearity of the sensor over the entire operating range.

[0067] The contents disclosed above are only preferred feasible embodiments of the present invention and do not limit the scope of protection of the claims of the present invention. Therefore, all equivalent technical changes made using the contents of the description and drawings of the present invention are included in the scope of protection of the claims of the present invention.

Claims

1. A signal gain value determination circuit for a sensing integration circuit, characterized in that: The signal gain value judgment circuit includes: a first buffer for storing a predetermined count value; a second buffer for storing a first count value; wherein the sensing integration circuit generates the first count value according to a first sensing signal within a first integration time; a digital comparator coupled to the first register and the second register, for comparing the first count value with the predetermined count value after the first integration time to generate a comparison result; a digital controller coupled to the digital comparator, for determining a signal gain value according to the comparison result, and generating a control signal indicating the signal gain value to provide to a signal amplifier of the sensing integration circuit; wherein the signal amplifier adjusts the first sensing signal according to the signal gain value to generate a second sensing signal, so that the sensing integration circuit generates a second count value corresponding to the second sensing signal within a second integration time, and the second register stores the second count value after the second integration time; a third register, coupled to the digital controller, for storing the signal gain value; an arithmetic module coupled to the third register and the second register, for generating an output count value corresponding to the first sensing signal according to the second count value and the signal gain value after the second integration time; and a fourth register for storing the output count value; When the signal gain value is greater than 1, the signal amplifier amplifies the first sensing signal according to the signal gain value to generate the second sensing signal, so that the second count value corresponding to the second sensing signal is greater than the first count value corresponding to the first sensing signal.

2. The signal gain value determination circuit according to claim 1, wherein: When the comparison result indicates that the first count value is less than the predetermined count value, the signal gain value is greater than 1; as well as When the comparison result indicates that the first count value is not less than the predetermined count value, the signal gain value is equal to 1.

3. The signal gain value determination circuit according to claim 1, wherein: The arithmetic module divides the second count value by the signal gain value after the second integration time to generate the output count value corresponding to the first sensing signal.

4. The signal gain value determination circuit according to claim 1, wherein: When the second integration time is X times the first integration time, the arithmetic module multiplies the second count value by X times and divides the result by the signal gain value after the second integration time to generate the output count value corresponding to the first sensing signal, where X is a value greater than 1.

5. The signal gain value determination circuit according to claim 1, wherein: The first buffer is used to store N predetermined count values, and the N predetermined count values ​​correspond to N signal gain values ​​respectively.

6. The signal gain value determination circuit according to claim 5, wherein: The M+1th predetermined count value among the N predetermined count values ​​is greater than the Mth predetermined count value; The M+1th signal gain value among the N signal gain values ​​is smaller than the Mth signal gain value; as well as N and M are positive integers, and 1≤M<N.

7. The signal gain value determination circuit according to claim 5, wherein: The N predetermined count values ​​are predetermined according to at least a target signal-to-noise ratio of the sensing integration circuit.

8. A method for determining a signal gain value, used in a sensing integration circuit, characterized in that: The method includes: The sensing integration circuit is configured to generate a first count value corresponding to a first sensing signal within a first integration time; After the first integration time, comparing the first count value with a predetermined count value to generate a comparison result; determining a signal gain value according to the comparison result to generate a control signal indicating the signal gain value; adjusting the first sensing signal according to the signal gain value to generate a second sensing signal; Configure the sensing integration circuit to generate a second count value corresponding to the second sensing signal within a second integration time; and After the second integration time, generating an output count value corresponding to the first sensing signal according to the second count value and the signal gain value; When the signal gain value is greater than 1, the signal amplifier amplifies the first sensing signal according to the signal gain value to generate the second sensing signal, so that the second count value corresponding to the second sensing signal is greater than the first count value corresponding to the first sensing signal.

9. The method for determining a signal gain value according to claim 8, wherein: The step of determining the signal gain value according to the comparison result includes: When the comparison result indicates that the first count value is less than the predetermined count value, the signal gain value is greater than 1; and When the comparison result indicates that the first count value is not less than the predetermined count value, the signal gain value is equal to 1.

10. The method for determining a signal gain value according to claim 9, wherein: After the second integration time, the step of generating the output count value corresponding to the first sensing signal according to the second count value and the signal gain value includes: The second count value is divided by the signal gain value to generate the output count value corresponding to the first sensing signal.

11. The method for determining a signal gain value according to claim 9, wherein: When the second integration time is X times the first integration time, after the second integration time, the step of generating the output count value corresponding to the first sensing signal according to the second count value and the signal gain value includes: The second count value is multiplied by the X times and divided by the signal gain value to generate the output count value corresponding to the first sensing signal, wherein X is a value greater than zero.

12. The method for determining a signal gain value according to claim 8, wherein: The method further includes: A first register is configured to store the predetermined count value, wherein the predetermined count value includes N predetermined count values.

13. The method for determining a signal gain value according to claim 12, wherein: The M+1th predetermined count value among the N predetermined count values ​​is greater than the Mth predetermined count value; The N predetermined count values ​​correspond to N signal gain values ​​respectively, and the M+1th signal gain value among the N signal gain values ​​is smaller than the Mth signal gain value; as well as N and M are positive integers, and 1≤M<N.

14. The method for determining a signal gain value according to claim 12, wherein: The method further includes: The N predetermined count values ​​are preset according to at least one predetermined signal-to-noise ratio.

Images