Crystal Oscillator Circuit Method for Adjusting Gain

Abstract

The present application proposes a method for adjusting a crystal oscillator circuit for gain, and relates to the field of integrated circuit design. The crystal oscillator circuit of the present application includes: a current source group, a field effect transistor, a feedback resistor, and a switch control component; the current source group includes a power supply, multiple current sources, and a switch of each current source; the input end of each current source is connected to the power supply, the output end of each current source is connected to the first end of the switch, and the second end of the switch is connected to the drain of the field effect transistor; the drain of the field effect transistor is respectively connected to the first end of the feedback resistor and the input end of the switch control component, the gate of the field effect transistor is connected to the second end of the feedback resistor, and the source of the field effect transistor is grounded; the control end of the switch control component is connected to the switch of each current source. The present application ensures that the crystal oscillator circuit has the maximum gain during the crystal oscillator startup phase so as to quickly start oscillation. After starting oscillation, the bias current is controlled by judging the attenuation of the crystal oscillator to ensure that the crystal oscillator works in low power consumption mode and does not stop oscillating.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design, to a crystal oscillator circuit, and in particular to a method for adjusting gain of a crystal oscillator circuit. Background Art

[0002] In the related art, a crystal oscillator needs a larger gain to achieve fast startup, but a large gain will lead to higher power consumption. After the crystal oscillator is started, if you want to maintain low power consumption, the crystal oscillator requires a smaller gain. However, due to the influence of temperature, humidity, and device aging, a crystal oscillator with a smaller gain will have the risk of stopping. Summary of the invention

[0003] The present application aims to solve one of the technical problems in the related art at least to some extent.

[0004] To this end, one purpose of the present application is to propose a method for adjusting a gain of a crystal oscillator circuit, wherein the crystal oscillator circuit comprises: a current source group, a field effect transistor, a feedback resistor and a switch control component; the current source group comprises a power supply, a plurality of current sources and a switch of each current source; wherein the input end of each current source is connected to the power supply, the output end of each current source is connected to the first end of the switch, and the second end of the switch is connected to the drain of the field effect transistor; the drain of the field effect transistor is also connected to the first end of the feedback resistor and the input end of the switch control component, respectively, and the field The gate of the field effect transistor is connected to the second end of the feedback resistor, and the source of the field effect transistor is grounded; the control end of the switch control component is connected to the switch of each of the current sources; the current source group is used to provide a bias current to the field effect transistor; the field effect transistor is used to drive an external passive crystal oscillator unit to oscillate under the excitation of the bias current; the switch control component is used to detect the crystal oscillation amplitude of the passive crystal oscillator unit, and generate a current source control instruction based on the crystal oscillation amplitude, and control the conduction or disconnection of each of the current sources based on the current source control instruction.

[0005] The present application proposes a method for adjusting the gain of a crystal oscillator circuit. In the initial startup stage of the crystal oscillator, the field effect transistor is biased by the largest current source to ensure that the crystal oscillator circuit has the largest gain when starting, so that it can start quickly. After the crystal oscillator starts, the bias current is gradually reduced, and the attenuation of the crystal oscillator is determined by a switch control component to control the bias current, thereby ensuring that the crystal oscillator works in a low power consumption mode without stopping due to external influences.

[0006] According to the gain adjustment crystal oscillator circuit method proposed in the present application, the multiple current sources are connected in parallel between the power supply and the field effect transistor, wherein the bias currents output by two adjacent parallel current sources are in a linear increasing relationship.

[0007] According to the gain adjustment crystal oscillator circuit method proposed in the present application, the switch control component includes: an inverter unit, a stop oscillation detection unit and an instruction generation unit; the input end of the inverter unit is connected to the drain of the field effect transistor, the output end of the inverter is connected to the input end of the stop oscillation detection unit, the output end of the stop oscillation detection unit is connected to the input end of the instruction generation unit, and the output end of the instruction generation unit is connected to the switch of each current source; the stop oscillation detection unit is used to perform stop oscillation detection on the crystal oscillator circuit based on the output of the inverter unit and output the stop oscillation detection result; the instruction generation unit is used to generate the current source control instruction based on the stop oscillation detection result.

[0008] According to the gain adjustment crystal oscillator circuit method proposed in the present application, the inverter unit includes a first Schmidt inverter, a second Schmidt inverter and a third Schmidt inverter; the oscillation stop detection unit includes a first oscillation stop detection subcircuit, a second oscillation stop detection subcircuit and a fourth inverter; wherein the input end of the first Schmidt inverter, the input end of the second Schmidt inverter and the input end of the third Schmidt inverter are respectively connected to the drain of the field effect transistor; the output end of the first Schmidt inverter is connected to the first input end of the first oscillation stop detection subcircuit, and the output end of the second Schmidt inverter is connected to the first input end of the first oscillation stop detection subcircuit. The first oscillation stop detection subcircuit is connected to the first input terminal of the second oscillation stop detection subcircuit; the second input terminal of the first oscillation stop detection subcircuit is connected to the output terminal of the third Schmidt inverter, the output terminal of the first oscillation stop detection subcircuit is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter is connected to the first input terminal of the instruction generation unit; the second input terminal of the second oscillation stop detection subcircuit is connected to the output terminal of the third Schmidt inverter, the output terminal of the second oscillation stop detection subcircuit is connected to the second input terminal of the instruction generation unit, and the output terminal of the instruction generation unit is connected to the switch of each of the current sources.

[0009] According to the gain adjustment crystal oscillator circuit method proposed in the present application, the window size of the first Schmitt inverter is larger than the window size of the second Schmitt inverter, and the window size of the second Schmitt inverter is larger than the window size of the third Schmitt inverter.

[0010] According to the gain adjustment crystal oscillator circuit method proposed in the present application, the inverter unit includes multiple Schmitt inverters and a data selector, the number of the Schmitt inverters is a positive integer greater than or equal to 3; the data selector is used to select three Schmitt inverters from the multiple Schmitt inverters as the first Schmitt inverter, the second Schmitt inverter and the third Schmitt inverter; the stop oscillation detection unit includes a first stop oscillation detection subcircuit, a second stop oscillation detection subcircuit and a fourth inverter; the input end of each of the Schmitt inverters is connected to the drain of the field effect transistor, and the output end of each of the Schmitt inverters is connected to the data input end of the data selector; the first stop oscillation detection subcircuit The first input end of the first stop oscillation detection subcircuit is connected to the first output end of the data selector, the second input end of the first stop oscillation detection subcircuit is connected to the third output end of the data selector, the output end of the first stop oscillation detection subcircuit is connected to the input end of the fourth inverter, and the output end of the fourth inverter is connected to the first input end of the instruction generation unit; the first input end of the second stop oscillation detection subcircuit is connected to the second output end of the data selector, the second input end of the second stop oscillation detection subcircuit is connected to the output end of the third Schmidt inverter, the output end of the second stop oscillation detection subcircuit is connected to the second input end of the instruction generation unit, and the output end of the instruction generation unit is connected to the switch of each of the current sources.

[0011] According to the gain adjustment crystal oscillator circuit method proposed in the present application, the multiple Schmitt inverters are connected in parallel between the field effect transistor and the current source group, and the window sizes of the adjacent parallel Schmitt inverters are linearly increasing, wherein the Schmitt inverter with the smallest window size is continuously selected by the data selector.

[0012] According to the crystal oscillator circuit method for adjusting gain proposed in the present application, the instruction generation unit is an addition and subtraction counter; the input of the first input end of the instruction generation unit is used to subtract the current count value in the addition and subtraction counter; the input of the second input end of the instruction generation unit is used to add the current count value in the addition and subtraction counter; the output end of the instruction generation unit is used to output the current source control instruction, and the current source control instruction is the target count value obtained after adding and subtracting the current count value.

[0013] According to the gain adjustment crystal oscillator circuit method proposed in the present application, the oscillation stop detection subcircuit includes: a fifth inverter and a sixth inverter, a first D flip-flop and a second D flip-flop, and a NOR gate; wherein the input end of the fifth inverter is connected to the output end of the Schmitt inverter with the smallest window size; the output end of the fifth inverter is connected to the input end of the sixth inverter and the first input end of the first D flip-flop, and the second input end of the first D flip-flop is connected to the output end of the Schmitt inverter with the non-smallest window; the output end of the sixth inverter is connected to the first input end of the second D flip-flop, and the second input end of the second D flip-flop is connected to the output end of the inverter with the non-smallest window; the output end of the first D flip-flop is connected to the first input end of the NOR gate, and the output end of the second D flip-flop is connected to the second input end of the NOR gate.

[0014] The crystal oscillator circuit method for adjusting gain proposed in the present application also includes: when the crystal oscillator amplitude is greater than the window size of the third Schmitt inverter and less than the window size of the first Schmitt inverter and the window size of the second Schmitt inverter, the third Schmitt inverter works to output a clock signal, and the outputs of the first Schmitt inverter and the second Schmitt inverter are always maintained at a high level or a low level; the outputs of the first oscillation stop detection subcircuit and the second oscillation stop detection subcircuit are high level.

[0015] The crystal oscillator circuit method for adjusting gain proposed in the present application also includes: when the crystal oscillator amplitude is greater than the window size of the second Schmitt inverter and less than the window size of the first Schmitt inverter, the second Schmitt inverter and the third Schmitt inverter work and output the clock signal, and the output of the first Schmitt inverter is always maintained at a high level or a low level; the output of the first stop oscillation detection subcircuit is a high level, and the output of the second stop oscillation detection subcircuit is a low level.

[0016] The crystal oscillator circuit method for adjusting gain proposed in the present application also includes: when the crystal oscillator amplitude is greater than the window size of the first Schmitt inverter, the first Schmitt inverter, the second Schmitt inverter and the third Schmitt inverter all work and output the clock signal; the outputs of the first oscillation stop detection subcircuit and the second oscillation stop detection subcircuit are low level. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a structural schematic diagram of a gain-adjustable crystal oscillator circuit according to an embodiment of the present application.

[0018] Figure 2 It is a structural schematic diagram of a gain-adjustable crystal oscillator circuit according to an embodiment of the present application.

[0019] Figure 3 It is a structural schematic diagram of a gain-adjustable crystal oscillator circuit according to an embodiment of the present application.

[0020] Figure 4 It is a structural schematic diagram of a gain-adjustable crystal oscillator circuit according to an embodiment of the present application.

[0021] Figure 5 It is a structural schematic diagram of a vibration stop detection subcircuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0023] In order to enable the crystal oscillator to start quickly and maintain continuous oscillation at low power consumption after startup, the present application proposes a structural schematic diagram of a crystal oscillator circuit with adjustable gain, such as Figure 1 As shown, the crystal oscillator circuit 100 includes a current source group 11 , a field effect transistor ( N1 ) 12 , a feedback resistor (Rf) 13 and a switch control component 14 .

[0024] The current source group 11 includes a power supply VDD, a plurality of current sources and a switch of each current source, and is used to provide a bias current to the field effect transistor 12. Figure 1 As shown, the input end of each current source is connected to the power supply, the output end of each current source is connected to the first end of the switch, and the second end of the switch is connected to the drain of the field effect transistor 12.

[0025] Optionally, the number of current sources can be set according to actual conditions, such as Figure 1 As shown, the number of current sources is 8, and the 8 current sources correspond to DI0-DI7, a total of 8 switches. It should be noted that the number of current sources and current source switches is 8 here only for example and cannot be used as a condition to limit the present application.

[0026] Optionally, in order to increase the gain of the crystal oscillator circuit, multiple current sources are connected in parallel between the power supply and the field effect transistor 12, such as Figure 1 As shown, eight current sources are connected in parallel between the power supply and the field effect transistor 12 .

[0027] Optionally, in the present application, the bias currents output by two adjacent parallel current sources are in a linear increasing relationship, such as Figure 1 As shown, the eight current sources are arranged in sequence from left to right, and the bias currents output by the current sources increase successively.

[0028] Optionally, the bias currents output by two adjacent parallel current sources are in a multiple relationship, such as Figure 1 As shown, the eight current sources are arranged in sequence from left to right. The bias current output by the first current source on the left is I. The bias current output by each current source is twice the bias current output by the current source on its left. The bias currents output by the eight current sources in sequence from left to right are I, 2I, 4I, 8I, 16I, 32I, 64I and 128I, respectively. This allows the gain of the crystal oscillator circuit to be controlled by the eight current source switches and to operate under different bias currents.

[0029] The drain of the field effect transistor 12 is also connected to the first end of the feedback resistor 13 and the input end of the switch control component 14, respectively. The gate of the field effect transistor 12 is connected to the second end of the feedback resistor 13, and the source of the field effect transistor 12 is grounded. When the field effect transistor 12 is turned on, since the source of the field effect transistor 12 is grounded, the voltage of the drain of the field effect transistor 12 is at a low level, and accordingly, the first end of the feedback resistor 13 is at a low level, and the second end of the feedback resistor 13 is at a high level, thereby realizing the reverse of the field effect transistor 12.

[0030] The gain-adjustable crystal oscillator circuit provided in the present application is also connected to a passive crystal oscillator unit 15 , and the passive crystal oscillator unit 15 is used to generate crystal oscillation under the drive of the field effect transistor 12 to output a clock signal.

[0031] The field effect transistor 12 is used to drive the external passive crystal oscillator unit 15 to generate crystal oscillation under the stimulation of the bias current.

[0032] In the present application, the control end of the switch control component 14 is connected to the switch of each current source. The switch control component 14 is used to detect the crystal oscillator amplitude of the passive crystal oscillator unit, generate a current source control instruction based on the crystal oscillator amplitude, and control the conduction or disconnection of each current source based on the current source control instruction.

[0033] When the crystal oscillator amplitude is large, the switch control component 14 generates a current source control instruction based on the crystal oscillator amplitude, wherein the control instruction is used to control the on or off of each current source to reduce the crystal oscillator amplitude.

[0034] When the crystal oscillator amplitude is small, the switch control component 14 generates a current source control instruction based on the crystal oscillator amplitude, wherein the control instruction is used to control the on or off of each current source to increase the crystal oscillator amplitude.

[0035] The present application proposes a method for adjusting the gain of a crystal oscillator circuit. In the initial startup stage of the crystal oscillator, the field effect transistor is biased by the largest current source to ensure that the crystal oscillator circuit has the largest gain when starting, so that it can start quickly; after the crystal oscillator starts, the bias current is gradually reduced; the attenuation of the crystal oscillator is determined by a switch control component, thereby controlling the bias current, thereby ensuring that the crystal oscillator works in a low power consumption mode without stopping due to external influences.

[0036] Figure 2 is a schematic diagram of a structure of a crystal oscillator circuit for adjusting gain proposed in this application, such as Figure 2 As shown, the crystal oscillator circuit 200 includes a current source group 21 , a field effect transistor ( N1 ) 22 , a feedback resistor (Rf) 23 and a switch control component 24 .

[0037] Regarding the current source group 21 , the field effect transistor ( N1 ) 22 , and the feedback resistor (Rf) 23 , reference may be made to the above description of the current source group 11 , the field effect transistor ( N1 ) 12 , and the feedback resistor (Rf) 13 .

[0038] The gain-adjusting crystal oscillator circuit provided in the present application is also connected to a passive crystal oscillator unit 25 , and the passive crystal oscillator unit 25 is used to generate crystal oscillation under the drive of the field effect transistor 22 to output a clock signal.

[0039] The switch control component 24 includes an inverter unit 241, a vibration stop detection unit 242 and an instruction generation unit 243. Further, the input end of the inverter unit 241 included in the switch control component is connected to the drain of the field effect transistor 22, the output end of the inverter unit 241 is connected to the input end of the vibration stop detection unit 242, the output end of the vibration stop detection unit 242 is connected to the input end of the instruction generation unit 243, and the output end of the instruction generation unit 243 is connected to the switch of each current source.

[0040] The inverter unit 241 is used to detect the crystal oscillator amplitude of the passive crystal oscillator unit 25, and generate a current source control instruction based on the crystal oscillator amplitude, and control the on or off of each current source based on the current source control instruction.

[0041] The oscillation stop detection unit 242 is used to perform oscillation stop detection on the crystal oscillator circuit based on the output of the inverter unit 241, and output the oscillation stop detection result;

[0042] The instruction generating unit 243 is used to generate the current source control instruction based on the vibration stop detection result.

[0043] When the oscillation stop detection result is that the crystal oscillator amplitude is large, the instruction generation unit 243 generates a current source control instruction, wherein the control instruction is used to control the on or off of each current source to reduce the crystal oscillator amplitude.

[0044] When the oscillation stop detection result is that the crystal oscillator amplitude is small, the instruction generation unit 243 generates a current source control instruction, wherein the control instruction is used to control the on or off of each current source to increase the crystal oscillator amplitude.

[0045] The present application proposes a method for adjusting the gain of a crystal oscillator circuit. In the initial startup stage of the crystal oscillator, the field effect transistor is biased by the largest current source to ensure that the crystal oscillator circuit has the largest gain when starting, so that it can start quickly. After the crystal oscillator starts, the bias current is gradually reduced, and the attenuation of the crystal oscillator is determined by a switch control component to control the bias current, thereby ensuring that the crystal oscillator works in a low power consumption mode without stopping due to external influences.

[0046] Figure 3 is a schematic diagram of a structure of a crystal oscillator circuit for adjusting gain proposed in the present application. Figure 3 As shown, the crystal oscillator circuit 300 includes a current source group 31 , a field effect transistor ( N1 ) 32 , a feedback resistor (Rf) 33 and a switch control component 34 .

[0047] Regarding the current source group 31 , the field effect transistor ( N1 ) 32 , and the feedback resistor (Rf) 33 , reference may be made to the above description of the current source group 11 , the field effect transistor ( N1 ) 12 , and the feedback resistor (Rf) 13 .

[0048] The switch control component 34 includes an inverter unit 341 , a vibration stop detection unit 342 and an instruction generation unit 343 .

[0049] like Figure 3 As shown, the inverter unit 341 includes a first Schmitt inverter S1, a second Schmitt inverter S2 and a third Schmitt inverter S3.

[0050] As a feasible approach, Figure 3As shown, the window size of the first Schmitt inverter S1 is larger than the window size of the second Schmitt inverter S2, and the window size of the second Schmitt inverter S2 is larger than the window size of the third Schmitt inverter S3. The input end of the first Schmitt inverter S1, the input end of the second Schmitt inverter S2, and the input end of the third Schmitt inverter S3 are respectively connected to the drain of the field effect transistor 32. The output end of the first Schmitt inverter S1 is connected to the first input end of the first stop oscillation detection sub-circuit TS1, and the output end of the second Schmitt inverter S2 is connected to the first input end of the second stop oscillation detection sub-circuit TS2. The second input end of the first stop oscillation detection sub-circuit TS1 is connected to the output end of the third Schmitt inverter S3, and the output end of the first stop oscillation detection sub-circuit TS1 is connected to the input end of the fourth inverter INV1, and the output end of the fourth inverter INV1 is connected to the first input end of the instruction generation unit 343. The second input terminal of the second stop detection subcircuit is connected to the output terminal of the third Schmidt inverter S3, the output terminal of the second stop detection subcircuit TS2 is connected to the second input terminal of the instruction generation unit 343, and the output terminal of the instruction generation unit 343 is connected to the switch of each current source.

[0051] Furthermore, the oscillation stop detection unit 342 included in the switch control component 34 includes a first oscillation stop detection subcircuit TS1, a second oscillation stop detection subcircuit TS2 and a fourth inverter INV1, which is used to perform oscillation stop detection on the crystal oscillator circuit based on the output of the above inverter units and output the oscillation stop detection result.

[0052] The instruction generation unit 343 is an addition and subtraction counter COUNTER, which is used to generate a current source control instruction based on the vibration stop detection result. The input of the first input end of the instruction generation unit 343 is used to subtract the current count value in the addition and subtraction counter COUNTER; the input of the second input end of the instruction generation unit 343 is used to add the current count value in the addition and subtraction counter COUNTER. The output end of the instruction generation unit 343 is used to output the current source control instruction, wherein the current source control instruction refers to the target count value obtained after adding and subtracting the current count value.

[0053] The gain-adjusting crystal oscillator circuit provided in the present application is also connected to a passive crystal oscillator unit 35 , and the passive crystal oscillator unit 35 is used to generate crystal oscillation under the drive of the field effect transistor 32 to output a clock signal.

[0054] The passive crystal oscillator unit 35 includes: a passive crystal 351, a first capacitor 352 and a second capacitor 353. The first end of the passive crystal 351 is connected to the gate of the field effect transistor 32 and the first end of the first capacitor 352, and the second end of the first capacitor 352 is grounded; the second end of the passive crystal 351 is connected to the drain of the field effect transistor 32 and the first end of the second capacitor 353, and the second end of the second capacitor 353 is grounded.

[0055] The present application proposes a method for adjusting the gain of a crystal oscillator circuit. In the initial startup stage of the crystal oscillator, the field effect transistor is biased by the largest current source to ensure that the crystal oscillator circuit has the largest gain when starting, so that it can start quickly; after the crystal oscillator starts, the bias current is gradually reduced; the attenuation of the crystal oscillator is judged by Schmidt inverters with different windows and a stop detection circuit, and the addition and subtraction counter is controlled to add or subtract, thereby controlling the bias current, thereby ensuring that the crystal oscillator works in a low power consumption mode without stopping due to external influences.

[0056] Figure 4 is a schematic diagram of a structure of a crystal oscillator circuit for adjusting gain proposed in the present application. Figure 4 As shown, the crystal oscillator circuit 400 includes a current source group 41 , a field effect transistor ( N1 ) 42 , a feedback resistor (Rf) 43 and a switch control component 44 .

[0057] Regarding the current source group 41 , the field effect transistor ( N1 ) 42 , and the feedback resistor (Rf) 43 , reference may be made to the above description of the current source group 11 , the field effect transistor ( N1 ) 12 , and the feedback resistor (Rf) 13 .

[0058] The switch control component 44 includes an inverter unit 441 , a vibration stop detection unit 442 , an instruction generation unit 443 and a data selector 444 .

[0059] As an implementable manner, the inverter unit 441 may include a plurality of Schmitt inverters, wherein the number of Schmitt inverters must be a positive integer greater than or equal to 3. The data selector 444 is used to select three Schmitt inverters from the plurality of Schmitt inverters as the first Schmitt inverter, the second Schmitt inverter, and the third Schmitt inverter.

[0060] like Figure 4As shown, a plurality of Schmitt inverters are connected in parallel between the field effect transistor 42 and the current source group 41, and the window sizes of adjacent parallel Schmitt inverters are linearly increasing, wherein the Schmitt inverter with the smallest window size is continuously selected by the data selector 444. The input end of each Schmitt inverter is connected to the drain of the field effect transistor 42, and the output end of each Schmitt inverter is connected to the data input end of the data selector 444. The first input end of the first stop oscillation detection subcircuit TS1 is connected to the first output end of the data selector 444, the second input end of the first stop oscillation detection subcircuit TS1 is connected to the third output end of the data selector 444, the output end of the first stop oscillation detection subcircuit TS1 is connected to the input end of the fourth inverter INV1, and the output end of the fourth inverter INV1 is connected to the first input end of the instruction generation unit 443. The first input terminal of the second oscillation stop detection sub-circuit TS2 is connected to the second output terminal of the data selector 444, the second input terminal of the second oscillation stop detection sub-circuit TS2 is connected to the output terminal of the third Schmitt inverter, the output terminal of the second oscillation stop detection sub-circuit TS2 is connected to the second input terminal of the instruction generation unit 443, and the output terminal of the instruction generation unit 443 is connected to the switch of each current source.

[0061] Furthermore, the oscillation stop detection unit 442 included in the switch control component 44 includes a first oscillation stop detection subcircuit TS1, a second oscillation stop detection subcircuit TS2 and a fourth inverter INV1, which is used to perform oscillation stop detection on the crystal oscillator circuit based on the output of the above inverter units and output the oscillation stop detection result.

[0062] The instruction generation unit 443 is an addition and subtraction counter COUNTER, which is used to generate a current source control instruction based on the vibration stop detection result. The input of the first input terminal of the instruction generation unit is used to subtract the current count value in the addition and subtraction counter COUNTER; the input of the second input terminal of the instruction generation unit is used to add the current count value in the addition and subtraction counter COUNTER. The output terminal of the instruction generation unit is used to output the current source control instruction, wherein the current source control instruction refers to the target count value obtained after adding and subtracting the current count value.

[0063] The gain-adjusting crystal oscillator circuit provided in the present application is also connected to a passive crystal oscillator unit 45 , and the passive crystal oscillator unit 45 is used to generate crystal oscillation under the drive of the field effect transistor 42 to output a clock signal.

[0064] The passive crystal oscillator unit 45 includes: a passive crystal 451, a first capacitor 452 and a second capacitor 453. The first end of the passive crystal 451 is connected to the gate of the field effect transistor 42 and the first end of the first capacitor 452, and the second end of the first capacitor 452 is grounded; the second end of the passive crystal 451 is connected to the drain of the field effect transistor 42 and the first end of the second capacitor 453, and the second end of the second capacitor 453 is grounded.

[0065] The present application proposes a method for adjusting the gain of a crystal oscillator circuit. In the initial startup stage of the crystal oscillator, the field effect transistor is biased by the largest current source to ensure that the crystal oscillator circuit has the largest gain when starting, so that it can start quickly; after the crystal oscillator starts, the bias current is gradually reduced; the attenuation of the crystal oscillator is judged by Schmidt inverters with different windows and a stop detection circuit, and the addition and subtraction counter is controlled to add or subtract, thereby controlling the bias current, thereby ensuring that the crystal oscillator works in a low power consumption mode without stopping due to external influences.

[0066] Figure 5 is a schematic diagram of the structure of a vibration stop detection subcircuit proposed in this application, such as Figure 5 As shown, the oscillation stop detection subcircuit 500 includes a fifth inverter 51 and a sixth inverter 52, a first D flip-flop 53 and a second D flip-flop 54, and a NOR gate 55. The input end of the fifth inverter 51 is connected to the output end of the Schmitt inverter with the smallest window size; the output end of the fifth inverter 51 is connected to the input end of the sixth inverter 52 and the first input end of the first D flip-flop 53, and the second input end of the first D flip-flop 53 is connected to the output end of the Schmitt inverter with the non-smallest window size; the output end of the sixth inverter 52 is connected to the first input end of the second D flip-flop 54, and the second input end of the second D flip-flop 54 is connected to the output end of the inverter with the non-smallest window size; the output end of the first D flip-flop 53 is connected to the first input end of the NOR gate 55, and the output end of the second D flip-flop 54 is connected to the second input end of the NOR gate 55.

[0067] Optionally, the vibration stop detection unit includes a first vibration stop detection sub-circuit TS1 and a second vibration stop detection sub-circuit TS2, and the result output by the vibration stop detection unit is a high level or a low level.

[0068] Based on the crystal oscillator circuit proposed above, when the crystal oscillator is powered on and started, the addition and subtraction counter COUNTER is reset, and the current source control instruction DI<7:0> is set to 11111111, so that at this moment, the eight current source switches DI0-DI7 are all in a closed state. At this moment, the current passing through the field effect transistor N1 is 15×I, and the current at this time is the largest, which can improve the transconductance of the field effect transistor N1 and the gain of the crystal oscillator, so that the crystal oscillator circuit can start quickly and stably.

[0069] Below Figure 3 To introduce the method of adjusting the gain of a crystal oscillator circuit by way of example, the relationship between the window sizes of the three Schmitt inverters is set as follows: the window size of the first Schmitt inverter S1 is larger than the window size of the second Schmitt inverter S2, and the window size of the second Schmitt inverter S2 is larger than the window size of the third Schmitt inverter S3.

[0070] If, after the crystal oscillator starts oscillating, the crystal oscillator amplitude is greater than the window size of the third Schmitt inverter S3 and less than the window size of the first Schmitt inverter S1 and the window size of the second Schmitt inverter S2, the third Schmitt inverter S3 works to output a clock signal, while the first Schmitt inverter S1 and the second Schmitt inverter S2 do not work, and the outputs of the first Schmitt inverter S1 and the second Schmitt inverter S2 are always kept at a high level or a low level. The outputs of the three Schmitt inverters are all output as a high level after passing through the first stop oscillation detection subcircuit TS1 and the second stop oscillation detection subcircuit TS2. The high level output by the first stop oscillation detection subcircuit TS1 passes through the fourth inverter INV1 and then outputs a low level to the first input end of the instruction generation unit, that is, the subtraction end of the add-subtract counter COUNTER. The high level output by the second stop oscillation detection subcircuit TS2 is output to the second input end of the instruction generation unit, that is, the addition end of the add-subtract counter COUNTER. At this time, the first input terminal of the instruction generation unit is at a low level, and the second input terminal of the instruction generation unit is at a high level. The adder and subtracter COUNTER performs an addition operation until the maximum value of the current source control instruction DI<7:0> is 11111111. At this time, the switch of the current source is controlled to increase the input current of the field effect transistor N1.

[0071] If the crystal oscillator amplitude is greater than the window size of the second Schmitt inverter S2 and less than the window size of the first Schmitt inverter S1 after the crystal oscillator starts oscillating, the second Schmitt inverter S2 and the third Schmitt inverter S3 work and output the clock signal, the first Schmitt inverter S1 does not work, and the output of the first Schmitt inverter S1 is always kept at a high level or a low level. After the outputs of the three Schmitt inverters pass through the first stop oscillation detection subcircuit TS1 and the second stop oscillation detection subcircuit TS2, the output of the first stop oscillation detection subcircuit TS1 is a high level, and the output of the second stop oscillation detection subcircuit TS2 is a low level. The high level output by the first stop oscillation detection subcircuit TS1 passes through the fourth inverter INV1 and then outputs a low level to the first input end of the instruction generation unit, that is, the subtraction end of the add-subtract counter COUNTER. The low level output by the second stop oscillation detection subcircuit TS2 is to the second input end of the instruction generation unit, that is, the addition end of the add-subtract counter COUNTER. At this time, the first input terminal of the instruction generation unit is at a low level, the second input terminal of the instruction generation unit is also at a low level, the addition and subtraction counter COUNTER maintains the original value, and the input current of the field effect transistor N1 is maintained.

[0072] If the crystal oscillator amplitude is greater than the window size of the first Schmitt inverter S1 after the crystal oscillator starts oscillating, the first Schmitt inverter S1, the second Schmitt inverter S2 and the third Schmitt inverter S3 all work and output clock signals. The outputs of the three Schmitt inverters are all output as low levels after passing through the first stop oscillation detection subcircuit TS1 and the second stop oscillation detection subcircuit TS2. The low level output by the first stop oscillation detection subcircuit TS1 passes through the fourth inverter INV1 and then outputs a high level to the first input end of the instruction generation unit, that is, the subtraction end of the add-subtract counter COUNTER. The low level output by the second stop oscillation detection subcircuit TS2 is output to the second input end of the instruction generation unit, that is, the addition end of the add-subtract counter COUNTER. At this time, the first input terminal of the instruction generation unit is at a high level, the second input terminal of the instruction generation unit is at a low level, and the add-subtract counter COUNTER performs a subtraction operation until the value of the current source control instruction DI<7:0> is 00000000. At this time, the switch of the current source is controlled to reduce the input current of the field effect transistor N1.

[0073] When the crystal oscillator is in a stable working state, due to the automatic gain adjustment, the amplitude of the crystal oscillator is between the windows of the first Schmidt inverter S1 and the second Schmidt inverter S2. If the amplitude of the crystal oscillator exceeds the window range of the first Schmidt inverter S1 and the second Schmidt inverter S2 due to external temperature, humidity, or device aging, the gain adjustment automatically adjusts the working current of the field effect transistor N1 to adjust the crystal oscillator amplitude to a stable range. This ensures that the crystal oscillator will not stop oscillating, and the power consumption is also the lowest.

[0074] The present application proposes a method for adjusting the gain of a crystal oscillator circuit. In the initial startup stage of the crystal oscillator, the field effect transistor is biased by the largest current source to ensure that the crystal oscillator circuit has the largest gain when starting, so that it can start quickly; after the crystal oscillator starts, the bias current is gradually reduced; the attenuation of the crystal oscillator is judged by Schmidt inverters with different windows and a stop detection circuit, and the addition and subtraction counter is controlled to add or subtract, thereby controlling the bias current, thereby ensuring that the crystal oscillator works in a low power consumption mode without stopping due to external influences.

[0075] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0076] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0077] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A gain-adjustable crystal oscillator circuit, characterized in that: The crystal oscillator circuit includes: Current source group, field effect transistor, feedback resistor and switch control components; The current source group includes a power supply, a plurality of current sources and a switch of each current source; wherein the input end of each current source is connected to the power supply, the output end of each current source is connected to the first end of the switch, and the second end of the switch is connected to the drain of the field effect transistor; The drain of the field effect transistor is also connected to the first end of the feedback resistor and the input end of the switch control component respectively, the gate of the field effect transistor is connected to the second end of the feedback resistor, and the source of the field effect transistor is grounded; The control end of the switch control component is connected to the switch of each current source; The current source group is used to provide a bias current to the field effect transistor; The field effect transistor is used to drive an external passive crystal oscillator unit to generate crystal oscillation under the stimulation of the bias current; The switch control component is used to detect the crystal oscillator amplitude of the passive crystal oscillator unit, generate a current source control instruction based on the crystal oscillator amplitude, and control the conduction or disconnection of each current source based on the current source control instruction; The switch control component includes an inverter unit, a stop oscillation detection unit and an instruction generation unit. The input end of the inverter unit is connected to the drain of the field effect transistor, the output end of the inverter is connected to the input end of the stop oscillation detection unit, the output end of the stop oscillation detection unit is connected to the input end of the instruction generation unit, and the output end of the instruction generation unit is connected to the switch of each current source; the stop oscillation detection unit is used to perform stop oscillation detection on the crystal oscillator circuit based on the output of the inverter unit and output the stop oscillation detection result; the instruction generation unit is used to generate the current source control instruction based on the stop oscillation detection result. The stop oscillation detection unit includes a first stop oscillation detection subcircuit, a second stop oscillation detection subcircuit and a fourth inverter; The inverter unit includes a first Schmitt inverter, a second Schmitt inverter and a third Schmitt inverter, wherein the input end of the first Schmitt inverter, the input end of the second Schmitt inverter and the input end of the third Schmitt inverter are respectively connected to the drain of the field effect transistor; the output end of the first Schmitt inverter is connected to the first input end of the first oscillation stop detection subcircuit, and the output end of the second Schmitt inverter is connected to the first input end of the second oscillation stop detection subcircuit; The second input terminal of the first oscillation stop detection subcircuit is connected to the output terminal of the third Schmidt inverter, the output terminal of the first oscillation stop detection subcircuit is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter is connected to the first input terminal of the instruction generation unit; The second input end of the second oscillation stop detection subcircuit is connected to the output end of the third Schmitt inverter, the output end of the second oscillation stop detection subcircuit is connected to the second input end of the instruction generation unit, and the output end of the instruction generation unit is connected to the switch of each current source.

2. The crystal oscillator circuit according to claim 1, characterized in that: The multiple current sources are connected in parallel between the power source and the field effect transistor, wherein bias currents output by two adjacent parallel current sources are in a linear increasing relationship.

3. The crystal oscillator circuit according to claim 1, characterized in that: The window size of the first Schmitt inverter is larger than the window size of the second Schmitt inverter, and the window size of the second Schmitt inverter is larger than the window size of the third Schmitt inverter.

4. The crystal oscillator circuit according to claim 1, characterized in that: The inverter unit includes a plurality of Schmitt inverters and a data selector, wherein the number of the Schmitt inverters is a positive integer greater than or equal to 3; the data selector is used to select three Schmitt inverters from the plurality of Schmitt inverters as a first Schmitt inverter, a second Schmitt inverter and a third Schmitt inverter; The vibration stop detection unit includes a first vibration stop detection subcircuit, a second vibration stop detection subcircuit and a fourth inverter; The input end of each Schmitt inverter is connected to the drain of the field effect transistor, and the output end of each Schmitt inverter is connected to the data input end of the data selector; The first input end of the first oscillation stop detection subcircuit is connected to the first output end of the data selector, the second input end of the first oscillation stop detection subcircuit is connected to the third output end of the data selector, the output end of the first oscillation stop detection subcircuit is connected to the input end of the fourth inverter, and the output end of the fourth inverter is connected to the first input end of the instruction generation unit; The first input terminal of the second oscillation stop detection subcircuit is connected to the second output terminal of the data selector, the second input terminal of the second oscillation stop detection subcircuit is connected to the output terminal of the third Schmitt inverter, the output terminal of the second oscillation stop detection subcircuit is connected to the second input terminal of the instruction generation unit, and the output terminal of the instruction generation unit is connected to the switch of each current source.

5. The crystal oscillator circuit according to claim 4, characterized in that: The multiple Schmitt inverters are connected in parallel between the field effect transistor and the current source group, and the window sizes of the adjacent parallel Schmitt inverters are linearly increasing, wherein the Schmitt inverter with the smallest window size is continuously selected by the data selector.

6. The crystal oscillator circuit according to claim 1 or 4, characterized in that: The instruction generation unit is an addition and subtraction counter; The input of the first input terminal of the instruction generation unit is used to subtract the current count value in the addition and subtraction counter; The input of the second input terminal of the instruction generation unit is used to add the current count value in the addition and subtraction counter; The output end of the instruction generation unit is used to output the current source control instruction, and the current source control instruction is a target count value obtained by adding and subtracting the current count value.

7. The crystal oscillator circuit according to claim 1 or 4, characterized in that: The oscillation stop detection subcircuit comprises: a fifth inverter and a sixth inverter, a first D flip-flop and a second D flip-flop, and a NOR gate; The input end of the fifth inverter is connected to the output end of the Schmitt inverter with the smallest window size; the output end of the fifth inverter is connected to the input end of the sixth inverter and the first input end of the first D flip-flop, and the second input end of the first D flip-flop is connected to the output end of the Schmitt inverter with a non-smallest window size; The output terminal of the sixth inverter is connected to the first input terminal of the second D flip-flop, and the second input terminal of the second D flip-flop is connected to the output terminal of the inverter with the non-minimum window; The output end of the first D flip-flop is connected to the first input end of the NOR gate, and the output end of the second D flip-flop is connected to the second input end of the NOR gate.

8. The crystal oscillator circuit according to claim 1, characterized in that: The passive crystal oscillator unit comprises: A passive crystal, a first capacitor, and a second capacitor; The first end of the passive crystal is connected to the gate of the field effect transistor and the first end of the first capacitor, and the second end of the first capacitor is grounded; The second end of the passive crystal is connected to the drain of the field effect transistor and the first end of the second capacitor, and the second end of the second capacitor is grounded.

9. The crystal oscillator circuit according to claim 3 or 4, characterized in that: Also includes: When the crystal oscillator amplitude is larger than the window size of the third Schmitt inverter and smaller than the window size of the first Schmitt inverter and the window size of the second Schmitt inverter, the third Schmitt inverter works to output a clock signal, and the outputs of the first Schmitt inverter and the second Schmitt inverter are always kept at a high level or a low level; The outputs of the first oscillation stop detection subcircuit and the second oscillation stop detection subcircuit are high level.

10. The crystal oscillator circuit according to claim 3, characterized in that: Also includes: When the crystal oscillator amplitude is larger than the window size of the second Schmitt inverter and smaller than the window size of the first Schmitt inverter, the second Schmitt inverter and the third Schmitt inverter operate and output a clock signal, and the output of the first Schmitt inverter is always kept at a high level or a low level; The output of the first oscillation stop detection subcircuit is a high level, and the output of the second oscillation stop detection subcircuit is a low level.

11. The crystal oscillator circuit according to claim 3, characterized in that: Also includes: When the crystal oscillator amplitude is greater than the window size of the first Schmitt inverter, the first Schmitt inverter, the second Schmitt inverter and the third Schmitt inverter all work and output a clock signal; The outputs of the first oscillation stop detection subcircuit and the second oscillation stop detection subcircuit are at a low level.

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