Chip performance verification method and device, electronic equipment and storage medium

Abstract

The embodiment of the application discloses a chip performance verification method and device, electronic equipment and storage medium, relates to the field of electronic design automation, and can effectively improve the chip performance verification efficiency.The method comprises the following steps: receiving model state information from a preset model environment of a chip to be verified through a performance statistical management platform; wherein the performance statistical management platform and the preset model environment communicate through a preset interface, and the preset model environment comprises at least one of the following: a function verification environment, a hardware simulation environment and a performance model environment; triggering the performance statistical management platform to generate a verification control signal according to the model state information; under the control of the verification control signal, receiving model running data of the chip to be verified from the preset model environment through a preset performance statistical component, and performing performance statistics on the model running data to obtain corresponding performance statistical results.The application is suitable for chip performance verification.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic design automation, and in particular to a chip performance verification method and device, an electronic device, and a storage medium. BACKGROUND

[0002] In the field of integrated circuit technology, a chip usually undergoes a series of functional verification and performance verification before being delivered to a foundry for manufacturing, so as to ensure that the manufactured chip can meet the design requirements. Among them, functional verification mainly refers to finding functional bugs and defects in the design through software simulation or hardware simulation before the chip is manufactured. Performance verification or performance evaluation mainly refers to evaluating whether the chip performance meets the expectation through software simulation or hardware simulation before the chip is manufactured.

[0003] In the field of integrated circuit verification, there is a very mature and general methodology for functional verification, such as UVM (Universal Verification Methodology), which has been widely used in functional verification. However, there is no industry-standard or methodology for performance verification or performance evaluation.

[0004] The performance verification method commonly used in the industry generally evaluates whether the performance meets the expectation by analyzing waveforms. The general process is as follows: some heavy-traffic test cases are run through software simulation or hardware simulation, and the generated waveforms are analyzed by design engineers or architecture engineers. The design engineers or architecture engineers need to open the waveforms in a waveform viewer, pull the signals related to performance to the waveform display window, and then perform some logical operations on the signals, such as performing logical AND operation on the Valid signal and the Clock signal, and then selecting a time period to count the number of rising edges or falling edges of the signal in the time period, so as to calculate the performance. However, due to the complicated steps, the performance analysis efficiency of this method is low. If multiple performance indicators of multiple modules need to be calculated, this process may take several hours. If the performance indicators in multiple application scenarios need to be analyzed, the required time will be multiplied.

[0005] There is no effective solution to the problem of low efficiency of integrated circuit chip performance verification in the related art. SUMMARY

[0006] Therefore, the embodiments of the present application provide a chip performance verification method and device, an electronic device, and a computer readable storage medium, which can effectively improve the chip performance verification efficiency.

[0007] In a first aspect, embodiments of the present application provide a chip performance verification method, the method comprising: receiving, by a performance statistical management platform, model state information from a preset model environment of a chip to be verified; wherein the performance statistical management platform and the preset model environment communicate through a preset interface, and the preset model environment comprises at least one of the following: a functional verification environment, a hardware simulation environment, and a performance model environment; triggering the performance statistical management platform to generate a verification control signal according to the model state information; under the control of the verification control signal, receiving, by a preset performance statistical component, model running data of the chip to be verified from the preset model environment, and performing performance statistics on the model running data to obtain corresponding performance statistical results, wherein the programming language based on which the performance statistical management platform is programmed is compatible with the programming language based on which the preset model environment is programmed and the programming language based on which the performance statistical component is programmed.

[0008] Optionally, the triggering the performance statistical management platform to generate a verification control signal according to the model state information comprises: triggering the performance statistical management platform to generate a start statistics signal according to a start running signal in the model state information; or triggering the performance statistical management platform to generate a stop statistics signal according to a stop running signal in the model state information.

[0009] Optionally, before the receiving, by a preset performance statistical component, model running data of the chip to be verified from the preset model environment under the control of the verification control signal, the method further comprises: adding a pointer of the performance statistical component to a component pointer index preset in the performance statistical management platform or to a component pointer index preset in a subordinate sub-platform of the performance statistical management platform according to a preset component affiliation; and / or adding a pointer of each of the subordinate sub-platforms to a sub-platform pointer index preset in a corresponding upper-level sub-platform or to a sub-platform pointer index preset in the performance statistical management platform according to a preset platform affiliation.

[0010] Optionally, the receiving, by a preset performance statistical component, model running data of the chip to be verified from the preset model environment under the control of the verification control signal, and performing performance statistics on the model running data comprises: the performance statistical management platform sending the verification control signal to each of the performance statistical components, wherein the performance statistical components are directly managed by the performance statistical management platform or are managed by a subordinate sub-platform of the performance statistical management platform; each of the performance statistical components receiving corresponding model running data according to the verification control signal; and each of the performance statistical components performing performance statistics on the model running data according to a respective statistical attribute.

[0011] Optionally, the performance statistics management platform sends the verification control signals to each of the performance statistics components, including: if each of the performance statistics components is directly managed by the performance statistics management platform, the performance statistics management platform acquires a pointer of each of the performance statistics components from a component pointer index preset by the performance statistics management platform, and sends the verification control signals to each of the performance statistics components according to the pointer of each of the performance statistics components; if each of the performance statistics components is managed by a subordinate sub-platform of the performance statistics management platform, the performance statistics management platform acquires a pointer of a first sub-platform where each of the performance statistics components is located from a sub-platform pointer index preset by the performance statistics management platform, acquires the first sub-platform according to the pointer of the first sub-platform, and acquires a pointer of each of the performance statistics components from a component pointer index preset by the first sub-platform, and sends the verification control signals to each of the performance statistics components according to the pointer of each of the performance statistics components.

[0012] Optionally, each of the performance statistics components receives the model running data corresponding thereto according to the verification control signals, including: each of the performance statistics components determines start or end of a statistical task according to the verification control signals; each of the performance statistics components receives the model running data corresponding thereto in response to start of the statistical task; and each of the performance statistics components stops receiving the model running data corresponding thereto in response to end of the statistical task.

[0013] Optionally, each of the performance statistics components performs performance statistics on the model running data according to a statistical attribute corresponding thereto, including: each of the performance statistics components determines each statistical window in a life cycle of the statistical task and a statistical category of the statistical task according to the statistical attribute corresponding thereto, wherein each of the statistical windows is sequentially connected at ends thereof to form the life cycle of the statistical task; each of the performance statistics components records a stage statistic quantity and a total statistic quantity of the model running data according to the verification control signals, the statistical windows and the statistical category, wherein a statistical time of the stage statistic quantity is one of the statistical windows, and a statistical time of the total statistic quantity is from start of the statistical task to a current time; each of the performance statistics components determines a stage performance of each of the statistical windows of the to-be-verified chip according to the stage statistic quantity, and determines a total performance of the to-be-verified chip according to the total statistic quantity.

[0014] Optionally, the statistical category includes a packet speed statistic; the stage statistic includes a stage packet number; the overall statistic includes an overall packet number; and the determining the stage performance of each statistical window according to the stage statistic and the determining the overall performance according to the overall statistic include determining a stage average packet speed according to the stage packet number and a statistical time of the stage statistic, and determining an overall average packet speed according to the overall packet number and a statistical time of the overall statistic.

[0015] Optionally, the statistical category includes a throughput rate statistic; the stage statistic includes a stage throughput; the overall statistic includes an overall throughput; and the determining the stage performance of each statistical window according to the stage statistic and the determining the overall performance according to the overall statistic include determining a stage average throughput rate according to the stage throughput and a statistical time of the stage statistic, and determining an overall average throughput rate according to the overall throughput and a statistical time of the overall statistic.

[0016] Optionally, the statistical category includes a numerical value statistic; the stage statistic includes a stage accumulated value; the overall statistic includes an overall accumulated value; and the determining the stage performance of each statistical window according to the stage statistic and the determining the overall performance according to the overall statistic include determining a stage average value according to the stage accumulated value and a statistical time of the stage statistic, and determining an overall average value according to the overall accumulated value and a statistical time of the overall statistic.

[0017] Optionally, the stage statistic further includes a stage maximum value and a stage minimum value, and the overall statistic further includes an overall maximum value and an overall minimum value.

[0018] Optionally, after the corresponding performance statistic result is obtained, the method further includes writing the performance statistic result into a log file, parsing the log file and writing a parsing result into a preset file, and generating a performance chart and / or curve of the chip to be verified by using the parsing result in the preset file, wherein the preset file includes a comma separated file and / or a data table file.

[0019] In a second aspect, embodiments of the present application also provide a chip performance verification device, comprising: a receiving unit configured to receive model state information from a preset model environment of a chip to be verified by a performance statistics management platform; wherein the performance statistics management platform and the preset model environment communicate through a preset interface, and the preset model environment comprises at least one of a function verification environment, a hardware simulation environment, and a performance model environment; a triggering unit configured to trigger the performance statistics management platform to generate a verification control signal according to the model state information; and a statistics unit configured to receive model running data of the chip to be verified from the preset model environment through a preset performance statistics component under control of the verification control signal, and perform performance statistics on the model running data to obtain corresponding performance statistics results, wherein a programming language based on which the performance statistics management platform is programmed is compatible with a programming language based on which the preset model environment is programmed and a programming language based on which the performance statistics component is programmed.

[0020] Optionally, the triggering unit is specifically configured to trigger the performance statistics management platform to generate a start statistics signal according to a start running signal in the model state information, or to trigger the performance statistics management platform to generate a stop statistics signal according to a stop running signal in the model state information.

[0021] Optionally, the chip performance verification device provided by the embodiments of the present application further comprises: a component adding unit configured to add a pointer of the performance statistics component to a component pointer index preset by the performance statistics management platform or to a component pointer index preset by a subordinate sub-platform of the performance statistics management platform in accordance with a preset component affiliation relationship before the model running data of the chip to be verified is received from the preset model environment by the performance statistics component under control of the verification control signal; and / or a sub-platform adding unit configured to add a pointer of each of the subordinate sub-platforms to a sub-platform pointer index preset by a corresponding superior sub-platform or to a sub-platform pointer index preset by the performance statistics management platform in accordance with a preset platform affiliation relationship before the model running data of the chip to be verified is received from the preset model environment by the performance statistics component under control of the verification control signal.

[0022] Optionally, the statistical unit comprises: a signal issuing module, configured to issue the verification control signal to each of the performance statistical components by the performance statistical management platform, wherein the performance statistical components are directly managed by the performance statistical management platform or are managed by a subordinate sub-platform of the performance statistical management platform; a data receiving module, configured to receive the model running data corresponding to each of the performance statistical components according to the verification control signal; and a data statistical module, configured to perform performance statistics on the model running data according to the statistical attribute of each of the performance statistical components.

[0023] Optionally, the signal issuing module is specifically configured to: if the performance statistical components are directly managed by the performance statistical management platform, acquire the pointer of the performance statistical components from the component pointer index preset by the performance statistical management platform, and issue the verification control signal to each of the performance statistical components according to the pointer of the performance statistical components; and if the performance statistical components are managed by the subordinate sub-platform of the performance statistical management platform, acquire the pointer of the first sub-platform where the performance statistical components are located from the sub-platform pointer index preset by the performance statistical management platform, acquire the first sub-platform according to the pointer of the first sub-platform, and acquire the pointer of the performance statistical components from the component pointer index preset by the first sub-platform, and issue the verification control signal to each of the performance statistical components according to the pointer of the performance statistical components.

[0024] Optionally, the data receiving module comprises: a first determining sub-module, configured to determine the start or end of the statistical task of each of the performance statistical components according to the verification control signal; a receiving sub-module, configured to receive the model running data corresponding to each of the performance statistical components in response to the start of the statistical task; and a stopping sub-module, configured to stop receiving the model running data corresponding to each of the performance statistical components in response to the end of the statistical task.

[0025] Optionally, the data statistics module comprises: a second determination submodule, configured to determine, for each performance statistics component, each statistics window in the life cycle of the statistics task and a statistics category of the statistics task according to a respective statistics attribute, wherein each statistics window is sequentially connected at the head and tail to form the life cycle of the statistics task; a recording submodule, configured to record, for each performance statistics component, a stage statistics quantity and an overall statistics quantity of the model running data according to the verification control signal, the statistics window and the statistics category, wherein the statistics time of the stage statistics quantity is one statistics window, and the statistics time of the overall statistics quantity is from the start of the statistics task to the current time; and a third determination submodule, configured to determine, for each performance statistics component, a stage performance of the to-be-verified chip in each statistics window according to the stage statistics quantity, and determine an overall performance of the to-be-verified chip according to the overall statistics quantity.

[0026] Optionally, the statistics category comprises packet speed statistics, the stage statistics quantity comprises a stage packet quantity, the overall statistics quantity comprises an overall packet quantity, and the third statistics submodule is specifically configured to determine a stage average packet speed according to the stage packet quantity and the statistics time of the stage statistics quantity, and determine an overall average packet speed according to the overall packet quantity and the statistics time of the overall statistics quantity.

[0027] Optionally, the statistics category comprises throughput rate statistics, the stage statistics quantity comprises a stage throughput quantity, the overall statistics quantity comprises an overall throughput quantity, and the third statistics submodule is specifically configured to determine a stage average throughput rate according to the stage throughput quantity and the statistics time of the stage statistics quantity, and determine an overall average throughput rate according to the overall throughput quantity and the statistics time of the overall statistics quantity.

[0028] Optionally, the statistics category comprises numerical value statistics, the stage statistics quantity comprises a stage cumulative value, and the overall statistics quantity comprises an overall cumulative value, and the third statistics submodule is specifically configured to determine a stage average value according to the stage cumulative value and the statistics time of the stage statistics quantity, and determine an overall average value according to the overall cumulative value and the statistics time of the overall statistics quantity.

[0029] Optionally, the stage statistics quantity further comprises a stage maximum value and a stage minimum value, and the overall statistics quantity further comprises an overall maximum value and an overall minimum value.

[0030] Optionally, the chip performance verification apparatus provided by the embodiments of the present application further comprises a writing unit configured to write the performance statistical result into a log file after obtaining the corresponding performance statistical result; an analyzing unit configured to analyze the log file and write the analysis result into a preset file, wherein the preset file comprises a comma separated file and / or a data table file; and a generating unit configured to generate a performance chart and / or a curve of the chip to be verified by using the analysis result in the preset file.

[0031] In a third aspect, the embodiments of the present application further provide an electronic device, comprising a housing, at least one processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is arranged inside a space enclosed by the housing, the processor and the memory are arranged on the circuit board; the power supply circuit is configured to supply power to each circuit or device of the electronic device; the memory is configured to store executable program codes; and the at least one processor is configured to run a program corresponding to the executable program codes by reading the executable program codes stored in the memory, so as to execute any chip performance verification method provided by the embodiments of the present application.

[0032] In a fourth aspect, the embodiments of the present application further provide a computer readable storage medium, which stores one or more programs executable by one or more processors to implement any chip performance verification method provided by the embodiments of the present application.

[0033] The chip performance verification method and apparatus, the electronic device and the computer readable storage medium provided by the embodiments of the present application can receive model state information from a preset model environment of a chip to be verified through a performance statistical management platform, trigger the performance statistical management platform to generate a verification control signal according to the model state information, and receive model running data of the chip to be verified from the preset model environment through a preset performance statistical component under the control of the verification control signal, and perform performance statistics on the model running data to obtain corresponding performance statistical result. In this way, since the programming language based on which the performance statistical management platform is implemented is compatible with the programming language based on which the preset model environment is implemented and the programming language based on which the performance statistical component is implemented, the performance statistical operation of the chip to be verified can be easily integrated with the preset model environment such as a function verification environment, a hardware simulation environment and a performance model environment of the chip to be verified, and the performance information of the chip to be verified can be easily obtained and the performance verification can be completed by means of the preset model environment or at the same time of performing the function verification or other simulation and verification operations, without generating a waveform and without manually performing statistical comparison, thereby effectively improving the chip performance verification efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to make the technical ideas, implementation schemes and beneficial technical effects of the embodiments of the present application clearer, the following will be described in detail through specific embodiments.

[0035] Figure 1 A flow chart of a chip performance verification method provided by an embodiment of the present application;

[0036] Figure 2 A schematic diagram of an organization structure of a statistical management platform in a chip performance verification method provided by an embodiment of the present application;

[0037] Figure 3 A program architecture schematic diagram for implementing a chip performance verification method in an embodiment of the present application;

[0038] Figure 4 A flow chart of outputting statistical results in an embodiment of the present application;

[0039] Figure 5 A flow chart of performing packet speed statistics in an embodiment of the present application;

[0040] Figure 6 A flow chart of performing numerical statistics in an embodiment of the present application;

[0041] Figure 7 A structural schematic diagram of a chip performance verification device provided by an embodiment of the present application;

[0042] Figure 8 A structural schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0043] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0044] It should be clear that the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0045] In order to make those skilled in the art better understand the technical ideas, implementation schemes and beneficial technical effects of the embodiments of the present application, the following will be described in detail through specific embodiments.

[0046] In a first aspect, an embodiment of the present application provides a chip performance verification method, which can effectively improve the chip performance verification efficiency.

[0047] As Figure 1 shown, the chip performance verification method provided by the embodiment of the application can include:

[0048] S11, receiving model state information from a preset model environment of a chip to be verified through a performance statistical management platform; wherein the performance statistical management platform and the preset model environment communicate through a preset interface, and the preset model environment includes at least one of the following: a functional verification environment, a hardware simulation environment, and a performance model environment;

[0049] The performance statistical management platform can be mainly used for managing the performance verification operation of the chip and statistically processing performance data, which can be, for example, transmission or processing delay, throughput rate, cache or FIFO (first in first out) occupancy depth, back pressure rate, signal flip rate, etc. The performance statistical management platform can be established through a programming language. For example, the related operations of performance statistical management can be encapsulated into a class, and the class is instantiated as an object to obtain the corresponding performance statistical management platform.

[0050] Since the performance of the chip is dynamically embodied in a certain running environment through the running of the chip, the performance statistical management platform can also be based on the running of the chip to be verified in the running environment when performing performance statistics. In the embodiment of the application, the running environment of the chip to be verified when performing performance verification can be referred to as a preset model environment. Optionally, the preset model environment can be specially designed for verifying the performance of the chip, or can be designed when the chip is functionally verified or verified in other aspects, as long as the chip can embody at least part of the performance in the preset model environment when running in the preset model environment. For example, in an embodiment of the application, the preset model environment can include one or more of a functional verification environment, a hardware simulation environment, and a performance model environment.

[0051] The performance statistical management platform can communicate with the preset model environment through a preset interface, for example, can receive model state information from the preset model environment through the preset interface. The model state information can refer to the state of the model running in the preset model environment, for example, starting running, pausing running, ending running, running, etc.

[0052] In order to make the performance verification more widely and efficiently applied, and also to make the performance verification of the chip more accurate, in the embodiment of the application, the programming language based on which the performance statistical management platform is established is compatible with the programming language based on which the preset model environment is established, thereby breaking down the barriers of different environments. For example, in an embodiment of the application, the performance statistical management platform and the preset model environment can both be established based on the hardware verification language systemVerilog.

[0053] S12, triggering the performance statistics management platform to generate a verification control signal according to the model state information;

[0054] After the performance statistics management platform receives the model state information from the preset model environment, in this step, the performance statistics management platform can be triggered to generate a verification control signal according to the preset model state information. The verification control signal can be used to control the performance statistics operation. The performance of the chip to be verified is embodied when the chip to be verified runs in the preset model environment. Therefore, the running state of the chip to be verified in the preset model environment will directly affect the performance statistics operation. For example, when performing performance statistics, the statistics can be started according to the running of the chip to be verified in the preset model environment, and the statistics can be ended according to the stop of the running of the chip to be verified.

[0055] S13, under the control of the verification control signal, receiving model running data of the chip to be verified from the preset model environment through a preset performance statistics component, and performing performance statistics on the model running data to obtain corresponding performance statistics results, wherein the programming language based on which the performance statistics management platform is based, the programming language based on which the preset model environment is based, and the programming language based on which the performance statistics component is based are compatible with each other.

[0056] After the performance statistics management platform generates the verification control signal, the preset performance statistics component can receive the model running data of the chip to be verified from the preset model environment under the control of the verification control signal, and perform performance statistics on the model running data. Similar to the performance statistics management platform, the performance statistics component can be implemented through a programming language. For example, the related operations of the performance statistics operation can be packaged into a corresponding statistics class, and the statistics class is instantiated into a statistics class object, and the statistics class object is the corresponding performance statistics component. Optionally, in an embodiment of the present application, some basic statistics operations can be packaged into a statistics base class, and different statistics classes can be derived from the statistics base class.

[0057] In an embodiment of the present application, performance statistics refers to mathematical statistics on the performance of the chip to be verified in the process of running in the preset model environment. Optionally, when performing performance statistics, the performance statistics component can receive each model running parameter transmitted from the preset model environment, analyze the model running parameter, and select a part of the data for recording. For example, the data that best represents the performance of the chip can be selected for recording, so as to accurately reflect the performance of the chip while greatly reducing the data storage burden, and further improving the performance statistics efficiency of the chip.

[0058] Optionally, the performance statistics components can also correspond to different according to the different specific performance statistics, and each performance statistics management platform can correspond to manage one or more performance statistics components, for example, in an embodiment of the present application, the performance statistics management platform can correspond to manage one or more performance statistics components for counting transmission delay, one or more performance statistics components for counting throughput, etc.

[0059] In order to make the performance verification more widely and efficiently applied, and also to make the performance verification of the chip more accurate, in an embodiment of the present application, the programming language based on which the performance statistics components are, the programming language based on which the performance statistics management platform is, and the programming language based on which the preset model environment is, are also compatible with each other, for example, all of them can be based on systemVerilog.

[0060] The chip performance verification method provided by the embodiment of the present application can receive model state information from a preset model environment of a chip to be verified by a performance statistics management platform, trigger the performance statistics management platform to generate a verification control signal according to the model state information, receive model running data of the chip to be verified from the preset model environment by a preset performance statistics component under the control of the verification control signal, and perform performance statistics on the model running data to obtain corresponding performance statistics results. In this way, since the programming language based on which the performance statistics management platform is, the programming language based on which the preset model environment is, and the programming language based on which the performance statistics component is, are compatible with each other, the performance statistics operation of the chip to be verified can be easily integrated with the preset model environment such as the function verification environment, the hardware simulation environment, and the performance model environment of the chip to be verified, and the performance information of the chip to be verified can be obtained and the performance verification can be completed by means of the above preset model environment or at the same time of performing the function verification or other simulation, verification, etc., without generating waveforms and manually performing statistics and comparison, thereby effectively improving the chip verification efficiency.

[0061] Further, in the case where the preset model environment includes the function verification environment or the hardware simulation environment, since the function verification and the hardware simulation are very close to the real situation of the chip and are widely used in the field of chip verification, the performance statistics results obtained therefrom will also have good accuracy, which is much better than the performance analysis by using other commercial tools or high-level modeling languages (for example, SystemC), and therefore, the accuracy of the performance verification can be greatly improved while effectively improving the efficiency of the chip verification.

[0062] Specifically, after receiving the model state information from the preset model environment of the chip to be verified in step Sll, the performance statistics management platform can be triggered to generate a verification control signal according to the received model state information in step S12. Optionally, the generated verification control signal is different according to the different model state information. For example, in an embodiment of the present application, a start statistics signal can be generated by the performance statistics management platform according to the start running signal in the model state information; or a stop statistics signal can be generated by the performance statistics management platform according to the stop running signal in the model state information.

[0063] For example, when the chip to be verified in the preset model environment is in a running state, the performance statistics management platform receives the model state information of "running", and generates a verification control signal of "performing statistics operation" according to the model state information of "running"; when the chip to be verified in the preset model environment is in a stop state, the performance statistics management platform receives the model state information of "stop running", and generates a verification control signal of "stopping statistics operation" according to the model state information of "stop running".

[0064] After the performance statistics management platform generates the verification control signal, the model running data of the chip to be verified can be received from the preset model environment by the preset performance statistics component under the control of the verification control signal in step S13, and the performance statistics of the model running data can be performed.

[0065] Specifically, in order to facilitate the performance verification of different circuit modules in the chip to be verified, in an embodiment of the present application, the performance statistics management platform can be managed in layers, and each relatively independent circuit module can correspond to a lower-level sub-platform, and the performance statistics operation of the circuit module can be controlled by controlling the lower-level sub-platform. For example, as shown in Figure 2 In an embodiment of the present application, one or more lower-level sub-platforms can be set under the performance management platform. Each lower-level sub-platform and the performance statistics management platform can be based on the same class, and different instantiations of the class are obtained, so that the variables and / or member functions corresponding to each lower-level sub-platform and the performance statistics management platform can be the same. Optionally, each performance statistics component can be directly managed by the performance statistics management platform, or can be managed by the lower-level sub-platform of the performance statistics management platform. The performance statistics management platform can call its direct lower-level sub-platform and / or performance statistics component, and similarly, each level of sub-platform can call its direct lower-level sub-platform and / or performance statistics component, thereby realizing the hierarchical logic.

[0066] Based on this, in step S12, under the control of the verification control signal, the model running data of the chip to be verified is received from the preset model environment by the preset performance statistical component, and the performance statistics of the model running data are specifically as follows:

[0067] The performance statistical management platform sends the verification control signal to each performance statistical component;

[0068] Each performance statistical component receives the corresponding model running data according to the verification control signal;

[0069] Each performance statistical component performs performance statistics on the model running data according to the statistical attribute.

[0070] Specifically, in order to better control each performance statistical component, in an embodiment of the present application, the performance statistical management platform and its subordinate sub-platforms can manage their respective subordinate sub-platforms and performance statistical components by means of a pointer queue. For example, a component pointer index and a sub-platform pointer index can be pre-set in the performance statistical management platform, the pointers of the components to be verified are added to the component pointer index, and the pointers of the sub-platforms to be verified are added to the sub-platform index. When the verification control signal needs to be sent to the performance statistical components and / or the subordinate sub-platforms, the verification control signal can be sent to the corresponding performance statistical components through the component pointer index and the sub-platform pointer index. Similarly, each subordinate sub-platform can also set its own component pointer index and sub-platform pointer index and perform similar management operations, thereby forming a hierarchical management structure. Optionally, the pointer index here can have various forms as long as the corresponding pointer can be obtained according to the pointer index. For example, the pointer index can include a pointer queue, a pointer array, a pointer set, a pointer linked list, etc.

[0071] In order to add the above various pointers to the corresponding pointer index, optionally, before receiving the model running data of the chip to be verified from the preset model environment by the preset performance statistical component under the control of the verification control signal, the chip performance verification method provided by the embodiment of the present application can further include: adding the pointer of the performance statistical component to the component pointer index pre-set in the performance statistical management platform or to the component pointer index pre-set in the subordinate sub-platform of the performance statistical management platform according to the pre-set component affiliation; and / or adding the pointer of each subordinate sub-platform to the sub-platform pointer index pre-set in the corresponding upper-level sub-platform or to the sub-platform pointer index pre-set in the performance statistical management platform according to the pre-set platform affiliation, so that the performance statistical management forms a hierarchical organizational structure.

[0072] Through this hierarchical organizational structure, the performance management and statistics platform can conveniently select a portion of the circuit modules of the chip to be verified for verification as needed, or verify each circuit module separately or uniformly, thereby effectively improving the flexibility of chip performance verification.

[0073] Based on the organizational structure of the performance statistics management platform described above, optionally, in one embodiment of the present invention, the performance statistics management platform sending the verification control signal to each of the performance statistics components may specifically include:

[0074] If the performance statistics component is directly under the management of the performance statistics management platform, the performance management platform obtains the pointer of the performance statistics component from the component pointer index preset by the performance management platform, and sends the verification control signal to the performance statistics component according to the pointer of the performance statistics component.

[0075] If the performance statistics component is under the management of a lower-level sub-platform of the performance statistics management platform, the performance management platform obtains the pointer of the first sub-platform where the performance statistics component is located from the sub-platform pointer index preset by the performance management platform; obtains the first sub-platform based on the pointer of the first sub-platform, and obtains the pointer of the performance statistics component from the component pointer index preset by the first sub-platform; and sends the verification control signal to the performance statistics component according to the pointer of the performance statistics component.

[0076] For example, such as Figure 2 As shown, when the statistical management platform A1 needs to send a verification control signal to the statistical component B1, the statistical management platform A1 can directly obtain the pointer of the statistical component B1 from the component pointer index under the statistical management platform A1, and send the verification control signal to the performance statistical component B1 according to the pointer. When the statistical management platform A1 needs to send a verification control signal to the statistical component B2, the statistical management platform A1 can obtain the pointer of the sub-platform A2 from the sub-platform pointer index under the statistical management platform A1, and obtain the sub-platform A2 according to the pointer. The sub-platform A2 can further obtain the pointer of the statistical component B2 from the component pointer index under the statistical management platform A2, and send the verification control signal to the performance statistical component B2 according to the pointer.

[0077] After the performance statistics management platform sends the verification control signal to each of the performance statistics components, each of the performance statistics components can receive its corresponding model running data according to the verification control signal, and perform performance statistics on the model running data according to its own statistical attributes.

[0078] Specifically, the performance statistics components respectively receive the model running data corresponding thereto according to the verification control signal can include: each performance statistics component determines whether to start or end a statistical task according to the verification control signal; in response to the statistical task being started, each performance statistics component respectively receives the model running data corresponding thereto; and in response to the statistical task being ended, each performance statistics component respectively stops receiving the model running data corresponding thereto. Here, the model running data can refer to various data generated by the chip to be verified when running in a preset model environment such as a functional verification environment or a hardware simulation environment, for example, transmission or processing delay, cache or FIFO (first-in first-out) occupation depth, number of transmission or processing packets, and length of each packet, etc.

[0079] It can be understood that when the chip to be verified runs in the preset model environment, the performance to be counted can be multi-faceted, for example, both transmission delay and throughput rate need to be counted, then for each performance to be counted, a corresponding performance statistics component can be used to implement, and each performance statistics component can work in parallel. For example, each performance statistics component can start receiving model running data or stop receiving model running data at the same time based on the received verification control signal, so that the performance statistics of each aspect are unified.

[0080] Further, after receiving the model running data, each performance statistics component can perform performance statistics on the model running data according to the statistical attribute of each performance statistics component. The specific method of performance statistics can be determined according to the statistical attribute of each performance statistics component. The statistical attribute is a parameter used to describe the statistical characteristics of each performance statistics component, for example, whether the performance statistics component is for continuous statistics or intermittent statistics, which data needs to be counted, and what strategy is used to filter out these data, etc.

[0081] In order to effectively obtain the performance of each stage of the chip to be verified during running so as to more specifically improve the chip design, and also in order not to excessively increase the data storage amount so as to improve the performance verification efficiency, in an embodiment of the present application, in addition to verifying the overall performance of the chip to be verified, the statistical tasks performed by the performance statistics components can be divided into multiple statistical windows, and the statistical amount corresponding to each statistical window can be recorded in each statistical window. Within a certain range, the smaller the statistical window, the shorter the corresponding time, the more accurate the window statistical amount obtained, and the larger the data storage amount; the larger the statistical window, the longer the corresponding time, the more rough the window statistical amount obtained, and the smaller the data storage amount. Optionally, the statistical windows corresponding to different performance statistics components can be flexibly set or adjusted as needed. The statistical windows corresponding to different performance statistics components can be equal or not equal.

[0082] In addition to the statistical windows, the statistical categories of the performance statistical components are also different, and the corresponding statistical strategies are also different. Based on this, in an embodiment of the present application, the performance statistics of the model running data by the performance statistical components according to the respective statistical attributes can specifically include:

[0083] The performance statistical components respectively determine the statistical windows in the life cycle of the statistical task and the statistical categories of the statistical task according to the respective statistical attributes, wherein the statistical windows are connected in time sequence and constitute the life cycle of the statistical task.

[0084] The performance statistical components respectively record the stage statistics and the overall statistics of the model running data according to the verification control signal, the statistical windows and the statistical categories, wherein the statistical time of the stage statistics is one statistical window, and the statistical time of the overall statistics is from the start of the statistical task to the current time.

[0085] The performance statistical components determine the stage performance of the to-be-verified chip in each statistical window according to the stage statistics, and determine the overall performance of the to-be-verified chip according to the overall statistics.

[0086] For example, in an embodiment of the present application, the statistical category of the performance statistical component includes packet speed statistics, the stage statistics includes stage packet quantity, and the overall statistics includes overall packet quantity. Based on this, determining the stage performance of each statistical window according to the stage statistics and determining the overall performance according to the overall statistics can include: determining the stage average packet speed according to the stage packet quantity and the statistical time of the stage statistics, and determining the overall average packet speed according to the overall packet quantity and the statistical time of the overall statistics. For example, the statistical window is 10 nanoseconds, and the current has run for 3 statistical windows, wherein the data packet quantities processed by the statistical windows W1, W2 and W3 are 12, 18 and 27 respectively, and the stage average packet speeds are 1.2, 1.8 and 2.7 per nanosecond respectively. The overall packet quantity is 12+18+27=57, and the overall statistical time is 10+10+10=30 nanoseconds, so the overall average packet speed is 57 / 30=1.9 per nanosecond.

[0087] Optionally, in another embodiment of the present application, the statistic category of the performance statistics component includes throughput statistics, the stage statistics include stage throughput, and the overall statistics include overall throughput; and based on this, determining the stage performance of each statistics window according to the stage statistics and determining the overall performance according to the overall statistics can specifically include: determining the stage average throughput according to the stage throughput and the statistics time of the stage statistics, and determining the overall average throughput according to the overall throughput and the statistics time of the overall statistics.

[0088] For example, the statistics window is 10 nanoseconds, and 3 statistics windows have been run, in which the data processed by the statistics windows W1, W2 and W3 is 512 bits, 1024 bits and 2048 bits respectively, and the stage throughput is 51.2 bits / nanosecond, 102.4 bits / nanosecond and 204.8 bits / nanosecond respectively. The overall data is 512+1024+2048=3584 bits, and the overall statistics time is 10+10+10=30 (nanoseconds), so the overall average packet speed is 3584 / 30=119.5 (bits / nanosecond).

[0089] Optionally, in another embodiment of the present application, the statistic category of the performance statistics component includes value statistics, the stage statistics include stage accumulated value, and the overall statistics include overall accumulated value; and based on this, determining the stage performance of each statistics window according to the stage statistics and determining the overall performance according to the overall statistics can include: determining the stage average value according to the stage accumulated value and the statistics time of the stage statistics, and determining the overall average value according to the overall accumulated value and the statistics time of the overall statistics.

[0090] For example, the statistics window is 10 nanoseconds, and 3 statistics windows have been run, in which the data processed by the statistics windows W1, W2 and W3 is 512 bits, 1024 bits and 2048 bits respectively, and the stage throughput is 51.2 bits / nanosecond, 102.4 bits / nanosecond and 204.8 bits / nanosecond respectively. The overall data is 512+1024+2048=3584 bits, and the overall statistics time is 10+10+10=30 (nanoseconds), so the overall average packet speed is 3584 / 30=119.5 (bits / nanosecond).

[0091] Optionally, in value statistics, in addition to the stage accumulated value and the overall accumulated value, other characteristic values can also be counted, for example, the stage statistics can also include the stage maximum value and the stage minimum value, and the overall statistics can also include the overall maximum value and the overall minimum value.

[0092] The stage statistics and the overall statistics are performance statistics corresponding to the to-be-verified chip. After obtaining the corresponding performance statistics, the chip performance verification method provided by the embodiment of the present application further comprises: writing the performance statistics into a log file; parsing the log file and writing the parsing result into a preset file, wherein the preset file comprises a comma-separated file and / or a data table file; and generating a performance chart and / or a curve of the to-be-verified chip by using the parsing result in the preset file.

[0093] Since the performance verification process can be realized by using a programming language, the obtained performance statistics can also be output into a corresponding file by using the programming language. In order to make the statistics have good readability, in an embodiment of the present application, the performance statistics can be written into a log file. Optionally, the log file can be a text type file.

[0094] Further, in order to more intuitively and visually show the performance of the to-be-verified chip, in an embodiment of the present application, after writing the performance statistics into the log file, the log file can be parsed by using a script language to obtain performance parsing results, and the performance parsing results can be written into a comma-separated file and / or a data table file. Then, the performance chart and / or the curve of the to-be-verified chip can be conveniently generated by using the parsing results in the comma-separated file and / or the data table file, thereby effectively improving the visualization degree of the chip performance.

[0095] The chip performance verification method provided by the embodiment of the present application will be described in detail below by using specific embodiments.

[0096] The chip performance verification method provided by the embodiment of the present application can be written based on a hardware verification language, and can be very conveniently integrated in a functional verification environment or a performance model based on the hardware verification language. As shown in FIG. 1, Figure 3 The method is implemented by a performance statistics management platform (stat_manage), a statistics base class (stat_base), a packet speed statistics class (tps_stat), a throughput rate statistics class (bps_stat), a numerical value statistics class (num_stat), a log parsing script tool and the like. The first five parts can be realized based on the hardware verification language, and the last part can be realized based on a script language.

[0097] The performance statistics management platform can be used to manage all the statistics class objects (the statistics class objects are the performance statistics components mentioned above). The statistics class objects are instantiated from corresponding statistics classes. The statistics classes are inherited from the statistics base class. The statistics base class is the parent class of the statistics classes, and the statistics base class declares and implements some common methods. The statistics base class and the statistics classes will be described below. Figure 3 The statistics base class and the statistics classes will be described below.

[0098] (I) Performance statistics management platform

[0099] The performance statistics management platform can manage various performance statistics components and is the top layer structure of performance verification. A pointer queue for storing performance statistics component pointers can be set inside the statistics management platform:

[0100] stat_base m_child_stat[$];

[0101] A function for adding statistics component pointers to the pointer queue is also set in the performance statistics management platform:

[0102] function void add_child_stat(stat_base child)。

[0103] Engineers can instantiate various statistics classes in a preset model environment (for example, a verification environment or a performance model), obtain corresponding statistics class objects, and instantiate a statistics management platform. The statistics class object is the performance statistics component described above. The statistics class object can be added to the statistics management platform by calling the add_child_stat function, facilitating unified management of the statistics management platform.

[0104] Further, a queue for storing pointers of lower-level child platforms of the statistics management platform can also be set inside the performance statistics management platform:

[0105] stat_manage m_child_manage[$];

[0106] Optionally, the lower-level child platforms and the statistics management platform can have the same statistics class as the parent class, and therefore, the member functions of the lower-level child platforms and the performance statistics management platform can be the same, and performance statistics components and lower-level child platforms can also be set in the lower-level child platforms.

[0107] A function for adding lower-level child platforms to the queue can be set in the performance statistics management platform:

[0108] function void add_child_manage(stat_manage child);

[0109] Engineers can instantiate the statistics management platform and its lower-level child platforms in a preset model environment (for example, a verification environment or a performance model), and perform hierarchical management in a tree structure by calling the add_child_manage function. Exemplarily, the hierarchical structure of the performance statistics management platform can be as shown in Figure 2

[0110] ​In order to output the performance statistics result, the performance statistics management platform can further provide a function print_result for printing the statistics result. The function print_result can have an integer type parameter file_handle, and the default value of the parameter is 0. As shown in Figure 4 if the parameter file_handle = 0, a log file can be created in an "open" mode and a file handle is obtained, otherwise, if the parameter file_handle ≠ 0, the parameter can be directly used as the file handle for writing the log. Then, the function print_result can traverse all the statistics windows of the statistics management platform and its sub-platforms, and for each statistics window, if the current platform to which the statistics window belongs is the top layer statistics management platform, the start time of the statistics window can be printed, and the print_result function of each sub-management platform can be called recursively. Finally, the statistics result of the current statistics window of each statistics class object (i.e. performance statistics component) under the statistics management platform and its sub-platforms can be printed.

[0111] For example, the function print_result for printing the statistics result can be implemented as follows:

[0112]

[0113]

[0114] Further, in order to control the start and end of the performance statistics operation, the performance statistics management platform further defines a function start_stat for starting statistics and a function stop_stat for stopping statistics, and the user can start or end statistics by calling the functions. In the two functions, each sub-platform and each statistics class object will be traversed, and the start statistics function or the stop statistics function of each sub-platform and each statistics class object will be called, so as to start the performance statistics or stop the performance statistics of each sub-platform and each statistics class object at the same time.

[0115] For example, the function start_stat for starting statistics can be implemented as follows:

[0116]

[0117] Similarly, the function stop_stat for stopping statistics can be obtained.

[0118] (II) Statistics base class

[0119] The stat_base is a parent class of various statistic classes, which declares and implements some common methods. All statistic classes inherit from the stat_base.

[0120] In the stat_base, a statistic function stat is implemented, which is called by users to count data. In the statistic function, it is determined whether the statistics has been started. If it is in the started state, the incoming data to be counted is stored in the statistic data box (m_stat_data_box). The statistic data box is equivalent to a cache.

[0121] For example, the statistic function stat can be implemented as follows:

[0122]

[0123]

[0124] wherein value is the incoming data to be counted, and the data type of value is bit, and the bit width of value is PERF_STAT_DATA_WIDTH.

[0125] In the stat_base, a pure virtual function phase_result2string is also declared, which is used to return the statistic result of a statistic window, and the start time of the statistic window is passed in through the function parameter.

[0126] pure virtual function void phase_result2string(bit[63:0]phase_time);

[0127] In the stat_base, a pure virtual statistic task do_stat is also declared, which is responsible for counting data and recording the result.

[0128] In the statistical base class, a function start_stat for starting statistics and a function stop_stat for stopping statistics are defined, and the two functions can be called by the function start_stat for starting statistics and the function stop_stat for stopping statistics in the statistical management platform, so that the statistical management platform can uniformly start or stop the statistical tasks of all statistical objects. It should be noted that the statistical base class is the parent class of each statistical class, and the function start_stat for starting statistics and the function stop_stat for stopping statistics are set in each statistical class, that is, the function start_stat for starting statistics and the function stop_stat for stopping statistics are member functions of each statistical class, and the name of the corresponding statistical class object needs to be added in front of the member function when the member function is called, so as not to be confused with the function start_stat for starting statistics and the function stop_stat for stopping statistics in the statistical management platform.

[0129] In the start_stat function of the statistical base class, a flag indicating that the statistics has been started can be set, and the time when the statistics starts can be recorded, and the do_stat task is started.

[0130] For example, the start_stat function of the statistical base class can be implemented as follows:

[0131]

[0132]

[0133] In the stop_stat function, the time when the statistics stops is recorded, and a flag indicating that the statistics has been stopped is set. For example, the stop_stat function of the statistical base class can be implemented as follows:

[0134]

[0135] Based on the statistical base class, various specific statistical classes can be derived, which are illustrated as follows.

[0136] (Three) Packet Speed Statistical Class

[0137] The packet speed statistical class (tps_stat) inherits from the above statistical base class, and can be used to count the packet speed of each node in the chip, that is, how many packets are transmitted or processed per second.

[0138] In the packet speed statistical class, the pure virtual statistical task do_stat declared in the statistical base class is implemented. For example, Figure 5When the task is started, it enters a while(1) loop immediately. In the loop body, it first delays for one time unit, then judges whether the statistics has been stopped. If the statistics has been stopped, it jumps out of the loop body and ends the task. If the statistics has not been stopped, it tries to get data from the statistics data box (m_stat_data_box). If it succeeds in getting data, it accumulates the statistics data. In the statistics class, two accumulations are recorded, one is the phase accumulation, and the other is the total accumulation, which are used to calculate the phase packet speed (i.e. the packet speed of the statistics window) and the total packet speed respectively. The next step in the loop body is to judge whether the current statistics window is over. If the statistics window is over, it calculates and records the statistics result. The statistics result is stored in the form of an associative array (hash), and the index is the start time of the statistics window. After calculating the phase packet speed, the phase accumulation is cleared.

[0139] The formula for calculating the phase packet speed is:

[0140] Phase packet speed = phase accumulation / statistics window time

[0141] The formula for calculating the total packet speed is:

[0142] Total packet speed = total accumulation / (current time - statistics start time)

[0143] Further, in the packet speed statistics class, the pure virtual function phase_result2string declared in the statistics base class is also implemented, which is used to return the window statistics data to the statistics management platform. The parameter passed into the function is the start time of the statistics window. In the function, it first judges whether the statistics result associative array contains the statistics result of the start time. If it contains the statistics result, it reads the statistics result from the associative array, and then splices the rate unit and the text description together to return a string. If it does not contain the statistics result, it returns an empty string.

[0144] (Four) Throughput Rate Statistics Class

[0145] The throughput rate statistics class (bps_stat) also inherits from the above statistics base class, and like the packet speed statistics class, it belongs to the rate class statistics. Its statistics function and statistics task are the same as those of the packet speed statistics class. The only difference between the two is that the rate unit used in the phase_result2string function is different. For example, the rate unit corresponding to the throughput rate statistics class is bits / nanosecond, while the rate unit corresponding to the packet speed statistics class is packets / nanosecond.

[0146] (Five) Numerical Statistics Class

[0147] The num_stat class also inherits from the above statistical base class, and can count the maximum, minimum and average of a performance metric within a statistical window. The target of the statistics can be any numerical metric, such as latency, backpressure rate, cache or FIFO occupancy depth, signal flip rate, etc.

[0148] Similar to the packet speed statistical class, the num_stat class also implements its own statistical task do_stat. As shown in Figure 6 the statistical task is a while(1) loop inside. In the loop body, first delay a time unit, and then determine whether the current has called the stop statistics function. If the statistics has been stopped, jump out of the loop body and end the task. If the statistics has not been stopped, try to get data from the statistical data box (m_stat_data_box). If the data acquisition is successful, record the maximum, minimum and cumulative value of the data, and record the data number for calculating the average. When a statistical window ends, calculate the phase average and overall average by dividing the cumulative value by the data number, and then record the statistical results in the associated array (hash) with the starting time of the statistical window as the index. After recording the data once, the phase maximum, minimum and average values need to be reset.

[0149] (VI) Statistical log format and parsing script

[0150] In the statistical log, the statistical starting time of each statistical window can be printed, and special symbols such as "#" and "+" can be added to the left and right of the statistical time. The special symbols are used to facilitate the extraction of time for parsing and to make the log neat and beautiful. Below the statistical time line, the names of the statistical objects and the statistical results are printed. The name of the statistical object can occupy a line, and special symbols "--" are added to the left and right to facilitate script parsing and aesthetics. The statistical result phase value and overall value are in the same line, separated by "|".

[0151] For example, part of the statistical log can be:

[0152] ############################100ns#########################

[0153] --------------------input_downstream_req_tps(MT / s)-------------------

[0154] Phase|Total:1030.00MT / s|188.7MT / s

[0155] --------------------input_downstream_data_bps(Gb / s)-------------------

[0156] Phase | Total: 263.00 Gb / s | 61.00 Gb / s

[0157] In order to show the statistical results to the user, the statistical log can be read by a log parsing script, and the statistical results can be parsed and extracted to write into a comma-separated (CSV, Comma-Separated Values) file or a data table file. The parsing script reads each line of the log file, and uses three regular expressions for matching for each line. The three regular expressions match the statistical time line, the statistical object name line and the statistical data line, respectively. After any of the above three regular expressions is matched successfully, the required strings, such as the statistical start time, the statistical object name, the statistical data and the like, are recorded. After the data line is matched, a line of data can be recorded into a DataFrame, and the line number of the DataFrame is increased by 1. Here, the DataFrame is a data structure in the Pandas library in Python, which is similar to excel, and is a two-dimensional table, and can be used to store numerical values, strings and the like. After all lines of the log are parsed, the data in the DataFrame can be written into a comma-separated file or a data table file. Further, a chart and / or a curve can be generated by using the data written into the comma-separated file or the data table file, so that the performance statistical results are more intuitively shown.

[0158] (Seven) Application of the performance verification method in pre-silicon performance analysis

[0159] The chip performance verification method provided by the embodiments of the present application is based on the hardware verification language systemverilog, and therefore can be applied to any simulation platform built using systemverilog. Typically, the method can be applied to an EDA functional verification platform and a performance model built using systemverilog.

[0160] Specifically, in the EDA functional verification platform, a statistics class can be instantiated within the monitor to obtain a statistics class object (i.e., a performance statistics component). The monitor, a component within the EDA functional verification platform, can also be instantiated from a corresponding monitor class. After the monitor collects input / output data packets, the corresponding performance statistics component's `stat` function can be called to perform performance statistics. For example, to calculate packet rate, the `tps_stat` function can be called after receiving a packet, passing in 1 as the parameter. To calculate throughput, the `bps_stat` function can be called after receiving a data packet, passing in the number of bits in the data packet as the parameter.

[0161] Optionally, the statistical management platform and monitor can be instantiated in the same location, for example, in the Agent, UVC (Universal Verification Component), or ENV (Environment).

[0162] After instantiating the monitor and the statistics management platform, the `add_child_stat` function of the statistics management platform can be called to add the statistics objects from the monitor to the management platform. After all traffic has been processed, the UVM environment can call the `print_result` function of the statistics management platform in the post_main phase to print the performance statistics results.

[0163] After introducing the performance verification method provided by the embodiments of this invention into the module-level, subsystem-level, and system-level EDA functional verification platform, various performance data such as packet speed, throughput, backpressure rate, FIFO / Buffer occupancy depth, and latency can be analyzed by running corresponding performance test cases. During data analysis, the data tables parsed by the script can be plotted as curves to more conveniently and intuitively observe the fluctuation of indicators over time.

[0164] Besides a functional verification environment, building a performance model using SystemVerilog and TLM (Transaction Level Modeling) and then analyzing various performance metrics of interest using performance statistics tools is also a viable approach. In the performance model, the `stat` function of the statistics class can be called within the TLM receiving function.

[0165] Accordingly, in a second aspect, embodiments of the present invention also provide a chip performance verification apparatus that can effectively improve chip performance verification efficiency.

[0166] like Figure 7 As shown, the chip performance verification apparatus provided in the embodiments of the present invention may include:

[0167] The receiving unit 31 is used to receive model status information from the preset model environment of the chip to be verified through the performance statistics management platform; wherein, the performance statistics management platform and the preset model environment communicate through a preset interface, and the preset model environment includes at least one of the following: a functional verification environment, a hardware simulation environment, and a performance model environment;

[0168] Triggering unit 32 is used to trigger the performance statistics management platform to generate a verification control signal based on the model state information;

[0169] The statistics unit 33 is used to receive the model running data of the chip to be verified from the preset model environment through the preset performance statistics component under the control of the verification control signal, and to perform performance statistics on the model running data to obtain the corresponding performance statistics results. The programming language on which the performance statistics management platform is based is compatible with the programming language on which the preset model environment is based and the programming language on which the performance statistics component is based.

[0170] The chip performance verification apparatus provided in this embodiment of the invention can receive model state information from a preset model environment of the chip to be verified through a performance statistics management platform. This triggers the performance statistics management platform to generate a verification control signal based on the model state information. Under the control of the verification control signal, a preset performance statistics component receives model running data of the chip to be verified from the preset model environment and performs performance statistics on the model running data to obtain corresponding performance statistics results. Since the programming language on which the performance statistics management platform is based is compatible with the programming languages ​​on which the preset model environment and the performance statistics component are based, the performance statistics operation of the chip to be verified can be easily integrated with preset model environments such as the functional verification environment, hardware simulation environment, and performance model environment of the chip to be verified. This allows for convenient acquisition of the chip's performance information and completion of performance verification by utilizing the aforementioned preset model environment or while performing functional verification or other simulation and verification operations, without the need to generate waveforms or perform manual statistical comparisons, thereby effectively improving chip verification efficiency.

[0171] Furthermore, when the preset model environment includes a functional verification environment or a hardware simulation environment, since functional verification and hardware simulation are widely used in the field of chip verification and are very close to the real situation of the chip, the performance statistics obtained therefrom will also have good accuracy, which is much better than the performance analysis using other commercial tools or high-level modeling languages ​​(such as SystemC). Therefore, it can effectively improve the efficiency of chip verification while greatly improving the accuracy of performance verification.

[0172] Optionally, the trigger unit 32 can be used for:

[0173] Based on the start running signal in the model status information, the performance statistics management platform is triggered to generate a start statistics signal;

[0174] or

[0175] Based on the stop operation signal in the model status information, the performance statistics management platform is triggered to generate a stop statistics signal.

[0176] Optionally, the chip performance verification apparatus provided in the embodiments of the present invention may further include:

[0177] The component adding unit is used to add the pointer of the performance statistics component to the preset component pointer index of the performance statistics management platform, or to the preset component pointer index of the lower-level sub-platform of the performance statistics management platform, according to the preset component affiliation relationship, before receiving the model running data of the chip to be verified from the preset model environment under the control of the verification control signal.

[0178] and / or

[0179] The sub-platform adding unit is used, under the control of the verification control signal, to add the pointers of each lower-level sub-platform to the preset sub-platform pointer index of the corresponding upper-level sub-platform, or to the preset sub-platform pointer index of the performance statistics management platform, according to the preset platform affiliation relationship, before receiving the model running data of the chip to be verified from the preset model environment through the preset performance statistics component.

[0180] Optionally, the statistical unit 33 may include:

[0181] The signal sending module is used by the performance statistics management platform to send the verification control signal to each of the performance statistics components, wherein the performance statistics components are directly under the management of the performance statistics management platform or under the management of a lower-level sub-platform of the performance statistics management platform.

[0182] The data receiving module is used by each of the performance statistics components to receive the corresponding model running data according to the verification control signal.

[0183] The data statistics module is used by each of the performance statistics components to perform performance statistics on the model running data according to their respective statistical attributes.

[0184] Optionally, the signal transmission module may be used specifically for:

[0185] If the performance statistics component is directly under the management of the performance statistics management platform, the performance management platform obtains the pointer of the performance statistics component from the component pointer index preset by the performance management platform, and sends the verification control signal to the performance statistics component according to the pointer of the performance statistics component.

[0186] If the performance statistics component is under the management of a lower-level sub-platform of the performance statistics management platform, the performance management platform obtains the pointer of the first sub-platform where the performance statistics component is located from the sub-platform pointer index preset by the performance management platform; obtains the first sub-platform based on the pointer of the first sub-platform, and obtains the pointer of the performance statistics component from the component pointer index preset by the first sub-platform; and sends the verification control signal to the performance statistics component according to the pointer of the performance statistics component.

[0187] Optionally, the data receiving module may include:

[0188] The first determining submodule is used by each of the performance statistics components to determine the start or end of their respective statistical tasks based on the verification control signal;

[0189] The receiving submodule is configured to, in response to the start of the statistical task, each of the performance statistics components receives its respective model running data.

[0190] The stop submodule is used to respond to the end of the statistical task by having each of the performance statistics components stop receiving the corresponding model running data.

[0191] Optionally, the data statistics module may include:

[0192] The second determining submodule is used by each of the performance statistics components to determine each statistical window in the life cycle of the statistical task and the statistical category of the statistical task according to their respective statistical attributes. The statistical windows are connected end to end in chronological order to form the life cycle of the statistical task.

[0193] The recording submodule is used by each of the performance statistics components to record the stage statistics and overall statistics of the model running data according to the verification control signal, the statistics window and the statistics category, respectively. The statistical time of the stage statistics is one statistics window, and the statistical time of the overall statistics is from the start of the statistical task to the current time.

[0194] The third determining submodule is used by each of the performance statistics components to determine the stage performance of each statistical window of the chip to be verified based on the stage statistics, and to determine the overall performance of the chip to be verified based on the overall statistics.

[0195] Optionally, the statistical categories include: packet rate statistics; the stage statistics include: the number of data packets in a stage; the overall statistics include: the total number of data packets; the third statistical submodule can be specifically used to: determine the stage average packet rate based on the number of data packets in a stage and the statistical time of the stage statistics, and determine the overall average packet rate based on the total number of data packets and the statistical time of the overall statistics.

[0196] Optionally, the statistical categories may include: throughput statistics; the stage statistics include: stage throughput; the overall statistics include: overall throughput; the third statistical submodule may be specifically used to: determine the stage average throughput based on the stage throughput and the statistical time of the stage statistics, and determine the overall average throughput based on the overall throughput and the statistical time of the overall statistics.

[0197] Optionally, the statistical categories include: numerical statistics; the stage statistics include: stage cumulative values; the overall statistics include: overall cumulative values; the third statistical submodule can be specifically used to: determine the stage average value based on the stage cumulative values ​​and the statistical time of the stage statistics, and determine the overall average value based on the overall cumulative values ​​and the statistical time of the overall statistics.

[0198] Optionally, the stage statistics may further include: stage maximum value and stage minimum value, and the overall statistics may further include: overall maximum value and overall minimum value.

[0199] Optionally, the chip performance verification apparatus provided in the embodiments of the present invention may further include:

[0200] The writing unit is used to write the corresponding performance statistics results into a log file after obtaining them.

[0201] A parsing unit is used to parse the log file and write the parsing results to a preset file, the preset file including: a comma-separated file and / or a data table file;

[0202] The generation unit is used to generate performance charts and / or curves of the chip to be verified using the parsing results in the preset file.

[0203] Thirdly, such as Figure 8 As shown, embodiments of the present invention also provide an electronic device, including: a housing 100, at least one processor 110, a memory 120, a circuit board 130, and a power supply circuit 140, wherein the circuit board 130 is disposed within the space enclosed by the housing 100, and the processor 110 and the memory 120 are disposed on the circuit board 130; the power supply circuit 140 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 120 is used to store executable program code; the processor 110 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 120, for executing any of the chip performance verification methods provided in the foregoing embodiments. The specific execution process of the processor 110 of the above steps and the steps further executed by the processor 110 by running the executable program code can be found in the description of the foregoing embodiments, and will not be repeated here.

[0204] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement any of the chip performance verification methods provided in the foregoing embodiments. The specific execution process of the processor on the above steps, and the steps further executed by the processor by running executable program code, can be found in the description of the foregoing embodiments, and will not be repeated here.

[0205] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0206] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0207] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0208] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this invention, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0209] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0210] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A chip performance verification method, characterized in that, include: The performance statistics management platform receives model status information from the preset model environment of the chip to be verified; wherein, the performance statistics management platform and the preset model environment communicate through a preset interface, and the preset model environment includes at least one of the following: functional verification environment, hardware simulation environment, and performance model environment; The performance statistics management platform is triggered to generate a verification control signal based on the model status information; Under the control of the verification control signal, the model running data of the chip to be verified is received from the preset model environment through the preset performance statistics component, and the performance statistics of the model running data are performed to obtain the corresponding performance statistics results. The programming language on which the performance statistics management platform is based is compatible with the programming language on which the preset model environment is based and the programming language on which the performance statistics component is based. Before receiving the model running data of the chip to be verified from the preset model environment through a preset performance statistics component under the control of the verification control signal, the method further includes: According to the preset component affiliation, the pointer of the performance statistics component is added to the preset component pointer index of the performance statistics management platform, or added to the preset component pointer index of the lower-level sub-platform of the performance statistics management platform; and / or According to the preset platform affiliation, the pointers of each lower-level sub-platform are added to the preset sub-platform pointer index of the corresponding upper-level sub-platform, or to the preset sub-platform pointer index of the performance statistics management platform; wherein, each relatively independent circuit module in the chip to be verified corresponds to one lower-level sub-platform, which is used to control the performance statistics operation of the circuit module; the performance statistics management platform includes one or more levels of the lower-level sub-platforms; The component pointer indexes and the sub-platform pointer indexes are used to send the verification control signal to the corresponding performance statistics component.

2. The method according to claim 1, characterized in that, The step of triggering the performance statistics management platform to generate a verification control signal based on the model state information includes: Based on the start running signal in the model status information, the performance statistics management platform is triggered to generate a start statistics signal; or Based on the stop operation signal in the model status information, the performance statistics management platform is triggered to generate a stop statistics signal.

3. The method according to any one of claims 1 to 2, characterized in that, Under the control of the verification control signal, the process of receiving model running data of the chip to be verified from the preset model environment through a preset performance statistics component, and performing performance statistics on the model running data, includes: The performance statistics management platform sends the verification control signal to each of the performance statistics components, wherein the performance statistics components are directly under the management of the performance statistics management platform or under the management of a lower-level sub-platform of the performance statistics management platform. Each of the performance statistics components receives its corresponding model running data according to the verification control signal; Each of the aforementioned performance statistics components performs performance statistics on the model's running data according to its own statistical attributes.

4. The method according to claim 3, characterized in that, The performance statistics management platform sends the verification control signal to each of the performance statistics components, including: If the performance statistics component is directly under the management of the performance statistics management platform, the performance statistics management platform obtains the pointer of the performance statistics component from the component pointer index preset by the performance statistics management platform, and sends the verification control signal to the performance statistics component according to the pointer of the performance statistics component. If the performance statistics component is under the management of a lower-level sub-platform of the performance statistics management platform, the performance statistics management platform obtains the pointer of the first sub-platform where the performance statistics component is located from the sub-platform pointer index preset by the performance statistics management platform; obtains the first sub-platform based on the pointer of the first sub-platform, and obtains the pointer of the performance statistics component from the component pointer index preset by the first sub-platform; and sends the verification control signal to the performance statistics component based on the pointer of the performance statistics component.

5. The method according to claim 3, characterized in that, Each of the performance statistics components receives its corresponding model running data according to the verification control signal, including: Each of the performance statistics components determines whether its respective statistics task is started or ended based on the verification control signal; In response to the start of the statistical task, each of the performance statistics components receives its corresponding model running data. In response to the completion of the statistical task, each of the performance statistics components stops receiving the corresponding model running data.

6. The method according to claim 5, characterized in that, Each of the aforementioned performance statistics components performs performance statistics on the model runtime data according to its respective statistical attributes, including: Each of the performance statistics components determines, according to its own statistical attributes, each statistical window in the lifecycle of the statistical task and the statistical category of the statistical task, wherein the statistical windows are connected end to end in chronological order to form the lifecycle of the statistical task. Each of the performance statistics components records the stage statistics and overall statistics of the model running data according to the verification control signal, the statistics window, and the statistics category, wherein the statistical time of the stage statistics is one statistics window, and the statistical time of the overall statistics is from the start of the statistical task to the current time. Each of the performance statistics components determines the stage performance of each statistical window of the chip to be verified based on the stage statistics, and determines the overall performance of the chip to be verified based on the overall statistics.

7. The method according to claim 6, characterized in that, The statistical categories include: packet rate statistics; the stage statistics include: the number of data packets in the stage; the overall statistics include: the total number of data packets. The step of determining the stage performance of each statistical window based on the stage statistics and determining the overall performance based on the overall statistics includes: The average packet rate for a stage is determined based on the number of data packets in that stage and the statistical time of the stage statistics. The overall average packet rate is then determined based on the total number of data packets in the overall stage and the statistical time of the overall statistics.

8. The method according to claim 6, characterized in that, The statistical categories include: throughput statistics; the stage statistics include: stage throughput; the overall statistics include: overall throughput. The step of determining the stage performance of each statistical window based on the stage statistics and determining the overall performance based on the overall statistics includes: The stage average throughput is determined based on the stage throughput and the statistical time of the stage statistics, and the overall average throughput is determined based on the overall throughput and the statistical time of the overall statistics.

9. The method according to claim 6, characterized in that, The statistical categories include: numerical statistics; the stage statistics include: stage cumulative values; the overall statistics include: overall cumulative values; The step of determining the stage performance of each statistical window based on the stage statistics and determining the overall performance based on the overall statistics includes: The stage average is determined based on the cumulative value of the stage and the statistical time of the stage statistic, and the overall average is determined based on the cumulative value of the overall statistic and the statistical time of the overall statistic.

10. The method according to claim 9, characterized in that, The stage statistics also include: stage maximum value and stage minimum value; the overall statistics also include: overall maximum value and overall minimum value.

11. The method according to any one of claims 1 to 2, characterized in that, After obtaining the corresponding performance statistics, the method further includes: Write the performance statistics results to a log file; The log file is parsed and the parsing results are written to a preset file, which includes: a comma-separated file and / or a data table file; Using the parsing results from the preset file, performance charts and / or curves of the chip to be verified are generated.

12. A chip performance verification device, characterized in that, include: The receiving unit is used to receive model status information from a preset model environment of the chip to be verified through a performance statistics management platform; wherein, the performance statistics management platform and the preset model environment communicate through a preset interface, and the preset model environment includes at least one of the following: a functional verification environment, a hardware simulation environment, and a performance model environment; The triggering unit is used to trigger the performance statistics management platform to generate a verification control signal based on the model state information; The statistics unit is used to receive the model running data of the chip to be verified from the preset model environment through the preset performance statistics component under the control of the verification control signal, and to perform performance statistics on the model running data to obtain the corresponding performance statistics results. The programming language on which the performance statistics management platform is based is compatible with the programming language on which the preset model environment is based and the programming language on which the performance statistics component is based. The device further includes: The component adding unit is used to add the pointer of the performance statistics component to the preset component pointer index of the performance statistics management platform, or to the preset component pointer index of the lower-level sub-platform of the performance statistics management platform, according to the preset component affiliation relationship, before receiving the model running data of the chip to be verified from the preset model environment under the control of the verification control signal. and / or A sub-platform adding unit, under the control of the verification control signal, before receiving the model running data of the chip to be verified from the preset model environment through a preset performance statistics component, adds the pointers of each lower-level sub-platform to the preset sub-platform pointer index of the corresponding upper-level sub-platform, or to the preset sub-platform pointer index of the performance statistics management platform, according to a preset platform affiliation; wherein, each relatively independent circuit module in the chip to be verified corresponds to one lower-level sub-platform, used to control the performance statistics operation on the circuit module; the performance statistics management platform includes one or more levels of the lower-level sub-platforms; The component pointer indexes and the sub-platform pointer indexes are used to send the verification control signal to the corresponding performance statistics component.

13. The apparatus according to claim 12, characterized in that, The triggering unit is specifically used for: Based on the start running signal in the model status information, the performance statistics management platform is triggered to generate a start statistics signal; or Based on the stop operation signal in the model status information, the performance statistics management platform is triggered to generate a stop statistics signal.

14. The apparatus according to any one of claims 12 to 13, characterized in that, The statistical unit includes: The signal sending module is used by the performance statistics management platform to send the verification control signal to each of the performance statistics components, wherein the performance statistics components are directly under the management of the performance statistics management platform or under the management of a lower-level sub-platform of the performance statistics management platform. The data receiving module is used by each of the performance statistics components to receive the corresponding model running data according to the verification control signal. The data statistics module is used by each of the performance statistics components to perform performance statistics on the model running data according to their respective statistical attributes.

15. The apparatus according to claim 14, characterized in that, The signal transmission module is specifically used for: If the performance statistics component is directly under the management of the performance statistics management platform, the performance statistics management platform obtains the pointer of the performance statistics component from the component pointer index preset by the performance statistics management platform, and sends the verification control signal to the performance statistics component according to the pointer of the performance statistics component. If the performance statistics component is under the management of a lower-level sub-platform of the performance statistics management platform, the performance statistics management platform obtains the pointer of the first sub-platform where the performance statistics component is located from the sub-platform pointer index preset by the performance statistics management platform. The first sub-platform is obtained based on the pointer of the first sub-platform, and the pointer of the performance statistics component is obtained from the preset component pointer index of the first sub-platform. Based on the pointer of the performance statistics component, the verification control signal is sent to the performance statistics component respectively.

16. The apparatus according to claim 14, characterized in that, The data receiving module includes: The first determining submodule is used by each of the performance statistics components to determine the start or end of their respective statistical tasks based on the verification control signal; The receiving submodule is configured to, in response to the start of the statistical task, each of the performance statistics components receives its respective model running data. The stop submodule is used to respond to the end of the statistical task by having each of the performance statistics components stop receiving the corresponding model running data.

17. The apparatus according to claim 16, characterized in that, The data statistics module includes: The second determining submodule is used by each of the performance statistics components to determine each statistical window in the life cycle of the statistical task and the statistical category of the statistical task according to their respective statistical attributes. The statistical windows are connected end to end in chronological order to form the life cycle of the statistical task. The recording submodule is used by each of the performance statistics components to record the stage statistics and overall statistics of the model running data according to the verification control signal, the statistics window and the statistics category, respectively. The statistical time of the stage statistics is one statistics window, and the statistical time of the overall statistics is from the start of the statistical task to the current time. The third determining submodule is used by each of the performance statistics components to determine the stage performance of each statistical window of the chip to be verified based on the stage statistics, and to determine the overall performance of the chip to be verified based on the overall statistics.

18. The apparatus according to claim 17, characterized in that, The statistical categories include: packet rate statistics; the stage statistics include: the number of data packets in the stage; the overall statistics include: the total number of data packets. The third determining submodule is specifically used for: The average packet rate for a stage is determined based on the number of data packets in that stage and the statistical time of the stage statistics. The overall average packet rate is then determined based on the total number of data packets in the overall stage and the statistical time of the overall statistics.

19. The apparatus according to claim 17, characterized in that, The statistical categories include: throughput statistics; the stage statistics include: stage throughput; the overall statistics include: overall throughput. The third determining submodule is specifically used for: The stage average throughput is determined based on the stage throughput and the statistical time of the stage statistics, and the overall average throughput is determined based on the overall throughput and the statistical time of the overall statistics.

20. The apparatus according to claim 17, characterized in that, The statistical categories include: numerical statistics; the stage statistics include: stage cumulative values; the overall statistics include: overall cumulative values; The third determining submodule is specifically used for: The stage average is determined based on the cumulative value of the stage and the statistical time of the stage statistic, and the overall average is determined based on the cumulative value of the overall statistic and the statistical time of the overall statistic.

21. The apparatus according to claim 20, characterized in that, The stage statistics also include: stage maximum value and stage minimum value; the overall statistics also include: overall maximum value and overall minimum value.

22. The apparatus according to any one of claims 12 to 13, characterized in that, Also includes: The writing unit is used to write the corresponding performance statistics results into a log file after obtaining them. A parsing unit is used to parse the log file and write the parsing results to a preset file, the preset file including: a comma-separated file and / or a data table file; The generation unit is used to generate performance charts and / or curves of the chip to be verified using the parsing results in the preset file.

23. An electronic device, characterized in that, include: The device comprises a housing, at least one processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed within the space enclosed by the housing, and the processor and memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the aforementioned electronic device; the memory is used to store executable program code; the at least one processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for performing the method of any one of claims 1-11.

24. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the method of any one of claims 1-11.

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