semiconductor devices

Abstract

According to one embodiment, a semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal whose voltage switches between a first level and a second level, output a first voltage to a first node in response to the voltage of the first signal being at the first level, and output a second voltage to the first node in response to the voltage of the first signal being at the second level. The first voltage is higher than the second voltage. The second circuit is configured to be connected to the first node and latch data generated based on the voltage at the first node. The third circuit includes a first inverter having a first input terminal connected to the first node and a first output terminal connected to the first node.

Description

[0001] Related applications

[0002] This application claims priority from Japanese Patent Application No. 2020-157763 (filing date: September 18, 2020), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments relate to a semiconductor device. Background Art

[0004] As a semiconductor memory device, a NAND (Not AND) type flash memory is known. Summary of the Invention

[0005] Embodiments provide a semiconductor device capable of high-speed operation.

[0006] In general, according to one embodiment, a semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal whose voltage switches between a first level and a second level, output a first voltage to a first node in response to the voltage of the first signal being at the first level, and output a second voltage to the first node in response to the voltage of the first signal being at the second level. The first voltage is higher than the second voltage. The second circuit is configured to be connected to the first node and latch data generated based on the voltage at the first node. The third circuit includes a first inverter having a first input terminal connected to the first node and a first output terminal connected to the first node. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a block diagram showing an example of the configuration of a memory system including the semiconductor memory device according to the first embodiment.

[0008] Figure 2 This is a block diagram showing an example of the configuration of the semiconductor memory device according to the first embodiment.

[0009] Figure 3 This is a block diagram showing an example of the configuration of a memory plane of the semiconductor memory device according to the first embodiment.

[0010] Figure 4 An example of the circuit configuration of the memory cell array of the semiconductor memory device according to the first embodiment is shown.

[0011] Figure 5 This is a cross-sectional view showing an example of a partial cross-sectional structure of the semiconductor memory device according to the first embodiment.

[0012] Figure 6 An example of a threshold voltage distribution formed by the memory cell transistors of the semiconductor memory device according to the first embodiment is shown.

[0013] Figure 7 This is a block diagram showing an example of the configuration of an input / output circuit of the semiconductor memory device according to the first embodiment.

[0014] Figure 8 This is a block diagram showing another example of the configuration of the input / output circuit of the semiconductor memory device according to the first embodiment.

[0015] Figure 9 An example of the configuration of two input circuits and one latch circuit in the input / output circuit of the semiconductor memory device according to the first embodiment is shown.

[0016] Figure 10 An example of the configuration of a local latch circuit in the latch circuit of the semiconductor memory device according to the first embodiment is shown.

[0017] Figure 11 An example of the circuit configuration of a local latch circuit in the semiconductor memory device according to the first embodiment is shown.

[0018] Figure 12 An example of a timing chart showing time changes of a command set and other various signals related to a certain write operation executed by the semiconductor memory device according to the first embodiment is shown.

[0019] Figure 13 An example of a timing chart showing time changes of various signals when the local latch circuit of the semiconductor memory device according to the first embodiment latches a certain bit of data transmitted by a certain signal is shown.

[0020] Figure 14 Another example of a timing chart showing time changes of various signals when the local latch circuit of the semiconductor memory device according to the first embodiment latches a certain bit of data transmitted by a certain signal is shown.

[0021] Figure 15 An example of a timing chart showing time changes of various signals when a local latch circuit of a semiconductor memory device according to a comparative example of the first embodiment latches a certain bit of data transmitted by a certain signal is shown.

[0022] Figure 16 An example of the configuration of a local latch circuit in a semiconductor memory device according to the second embodiment is shown.

[0023] Figure 17 An example of the circuit configuration of a local latch circuit in a semiconductor memory device according to the second embodiment is shown.

[0024] Figure 18 An example of a timing chart showing time changes of various signals when a local latch circuit of the semiconductor memory device according to the second embodiment latches a certain bit of data transmitted by a certain signal is shown.

[0025] Figure 19 Another example of the circuit configuration of the voltage adjustment circuit of the local latch circuit of the semiconductor memory device according to the second embodiment is shown.

[0026] Figure 20 An example of the configuration of a local latch circuit in a semiconductor memory device according to the third embodiment is shown.

[0027] Figure 21 An example of the circuit configuration of a local latch circuit in a semiconductor memory device according to the third embodiment is shown.

[0028] Figure 22 This is a block diagram showing an example of the configuration of an input / output circuit of a semiconductor memory device according to a fourth embodiment.

[0029] Figure 23 An example of the circuit configuration of a signal shaping circuit in the input / output circuit of the semiconductor memory device according to the fourth embodiment is shown.

[0030] Figure 24 An example of the configuration of a local latch circuit in a semiconductor memory device according to a fourth embodiment is shown.

[0031] Figure 25 An example of the circuit configuration of a local latch circuit in a semiconductor memory device according to a fourth embodiment is shown.

[0032] Figure 26 An example of a timing chart showing time changes of various signals when a local latch circuit of the semiconductor memory device according to the fourth embodiment latches a certain bit of data transmitted by a certain signal is shown.

[0033] Figure 27 An example of the circuit configuration of a signal shaping circuit in a semiconductor memory device according to the fifth embodiment is shown.

[0034] Figure 28 An example of a timing chart showing time changes of various signals when a local latch circuit of the semiconductor memory device according to the fifth embodiment latches a certain bit of data transmitted by a certain signal is shown.

[0035] Figure 29 An example of the configuration of a local latch circuit of a semiconductor memory device according to the sixth embodiment is shown.

[0036] Figure 30 An example of the circuit configuration of a local latch circuit in a semiconductor memory device according to the sixth embodiment is shown.

[0037] Figure 31 An example of the circuit configuration of a signal shaping circuit in a semiconductor memory device according to the sixth embodiment is shown.

[0038] Figure 32 An example of a timing chart showing time changes of various signals when a local latch circuit of the semiconductor memory device according to the sixth embodiment latches a certain bit of data transmitted by a certain signal is shown.

[0039] Figure 33 An example of the circuit configuration of a signal shaping circuit in a semiconductor memory device according to the seventh embodiment is shown.

[0040] Figure 34 An example of a timing chart showing time changes of various signals when a local latch circuit of the semiconductor memory device according to the seventh embodiment latches a certain bit of data transmitted by a certain signal is shown.

[0041] Figure 35 An example of the configuration of a local latch circuit of a semiconductor memory device according to the eighth embodiment is shown.

[0042] Figure 36 An example of the configuration of a local latch circuit in a semiconductor memory device according to a ninth embodiment is shown.

[0043] Figure 37 An example of the circuit configuration of a local latch circuit in a semiconductor memory device according to the ninth embodiment is shown.

[0044] Figure 38 An example of the configuration of a local latch circuit in a semiconductor memory device according to a tenth embodiment is shown.

[0045] Figure 39 An example of the circuit configuration of a local latch circuit in a semiconductor memory device according to a tenth embodiment is shown.

[0046] Figure 40 Another example of the circuit configuration of the local latch circuit of the semiconductor memory device according to the tenth embodiment is shown.

[0047] Figure 41 An example of a timing chart showing time changes of various signals when a local latch circuit of the semiconductor memory device according to the tenth embodiment latches a certain bit of data transmitted by a certain signal is shown. DETAILED DESCRIPTION

[0048] The following describes the embodiments with reference to the accompanying drawings. In the following description, components having the same function and configuration are denoted by common reference numerals. To distinguish multiple components having a common reference numeral, a subscript is assigned to the common reference numeral to distinguish them. When there is no need to specifically distinguish multiple components, the components are denoted by the common reference numeral without a subscript.

[0049] Each functional block can be implemented using either hardware or software, or a combination of both. Furthermore, it is not necessary to distinguish between functional blocks as described below. For example, some functions may be performed by functional blocks different from the illustrated functional blocks. Furthermore, the illustrated functional blocks may be divided into even more detailed functional sub-blocks. The names of the functional blocks and components in the following description are used for convenience only and do not limit the configuration or operation of the functional blocks and components.

[0050] <First embodiment>

[0051] Hereinafter, a semiconductor memory device 1 according to the first embodiment will be described.

[0052] [Example of configuration]

[0053] (1) Memory system

[0054] Figure 1 This is a block diagram showing an example of the configuration of a memory system 3 including the semiconductor memory device 1 according to the first embodiment.

[0055] The memory system 3 includes a semiconductor memory device 1 and a memory controller 2, and is controlled by a host device 4. The memory system 3 is, for example, an SSD (Solid State Drive) or an SD (Secure Digital) TM Cards, etc.

[0056] The semiconductor memory device 1 is controlled by a memory controller 2. The memory controller 2 receives a host command from a host device 4 and controls the semiconductor memory device 1 based on the host command.

[0057] The memory controller 2 includes a host interface circuit 21, a CPU (Central Processing Unit) 22, a RAM (Random Access Memory) 23, a ROM (Read Only Memory) 24, and a memory interface circuit 25. The memory controller 2 is configured as, for example, a SoC (System-on-a-Chip).

[0058] ROM 24 stores firmware (programs). RAM 23 can store this firmware and is used as a work area for CPU 22. Furthermore, RAM 23 temporarily stores data and functions as a buffer and cache memory. The firmware stored in ROM 24 and loaded into RAM 23 is executed by CPU 22. Thus, memory controller 2 performs various operations, including write and read operations, as well as some of the functions of host interface circuit 21 and memory interface circuit 25.

[0059] The host interface circuit 21 is connected to the host device 4 via a host interface and manages communication between the memory controller 2 and the host device 4. For example, the host interface circuit 21 receives host commands transmitted from the host device 4 to the memory controller 2. The memory interface circuit 25 is connected to the semiconductor memory device 1 via a memory interface and manages communication between the memory controller 2 and the semiconductor memory device 1. The memory interface transmits, for example, the chip enable signal bCE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal bWE, the read enable signal bRE, the write protect signal bWP, the ready / busy signals bR / B, the input / output timing control signals DQS and bDQS, and the signals DQ<0> to DQ<7>. Hereinafter, the signals DQ<0> to DQ<7> will be referred to as signals DQ<7:0>. This applies to the same notation below. Based on the host command from the host device 4, the memory interface circuit 25 generates a command set including command and address information and transmits this command set to the semiconductor memory device 1 via the signals DQ<7:0>.

[0060] (2) Semiconductor storage device

[0061] Figure 2 This is a block diagram showing an example of the configuration of the semiconductor memory device 1 according to the first embodiment. The semiconductor memory device 1 according to the first embodiment is, for example, a NAND flash memory capable of storing data in a nonvolatile manner.

[0062] The semiconductor memory device 1 includes a core unit 11 , an input / output circuit 12 , a logic control circuit 13 , a register 14 , a sequencer 15 , a voltage generating circuit 16 , and a driver unit 17 .

[0063] The core unit 11 includes a plurality of memory planes PB ( Figure 2 1 and 2. Memory planes PB0 and PB1 are illustrated in FIG. 1 . Each memory plane PB includes a memory cell array. The semiconductor memory device 1 performs various operations, such as a write operation to store write data DAT in the memory cell array of a certain memory plane and a read operation to read read data DAT from the memory cell array of a certain memory plane.

[0064] The input / output circuit 12 controls the input and output of signals DQ<7:0>, DQS, and bDQS with the memory controller 2. Signal DQ<7:0> includes a command CMD, data DAT, and address information ADD. Command CMD, for example, includes a command for causing the semiconductor memory device 1 to execute processing corresponding to a host command from the host device 4. Data DAT includes write data or read data (hereinafter, both write data and read data are described using the reference symbol DAT). Address information ADD includes, for example, a column address and a block address. A block address includes, for example, a memory plane address. Hereinafter, the block address will be described as including a memory plane address. Signals DQS and bDQS are signals used to implement input and output of signal DQ<7:0> using the input / output circuit 12. The voltages of signals DQS and bDQS periodically switch (toggle) between a high (H) level and a low (L) level, for example, while data DAT is being transmitted using signal DQ<7:0>. While the voltage of the signal DQS is at an H level, the voltage of the signal bDQS is at an L level. While the voltage of the signal DQS is at an L level, the voltage of the signal bDQS is at an H level. When two signals exist in this relationship, each of the two signals is also referred to as the complementary signal of the other. Hereinafter, when the term "level" is used, the voltage level will be referred to as described unless otherwise specified.

[0065] The input and output of the signal DQ<7:0> using the input / output circuit 12 will be described in more detail. The input / output circuit 12 receives write data DAT, a command CMD, and address information ADD from the memory controller 2, transfers the received write data DAT to the core unit 11, and transfers the received address information ADD and command CMD to the register 14. The input / output circuit 12 receives read data DAT from the core unit 11 and transmits the read data DAT to the memory controller 2.

[0066] The logic control circuit 13 receives, for example, a chip enable signal bCE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal bWE, a read enable signal bRE, and a write protect signal bWP from the memory controller 2. The logic control circuit 13 controls the input / output circuit 12 and the sequencer 15 based on the received signals.

[0067] Chip enable signal bCE is a signal for activating semiconductor memory device 1. Command latch enable signal CLE is a signal for notifying input / output circuit 12 of the transmission of command CMD using signal DQ<7:0> input to semiconductor memory device 1. Address latch enable signal ALE is a signal for notifying input / output circuit 12 of the transmission of address information ADD using signal DQ<7:0> input to semiconductor memory device 1. Write enable signal bWE is a signal for enabling input of signal DQ<7:0> using input / output circuit 12. Write enable signal bWE switches, for example, during the transmission of command CMD or address information ADD using signal DQ<7:0>. Read enable signal bRE is a signal for enabling output of signal DQ<7:0> using input / output circuit 12. Write protect signal bWP is a signal for prohibiting writing and erasing of data in semiconductor memory device 1.

[0068] The logic control circuit 13 generates a ready / busy signal bR / B under the control of the sequencer 15 and transmits the generated ready / busy signal bR / B to the memory controller 2. The ready / busy signal bR / B is a signal used to notify the memory controller 2 whether the semiconductor memory device 1 is in the ready state or the busy state. In the ready state, the semiconductor memory device 1 accepts commands from the memory controller 2. In the busy state, the semiconductor memory device 1 does not accept commands from the memory controller 2, except in exceptional circumstances.

[0069] The register 14 stores the command CMD and address information ADD transmitted from the input / output circuit 12. The register 14 transmits the command CMD and address information ADD to the sequencer 15, for example.

[0070] The sequencer 15 controls the overall operation of the semiconductor memory device 1 based on the command CMD stored in the register 14. For example, the sequencer 15 generates a control signal CNT based on the address information ADD stored in the register 14 and outputs the generated control signal CNT to the core unit 11. The control signal CNT includes, for example, a block address. The control signal CNT can be used to control a target memory plane PB among the multiple memory planes PB included in the core unit 11. The sequencer 15 controls the voltage generation circuit 16, the driver component 17, and the target memory plane PB to execute various operations, such as writing, reading, and erasing data on the target memory plane PB.

[0071] The voltage generating circuit 16 generates various voltages used in a write operation, a read operation, an erase operation, etc. based on the control of the sequencer 15 , and supplies the generated voltages to the driver unit 17 .

[0072] The driver unit 17 transmits various voltages used in, for example, a write operation and a read operation, from the voltage supplied from the voltage generating circuit 16 to the core unit 11 .

[0073] (3) Memory surface

[0074] Figure 3 This is a block diagram showing an example of the configuration of memory planes PB0 and PB1 of the semiconductor memory device 1 according to the first embodiment.

[0075] The memory plane PB0 includes a memory cell array MCA0, a row decoder module RD0, a data register DR0, and a sense amplifier module SA0.

[0076] The memory plane PB1 includes a memory cell array MCA1 , a row decoder module RD1 , a data register DR1 , and a sense amplifier module SA1 .

[0077] The memory plane PB0 is specified as a target memory plane by the control signal CNT, and the configuration of the memory plane PB0 will be described.

[0078] The memory cell array MCA0 includes blocks BLK0 to BLK(n-1) (n is an integer greater than or equal to 1). Block BLK includes a plurality of non-volatile memory cells associated with bit lines and word lines, and serves as a unit for erasing data, for example. In the semiconductor memory device 1, for example, an SLC (Single-Level Cell) method, an MLC (Multi-Level Cell) method, a TLC (Three-Level Cell) method, or a QLC (Quad-Level Cell) method can be applied. In the SLC method, each memory cell stores 1 bit of data, in the MLC method, each memory cell stores 2 bits of data, in the TLC method, each memory cell stores 3 bits of data, and in the QLC method, each memory cell stores 4 bits of data. In addition, each memory cell can also store more than 5 bits of data.

[0079] The row decoder module RD0 receives the block address in the address information ADD stored in the register 14 and selects a target block BLK for various operations such as read and write based on the block address. The row decoder module RD0 can transmit various voltages supplied from the driver unit 17 to the selected block BLK.

[0080] Data register DR0 is connected to input / output circuit 12 via a data bus. This data bus consists of, for example, eight data lines corresponding to signals DQ<7:0>. Data register DR0 includes multiple latch circuits. Data register DR0 receives write data DAT from input / output circuit 12, temporarily stores this write data DAT in the multiple latch circuits, and then transmits the stored write data DAT to sense amplifier module SA0. Data register DR0 receives read data DAT from sense amplifier module SA1 and temporarily stores this read data DAT in the multiple latch circuits. Data register DR0 receives, for example, a column address from address information ADD stored in register 14 and, based on this column address, transmits the stored read data DAT to input / output circuit 12.

[0081] Sense amplifier module SA0 receives write data DAT from data register DR0 and transmits this write data DAT to memory cell array MCA0. Sense amplifier module SA0 also senses the threshold voltages of multiple memory cell transistors within memory cell array MCA0 and generates read data DAT, which it transmits to data register DR0.

[0082] The same descriptions as above regarding memory plane PB0 apply to memory plane PB1. For example, in the description above, memory plane PB0 can be replaced with memory plane PB1, memory cell array MCA0 can be replaced with memory cell array MCA1, row decoder module RD0 can be replaced with row decoder module RD1, data register DR0 can be replaced with data register DR1, and sense amplifier module SA0 can be replaced with sense amplifier module SA1. In this way, each memory plane PB included in core unit 11 can have the same configuration as described for memory plane PB0.

[0083] (4) Memory cell array

[0084] The following describes the details of the configuration of the memory cell array MCA0 of the memory plane PB0. The memory cell array MCA of each memory plane PB included in the core unit 11 can have the same configuration as described below.

[0085] Figure 4 An example of the circuit configuration of the memory cell array MCA0 of the semiconductor memory device 1 according to the first embodiment is shown. As an example of the circuit configuration of the memory cell array MCA0, an example of the circuit configuration of a certain block BLK included in the memory cell array MCA0 is shown. Each block BLK included in the memory cell array MCA0 may have the same Figure 4 The circuit configuration shown is the same circuit configuration.

[0086] The block BLK includes, for example, four string components SU0 to SU3. Each string component SU includes a plurality of NAND strings NS. These multiple NAND strings NS are respectively associated with m bit lines BL0 to BL(m-1) (m is an integer greater than or equal to 1). Each NAND string NS is connected to the corresponding bit line BL and, for example, includes memory cell transistors MT0 to MT7 and selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate (hereinafter also referred to as a gate) and a charge storage layer to store data non-volatilely. The selection transistors ST1 and ST2 are each used to select the NAND string NS including the selection transistors ST1 and ST2 during various operations.

[0087] The drain of the select transistor ST1 is connected to the bit line BL corresponding to the NAND string NS including the select transistor ST1. Memory cell transistors MT0 to MT7 are connected in series between the source of the select transistor ST1 and the drain of the select transistor ST2 of the NAND string NS. The source of the select transistor ST2 is connected to the source line SL.

[0088] The following instructions are Figure 4 In the example, this applies to each case where p is an integer from 0 to 3, and also to each case where q is an integer from 0 to 7. The gates of the select transistors ST1 of each NAND string NS included in the string unit SUP are commonly connected to the select gate line SGDp. The gates of the select transistors ST2 of each NAND string NS included in the string unit SUP are commonly connected to the select gate line SGSp. The gates of the memory cell transistors MTq of each NAND string NS included in the same block BLK are commonly connected to the word line WLq.

[0089] Each bit line BL is connected to the drain of a select transistor ST1 of each string unit SU in the same block BLK, which establishes a corresponding NAND string NS. The source line SL is shared by multiple string units SU.

[0090] In a string unit SU, a collection of memory cell transistors MT commonly connected to a single word line WL is referred to as a unit unit CU, for example. For example, a collection of identical 1-bit data stored in each of the memory cell transistors MT within a unit unit CU is referred to as "a page of data." A unit unit CU can store multiple such "pages of data."

[0091] The circuit configuration of the memory cell array MCA0 has been described above, but the circuit configuration of the memory cell array MCA0 is not limited to the configuration described above. For example, the number of string components SU included in each block BLK can be designed to be any number. Furthermore, the number of memory cell transistors MT and select transistors ST1 and ST2 included in each NAND string NS can be designed to be any number. The number of word lines WL and select gate lines SGD and SGS varies based on the number of memory cell transistors MT and select transistors ST1 and ST2 in the NAND string NS, respectively.

[0092] Figure 5 This is a cross-sectional view showing an example of a partial cross-sectional structure of the semiconductor memory device 1 according to the first embodiment. Figure 5 The interlayer insulator is omitted in the example. Figure 5 The illustrated cross-sectional structure is merely an example, and the cross-sectional structure of the semiconductor memory device 1 is not limited to the illustrated cross-sectional structure.

[0093] Below, refer to Figure 5 The structure of a block BLK of the memory cell array MCA0 is described below. The blocks BLK included in the memory cell array MCA0 can be connected to the memory cell array MCA0. Figure 5 The same construction as shown is achieved.

[0094] Semiconductor memory device 1 includes a semiconductor substrate 31. Two directions parallel to and intersecting the surface of semiconductor substrate 31 are defined as the X direction and the Y direction. The direction intersecting this surface and toward the side where memory cell array MCA0 is formed is defined as the Z direction. While the X direction is described as being orthogonal to the Y direction, and the Z direction is described as being orthogonal to both the X and Y directions, the relationship between these three directions is not necessarily limited to this. The following description will refer to the Z direction as "up" and the direction opposite to the Z direction as "down," but this description is for convenience only and has no bearing on, for example, the direction of gravity.

[0095] The semiconductor substrate 31 is provided with a P-type well region W. The P-type well region W reaches the upper surface of the semiconductor substrate 31. The P-type well region W is a region in the semiconductor substrate 31 doped with, for example, boron (B).

[0096] Above the P-type well region W, for example, along the Y direction, are located the region where the memory cell transistors MT0-MT7 and select transistors ST1 and ST2 of string unit SU0 are located, the same region of string unit SU1, the same region of string unit SU2, and the same region of string unit SU3. More details are as follows.

[0097] A conductor 41 is provided above the P-type well region W, separated by an insulator. This conductor 41 functions as a select gate line SGS. Each string unit SU is provided with a corresponding conductor 41. These conductors 41 are spaced apart from each other, for example, along the Y direction. These conductors 41 are created, for example, by dividing a conductor extending in the X and Y directions. Each conductor 41 extends, for example, in the X direction.

[0098] Eight layers of conductors 42 are stacked sequentially above these conductors 41, with insulators interposed between adjacent conductors. The conductors 42 function as word lines WL0, WL1, WL2, ..., and WL7, for example, in descending order of distance from the semiconductor substrate 31. Each conductor 42 extends, for example, in the X and Y directions.

[0099] Above the topmost conductor 42, a conductor 43 is provided through an insulator. Conductor 43 functions as a select gate line SGD. Each string unit SU is provided with a corresponding conductor 43. These conductors 43 are spaced apart from each other, for example, along the Y direction. These conductors 43 are created, for example, by dividing a conductor extending in the X and Y directions. Each conductor 43 extends, for example, in the X direction.

[0100] A memory column MP is provided in the conductors 41 and 43, and in the eight layers of conductors 42, which correspond to the string component SU0. The memory column MP corresponds to the region where the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2 are located in one NAND string NS of the string component SU0. The memory column MP extends, for example, in the Z direction. For example, the upper end of the memory column MP is located above the upper surface of the conductor 43, and the lower end of the memory column MP reaches the P-type well region W. Hereinafter, this memory column MP will also be referred to as the memory column corresponding to the string component SU0. The same applies to the same expressions that appear below.

[0101] The memory pillar MP, for example, includes a semiconductor 441 and insulating films 442, 443, and 444. The semiconductor 441 is pillar-shaped, with the upper end of the semiconductor 441 reaching the upper end of the memory pillar MP and the lower end of the semiconductor 441 reaching the P-type well region W. The insulating films 442, 443, and 444 are arranged on the side of the semiconductor 441 in the order of insulating film 442, insulating film 443, and insulating film 444. The semiconductor 441 functions as a channel for the memory cell transistor MT and the selection transistor ST. The insulating film 442 functions as a tunnel oxide film for the memory cell transistor MT and the selection transistor ST. The insulating film 443 functions as a charge storage layer for the memory cell transistor MT. The insulating film 444 functions as a blocking insulating film for the memory cell transistor MT and the selection transistor ST. The portion of the memory pillar MP that intersects with the conductor 41 functions as, for example, the selection transistor ST2. The portions of the memory pillar MP that intersect the conductor 42 function as memory cell transistors MT0, MT1, ..., and MT7, respectively, in descending order from the semiconductor substrate 31. The portion of the memory pillar MP that intersects the conductor 43 functions as a select transistor ST1, for example.

[0102] A columnar contact plug CP1 is provided on the upper surface of the semiconductor 441. The upper surface of the contact plug CP1 contacts a conductor 51 in a layer provided with a bit line. The conductor 51 functions as the bit line BL and extends in the Y direction, for example.

[0103] Similarly, each of the other three string units SU is provided with a memory pillar MP corresponding to the string unit SU. Each of these memory pillars MP is connected to the conductor 51 via a contact plug CP1.

[0104] A plurality of conductors 51 are provided, for example, spaced apart from each other along the X direction. Each conductor 51 extends, for example, in the Y direction. Each conductor 51 is provided with four memory pillars MP, similar to the structure described above. These four memory pillars MP are connected to the conductor 51 and correspond to string assemblies SU0, SU1, SU2, and SU3, respectively.

[0105] The P-type well region W is provided with n + Impurity diffusion region NR and p + Impurity diffusion region PR. n + Impurity diffusion region NR and p + The impurity diffusion regions PR each reach the upper surface of the semiconductor substrate 31. + The impurity diffusion region NR is a region in the semiconductor substrate 31 doped with, for example, phosphorus (P). +The impurity diffusion region PR is a region in the semiconductor substrate 31 that is further doped with, for example, boron (B).

[0106] n + A columnar contact plug CP2 is provided on the impurity diffusion region NR. The upper surface of the contact plug CP2 is in contact with the conductor 52. The conductor 52 functions as a source line. + A columnar contact plug CP3 is provided on the impurity diffusion region PR. The upper surface of the contact plug CP3 is in contact with the conductor 53. The voltage of the P-type well region W can be controlled via the conductor 53.

[0107] also, Figure 4 and Figure 5 4 shows an example in which four select gate lines SGS and conductors 41 are provided for each of the four string units SU included in the block BLK, but the present invention is not limited thereto. For each of the four string units SU included in the block BLK, only one select gate line SGS and conductor 41 may be provided. In other words, the gates of the select transistors ST2 included in each of the four string units SU0-SU3 may be electrically connected in common.

[0108] (5) Threshold voltage distribution of memory cell transistors

[0109] Figure 6 express Figure 4 The illustrated example shows a threshold voltage distribution, data allocation, read voltage, and verification voltage when each memory cell transistor MT in the memory cell array MCA0 stores 2-bit data. Memory cell array MCA applicable to each memory plane PB included in the core unit 11 will be described below.

[0110] The memory cell transistor MT stores the two-bit data based on the minimum voltage difference between the gate and source (hereinafter referred to as the threshold voltage) that can switch the memory cell transistor MT from the off state to the on state. During the write operation, a program operation is performed to increase the threshold voltage of the memory cell transistor MT by injecting electrons into the charge storage layer of the memory cell transistor MT.

[0111] Figure 6 An example of a graph schematically illustrates four threshold voltage distributions resulting from the aforementioned threshold voltage control. This graph plots the number of memory cell transistors MT having a certain threshold voltage value, using that value as a variable. The horizontal axis represents the threshold voltage value of the memory cell transistor MT, and the vertical axis represents the number of memory cell transistors MT.

[0112] The four threshold voltage distributions correspond to, for example, the "Er" state, the "A" state, the "B" state, and the "C" state. Thus, it is possible to distinguish which state the memory cell transistor MT is in, among the "Er" state, the "A" state, the "B" state, and the "C" state, based on the threshold voltage of the memory cell transistor MT. The threshold voltage of the memory cell transistor MT increases in the order in which the memory cell transistor MT is in the "Er" state, the "A" state, the "B" state, and the "C" state. For example, "11" ("high-order bit / low-order bit") data is assigned to the "Er" state, "01" data is assigned to the "A" state, "00" data is assigned to the "B" state, and "10" data is assigned to the "C" state. The data assigned to each state is the data stored in the memory cell transistor MT in that state.

[0113] During a write operation, a verification operation is performed to confirm whether the threshold voltage of the memory cell transistor MT exceeds a specific voltage. The verification voltage used in the verification operation is set. Specifically, a verification voltage AV is set for the "A" state, a verification voltage BV is set for the "B" state, and a verification voltage CV is set for the "C" state.

[0114] The following describes the case where a verification voltage AV is applied between the gate and source of a certain memory cell transistor MT. It can be seen that if the memory cell transistor MT is in the on state, the memory cell transistor is in the "Er" state. On the other hand, it can be seen that if the memory cell transistor MT is in the off state, the memory cell transistor MT is in any of the "A" state, the "B" state, and the "C" state. Thus, for example, after the "01" data is written, it is possible to confirm whether the threshold voltage of the target memory cell transistor MT is included in the threshold voltage distribution of any of the "A" state, the "B" state, and the "C" state. The same is true for the verification voltages BV and CV.

[0115] During a read operation, the state of the memory cell transistor MT is determined. The read voltage used in the read operation is set. Specifically, read voltage AR is set for the "A" state, read voltage BR is set for the "B" state, and read voltage CR is set for the "C" state.

[0116] The following describes the case where a read voltage AR is applied between the gate and source of a memory cell transistor MT. It can be seen that if the memory cell transistor MT is in the on state, the memory cell transistor MT is in the "Er" state. On the other hand, if the memory cell transistor MT is in the off state, the memory cell transistor MT is in any of the "A" state, the "B" state, and the "C" state. This allows determination of whether the memory cell transistor MT is in the "Er" state or in any of the "A" state, the "B" state, and the "C" state. The same applies to the read voltages BR and CR.

[0117] During a read operation, some of the electrons stored in the charge storage layer of the memory cell transistor MT escape from the charge storage layer over time, causing the threshold voltage of the memory cell transistor MT to decrease. To address this decrease in threshold voltage, each read voltage is set lower than a verification voltage, which corresponds to the same state as the read voltage. Specifically, read voltage AR is lower than verification voltage AV, read voltage BR is lower than verification voltage BV, and read voltage CR is lower than verification voltage CV.

[0118] Furthermore, the read pass voltage VREAD is set to be always greater than the highest threshold voltage of the memory cell transistor MT in the “C” state. The memory cell transistor MT to which the read pass voltage VREAD is applied between the gate and the source is turned on regardless of the stored data.

[0119] Note that the number of bits of data stored in one memory cell transistor MT and the data allocation to the threshold voltage distribution described above are merely examples and are not limiting.

[0120] (6) Input and output circuits

[0121] The following describes the details of the configuration of the input / output circuit 12. The following describes an example in which data DAT is transmitted using the signal DQ<7:0>. The following description applies to cases in which r is an integer from 0 to 7.

[0122] While data DAT is being transmitted using the signal DQ<7:0>, the signal DQ<r> selects either the H level or the L level for a certain period of time, which is, for example, a unit time for transmitting 1 bit of data.

[0123] Figure 7 This is a block diagram showing an example of the configuration of the input / output circuit 12 of the semiconductor memory device 1 according to the first embodiment.

[0124] The input / output circuit 12 includes an input circuit 121 <7:0>, an input circuit 122 , and a latch circuit 123 <7:0>.

[0125] Input circuit 121<r> receives signal DQ<r>, generates signal Din<r> based on signal DQ<r>, and outputs signal Din<r> to latch circuit 123<r>. Signal Din<r> is, for example, a signal obtained by amplifying the voltage of signal DQ<r>. A portion of data DAT transmitted via signal DQ<r> is also transmitted via signal Din<r>.

[0126] Input circuit 122 receives signals DQS and bDQS, generates signals Sig1 and Sig2 based on these signals, and outputs these signals to latch circuits 123<7:0>. Signal Sig1 is, for example, a signal obtained by amplifying the voltage of signal DQS. Signal Sig2 is the complement of signal Sig1.

[0127] Latch circuit 123<r> receives signal Din<r> from input circuit 121<r> and signals Sig1 and Sig2 from input circuit 122. Latch circuit 123<r> latches a portion of data DAT transmitted via signal DQ<r> in the order of 0th bit data, 1st bit data, 2nd bit data, etc., based on signals Din<r>, Sig1, and Sig2, for example.

[0128] Figure 8 This is a block diagram showing another example of the configuration of the input / output circuit 12 of the semiconductor memory device 1 according to the first embodiment.

[0129] The input / output circuit 12 further includes a shift register circuit 124 <7:0> and a multiplexer MUX.

[0130] Latch circuit 123<r> outputs each bit of latched data to shift register circuit 124<r>. Specifically, latch circuit 123<r> outputs signal De<r> and signal Do<r> to shift register circuit 124<r>. Using signal De<r>, the 0th bit data, 2nd bit data, 4th bit data, ..., (hereinafter referred to as the even-numbered bits of signal DQ<r>) of signal DQ<r> latched by latch circuit 123<r> are transmitted in the order of appearance. Using signal Do<r>, the 1st bit data, 3rd bit data, 5th bit data, ..., (hereinafter referred to as the odd-numbered bits of signal DQ<r>) of signal DQ<r> latched by latch circuit 123<r> are transmitted in the order of appearance.

[0131] Shift register circuit 124 <0> includes shift registers SR0 and SR1. The same applies to the other shift register circuits 124. Hereinafter, shift register circuit 124 <0> will be described as an example, but the other shift register circuits 124 <7:1> also have the same configuration as that described for shift register circuit 124 <0>.

[0132] Shift register SR0 includes multiple flip-flop circuits F / F. Each flip-flop circuit F / F is, for example, a D-type flip-flop circuit. These multiple flip-flop circuits F / F are connected in series, with the output terminal of one flip-flop circuit F / F repeatedly connected to the input terminal of another. The number of flip-flop circuits F / F constituting shift register SR0 is appropriately designed based on timing control, and is, for example, eight. An internal clock signal iCLK, for example, supplied from sequencer 15, is input to a clock terminal of each flip-flop circuit F / F. The periods of the internal clock signal iCLK supplied to each of the multiple flip-flop circuits F / F do not necessarily have to be identical.

[0133] Shift register SR0 receives signal De<0>. As a result, the even-numbered bits of signal DQ<0> are sequentially input to the input terminals of the primary flip-flop circuits of shift register SR0. Each flip-flop circuit F / F latches the data input to its input terminal at, for example, the timing when the internal clock signal iCLK rises from an L level to an H level, and outputs the latched data at its output terminal. The output data is input to the input terminal of the next-stage flip-flop circuit F / F. In this manner, shift register SR0 transfers the even-numbered bits of signal DQ<0> and outputs them in the order of bit 0, bit 2, bit 4, and so on, at the output terminals of the final-stage flip-flop circuit F / F of shift register SR0.

[0134] Shift register SR1 has the same structure as shift register SR0. Shift register SR1 receives signal Do<0> and similarly transmits the odd-numbered bits of signal DQ<0>. The data is output from the output terminals of the final-stage flip-flop circuit F / F of shift register SR1 in the order of the first bit, the third bit, the fifth bit, and so on.

[0135] The multiplexer MUX, for example, has a first input terminal, a second input terminal, ..., and a sixteenth input terminal. The first input terminal of the multiplexer MUX is connected to the output terminal of the final-stage flip-flop circuit F / F of the shift register SR0 of the shift register circuit 124 <0>. The even-numbered bit data of the signal DQ <0> is input to the first input terminal in the order of the 0th bit data, the 2nd bit data, the 4th bit data, .... The second input terminal of the multiplexer MUX is connected to the output terminal of the final-stage flip-flop circuit F / F of the shift register SR1 of the shift register circuit 124 <0>. The odd-numbered bit data of the signal DQ <0> is input to the second input terminal in the order of the 1st bit data, the 3rd bit data, the 5th bit data, .... The relationship between the multiplexer MUX and the other shift register circuits <7:1> is similar. That is to say, the (2r+1)th input terminal and the (2r+2)th input terminal of the multiplexer MUX are connected to the shift register circuit 124<r>, and the even-bit data of the signal DQ<r> is input to the (2r+1)th input terminal in the order of 0th-bit data, 2nd-bit data, 4th-bit data, ..., and the odd-bit data of the signal DQ<r> is input to the (2r+2)th input terminal in the order of 1st-bit data, 3rd-bit data, 5th-bit data, ...

[0136] The multiplexer MUX has, for example, eight output terminals per memory plane PB. The eight output terminals of the multiplexer MUX are connected to the data register DR0 via eight data lines, and the other eight output terminals of the multiplexer MUX are connected to the data register DR1 via another eight data lines.

[0137] The multiplexer MUX is supplied with a control signal SEL, for example, from the sequencer 15. The control signal SEL is a signal related to the selection of the memory plane PB, and can be, for example, a signal based on a block address. Based on the control signal SEL, the multiplexer MUX transmits the data DAT received at the 16 input terminals to the data register DR of the target memory plane PB. More specifically, the multiplexer MUX transmits the 0th bit data of each of the signals DQ<7:0> to the data register DR via 8 data lines, then transmits the 1st bit data of each of the signals DQ<7:0>, then transmits the 2nd bit data of each of the signals DQ<7:0>, and so on. The data register DR receives the data DAT and transmits the data DAT to the sense amplifier module SA of the target memory plane PB.

[0138] (7) Latch circuit

[0139] The following describes the configuration of latch circuit 123 <0> in more detail. Furthermore, the configurations of input circuits 121 <0> and 122 are also described in more detail. While latch circuit 123 <0> is used as an example for the description, the configuration described below can be applied to each latch circuit in latch circuits 123 <7:0>. Furthermore, each of the other input circuits 121 <7:1> can have the same configuration as input circuit 121 <0> described below. This applies similarly to the other embodiments.

[0140] Figure 9 An example of a more detailed configuration of the input circuit 121 < 0 >, the input circuit 122 , and the latch circuit 123 < 0 > of the semiconductor memory device 1 according to the first embodiment is shown.

[0141] The input circuit 121 <0> includes a comparator CMP1 and an inverter group INVG1. The signal DQ<0> is processed as follows within the input circuit 121 <0>.

[0142] For example, a signal DQ<0> is input to the non-inverting input terminal of comparator CMP1, and a voltage VREF is applied to the inverting input terminal of comparator CMP1. Voltage VREF is, for example, a substantially fixed reference voltage, and may be the average of the high and low voltages of signal DQ<0>. Comparator CMP1 amplifies the voltage of signal DQ<0> using voltage VREF as a reference and outputs a signal representing the amplification result.

[0143] The inverter group INVG1 is composed of a plurality of inverters. These plurality of inverters are connected in series so that the output terminal of one inverter is repeatedly connected to the input terminal of another inverter. The same applies to the other inverter groups INVG below. Figure 9 shows an example where the inverter group INVG1 is composed of three inverters. The inverter group INVG1 receives the signal output from the comparator CMP1 and outputs a signal obtained by propagating the signal through the multiple inverters in the inverter group INVG1. This signal is output from the input circuit 121 <0> as the signal Din<0>.

[0144] The input circuit 122 includes a comparator CMP2, an inverter group INVG2, and an inverter group INVG3. The signals DQS and bDQS are processed within the input circuit 122 as follows.

[0145] Comparator CMP2 has a first output terminal and a second output terminal. For example, signal DQS is input to the non-inverting input terminal of comparator CMP2, and signal bDQS is input to the inverting input terminal of comparator CMP2. Comparator CMP2 amplifies the voltage of signal DQS with reference to the voltage of signal bDQS, outputs the resulting signal at its first output terminal, and outputs the complementary signal of the resulting signal at its second output terminal. The signal output at the first output terminal is essentially equivalent to the amplified signal of signal DQS, while the signal output at the second input terminal is essentially equivalent to the amplified signal of signal bDQS. By amplifying signal DQS with reference to signal bDQS in this manner, electrical noise that may be present on signals DQS and bDQS is mitigated (common-phase noise is removed) in these signals output from comparator CMP2.

[0146] Figure 9 1 shows an example where the inverter group INVG2 and the inverter group INVG3 each consist of four inverters. The inverter group INVG2 receives the signal output from the first output terminal of the comparator CMP2 and outputs the signal resulting from the transmission of this signal through the multiple inverters in the inverter group INVG2. This signal is output from the input circuit 122 as signal Sig1. The inverter group INVG3 receives the signal output from the second output terminal of the comparator CMP2 and outputs the signal resulting from the transmission of this signal through the multiple inverters in the inverter group INVG3. This signal is output from the input circuit 122 as signal Sig2.

[0147] about Figure 9 The three inverter groups INVG shown can adjust the delay amounts of the three signals respectively transmitted by the three inverter groups INVG by adjusting the number of inverters constituting each inverter group INVG.

[0148] Next, the latch circuit 123 <0> will be described.

[0149] The latch circuit 123 < 0 > includes a local latch circuit LC0 and a local latch circuit LC1 . The signal Din < 0 >, the signal Sig1 , and the signal Sig2 are processed as follows within the latch circuit 123 < 0 >.

[0150] The local latch circuit LC0 includes a latch input circuit LIC0 and an internal processing circuit INC0. The latch input circuit LIC0 includes, for example, an inverter INV1 and a switch SW1.

[0151] Latch input circuit LIC0 receives signal Din<0>. Inverter INV1 receives signal Din<0> and outputs a voltage whose level is the inverted version of signal Din<0>. More specifically, inverter INV1 outputs an L-level voltage while signal Din<0> is H, and outputs an H-level voltage while signal Din<0> is L. Latch input circuit LIC0 outputs the voltage output from inverter INV1 described above while switch SW1 is on. For example, switch SW1 is on while signal Sig1 is L and signal Sig2 is H, and is off while signal Sig1 is H and signal Sig2 is L. In this way, switch SW1 alternates between an on and off state in response to the switching of signals DQS and bDQS. The same applies to the other switches SW that similarly switch between an on and off state based on signals Sig1 and Sig2.

[0152] The internal processing circuit INC0 receives the voltage signal output from the latch input circuit LIC0, and based on this signal, latches the even-bit data of the signal DQ<0> in the order of bit 0, bit 2, bit 4, ... The internal processing circuit INC0 outputs the latched even-bit data in the order of latching. This output is equivalent to Figure 8 The output of the signal De<0> is shown.

[0153] The local latch circuit LC1 includes a latch input circuit LIC1 and an internal processing circuit INC1. The latch input circuit LIC1 includes, for example, an inverter INV2 and a switch SW2.

[0154] Latch input circuit LIC1 receives signal Din<0>. Inverter INV2 receives signal Din<0> and outputs a voltage at an inverted level of signal Din<0>. While switch SW2 is on, latch input circuit LIC1 outputs the voltage output from inverter INV2 in the aforementioned manner. Switch SW2 is off when signal Sig1 is low and signal Sig2 is high, and is on when signal Sig1 is high and signal Sig2 is low. Therefore, while switch SW1 is on, switch SW2 is off, and while switch SW1 is off, switch SW2 is on.

[0155] The internal processing circuit INC1 receives the voltage signal output from the latch input circuit LIC1, and based on this signal, latches the odd-bit data of the signal DQ<0> in the order of the 1st bit, the 3rd bit, the 5th bit, ... The internal processing circuit INC1 outputs the latched odd-bit data in the order of latching. This output is equivalent to Figure 8 The output of the signal Do<0> is shown.

[0156] While the above description describes an example configuration of each of the latch input circuits LIC0 and LIC1, this embodiment is not limited thereto. Each of the latch input circuits LIC0 and LIC1 may have another configuration capable of outputting a voltage in the manner described above based on the signal Din<0> and the signals Sig1 and Sig2. This also applies to the other circuits shown in the following figures as circuits including the inverter INV and the switch SW.

[0157] Hereinafter, when the switch SW included in the latch input circuit LIC is in the on state, as described above, and the latch input circuit LIC is capable of outputting a voltage, the latch input circuit LIC is referred to as being in the on state. In all other cases, the latch input circuit LIC is referred to as being in the off state. This also applies to other circuits shown in the following figures that control whether or not a voltage can be output based on the switch SW.

[0158] (8) Local latch circuit

[0159] The following describes the details of the structure of the local latch circuit LC1 of the latch circuit 123 <0>. Although the local latch circuit LC1 is used as an example for the description, the structure described below can be applied to both the local latch circuits LC0 and LC1. The same applies to other embodiments.

[0160] Figure 10 An example of a more detailed configuration of the local latch circuit LC1 of the semiconductor memory device 1 according to the first embodiment is shown. Hereinafter, the latch input circuit LIC1 is also referred to as a latch input circuit 1231 .

[0161] Signal Din<0> is input to the input terminal of inverter INV2, and the output terminal of inverter INV2 is connected to the first terminal of switch SW2. The second terminal of switch SW2 is connected to node N1. Switch SW2 is, for example, a two-terminal switch element capable of transmitting a signal between the first and second terminals while switch SW2 is in the on state. The same applies to the other switches SW described below.

[0162] Inverter INV2 supplies a voltage having an inverted level of the signal Din<0> input to the input terminal to the first terminal of switch SW2 connected to the output terminal. Switch SW2 transmits the voltage supplied to the first terminal in this manner to node N1 connected to the second terminal while switch SW2 is in the on state.

[0163] By supplying a voltage to the node N1 using the latch input circuit 1231 in the above manner, a certain bit of data transmitted by the signal Din<0> can be captured as the voltage of the node N1 into the local latch circuit LC1.

[0164] The internal processing circuit INC1 includes a positive feedback circuit 1232 and a voltage adjustment circuit 1233 .

[0165] The positive feedback circuit 1232 includes an inverter circuit 12321 and an inverter circuit with a release function 12322. The inverter circuit 12321 is also referred to as an inverter INV3. The inverter circuit 12322 with a release function includes, for example, an inverter INV4 and a switch SW3.

[0166] The input terminal of the inverter INV3 is connected to the node N1, and the output terminal of the inverter INV3 is connected to the node N2. For example, when the voltage value of the node N1 connected to the input terminal is greater than or equal to the threshold value Vth3, the inverter INV3 supplies an L-level voltage to the node N2 connected to the output terminal. When the voltage value of the node N1 connected to the input terminal is less than the threshold value Vth3, the inverter INV3 supplies an H-level voltage to the node N2 connected to the output terminal. As a result, the voltage of the node N2 can be either H or L.

[0167] The input terminal of the inverter INV4 is connected to the node N2, and the output terminal of the inverter INV4 is connected to the first terminal of the switch SW3. The second terminal of the switch SW3 is connected to the node N1.

[0168] The inverter circuit 12322 with a release function outputs a voltage based on the voltage of the node N2 in the following manner.

[0169] For example, when the voltage value of node N2 connected to the input terminal is greater than or equal to threshold Vth4, inverter INV4 supplies an L-level voltage to the first terminal of switch SW3 connected to the output terminal. When the voltage value of node N2 connected to the input terminal is less than threshold Vth4, inverter INV4 supplies an H-level voltage to the first terminal of switch SW3 connected to the output terminal. Switch SW3 transmits the voltage supplied to the first terminal in this manner to node N1 connected to the second terminal while switch SW3 is in the on state. Switch SW3 is in the on state when signal Sig1 is at an L level and signal Sig2 is at an H level, and is in the off state when signal Sig1 is at an H level and signal Sig2 is at an L level. Therefore, while switch SW2 is in the on state, switch SW3 is in the off state, and while switch SW2 is in the off state, switch SW3 is in the on state.

[0170] By supplying voltages to nodes N1 and N2 using inverter circuits 12321 and 12322, the captured data bit can be latched into local latch circuit LC1 as voltages at nodes N1 and N2. Signal Do<0> is generated based on the voltage at node N2.

[0171] The H-level voltages supplied by inverters INV2, INV3, and INV4 are, for example, substantially the same voltage, and the L-level voltages supplied by inverters INV2, INV3, and INV4 are, for example, substantially the same voltage. Thresholds Vth3 and Vth4 are, for example, the average of the H-level and L-level voltages, respectively. The same applies to the other inverters INV and other thresholds Vth described below. The following description assumes that the above description still holds true.

[0172] Next, the voltage adjustment circuit 1233 will be described.

[0173] The voltage adjustment circuit 1233 includes an inverter INV5. The input terminal and output terminal of the inverter INV5 are connected to the node N1. For example, when the voltage value of the node N1 connected to the input terminal is greater than or equal to a threshold value Vth5, the inverter INV5 supplies an L-level voltage to the node N1 connected to the output terminal. When the voltage value of the node N1 connected to the input terminal is less than the threshold value Vth5, the inverter INV5 supplies an H-level voltage to the node N1 connected to the output terminal.

[0174] The function of voltage regulator circuit 1233 to regulate the voltage at node N1 while signal Sig1 is at H level will be described. During this period, switch SW2 is on and switch SW3 is off. In other words, latch input circuit 1231 is on and inverter circuit 12322 is off.

[0175] When latch input circuit 1231 supplies an H-level voltage to node N1, the voltage at node N1 may rise. If this voltage exceeds threshold Vth5, voltage adjustment circuit 1233 supplies an L-level voltage to node N1, corresponding to the voltage exceeding threshold Vth5. Latch input circuit 1231 supplies an H-level voltage, and voltage adjustment circuit 1233 supplies an L-level voltage, resulting in the voltage at node N1 being stabilized at an H-level. This H-level voltage is lower than when no voltage is supplied from voltage adjustment circuit 1233, but the voltage at node N1 is stabilized based on the H-level voltage supplied from latch input circuit 1231. This is because, when the voltage at node N1 is stabilized at an H-level, the resistance R5L of the path from the source of the L-level voltage supplied by voltage adjustment circuit 1233 to node N1 is greater than the resistance R2H of the path from the source of the H-level voltage supplied by latch input circuit 1231 to node N1. In this specification, the term "supply source" of a voltage at a certain level refers to a node connected to a circuit that supplies that voltage and to which that voltage is applied. For example, when the voltage at node N1 is stable at an H level, (the magnitude of resistor R5L) / (the magnitude of resistor R2H) is within the range of 5 / 3 or more and 3 or less.

[0176] When latch input circuit 1231 supplies an L-level voltage to node N1, the voltage at node N1 may drop. If the value of this voltage is less than threshold value Vth5, voltage adjustment circuit 1233 supplies an H-level voltage to node N1 accordingly. Latch input circuit 1231 supplies an L-level voltage, and voltage adjustment circuit 1233 supplies an H-level voltage, resulting in the voltage at node N1 being stabilized at an L-level. This L-level voltage is higher than when no voltage is supplied from voltage adjustment circuit 1233, but the voltage at node N1 is stabilized by the L-level voltage supplied from latch input circuit 1231. This is because, when the voltage at node N1 is stabilized at an L-level, the resistance R5H of the path from the source of the H-level voltage supplied by voltage adjustment circuit 1233 to node N1 is greater than the resistance R2L of the path from the source of the L-level voltage supplied by latch input circuit 1231 to node N1. For example, when the voltage of the node N1 is stable at the L level, (the size of the resistor R5H) / (the size of the resistor R2L) is in the range of not less than 5 / 3 and not more than 3.

[0177] The same applies to the voltage regulation circuit 1233's function of regulating the voltage at node N1 while signal Sig1 is at an L level. During this period, switch SW2 is off and switch SW3 is on. In other words, latch input circuit 1231 is off and inverter circuit 12322 is on. In the above description, latch input circuit 1231 can be replaced with inverter circuit 12322.

[0178] The above describes the configuration of local latch circuit LC1. The following describes a case where the same configuration is applied to local latch circuit LC0. In this case, even if the conditions for turning on each switch and turning off each switch are reversed in the configuration of local latch circuit LC1, the same configuration as local latch circuit LC0 can still be applied. Unless otherwise specified, the same applies to other embodiments.

[0179] Figure 11 An example of the circuit configuration of the local latch circuit LC1 of the semiconductor memory device 1 according to the first embodiment is shown. Figure 11 In the embodiment, the implementation and Figure 10 The functions implemented by the inverters INV and the switches SW as part of the local latch circuit LC1 are described in detail in the following. The same applies to the following drawings.

[0180] First, the circuit configuration of the latch input circuit 1231 will be described. Figure 11In the example, latch input circuit 1231 is implemented using a clocked inverter circuit. More specifically, latch input circuit 1231 is implemented using a clocked CMOS (Complementary Metal Oxide Semiconductor) inverter circuit. The clocked inverter circuit switches between an inverter output state and an inverter output stop state. When the clocked inverter is in the inverter output state, a signal with an inverted logic level of the signal input to the input terminal is output from the output terminal. When the clocked inverter is in the inverter output stop state, no signal is output from the output terminal, regardless of the logic level of the signal input to the input terminal.

[0181] The latch input circuit 1231 includes, for example, p-channel MOS (Metal Oxide Semiconductor) transistors Tr11 and Tr12 , and n-channel MOS transistors Tr13 and Tr14 .

[0182] A voltage VDD, for example, is applied to the first terminal of transistor Tr11. Voltage VDD is, for example, a power supply voltage and is the aforementioned high-level voltage. The second terminal of transistor Tr11 is connected to the first terminal of transistor Tr12, and the second terminal of transistor Tr12 is connected to node N1. The first terminal of transistor Tr13 is connected to node N1, and the second terminal of transistor Tr13 is connected to the first terminal of transistor Tr14. A voltage VSS, for example, is applied to the second terminal of transistor Tr14. Voltage VSS is, for example, a reference voltage such as ground and is the aforementioned low-level voltage. Voltage VSS is lower than voltage VDD. Signal Din<0> is input to the gates of transistors Tr11 and Tr14. Signal Sig2 is input to the gate of transistor Tr12. Signal Sig1 is input to the gate of transistor Tr13.

[0183] While the signal Sig1 is at L level and the signal Sig2 is at H level, the transistors Tr12 and Tr13 are in the OFF state. Therefore, the voltage VDD applied to the first terminal of the transistor Tr11 and the voltage VSS applied to the second terminal of the transistor Tr14 are not supplied to the node N1.

[0184] While the signal Sig1 is at H level and the signal Sig2 is at L level, the transistors Tr12 and Tr13 are in the on state. During this period, the latch input circuit 1231 supplies a voltage of a level inverted from the level of the signal Din<0> to the node N1 as follows.

[0185] When the signal Din<0> is at an H level, transistor Tr11 is turned off and transistor Tr14 is turned on. Therefore, in response to the signal Din<0> being at an H level, the voltage VSS applied to the second terminal of transistor Tr14 is supplied to node N1. On the other hand, when the signal Din<0> is at an L level, transistor Tr11 is turned on and transistor Tr14 is turned off. Therefore, in response to the signal Din<0> being at an L level, the voltage VDD applied to the first terminal of transistor Tr11 is supplied to node N1.

[0186] Next, the circuit configuration of the positive feedback circuit 1232 will be described. Figure 11 In the example, the inverter circuit 12321 is implemented using a CMOS inverter circuit, and the inverter circuit with a release function 12322 is implemented using a clock-synchronized CMOS inverter circuit.

[0187] The inverter circuit 12321 includes, for example, a p-channel MOS transistor Tr211 and an n-channel MOS transistor Tr212 .

[0188] A voltage VDD, for example, is applied to the first terminal of transistor Tr211, and a second terminal of transistor Tr211 is connected to node N2. A first terminal of transistor Tr212 is connected to node N2, and a voltage VSS, for example, is applied to the second terminal of transistor Tr212. The gates of transistors Tr211 and Tr212 are each connected to node N1.

[0189] When the voltage at node N1 is less than the threshold value Vth3, for example, transistor Tr211 is in the on state and transistor Tr212 is in the off state. Therefore, the voltage VDD applied to the first terminal of transistor Tr211 is supplied to node N2, corresponding to the voltage at node N1 being less than the threshold value Vth3. On the other hand, when the voltage at node N1 is greater than the threshold value Vth3, for example, transistor Tr211 is in the off state and transistor Tr212 is in the on state. Therefore, the voltage VSS applied to the second terminal of transistor Tr212 is supplied to node N2, corresponding to the voltage at node N1 being greater than the threshold value Vth3.

[0190] The inverter circuit with a release function 12322 includes, for example, p-channel MOS transistors Tr221 and Tr222 , and n-channel MOS transistors Tr223 and Tr224 .

[0191] A voltage VDD, for example, is applied to the first terminal of transistor Tr221. The second terminal of transistor Tr221 is connected to the first terminal of transistor Tr222, and the second terminal of transistor Tr222 is connected to node N1. The first terminal of transistor Tr223 is connected to node N1, and the second terminal of transistor Tr223 is connected to the first terminal of transistor Tr224. A voltage VSS, for example, is applied to the second terminal of transistor Tr224. The gates of transistors Tr221 and Tr224 are each connected to node N2. Signal Sig1 is input to the gate of transistor Tr222. Signal Sig2 is input to the gate of transistor Tr223.

[0192] While the signal Sig1 is at H level and the signal Sig2 is at L level, the transistors Tr222 and Tr223 are in the OFF state. Therefore, the voltage VDD applied to the first terminal of the transistor Tr221 and the voltage VSS applied to the second terminal of the transistor Tr224 are not supplied to the node N1.

[0193] While the signal Sig1 is at the L level and the signal Sig2 is at the H level, the transistors Tr222 and Tr223 are in the on state. During this period, the inverter circuit 12322 with the release function supplies a voltage to the node N1 as follows.

[0194] When the voltage value at node N2 is greater than or equal to threshold value Vth4, for example, transistor Tr221 is in the off state and transistor Tr224 is in the on state. Therefore, corresponding to the voltage value at node N2 being greater than or equal to threshold value Vth4, the voltage VSS applied to the second terminal of transistor Tr224 is supplied to node N1. On the other hand, when the voltage value at node N2 is less than threshold value Vth4, for example, transistor Tr221 is in the on state and transistor Tr224 is in the off state. Therefore, corresponding to the voltage value at node N2 being less than threshold value Vth4, the voltage VDD applied to the first terminal of transistor Tr221 is supplied to node N1.

[0195] Next, the circuit configuration of the voltage regulating circuit 1233 will be described. Figure 11 In the example shown in FIG. 1 , the voltage adjustment circuit 1233 is implemented using a CMOS inverter circuit.

[0196] The voltage adjustment circuit 1233 includes, for example, a p-channel MOS transistor Tr31 and an n-channel MOS transistor Tr32 .

[0197] The first terminal of transistor Tr31 is applied with voltage VDD, for example, and the second terminal and gate of transistor Tr31 are connected to node N1. The first terminal and gate of transistor Tr32 are connected to node N1, and the second terminal of transistor Tr32 is applied with voltage VSS, for example.

[0198] When the voltage at node N1 is less than the threshold value Vth5, for example, transistor Tr31 is in the on state and transistor Tr32 is in the off state. Therefore, the voltage VDD applied to the first terminal of transistor Tr31 is supplied to node N1, corresponding to the voltage at node N1 being less than the threshold value Vth5. On the other hand, when the voltage at node N1 is greater than the threshold value Vth5, for example, transistor Tr31 is in the off state and transistor Tr32 is in the on state. Therefore, the voltage VSS applied to the second terminal of transistor Tr32 is supplied to node N1, corresponding to the voltage at node N1 being greater than the threshold value Vth5.

[0199] For example, Figure 11 The p-channel MOS transistor Tr11 and the n-channel MOS transistor Tr14 are shown as Figure 10 The inverter INV2 shown in FIG. 1 is functional. Figure 11 The p-channel MOS transistor Tr12 and the n-channel MOS transistor Tr13 are shown as Figure 10 Similarly, for example, p-channel MOS transistor Tr211 and n-channel MOS transistor Tr212 function as inverter INV3, p-channel MOS transistor Tr221 and n-channel MOS transistor Tr224 function as inverter INV4, p-channel MOS transistor Tr222 and n-channel MOS transistor Tr223 function as switch SW3, and p-channel MOS transistor Tr31 and n-channel MOS transistor Tr32 function as inverter INV5.

[0200] As reference Figure 10 As explained above, when the voltage of node N1 is stabilized at an L level by supplying an L level voltage to node N1 through the latch input circuit 1231, the on-resistance of transistor Tr31 is greater than the sum of the on-resistances of transistors Tr13 and Tr14. Each transistor Tr is formed so that this relationship is established. The same applies to the following description. Figure 10 As described above, when the latch input circuit 1231 supplies an H-level voltage to the node N1 and the voltage of the node N1 is stabilized at the H level, the on-resistance of the transistor Tr32 becomes larger than the sum of the on-resistances of the transistors Tr11 and Tr12.

[0201] As reference Figure 10 As described above, when the voltage of the node N1 is stabilized at the L level by supplying the L level voltage to the node N1 through the inverter circuit 12322, the on-resistance of the transistor Tr31 is larger than the sum of the on-resistances of the transistors Tr223 and Tr224. Figure 10As described above, when the voltage of the node N1 is stabilized at the H level by supplying the H level voltage to the node N1 through the inverter circuit 12322, the on-resistance of the transistor Tr32 becomes larger than the sum of the on-resistances of the transistors Tr221 and Tr222.

[0202] The circuit configuration of local latch circuit LC1 has been described above. The following describes a case where the same circuit configuration is applied to local latch circuit LC0. In this case, although, for example, signal Sig2 is input to each gate described as input signal Sig1, and signal Sig1 is input to each gate described as input signal Sig2, the circuit configuration of local latch circuit LC1 can still be applied to the circuit configuration of local latch circuit LC0. Unless otherwise specified, the same applies to other embodiments.

[0203] [Action Example]

[0204] Hereinafter, an operation example of latching data DAT transmitted by the signal DQ<7:0> sent from the memory controller 2 by the semiconductor memory device 1 according to the first embodiment will be described in detail.

[0205] (1) Latching action of the latch circuit

[0206] Figure 12 An example of a timing chart showing temporal changes of a command set and other various signals related to a certain write operation executed by the semiconductor memory device 1 according to the first embodiment is shown. Figure 12 In the figure, the time variation of the DQS signal is shown by a solid line, and the time variation of the bDQS signal is shown by a dashed line. Below, when a signal is described as being at a certain level, unless control for changing the signal to another level is explicitly described later, the signal remains at the described level. This applies similarly to the other figures.

[0207] While memory controller 2 receives the ready / busy signal bR / B at an H level, that is, while semiconductor memory device 1 is in the ready state, memory controller 2 generates a command set for causing semiconductor memory device 1 to execute a write operation and transmits this command set to semiconductor memory device 1 via signals DQ<7:0>. This command set includes command "80h," address information ADD, write data DAT, and command "10h." After receiving this command set, semiconductor memory device 1 begins the write operation. More details are as follows.

[0208] First, memory controller 2 generates command "80h" and simultaneously toggles write enable signal bWE, sending this command "80h" to semiconductor memory device 1. Command "80h" is used to cause semiconductor memory device 1 to execute a write operation. Logic control circuit 13 can instruct input / output circuit 12 to transmit command "80h" to register 14 based on the toggling of write enable signal bWE.

[0209] Subsequently, the memory controller 2 generates address information ADD within, for example, five cycles and simultaneously transmits this address information ADD to the semiconductor memory device 1 while switching the write enable signal bWE. The address information ADD generated over five cycles specifies, for example, the write target block BLK and a region within that block BLK. Based on this address information ADD, the sequencer 15 specifies, for example, the region within the memory cell array MCA where the data is to be written. Furthermore, the address information ADD is not limited to five cycles; any number of cycles can be used. Based on the switching of the write enable signal bWE, the logic control circuit 13 instructs the input / output circuit 12 to transmit the address information ADD to the register 14.

[0210] Then, the memory controller 2 switches the signal DQS and the signal bDQS, and transmits the data DAT in the order of bit 0, bit 1, bit 2, . . . to the semiconductor memory device 1 via the signals DQ<7:0>.

[0211] This switching is explained. For example, the signal DQS is at an L level before the data DAT is sent to the semiconductor memory device 1. Subsequently, the signal DQS rises from an L level to an H level while the 0th bit of data is transmitted using each signal DQ<7:0>. Subsequently, the signal DQS falls from an H level to an L level while the 1st bit of data is transmitted using each signal DQ<7:0>. In this way, the switching of changing the level of the signal DQS once is periodically repeated while 1 bit of data is transmitted using each signal DQ<7:0>. This periodic switching continues while the data DAT is transmitted using the signal DQ<7:0>. The signal bDQS is switched so as to become a complementary signal of the signal DQS.

[0212] Local latch circuit LC0 of latch circuit 123<0> latches each even-numbered bit of signal DQ<0> at the timing of the rising edge of signal DQS. Local latch circuit LC1 of latch circuit 123<0> latches each odd-numbered bit of signal DQ<0> at the timing of the falling edge of signal DQS. The other latch circuits 123<7:1> operate similarly. Sequencer 15 inputs each bit of data DAT latched in this manner to the latch circuits of data register DR corresponding to the area in memory cell array MCA to which data is to be written.

[0213] Memory controller 2 then generates command "10h" and simultaneously switches write enable signal bWE to transmit this command "10h" to semiconductor memory device 1. Command "10h" causes semiconductor memory device 1 to execute a write operation based on address information ADD and data DAT received after receiving command "80h." Logic control circuit 13 can instruct input / output circuit 12 to transmit command "10h" to register 14 based on the switching of write enable signal bWE.

[0214] In response to receiving the command "10h," the sequencer 15 causes the logic control circuit 13 to transmit the ready / busy signal bR / B at an L level to the memory controller 2. This notifies the memory controller 2 that the semiconductor memory device 1 is in a busy state. In response to receiving the command "10h," the sequencer 15 controls the voltage generating circuit 16, the driver unit 17, and the target memory plane PB to initiate a write operation.

[0215] After the write operation is completed, the sequencer 15 causes the logic control circuit 13 to transmit the ready / busy signal bR / B at an H level to the memory controller 2. This notifies the memory controller 2 that the semiconductor memory device 1 is in the ready state.

[0216] (2) Latching action of the local latch circuit

[0217] Figure 13 An example of a timing chart showing time changes of various signals when the local latch circuit LC1 of the semiconductor memory device 1 according to the first embodiment latches a certain bit of data transmitted by the signal DQ<0> is shown. Figure 13 In FIG. 1 , the signal transmitted at the node N1 and indicating the voltage of the node N1 is represented as the signal SigN1 . The same is true for the other drawings.

[0218] At time T00, signal Sig1 is at L level and signal Sig2 is at H level. The levels of signals Sig1 and Sig2 remain unchanged until time T01. Therefore, from time T00 to time T01, latch input circuit 1231 is in the OFF state, while inverter circuit 12322 with a release function is in the ON state.

[0219] From time T00 to time T01, signal Din<0> is at an L level. For example, signal Din<0> has been at an L level since before time T00. Before time T00, latch input circuit 1231 supplies an H-level voltage, for example, voltage VDD, which is an inversion of the L level of signal Din<0>, to node N1. At time T00, the voltage at node N1 is stabilized at an H level. From time T00 to time T01, inverter circuit 12322 supplies an H-level voltage, for example, voltage VDD, to node N1. Consequently, the voltage at node N1 is stabilized at an H level.

[0220] As reference Figure 10 As described above, compared to the case where the voltage of the node N1 is stabilized based on, for example, the voltage VDD supplied from one of the latch input circuit 1231 and the inverter circuit 12322 without the voltage adjustment circuit 1233, the H level voltage of the node N1 is reduced by the voltage difference ΔVH through the voltage adjustment circuit 1233.

[0221] At time T01, signal Sig1 rises from L level to H level, and signal Sig2 falls from H level to L level. The levels of signals Sig1 and Sig2 remain unchanged until time T02. Therefore, from time T01 to time T02, latch input circuit 1231 is in the on state, while inverter circuit 12322 with a release function is in the off state.

[0222] From time T01 to time T01d, signal Din<0> is at an L level. Time T01d is after time T01 and before time T02. From time T01 to time T01d, latch input circuit 1231 supplies a voltage that is an inverted version of the L level of signal Din<0>, for example, voltage VDD, to node N1. This stabilizes the voltage at node N1 at an H level.

[0223] At time T01d, signal Din<0> rises from L level to H level. Signal Din<0> remains at H level until time T02d. Time T02d is after time T02. From time T01d to time T02, latch input circuit 1231 supplies a voltage at a level that is the inverted version of the H level of signal Din<0>, for example, voltage VSS, to node N1. As a result, the voltage at node N1 drops from H level.

[0224] At time T02, signal Sig1 falls from H level to L level, and signal Sig2 rises from L level to H level. The time from time T01d, when signal Din<0> rises, to time T02, when signal Sig1 falls, is time ΔT. Signals Sig1 and Sig2 maintain their levels until time T03. Time T03 is, for example, after time T02d. Therefore, from time T02 to time T03, latch input circuit 1231 is in the OFF state, while inverter circuit 12322 with a release function is in the ON state.

[0225] At time T02, the voltage at node N1 falls below threshold Vth3, reaching a low level. In response to the voltage at node N1 falling below threshold Vth3, inverter circuit 12321 supplies an H-level voltage to node N2. This causes the voltage at node N2 to rise above threshold Vth4. In response to the voltage at node N2 rising above threshold Vth4, inverter circuit 12322 supplies an L-level voltage, for example, voltage VSS, to node N1. This further lowers the voltage at node N1. Despite the decrease in the voltage at node N1 described above, this voltage remains below threshold Vth3, and the voltage at node N2 remains above threshold Vth4. Therefore, from time T02 to time T03, inverter circuit 12321 continues to supply an H-level voltage to node N2, while inverter circuit 12322 continues to supply, for example, voltage VSS to node N1. As a result, the voltage at node N1 reaches and stabilizes at a low level. The voltage at node N2 remains stable at a high level.

[0226] As reference Figure 10 As described above, compared to the case where the voltage at the node N1 is stabilized based on, for example, the voltage VSS supplied from one of the latch input circuit 1231 and the inverter circuit 12322 without the voltage adjustment circuit 1233, the L-level voltage at the node N1 is increased by the voltage difference ΔVL by the voltage adjustment circuit 1233.

[0227] Thus, the H level of the signal Din<0> immediately before the time T02 at which the signal Sig1 falls is reflected in the voltages of the nodes N1 and N2. More specifically, the node N1 is stabilized at the L level as a result of the latch input circuit 1231 inverting the H level of the signal Din<0>, and the node N2 is stabilized at the H level as a result of the inverter circuit 12321 inverting the L level. As a result, as shown in FIG. Figure 12 As described above, at the timing when the signal DQS falls, a certain odd-numbered bit of data transmitted by the signal DQ<0> is latched by the local latch circuit LC1.

[0228] At time T02d, signal Din<0> drops from H level to L level. From time T02d to time T03, latch input circuit 1231, which is in the OFF state, does not supply voltage to node N1. Thus, even though the voltage of signal Din<0> changes at this timing, latch input circuit 1231 does not immediately change the voltage of node N1.

[0229] At time T03, signal Sig1 rises from L level to H level, and signal Sig2 falls from H level to L level. The levels of signals Sig1 and Sig2 remain unchanged until time T04. Therefore, from time T03 to time T04, latch input circuit 1231 is in the on state, while inverter circuit 12322 with a release function is in the off state. At time T04, signal Sig1 falls from H level to L level, and signal Sig2 rises from L level to H level.

[0230] From time T02d to time T04, signal Din<0> is at L level. From time T03 to time T04, latch input circuit 1231 supplies a voltage that is an inverted version of the L level of signal Din<0>, for example, voltage VDD, to node N1. Consequently, the voltage at node N1 rises from L level to the aforementioned H level.

[0231] Figure 14 Another example of a timing chart showing time changes of various signals when the local latch circuit LC1 of the semiconductor memory device 1 according to the first embodiment latches a certain bit of data transmitted by the signal DQ<0> is shown.

[0232] Regarding the time variation of the signal Sig1, the signal Sig2, and the signal Din<0>, Figure 13 In the description, the time T00 is replaced by the time T10, the time T01 is replaced by the time T11, the time T02 is replaced by the time T12, the time T03 is replaced by the time T13, the time T04 is replaced by the time T14, the time T01d is replaced by the time T11d, and the time T02d is replaced by the time T12d. Furthermore, after the H level and the L level of the signal Din<0> are swapped, the content still holds. The time from the time T11d to the time T12 is the same as the time ΔT from the time T01d to the time T02. In addition, whether the latch input circuit 1231 and the inverter circuit with release function 12322 are in the on state or the off state, Figure 13 Even if the time is replaced in the manner described in the description, the content still holds true.

[0233] The voltage at the node N1 will be described below.

[0234] At time T10, the voltage at node N1 is stabilized at L level. During the period from time T10 to time T11, the inverter circuit 12322 supplies an L level voltage, for example, voltage VSS, to node N1. As a result, the voltage at node N1 is stabilized at L level.

[0235] and Figure 13 Similarly, compared to the case where there is no voltage adjustment circuit 1233 and the voltage of the node N1 is stabilized based on, for example, the voltage VSS supplied from one of the latch input circuit 1231 and the inverter circuit 12322, the L-level voltage of the node N1 increases by the voltage difference ΔVL through the voltage adjustment circuit 1233.

[0236] From time T11 to time T11d, the latch input circuit 1231 supplies a voltage of the inverted H level of the signal Din<0>, that is, for example, the voltage VSS, to the node N1, thereby stabilizing the voltage of the node N1 at the L level.

[0237] From time T11d to time T12, the latch input circuit 1231 supplies a voltage of a level inverted from the L level of the signal Din<0>, that is, for example, the voltage VDD, to the node N1.

[0238] At time T12 , the voltage value of the node N1 is equal to or higher than the threshold value Vth3 , but the voltage of the node N1 is lower than the H level.

[0239] Inverter circuit 12321 supplies an L-level voltage to node N2 in response to the voltage value at node N1 being above threshold Vth3. This causes the voltage value at node N2 to fall below threshold Vth4. Inverter circuit 12322 supplies an H-level voltage, for example, voltage VDD, to node N1 in response to the voltage value at node N2 falling below threshold Vth4. This causes the voltage at node N1 to rise further. Despite the increase in the voltage at node N1 described above, this voltage remains above threshold Vth3, and the voltage value at node N2 remains below threshold Vth4. Therefore, from time T12 to time T13, inverter circuit 12321 continues to supply an L-level voltage to node N2, while inverter circuit 12322 continues to supply, for example, voltage VDD to node N1. As a result, the voltage at node N1 reaches and stabilizes at an H-level. The voltage at node N2 stabilizes at an L-level.

[0240] and Figure 13 Similarly, compared to the case where the voltage of the node N1 is stabilized based on, for example, the voltage VDD supplied from one of the latch input circuit 1231 and the inverter circuit 12322 without the voltage adjustment circuit 1233, the H-level voltage of the node N1 is reduced by the voltage difference ΔVH through the voltage adjustment circuit 1233.

[0241] In this way, the L level of the signal Din<0> immediately before the time T12 at which the signal Sig1 falls is reflected in the voltages of the nodes N1 and N2. Figure 12 As described above, at the timing when the signal DQS falls, a certain odd-numbered bit of data transmitted by the signal DQ<0> is latched by the local latch circuit LC1.

[0242] From time T13 to time T14, the latch input circuit 1231 supplies a voltage of the inverted H level of the signal Din<0>, that is, for example, the voltage VSS, to the node N1. As a result, the voltage of the node N1 drops from the H level to the L level.

[0243] [Effect]

[0244] Figure 15 This diagram shows an example of a timing diagram illustrating the temporal changes of various signals when a local latch circuit in a semiconductor memory device, in a comparative example of the first embodiment, latches a certain bit of data transmitted by the signal DQ<0>. The temporal changes of signal Sig2 are omitted in this timing diagram because signal Sig2 is simply the complement of signal Sig1, which shows the temporal changes.

[0245] The configuration of the local latch circuit is obtained by removing the voltage adjustment circuit 1233 from the configuration of the local latch circuit LC1 of the semiconductor memory device 1 in the first embodiment. In the following description, when describing each component within the local latch circuit, the same reference numerals as those used in the first embodiment are used to describe the component.

[0246] Figure 15 The timing chart shown by the solid line in the middle shows that the local latch circuit of the comparative example is in Figure 13 The time variation of various signals under the same conditions as the example. Figure 13 In the description of , the content still holds even if time T00 is replaced by time T0, time T01 is replaced by time T1, time T02 is replaced by time T2, time T03 is replaced by time T3, time T04 is replaced by time T4, time T01d is replaced by time T1d, and time T02d is replaced by time T2d. The time from time T1d to time T2 is the same as the time ΔT from time T01d to time T02. In addition, whether the latch input circuit 1231 and the inverter circuit with release function 12322 are in the on state or the off state, Figure 13 Even if the time is replaced in the manner described in the description, the content still holds true.

[0247] The voltage at the node N1 will be described below.

[0248] Figure 15 From time T0 to time T1d, Figure 13 In the example of FIG. 1 , the voltage of the node N1 is stable at the H level from time T00 to time T01d. Since the local latch circuit does not include the voltage adjustment circuit 1233, the voltage at the H level is the same as that at the node N1. Figure 13 Unlike the example above, no voltage drop occurs.

[0249] Figure 15 From time T1d to time T2, Figure 13 In the example of FIG, from time T01d to time T02, the voltage of the node N1 decreases from the H level.

[0250] exist Figure 15 At time T2, Figure 13 Unlike the time T02 in the example, the voltage value of the node N1 is still above the threshold value Vth3. Therefore, from time T2 to time T3, the inverter circuit 12321 and the inverter circuit 12322 each output the same value as Figure 13 In the example of FIG. 1 , the voltages at opposite levels are from time T02 to time T03. Therefore, the voltages at the nodes N1 and N2 are stabilized at the same level as the voltages at the nodes N1 and N2. Figure 13 Example of opposite level.

[0251] Next, a case where the temporal variation of the signal Sig1 is the same as that described above, but the signal Din<0> is raised from the L level to the H level earlier than described above will be described. In this case, the temporal variation of the signal Din<0> and the voltage variation of the node N1 are as follows. Figure 15 Indicated by dotted line.

[0252] exist Figure 15 At time T1e in the example, signal Din<0> rises from L level to H level. Time T1e is after time T1 and before time T1d. The time from time T1e to time T2 is time ΔTa, which is longer than time ΔT. Figure 13 Similarly, in the example of FIG, from time T01d to time T02, the voltage of the L level, that is, for example, the voltage VSS is supplied to the node N1. As a result, the voltage of the node N1 drops from the H level.

[0253] exist Figure 15 At time T2, Figure 13 Similarly, at time T02 in the example, the voltage value of the node N1 is lower than the threshold value Vth3. Figure 13 Similarly, after the voltage value of the node N1 becomes lower than the threshold value Vth3, the voltage value of the node N2 quickly becomes higher than the threshold value Vth4. Therefore, from time T2 to time T3, the inverter circuit 12321 and the inverter circuit 12322 each output the same value as Figure 13 In the example of , the voltage of the same level from time T02 to time T03 is Figure 13 Similarly to the example, the voltage of the node N1 reaches and stabilizes at the L level, and the voltage of the node N2 stabilizes at the H level. However, since the local latch circuit does not include the voltage adjustment circuit 1233, the L level voltage of the node N1 is different from the Figure 13 Unlike the example above, no voltage rise occurs.

[0254] In both cases described above for the comparative example, the signal Din<0> rises while the signal Sig1 is at the H level. Figure 15 The first case ( Figure 15 In the waveform shown by the solid line in the middle, the H level of signal Din<0> immediately before time T2, when signal Sig1 falls, is not reflected in the voltages of nodes N1 and N2. This means that while signal Din<0> is at this H level, a certain bit of data transmitted by signal Din<0> is not correctly latched by the local latch circuit. This can cause malfunction.

[0255] As in the first case ( Figure 15 (See the waveform shown by the solid line in the middle). If the time ΔT from the start of the level change of signal Din<0> to the fall of signal Sig1 is short, latch input circuit 1231 has less time to change the voltage of node N1 in response to the level change of signal Din<0>. Therefore, as described above, the bit data transmitted to node N1 by signal Din<0> at the timing of the fall of signal Sig1 may not be correctly latched by the local latch circuit.

[0256] The local latch circuit LC1 of the semiconductor memory device 1 according to the first embodiment is as shown in FIG. Figure 13 As described above, even when the time from when signal Din<0> rises to when signal Sig1 falls is as short as time ΔT, a certain bit of data transmitted by signal Din<0> can be accurately latched at the timing of the fall. This is because, in the semiconductor memory device 1 of the first embodiment, the voltage at node N1 is lowered from an H level by voltage difference ΔVH by voltage adjustment circuit 1233, so that latch input circuit 1231 also lowers the voltage at node N1 from an H level to below threshold value Vth3 within a time as short as time ΔT.

[0257] As described above, the time from the rise of signal Din<0> to the fall of signal Sig1 is shortened, which can lead to a situation where, for example, the semiconductor memory device 1 operates at high speed. Therefore, the local latch circuit LC1 of the semiconductor memory device 1 of the first embodiment can accurately latch the data of the odd-numbered bits of signal Din<0> even when the semiconductor memory device 1 operates at high speed.

[0258] The comparison between the local latch circuit of the semiconductor memory device of the comparative example of the first embodiment and the local latch circuit LC1 of the semiconductor memory device 1 of the first embodiment is as follows. Figure 13 and Figure 15 The local latch circuit LC1 of the semiconductor memory device 1 of the first embodiment is based on Figure 14 The same applies to the operation of signals Sig1, Sig2, and Din<0> shown above. Even when the time from the fall of signal Din<0> to the fall of signal Sig1 is short, the local latch circuit LC1 of the semiconductor memory device 1 according to the first embodiment can latch a certain bit of data transmitted by signal Din<0> at the timing of the fall. This is because, in the semiconductor memory device 1 according to the first embodiment, the voltage adjustment circuit 1233 raises the voltage at node N1 from the low level by the voltage difference ΔVL, so the latch input circuit 1231 also raises the voltage at node N1 from the low level to above the threshold value Vth3 within such a short time.

[0259] <Second embodiment>

[0260] Hereinafter, a semiconductor memory device 1 a according to a second embodiment will be described.

[0261] [Example of configuration]

[0262] The configuration of the semiconductor storage device 1 a according to the second embodiment will be described focusing on differences from the configuration of the semiconductor storage device 1 according to the first embodiment.

[0263] The semiconductor memory device 1a of the second embodiment is obtained by replacing the local latch circuit LC1 with a local latch circuit LC1a in the semiconductor memory device 1 of the first embodiment. When describing certain components of the semiconductor memory device 1a of the second embodiment that include the local latch circuit LC1a, the components are described using the reference numerals a used in the first embodiment. For example, the semiconductor memory device of the second embodiment will be referred to as the semiconductor memory device 1a.

[0264] Figure 16 An example of the configuration of a local latch circuit LC1a of a semiconductor memory device 1a according to the second embodiment is shown.

[0265] Figure 16 The local latch circuit LC1a is constructed in Figure 10 The configuration of local latch circuit LC1 shown here is the result of replacing voltage adjustment circuit 1233 with voltage adjustment circuit 1233a. Although not shown in the figure, voltage adjustment circuit 1233a is also included in internal processing circuit INC1a. In other figures referring to the configuration of local latch circuits, all circuits except latch input circuit 1231 are also included in the internal processing circuit.

[0266] The voltage adjustment circuit 1233a includes, for example, an inverter INV6 and a switch SW4.

[0267] The input terminal of the inverter INV6 is connected to the node N1, and the output terminal of the inverter INV6 is connected to the first terminal of the switch SW4. The second terminal of the switch SW4 is connected to the node N1.

[0268] The voltage adjustment circuit 1233a outputs a voltage based on the voltage of the node N1 as follows.

[0269] For example, when the voltage value of node N1 connected to the input terminal is greater than or equal to threshold Vth6, inverter INV6 supplies an L-level voltage to the first terminal of switch SW4 connected to the output terminal. When the voltage value of node N1 connected to the input terminal is less than threshold Vth6, inverter INV6 supplies an H-level voltage to the first terminal of switch SW4 connected to the output terminal. Switch SW4 transmits the voltage supplied to the first terminal in this manner to node N1 connected to the second terminal while switch SW4 is in the on state. Switch SW4 is in the off state when signal Sig1 is at an L level and signal Sig2 is at an H level, and is in the on state when signal Sig1 is at an H level and signal Sig2 is at an L level. Therefore, while switch SW2 is in the on state, switch SW4 is also in the on state, and while switch SW2 is in the off state, switch SW4 is also in the off state.

[0270] The function of voltage adjustment circuit 1233a to adjust the voltage at node N1 while signal Sig1 is at an H level will be described. During this period, switches SW2 and SW4 are on, and switch SW3 is off. In other words, latch input circuit 1231 and voltage adjustment circuit 1233a are on, and inverter circuit 12322 is off.

[0271] When latch input circuit 1231 supplies an H-level voltage to node N1, the voltage at node N1 may rise. When this voltage exceeds threshold Vth6, voltage adjustment circuit 1233a supplies an L-level voltage to node N1, corresponding to the voltage exceeding threshold Vth6. As a result, the voltage at node N1 stabilizes at an H level. This H-level voltage is lower than when no voltage is supplied by voltage adjustment circuit 1233a, but the voltage at node N1 is stabilized by the H-level voltage supplied from latch input circuit 1231. This is because, when the voltage at node N1 stabilizes at an H level, the resistance R6L of the path from the source of the L-level voltage supplied by voltage adjustment circuit 1233a to node N1 is greater than the resistance R2H of the path from the source of the H-level voltage supplied by latch input circuit 1231 to node N1. For example, when the voltage at node N1 stabilizes at an H level, (the magnitude of resistance R6L) / (the magnitude of resistance R2H) is within the range of 5 / 3 to 3.

[0272] When latch input circuit 1231 supplies an L-level voltage to node N1, the voltage at node N1 may drop. If this voltage is less than threshold Vth6, voltage adjustment circuit 1233a supplies an H-level voltage to node N1 in response to the voltage being less than threshold Vth6. As a result, the voltage at node N1 stabilizes at an L-level. This L-level voltage is higher than when the voltage adjustment circuit 1233a does not supply a voltage, but rather stabilizes the voltage at node N1 based on the L-level voltage supplied from latch input circuit 1231. This is because, when the voltage at node N1 stabilizes at an L-level, the resistance R6H of the path from the source of the H-level voltage supplied by voltage adjustment circuit 1233a to node N1 is greater than the resistance R2L of the path from the source of the L-level voltage supplied by latch input circuit 1231 to node N1. For example, when the voltage at node N1 stabilizes at an L-level, (the magnitude of resistance R6H) / (the magnitude of resistance R2L) is within a range of 5 / 3 to 3.

[0273] The following describes the period when signal Sig1 is at an L level. During this period, switches SW2 and SW4 are off, while switch SW3 is on. In other words, latch input circuit 1231 and voltage adjustment circuit 1233a are off, while inverter circuit 12322 is on. Therefore, even if the voltage at node N1 is stabilized at an H level or an L level, voltage adjustment circuit 1233a does not cause the voltage at node N1 to drop or rise as described above.

[0274] Figure 17 An example of the circuit configuration of the local latch circuit LC1a of the semiconductor memory device 1a according to the second embodiment is shown.

[0275] Figure 17 The latch input circuit 1231 and the positive feedback circuit 1232 shown in FIG. Figure 11 The circuit configuration of the voltage regulating circuit 1233a is described below. Figure 17 In the example shown in FIG. 1 , the voltage adjustment circuit 1233 a is implemented using a clock-synchronized CMOS inverter circuit.

[0276] The voltage adjustment circuit 1233 a includes, for example, p-channel MOS transistors Tr33 and Tr34 , and n-channel MOS transistors Tr35 and Tr36 .

[0277] A voltage VDD, for example, is applied to the first terminal of transistor Tr33. A second terminal of transistor Tr33 is connected to the first terminal of transistor Tr34, and the second terminal of transistor Tr34 is connected to node N1. A first terminal of transistor Tr35 is connected to node N1, and a second terminal of transistor Tr35 is connected to the first terminal of transistor Tr36. A voltage VSS, for example, is applied to the second terminal of transistor Tr36. The gates of transistors Tr33 and Tr36 are each connected to node N1. Signal Sig2 is input to the gate of transistor Tr34. Signal Sig1 is input to the gate of transistor Tr35.

[0278] While the signal Sig1 is at L level and the signal Sig2 is at H level, the transistors Tr34 and Tr35 are in the OFF state. Therefore, the voltage VDD applied to the first terminal of the transistor Tr33 and the voltage VSS applied to the second terminal of the transistor Tr36 are not supplied to the node N1.

[0279] While the signal Sig1 is at the H level and the signal Sig2 is at the L level, the transistors Tr34 and Tr35 are in the on state. During this period, the voltage regulating circuit 1233a supplies a voltage to the node N1 as follows.

[0280] When the voltage at node N1 is less than threshold Vth6, transistor Tr33 is turned on and transistor Tr36 is turned off. Therefore, when the voltage at node N1 is less than threshold Vth6, the voltage VDD applied to the first terminal of transistor Tr33 is supplied to node N1. On the other hand, when the voltage at node N1 is greater than threshold Vth6, transistor Tr33 is turned off and transistor Tr36 is turned on. Therefore, when the voltage at node N1 is greater than threshold Vth6, the voltage VSS applied to the second terminal of transistor Tr36 is supplied to node N1.

[0281] As reference Figure 16As described above, when the voltage at node N1 is stabilized at an H level by the latch input circuit 1231 supplying an H-level voltage to the node N1 and the voltage adjustment circuit 1233a supplying an L-level voltage to the node N1, the sum of the on-resistances of transistors Tr35 and Tr36 is greater than the sum of the on-resistances of transistors Tr11 and Tr12. To achieve this, for example, the dimensions of each of these transistors Tr, defined by (gate width of transistor Tr) / (gate length of transistor Tr), are set to have the following relationship: the size of transistor Tr35 is minimized, and the dimensions of transistors Tr11, Tr12, and Tr36 are substantially the same. To this end, for example, the gate lengths of each of these transistors Tr can be made substantially the same, and the gate widths of each of these transistors Tr can be set to have the following relationship: the gate width of transistor Tr35 is minimized, and the gate widths of transistors Tr11, Tr12, and Tr36 are substantially the same.

[0282] As reference Figure 16 As described above, when the voltage at node N1 is stabilized at an L level by the latch input circuit 1231 supplying an L level voltage to the node N1 and the voltage adjustment circuit 1233a supplying an H level voltage to the node N1, the sum of the on-resistances of transistors Tr33 and Tr34 is greater than the sum of the on-resistances of transistors Tr13 and Tr14. To achieve this, for example, the dimensions of the transistors Tr are set to the following relationship: the dimension of transistor Tr34 is minimized, and the dimensions of transistors Tr13, Tr14, and Tr33 are substantially the same. To this end, for example, the gate lengths of the transistors Tr can be made substantially the same, and the gate widths of the transistors Tr can be set to the following relationship: the gate width of transistor Tr34 is minimized, and the gate widths of transistors Tr13, Tr14, and Tr33 are substantially the same.

[0283] [Action Example]

[0284] Figure 18 An example of a timing chart showing time changes of various signals when the local latch circuit LC1a of the semiconductor memory device 1a according to the second embodiment latches a certain bit of data transmitted by the signal DQ<0> is shown.

[0285] Regarding the time variation of the signal Sig1, the signal Sig2, and the signal Din<0>, Figure 13In the description of , the content still holds even if time T00 is replaced by time T20, time T01 is replaced by time T21, time T02 is replaced by time T22, time T03 is replaced by time T23, time T04 is replaced by time T24, time T01d is replaced by time T21d, and time T02d is replaced by time T22d. The time from time T21d to time T22 is the same as the time ΔT from time T01d to time T02. In addition, whether the latch input circuit 1231 and the inverter circuit with release function 12322 are in the on state or the off state, Figure 13 Even if the time is replaced in the manner described in the description, the content still holds true.

[0286] Similar to latch input circuit 1231, voltage regulator circuit 1233a is in the off state while signal Sig1 is at an L level, and is in the on state while signal Sig1 is at an H level. Therefore, voltage regulator circuit 1233a is in the off state from time T20 to time T21 and from time T22 to time T23, and is in the on state from time T21 to time T22 and from time T23 to time T24.

[0287] The voltage at the node N1 will be described below.

[0288] From time T20 to time T21d, Figure 13 In the example of the comparative example, the voltage of the node N1 is H level from time T00 to time T01d. However, from time T20 to time T21, the voltage adjustment circuit 1233a is in the off state, so the H level voltage is different from that of the comparative example. Figure 15 As in the example, no voltage drop occurs. From the moment T21 when the voltage regulating circuit 1233a becomes conductive, the control of the voltage regulating circuit 1233a takes effect. As a result, the voltage of the node N1 is equal to Figure 13 Similarly to the example of , the voltage at the node N1 is stabilized at the H level after the voltage is dropped by the voltage difference ΔVH, and the voltage at the node N1 is stabilized at the H level until time T21d.

[0289] From time T21d to time T22, Figure 13 In the example of FIG. 1 , the voltage at the node N1 decreases from the H level from the time T01d to the time T02. During this period, the voltage regulating circuit 1233a is also in the on state.

[0290] At time T22, with Figure 13 Similarly, at time T02 in the example, the voltage value of the node N1 is lower than the threshold value Vth3. Figure 13 Similarly to the example, after the voltage value of the node N1 becomes lower than the threshold value Vth3, the voltage value of the node N2 quickly becomes higher than the threshold value Vth4. Therefore, from time T22 to time T23, Figure 13 In the example of FIG. 1 , from time T02 to time T03, an H-level voltage is supplied to the node N2, and an L-level voltage is supplied to the node N1. Figure 13 Similarly to the example of the comparative example, the voltage of the node N1 reaches and stabilizes at the L level, and the voltage of the node N2 stabilizes at the H level. However, during this period, the voltage regulating circuit 1233a is in the off state, so the L level voltage of the node N1 is different from that of the comparative example. Figure 15 In the same example, no voltage rise occurs.

[0291] In this way, with Figure 13 Similarly to the example of , the H level of the signal Din<0> immediately before the time T22 at which the signal Sig1 falls is reflected in the voltages of the nodes N1 and N2. Figure 12 As described above, at the timing when the signal DQS falls, a certain odd-numbered bit of data transmitted by the signal DQ<0> is latched by the local latch circuit LC1a.

[0292] From time T23 to time T24, Figure 13 In the example of FIG. 1 , from time T03 to time T04, a voltage of H level is supplied to node N1. As a result, the voltage of node N1 changes from L level to H level and stabilizes. During this period, the voltage adjustment circuit 1233a is in the on state. Therefore, the voltage of node N1 at H level is the same as Figure 13 Similarly to the example, the voltage adjustment circuit 1233a reduces the voltage by the voltage difference ΔVH.

[0293] [Effect]

[0294] According to the local latch circuit LC1a of the semiconductor memory device 1a of the second embodiment, in addition to the effects similar to those described in the first embodiment, the following effects can be achieved.

[0295] First, the power consumption of the local latch circuit LC1 of the semiconductor memory device 1 according to the first embodiment, which is caused by the voltage regulating circuit 1233, will be described. The description will be divided into periods when the signal Sig1 is at the H level and periods when the signal Sig1 is at the L level.

[0296] The following describes the period when signal Sig1 is at an H level. During this period, latch input circuit 1231 is in an on state and inverter circuit 12322 is in an off state. Sometimes, while latch input circuit 1231 supplies an H or L level voltage to node N1, voltage adjustment circuit 1233 also supplies a voltage at an opposite level to that of latch input circuit 1231. During this period, current flows from the source of the H level voltage to the source of the L level voltage. This current is generated to implement control of voltage adjustment circuit 1233, and the power generated by this current is consumed by local latch circuit LC1.

[0297] The following describes the period when signal Sig1 is at an L level. During this period, latch input circuit 1231 is off and inverter circuit 12322 is on. The above description of the period when signal Sig1 is at an H level still holds true even if latch input circuit 1231 is replaced by inverter circuit 12322.

[0298] The configuration of local latch circuit LC1a in semiconductor memory device 1a according to the second embodiment is obtained by replacing voltage regulator circuit 1233 with voltage regulator circuit 1233a in the configuration of local latch circuit LC1. Like latch input circuit 1231, voltage regulator circuit 1233a is OFF when signal Sig1 is at an L level and ON when signal Sig1 is at an H level. Therefore, the power consumption of local latch circuit LC1 in semiconductor memory device 1a according to the second embodiment, which is attributable to voltage regulator circuit 1233a, is as follows.

[0299] When signal Sig1 is at an H level, voltage regulation circuit 1233a is in an on-state, so local latch circuit LC1a consumes substantially the same amount of power as described for semiconductor memory device 1 according to the first embodiment. When signal Sig1 is at an L level, voltage regulation circuit 1233a is in an off-state, so no current flows. Consequently, the power consumption described for semiconductor memory device 1 according to the first embodiment is eliminated. Therefore, the local latch circuit LC1a of semiconductor memory device 1a according to the second embodiment can reduce power consumption.

[0300] [Example of Change]

[0301] The circuit configuration of the voltage regulating circuit 1233a is not limited to Figure 17 Another example of the circuit configuration of the voltage regulating circuit 1233a will be described below.

[0302] Figure 19Another example of the circuit configuration of the voltage adjustment circuit 1233a of the local latch circuit LC1a of the semiconductor memory device 1a according to the second embodiment is shown.

[0303] The voltage adjustment circuit 1233 a includes, for example, p-channel MOS transistors Tr301 , Tr302 , and Tr303 , and n-channel MOS transistors Tr304 , Tr305 , and Tr306 .

[0304] A voltage VDD, for example, is applied to the first terminal of transistor Tr301, and a second terminal of transistor Tr301 is connected to the first terminal of transistor Tr302. The second terminal of transistor Tr302 is connected to the first terminal of transistor Tr303, and the second terminal of transistor Tr303 is connected to node N1. The first terminal of transistor Tr304 is connected to node N1, and the second terminal of transistor Tr304 is connected to the first terminal of transistor Tr305. The second terminal of transistor Tr305 is connected to the first terminal of transistor Tr306, and a voltage VSS, for example, is applied to the second terminal of transistor Tr306. The gates of transistors Tr301 and Tr306 are each connected to node N1. Signal Sig2 is input to the gate of transistor Tr302, and signal Sig1 is input to the gate of transistor Tr305. Voltage VSS, for example, is applied to the gate of transistor Tr303, and voltage VDD, for example, is applied to the gate of transistor Tr304.

[0305] For example, a voltage VSS is applied to the gate of the transistor Tr303, so that the transistor Tr303 is in an on state. For example, a voltage VDD is applied to the gate of the transistor Tr304, so that the transistor Tr304 is in an on state.

[0306] Regarding the voltage supply to the node N1 by the voltage adjustment circuit 1233a based on the signals Sig1 and Sig2 and the voltage of the node N1, Figure 17 In the description, the content still holds true even if the transistor Tr33 is replaced by the transistor Tr301, the transistor Tr34 is replaced by the transistor Tr302, the transistor Tr35 is replaced by the transistor Tr305, and the transistor Tr36 is replaced by the transistor Tr306.

[0307] As reference Figure 16 As described above, when the voltage at the node N1 is stabilized at the H level by the latch input circuit 1231 supplying an H level voltage to the node N1 and the voltage adjustment circuit 1233a supplying an L level voltage to the node N1, the sum of the on-resistances of the transistors Tr304, Tr305, and Tr306 is greater than the sum of the on-resistances of the transistors Tr11 and Tr12. Figure 16As explained, when the latch input circuit 1231 supplies an L-level voltage to the node N1 and the voltage adjustment circuit 1233a supplies an H-level voltage to the node N1, and the voltage of the node N1 is stabilized at the L-level, the sum of the on-resistances of the transistors Tr301, Tr302 and Tr303 is greater than the sum of the on-resistances of the transistors Tr13 and Tr14.

[0308] Figure 19 In the example of FIG, in order to realize the input of the signal Sig2 to the gate of the transistor Tr302 and the connection between the second terminal of the transistor Tr303 and the first terminal of the transistor Tr304 and the node N1, contact plugs are used. Figure 17 In the example of FIG, contact plugs are used to input the signal Sig2 to the gate of the transistor Tr34 and to connect the second terminal of the transistor Tr34 and the first terminal of the transistor Tr35 to the node N1. Figure 19 In the example, the distance between the two contact plugs is greater than Figure 17 Therefore, Figure 19 The capacitive coupling between the contact plugs in the example is less than Figure 17 The capacitive coupling between the contact plugs in the example. Figure 19 In the example of FIG, the relationship between the contact plug for inputting the signal Sig1 to the gate of the transistor Tr305 and the contact plug for connecting the second terminal of the transistor Tr303 and the first terminal of the transistor Tr304 to the node N1 is the same. Figure 19 Examples Figure 17 In the example of FIG, the influence between the voltage of the node N1 and the signals Sig1 and Sig2 input to the voltage adjustment circuit 1233a is reduced. Figure 19 Examples Figure 17 For example, the local latch circuit LC1a of the semiconductor memory device 1a according to the second embodiment can operate with high accuracy.

[0309] In order to reduce the capacitive coupling between the contact plug connected to a certain node and the contact plug for inputting a signal such as a signal Sig1 or Sig2 to the gate of a certain transistor Tr, the contact plug connected to a certain node may be connected to the gate of the transistor Tr. Figure 19 The same circuit configuration as that shown is provided in other circuit configurations disclosed in this specification.

[0310] <Third embodiment>

[0311] Hereinafter, a semiconductor memory device 1b according to a third embodiment will be described.

[0312] [Example of configuration]

[0313] The configuration of the semiconductor storage device 1 b according to the third embodiment will be described focusing on differences from the configuration of the semiconductor storage device 1 according to the first embodiment.

[0314] The semiconductor memory device 1b of the third embodiment is obtained by replacing the local latch circuit LC1 with a local latch circuit LC1b in the semiconductor memory device 1 of the first embodiment. When describing certain components of the semiconductor memory device 1b of the third embodiment that include the local latch circuit LC1b, or certain components that may have the same components as the local latch circuit LC1b, the components will be described using the reference numeral b used in the first embodiment.

[0315] Figure 20 An example of the configuration of a local latch circuit LC1b of a semiconductor memory device 1b according to the third embodiment is shown.

[0316] Figure 20 The local latch circuit LC1b is constructed in Figure 10 In the configuration of the local latch circuit LC1 shown, the positive feedback circuit 1232 and the voltage adjustment circuit 1233 are replaced by a positive feedback circuit 1232b. The positive feedback circuit 1232b is obtained by replacing the inverter circuit 12321 in the positive feedback circuit 1232 with an inverter circuit 12321b. The configuration of the inverter circuit 12322 in the positive feedback circuit 1232b is similar to that of the reference circuit 12321. Figure 10 The descriptions given are consistent.

[0317] The inverter circuit 12321b includes, for example, an inverter INV7 and a switch SW5.

[0318] The input terminal of the inverter INV7 is connected to the node N1, and the output terminal of the inverter INV7 is connected to the node N2. The first terminal of the switch SW5 is connected to the node N2, and the second terminal of the switch SW5 is connected to the node N1.

[0319] The inverter circuit 12321b outputs a voltage based on the voltage of the node N1 in the following manner.

[0320] Inverter INV7, for example, Figure 10Similarly, inverter INV3 in the example supplies an L-level voltage to node N2 connected to the output terminal while the voltage value of node N1 connected to the input terminal is greater than or equal to threshold Vth7. When the voltage value of node N1 connected to the input terminal is less than threshold Vth7, an H-level voltage is supplied to node N2 connected to the output terminal. Switch SW5 transmits the voltage supplied to node N2 connected to the first terminal in this manner to node N1 connected to the second terminal while switch SW5 is in the on state. Switch SW5 is in the off state while signal Sig1 is at an L level and signal Sig2 is at an H level, and is in the on state while signal Sig1 is at an H level and signal Sig2 is at an L level. Therefore, while switch SW2 is in the on state, switch SW5 is also in the on state, and while switch SW2 is in the off state, switch SW5 is also in the off state.

[0321] Hereinafter, when the switch SW5 is in the on state and the inverter circuit 12321b can transmit the voltage output by the inverter circuit 12321b to the node N1, the inverter circuit 12321b is referred to as being in the adjusted on state. Otherwise, the inverter circuit 12321b is referred to as being in the adjusted off state.

[0322] The function of inverter circuit 12321b to adjust the voltage at node N1 during the period when signal Sig1 is at an H level will be described. During this period, switches SW2 and SW5 are on, and switch SW3 is off. In other words, latch input circuit 1231 is on, inverter circuit 12321b is in an adjusted on state, and inverter circuit 12322 is off.

[0323] When latch input circuit 1231 supplies an H-level voltage to node N1, the voltage at node N1 may rise. If this voltage is greater than threshold Vth7, inverter circuit 12321b supplies an L-level voltage to node N1 in response to this voltage being greater than threshold Vth7. As a result, the voltage at node N1 stabilizes at an H level. This H-level voltage is lower than when the voltage at node N1 is stabilized based on an H-level voltage supplied from latch input circuit 1231 without inverter circuit 12321b supplying a voltage. This is because, when the voltage at node N1 stabilizes at an H level, the resistance R7L of the path from the source of the L-level voltage supplied by inverter circuit 12321b to node N1 is greater than the resistance R2H of the path from the source of the H-level voltage supplied by latch input circuit 1231 to node N1. For example, when the voltage of the node N1 is stable at the H level, (the size of the resistor R7L) / (the size of the resistor R2H) is within the range of not less than 5 / 3 and not more than 3.

[0324] When latch input circuit 1231 supplies an L-level voltage to node N1, the voltage at node N1 may drop. If the value of this voltage is less than threshold value Vth7, inverter circuit 12321b supplies an H-level voltage to node N1 in response to the voltage being less than threshold value Vth7. As a result, the voltage at node N1 stabilizes at an L-level. This L-level voltage is higher than when the voltage at node N1 is stabilized by the L-level voltage supplied from latch input circuit 1231 without the voltage supplied by inverter circuit 12321b. This is because, when the voltage at node N1 stabilizes at an L-level, the resistance R7H of the path from the source of the H-level voltage supplied by inverter circuit 12321b to node N1 is greater than the resistance R2L of the path from the source of the L-level voltage supplied by latch input circuit 1231 to node N1. For example, when the voltage of the node N1 is stable at the L level, (the size of the resistor R7H) / (the size of the resistor R2L) is within the range of not less than 5 / 3 and not more than 3.

[0325] The following describes the period when signal Sig1 is at an L level. During this period, switches SW2 and SW5 are off, and switch SW3 is on. Specifically, latch input circuit 1231 is off, inverter circuit 12321b is in an adjusted off state, and inverter circuit 12322 is on. Therefore, even if the voltage at node N1 is stabilized at an H level or an L level, inverter circuit 12321b does not cause the voltage at node N1 to drop or rise as described above.

[0326] Figure 21 An example of the circuit configuration of the local latch circuit LC1b of the semiconductor memory device 1b according to the third embodiment is shown.

[0327] Figure 21 The latch input circuit 1231 and the inverter circuit 12322 with a release function are shown in FIG. Figure 11 The circuit configuration of the inverter circuit 12321b is described below.

[0328] The inverter circuit 12321b includes, for example, p-channel MOS transistors Tr213 and Tr214, and n-channel MOS transistors Tr215 and Tr216.

[0329] A voltage VDD, for example, is applied to the first terminal of transistor Tr213, and a second terminal of transistor Tr213 is connected to node N2. A first terminal of transistor Tr214 is connected to node N2, and a second terminal of transistor Tr214 is connected to node N1. A first terminal of transistor Tr215 is connected to node N1, and a second terminal of transistor Tr215 is connected to node N2. A first terminal of transistor Tr216 is connected to node N2, and a voltage VSS, for example, is applied to the second terminal of transistor Tr216. The gates of transistors Tr213 and Tr216 are each connected to node N1. A signal Sig2 is input to the gate of transistor Tr214. A signal Sig1 is input to the gate of transistor Tr215.

[0330] While the signal Sig1 is at L level and the signal Sig2 is at H level, the transistors Tr214 and Tr215 are in the OFF state. Therefore, the voltage VDD applied to the first terminal of the transistor Tr213 and the voltage VSS applied to the second terminal of the transistor Tr216 are not supplied to the node N1.

[0331] While the signal Sig1 is at the H level and the signal Sig2 is at the L level, the transistors Tr214 and Tr215 are in the on state. During this period, the inverter circuit 12321b supplies a voltage to the node N1 as follows.

[0332] When the voltage at node N1 is less than threshold Vth7, transistor Tr213 is turned on and transistor Tr216 is turned off. Therefore, when the voltage at node N1 is less than threshold Vth7, the voltage VDD applied to the first terminal of transistor Tr213 is supplied to node N1. On the other hand, when the voltage at node N1 is greater than threshold Vth7, transistor Tr213 is turned off and transistor Tr216 is turned on. Therefore, when the voltage at node N1 is greater than threshold Vth7, the voltage VSS applied to the second terminal of transistor Tr216 is supplied to node N1.

[0333] For example, Figure 21 The p-channel MOS transistor Tr11 and the n-channel MOS transistor Tr14 are shown as Figure 20 The inverter INV2 shown in FIG. 1 is functional. Figure 21 The p-channel MOS transistor Tr12 and the n-channel MOS transistor Tr13 are shown as Figure 20Similarly, for example, p-channel MOS transistor Tr213 and n-channel MOS transistor Tr216 function as inverter INV7, p-channel MOS transistor Tr214 and n-channel MOS transistor Tr215 function as switch SW5, p-channel MOS transistor Tr221 and n-channel MOS transistor Tr224 function as inverter INV4, and p-channel MOS transistor Tr222 and n-channel MOS transistor Tr223 function as switch SW3.

[0334] As reference Figure 20 As described above, when the voltage at node N1 is stabilized at an H level by latch input circuit 1231 supplying an H-level voltage to node N1 and inverter circuit 12321b supplying an L-level voltage to node N1, the sum of the on-resistances of transistors Tr215 and Tr216 is greater than the sum of the on-resistances of transistors Tr11 and Tr12. To achieve this, for example, the dimensions of the transistors Tr are set to the following relationship: the dimension of transistor Tr215 is minimized, and the dimensions of transistors Tr11, Tr12, and Tr216 are substantially the same. To this end, for example, the gate lengths of the transistors Tr can be made substantially the same, and the gate widths of the transistors Tr can be set to the following relationship: the gate width of transistor Tr215 is minimized, and the gate widths of transistors Tr11, Tr12, and Tr216 are substantially the same.

[0335] As reference Figure 20 As described above, when the voltage at node N1 is stabilized at an L level by latch input circuit 1231 supplying an L-level voltage to node N1 and inverter circuit 12321b supplying an H-level voltage to node N1, the sum of the on-resistances of transistors Tr213 and Tr214 is greater than the sum of the on-resistances of transistors Tr13 and Tr14. To achieve this, for example, the dimensions of the transistors Tr are set to the following relationship: the dimension of transistor Tr214 is minimized, and the dimensions of transistors Tr13, Tr14, and Tr213 are substantially the same. To this end, for example, the gate lengths of the transistors Tr can be made substantially the same, and the gate widths of the transistors Tr can be set to the following relationship: the gate width of transistor Tr214 is minimized, and the gate widths of transistors Tr13, Tr14, and Tr213 are substantially the same.

[0336] The inverter circuit 12321b described in detail above can realize the same function as the voltage regulating circuit 1233a of the second embodiment, but the configuration of the inverter circuit 12321b of the local latch circuit LC1b of the semiconductor memory device 1b of this embodiment is not limited thereto. For example, the inverter circuit 12321b can be configured to realize the same function as the voltage regulating circuit 1233 of the first embodiment. Figure 21 Taking the circuit configuration shown as an example, for example, transistors Tr214 and Tr215 can be omitted from the circuit configuration and the sizes of transistors Tr213 and Tr216 can be adjusted. Alternatively, a voltage can be applied to the gates of transistors Tr214 and Tr215 to keep transistors Tr214 and Tr215 always on.

[0337] [Action Example]

[0338] The semiconductor memory device 1b of the third embodiment performs the same operations as those described for the semiconductor memory device 1a of the second embodiment. Figure 18 More specifically, in Figure 18 In the description of the example, the content still holds true even after the local latch circuit LC1a is replaced by the local latch circuit LC1b, the inverter circuit 12321 and the voltage adjustment circuit 1233a are replaced by the inverter circuit 12321b, the threshold Vth3 is replaced by the threshold Vth7, and the on state and the off state of the voltage adjustment circuit 1233a are respectively replaced by the adjusted on state and the adjusted off state of the inverter circuit 12321b.

[0339] [Effect]

[0340] According to the local latch circuit LC1b of the semiconductor memory device 1b of the third embodiment, in addition to the effects similar to those described in the first and second embodiments, the effects described below can also be achieved.

[0341] Inverter circuit 12321b of local latch circuit LC1b implements the functions of inverter circuit 12321 and voltage regulator circuit 1233a of local latch circuit LC1a using fewer transistors Tr than the number of transistors Tr used in inverter circuit 12321 and voltage regulator circuit 1233a. Therefore, local latch circuit LC1b can achieve the following effects. Specifically, the circuit area of ​​local latch circuit LC1b of semiconductor memory device 1b according to the third embodiment can be smaller than that of local latch circuit LC1a of semiconductor memory device 1a according to the second embodiment. Furthermore, local latch circuit LC1b of semiconductor memory device 1b according to the third embodiment can further reduce power consumption compared to local latch circuit LC1a of semiconductor memory device 1a according to the second embodiment.

[0342] <Fourth embodiment>

[0343] Hereinafter, a semiconductor memory device 1bh according to a fourth embodiment will be described.

[0344] [Example of configuration]

[0345] The configuration of the semiconductor storage device 1bh according to the fourth embodiment will be described focusing on differences from the configuration of the semiconductor storage device 1b according to the third embodiment.

[0346] The semiconductor memory device 1bh of the fourth embodiment is obtained by replacing the input / output circuit 12b with an input / output circuit 12bh in the semiconductor memory device 1b of the third embodiment. When describing certain components of the semiconductor memory device 1bh of the fourth embodiment including the input / output circuit 12bh, the components are described using the reference numerals h used in the third embodiment.

[0347] Figure 22 This is a block diagram showing an example of the configuration of an input / output circuit 12bh of a semiconductor memory device 1bh according to the fourth embodiment. Figure 22 Reference numerals 12bi, 12bj, 12bk, 126i, 126j, and 126k will be described in subsequent embodiments.

[0348] In addition to the components of the input / output circuit 12b of the semiconductor memory device 1b according to the third embodiment, the input / output circuit 12bh further includes a signal shaping circuit 126h. The signal shaping circuit 126h may be provided within the input circuit 122 or elsewhere in the semiconductor memory device 1bh, such as within the sequencer 15. The same applies to the other embodiments.

[0349] The input circuit 122 outputs the signal Sig1 and the signal Sig2 to the signal shaping circuit 126h, for example.

[0350] Signal shaping circuit 126h receives signals Sig1 and Sig2 from input circuit 122, generates signals Sigαh and Sigβh based on signals Sig1 and Sig2, and outputs these signals Sigαh and Sigβh to latch circuit 123b <0>. Signal shaping circuit 126h may also output signals Sigαh and Sigβh to other latch circuits in latch circuit 123b <7:1>. Signal Sigαh is shaped so that signal Sig1 is at an L level for a portion of the time that signal Sig1 is at an H level. Signal Sigβh is the complement of signal Sigαh. The same applies to signals Sigα and Sigβ in other embodiments.

[0351] Latch circuit 123b<0> receives signals Sigαh and Sigβh from signal shaping circuit 126h. Local latch circuit LC1b of latch circuit 123b<0> also sequentially latches the odd-numbered bits of signal DQ<0> based on signals Sigαh and Sigβh, for example. This also applies to other embodiments described below in which signals Sigα and Sigβ are output to latch circuit 123b<0>.

[0352] Figure 23 An example circuit configuration of a signal shaping circuit 126h in a semiconductor memory device 1bh according to a fourth embodiment is shown. The circuit configuration of the signal shaping circuit 126h shown below is merely an example. Other circuit configurations capable of similarly generating signals Sigαh and Sigβh can also be applied to the circuit configuration of the signal shaping circuit 126h. This also applies to the same figures in the following embodiments.

[0353] The signal shaping circuit 126h includes, for example, a delay circuit DC1, an AND gate AND1, a delay circuit DC2, and an OR gate OR1.

[0354] The signals Sig1 and Sig2 are processed as follows within the signal shaping circuit 126h: Operations such as AND operations described below are performed under the conditions that the H level is set to 1 and the L level is set to 0.

[0355] Delay circuit DC1 receives signal Sig1, generates signal SigD1 based on signal Sig1, and outputs signal SigD1. Signal SigD1 is a delayed signal Sig1. For example, the phase of signal SigD1 is delayed by π / 2 radians compared to the phase of signal Sig1. Signal SigD1 rises after signal Sig1 and remains at an H level along with signal Sig1 until signal Sig1 falls, and then falls after signal Sig1.

[0356] AND gate AND1 receives signal Sig1 at its first input terminal and receives signal SigD1 at its second input terminal. AND gate AND1 performs AND operation on the two received signals and outputs a signal as the result of the operation. The output signal is equivalent to Figure 22 The signal Sigαh shown in FIG. The signal Sigαh rises later than the signal Sig1 and remains at the H level together with the signal Sig1 until the signal Sig1 falls, and falls substantially simultaneously with the signal Sig1.

[0357] Delay circuit DC2 receives signal Sig2, generates signal SigD2 based on signal Sig2, and outputs signal SigD2. Signal SigD2 is a delayed signal Sig2. The delay amount of delay circuit DC2 is substantially the same as that of delay circuit DC1. Signal SigD2 falls after signal Sig2 and remains at an L level along with signal Sig2 until signal Sig2 rises, and then rises after signal Sig2.

[0358] The OR gate OR1 receives the signal Sig2 at the first input terminal and receives the signal SigD2 at the second input terminal. The OR gate OR2 performs an OR operation on the two received signals and outputs a signal as the result of the operation. The output signal is equivalent to Figure 22 The signal Sigβh shown in FIG. The signal Sigβh falls later than the signal Sig2 and then remains at the L level together with the signal Sig2 until the signal Sig2 rises, and rises substantially simultaneously with the signal Sig2.

[0359] The circuit configuration of signal shaping circuit 126h, which generates signals Sigαh and Sigβh to be used by local latch circuit LC1b, has been described above. A case will now be described in which the same circuit configuration is applied to a signal shaping circuit that generates the same two signals used by local latch circuit LC0b. In this case, the circuit configuration of this signal shaping circuit can be one that shapes signal Sig2 in the same manner as signal Sig1, and shapes signal Sig1 in the same manner as signal Sig2. Unless otherwise specified, the same applies to signal shaping circuits 126 generating signals Sigα and Sigβ in other embodiments.

[0360] Figure 24 An example of the structure of the local latch circuit LC1b of the semiconductor memory device 1bh according to the fourth embodiment is shown. The structure of the local latch circuit LC1b is similar to that of the semiconductor memory device 1bh except for the following aspects. Figure 20 Same as the example.

[0361] The switch SW5 is in an off state while the signal Sigαh is at the L level and the signal Sigβh is at the H level, and is in an on state while the signal Sigαh is at the H level and the signal Sigβh is at the L level.

[0362] The configuration of the local latch circuit LC1b has been described above. The following describes a case where the same configuration is applied to the local latch circuit LC0b. In this case, in the configuration of the local latch circuit LC1b, for example, the signal Sigαh is replaced by the signal Sigαh as shown in FIG. Figure 23 After shaping the signal Sig2 as described above, the signal Sigβh is replaced by the signal Sigβh as shown in the reference Figure 23 Although the signal Sig1 is shaped as described above, the configuration of the local latch circuit LC0b can still be applied. The same is true for the local latch circuit LC1b using the signals Sigα and Sigβ in other embodiments.

[0363] Figure 25 An example of the circuit configuration of the local latch circuit LC1b of the semiconductor memory device 1bh according to the fourth embodiment is shown. The circuit configuration of the local latch circuit LC1b is similar to that of the semiconductor memory device 1bh except for the following aspects. Figure 21 Same as the example.

[0364] The gate of the transistor Tr214 receives the signal Sigβh instead of the signal Sig2, and the gate of the transistor Tr215 receives the signal Sigαh instead of the signal Sig1.

[0365] While the signal Sigαh is at L level and the signal Sigβh is at H level, transistors Tr214 and Tr215 are off. Therefore, neither the voltage VDD applied to the first terminal of the transistor Tr213 nor the voltage VSS applied to the second terminal of the transistor Tr216 is supplied to the node N1.

[0366] During the period when the signal Sigαh is at the H level and the signal Sigβh is at the L level, the transistors Tr214 and Tr215 are in the on state. Figure 21 Similarly to the example of , a voltage is supplied to the node N1.

[0367] The circuit configuration of the local latch circuit LC1b has been described above. The following describes a case where the same circuit configuration is applied to the local latch circuit LC0b. In this case, in the circuit configuration of the local latch circuit LC1b, for example, the gate to which the signal Sigαh is input is input as shown in FIG. Figure 23 The signal Sig2 is formed as described above, and the gate to which the signal Sigβh is input is input as described above. Figure 23 Although the signal Sig1 is shaped as described above, the circuit configuration of the local latch circuit LC0b can be applied. The same is true for the local latch circuit LC1b using the signals Sigα and Sigβ in other embodiments.

[0368] While the above description describes a case where the local latch circuit LC1b, having the same configuration as that described in the third embodiment, is configured to operate based on the signals Sigαh and Sigβh generated by the signal shaping circuit 126h, this embodiment is not limited thereto. For example, a local latch circuit having the same configuration as that described in the second embodiment may also be configured to operate based on the signals Sigαh and Sigβh generated by the signal shaping circuit 126h. This also applies to another embodiment described below, in which the local latch circuit LC1b is configured to operate based on the signals Sigα and Sigβ.

[0369] [Action Example]

[0370] Figure 26 An example of a timing chart showing time changes of various signals when the local latch circuit LC1b of the semiconductor memory device 1bh according to the fourth embodiment latches a certain bit of data transmitted by the signal DQ<0> is shown.

[0371] Regarding the time variation of the signal Sig1, the signal Sig2, and the signal Din<0>, Figure 13 In the description of , the content is still valid even if time T00 is replaced by time T40, time T01 is replaced by time T41, time T02 is replaced by time T42, time T03 is replaced by time T43, time T04 is replaced by time T44, time T01d is replaced by time T41d, and time T02d is replaced by time T42d. The time from time T41d to time T42 is the same as the time ΔT from time T01d to time T02. In addition, whether the latch input circuit 1231 and the inverter circuit with release function 12322 are in the on state or the off state, Figure 13 Even if the time is replaced in the manner described in the description, the content still holds true.

[0372] First, the signal Sigαh and the signal Sigβh will be described.

[0373] At time T40, signal Sigαh is at an L level, and signal Sigβh is at an H level. These levels of signals Sigαh and Sigβh remain unchanged until time T41s. Time T41s is after time T41 and before time T41d. At time T41s, signal Sigαh rises from an L level to an H level, and signal Sigβh falls from an H level to an L level. These levels of signals Sigαh and Sigβh remain unchanged until time T42. At time T42, signal Sigαh falls from an H level to an L level, and signal Sigβh rises from an L level to an H level. These levels of signals Sigαh and Sigβh remain unchanged until time T43s. Time T43s is after time T43 and before time T44. At time T43s, signal Sigαh rises from an L level to an H level, and signal Sigβh falls from an H level to an L level. The levels of the signals Sigαh and Sigβh are maintained until time T44.

[0374] Inverter circuit 12321b is in an adjusted OFF state when signal Sigαh is at an L level, and in an adjusted ON state when signal Sigαh is at an H level. Therefore, the periods during which inverter circuit 12321b is in an adjusted ON state and an adjusted OFF state are as follows. During the period from time T41 to time T42, when latch input circuit 1231 is in an ON state, inverter circuit 12321b is in an adjusted ON state from time T41s to time T42. During the period from time T43 to time T44, when latch input circuit 1231 is in an ON state, inverter circuit 12321b is in an adjusted ON state from time T43s to time T44. Except for these periods, inverter circuit 12321b is in an adjusted OFF state.

[0375] Next, the voltage of the node N1 will be described.

[0376] From time T40 to time T41d, Figure 13 In the example of FIG. 1 , the voltage of the node N1 is at the H level from time T00 to time T01d. However, from time T40 to time T41s, the inverter circuit 12321b is in the adjustment off state, so the H level voltage is different from that of the comparative example. Figure 15 Similarly to the example, no voltage drop occurs. From time T41s to time 41d, the inverter circuit 12321b is in the adjusted on state. From time T41s when the inverter circuit 12321b becomes in the adjusted on state, the control of the inverter circuit 12321b takes effect. As a result, the voltage of the node N1 is, for example, Figure 13 Similarly to the example of , the voltage of the node N1 is stabilized at the H level after the voltage is dropped by the voltage difference ΔVH, and the voltage of the node N1 is stabilized at the H level until time T41d.

[0377] From time T41d to time T42, Figure 13 In the example of FIG. 1 , the voltage of the node N1 decreases from the H level from the time T01d to the time T02. During this period, the inverter circuit 12321b is also in the adjusted conductive state.

[0378] At time T42, with Figure 13 Similarly, at time T02 in the example, the voltage value of the node N1 is lower than the threshold value Vth7. Figure 13 Similarly to the example, after the voltage value of the node N1 becomes less than the threshold value Vth7, the voltage value of the node N2 quickly becomes greater than the threshold value Vth4. Therefore, from time T42 to time T43, Figure 13 In the example of FIG. 1 , from time T02 to time T03, the inverter circuit 12321b supplies an H-level voltage to the node N2, and an L-level voltage is supplied to the node N1. Figure 13 Similarly to the example of the comparative example, the voltage of the node N1 reaches and stabilizes at the L level, and the voltage of the node N2 stabilizes at the H level. However, during this period, the inverter circuit 12321b is in the adjustment off state, so the L level voltage of the node N1 is different from that of the comparative example. Figure 15 In the same example, no voltage rise occurs.

[0379] In this way, with Figure 13 Similarly to the example of , the H level of the signal Din<0> immediately before the time T42 when the signal Sig1 falls is reflected in the voltages of the nodes N1 and N2. Figure 12 As described above, at the timing when the signal DQS falls, a certain odd-numbered bit of data transmitted by the signal DQ<0> is latched by the local latch circuit LC1b.

[0380] From time T43 to time T44, Figure 13 Similarly, in the example of the comparative example, from time T03 to time T04, an H-level voltage is supplied to the node N1. As a result, the voltage of the node N1 changes from the L-level to the H-level and stabilizes. From time T43 to time T43s, the inverter circuit 12321b is in the adjustment-off state. Therefore, when the voltage of the node N1 reaches the H-level during this period, the H-level voltage is the same as that of the comparative example. Figure 15 Similarly to the example, no voltage drop occurs. From time T43s to time T44, the inverter circuit 12321b is in the adjusted on state. From time T43s when the inverter circuit 12321b becomes in the adjusted on state, the control of the inverter circuit 12321b takes effect. As a result, the voltage of the node N1 is equal to Figure 13 Similarly to the example of , the voltage of the node N1 is stabilized at the H level after being dropped by the voltage difference ΔVH, and the voltage of the node N1 is stabilized at the H level until time T44.

[0381] [Effect]

[0382] According to the local latch circuit LC1b of the semiconductor memory device 1bh of the fourth embodiment, in addition to the effects similar to those described in the first to third embodiments, the following effects can be achieved.

[0383] Inverter circuit 12321b of local latch circuit LC1b of semiconductor memory device 1bh according to the fourth embodiment is adjusted to an OFF state while signal Sigαh is at an L level, and is adjusted to an ON state while signal Sigαh is at an H level. Signal Sigαh rises later than signal Sig1, remains at an H level along with signal Sig1 until signal Sig1 falls, and falls substantially simultaneously with signal Sig1.

[0384] Therefore, the inverter circuit 12321b of the local latch circuit LC1b of the semiconductor memory device 1bh of the fourth embodiment becomes adjusted to the on state later than the rise of the signal Sig1, and becomes adjusted to the off state substantially simultaneously with the fall of the signal Sig1. Even if the inverter circuit 12321b becomes adjusted to the on state later than the latch input circuit 1231 becomes on, the local latch circuit LC1b can still accurately latch the odd-numbered bits of the signal Din<0> as described in the first embodiment. This is because, for example, when the time from the level change of the signal Din<0> to the fall of the signal Sig1 is as short as the time ΔT, as in the case where Figure 26 As shown in the example, at the timing when the level of the signal Din<0> changes, the inverter circuit 12321b is already in the adjusted on state, so the H-level voltage of the node N1 drops or the L-level voltage of the node N1 rises.

[0385] As described above, the period during which the inverter circuit 12321b of the local latch circuit LC1b of the semiconductor memory device 1bh of the fourth embodiment is adjusted to its on-state is shortened compared to the period during which the inverter circuit 12321b is adjusted to its on-state in the third embodiment. While the inverter circuit 12321b is adjusted to its on-state, power may be consumed by the local latch circuit LC1b, as described in the second embodiment. Therefore, the local latch circuit LC1b of the semiconductor memory device 1bh of the fourth embodiment can further reduce power consumption compared to the third embodiment.

[0386] <Fifth embodiment>

[0387] Hereinafter, a semiconductor memory device 1bi according to a fifth embodiment will be described.

[0388] [Example of configuration]

[0389] The configuration of the semiconductor storage device 1bi according to the fifth embodiment will be described focusing on differences from the configuration of the semiconductor storage device 1b according to the third embodiment.

[0390] The semiconductor memory device 1bi of the fifth embodiment is obtained by replacing the input / output circuit 12b with an input / output circuit 12bi in the semiconductor memory device 1b of the third embodiment. When describing certain components of the semiconductor memory device 1bi of the fifth embodiment including the input / output circuit 12bi, the components are described using the reference numerals i used in the third embodiment.

[0391] like Figure 22 As described above, the input / output circuit 12bi includes a signal shaping circuit 126i in addition to the configuration of the input / output circuit 12b of the semiconductor memory device 1b according to the third embodiment. Figure 22 , only the differences from those already described are described.

[0392] The input circuit 122 outputs the signal Sig1 to the signal shaping circuit 126i, for example.

[0393] The signal shaping circuit 126 i receives the signal Sig1 from the input circuit 122 , for example, generates a signal Sigαi and a signal Sigβi based on the signal Sig1 , and outputs the signal Sigαi and the signal Sigβi to the latch circuit 123 b <0>.

[0394] Regarding the configuration of the local latch circuit LC1b of the semiconductor memory device 1bi according to the fifth embodiment, Figure 24 and Figure 25 In the description of , the contents still hold true even after the signal Sigαh is replaced by the signal Sigαi and the signal Sigβh is replaced by the signal Sigβi.

[0395] Figure 27 An example of the circuit configuration of the signal shaping circuit 126i of the semiconductor memory device 1bi according to the fifth embodiment is shown.

[0396] The signal shaping circuit 126i includes, for example, a delay circuit DC3, an AND gate AND2, an XNOR gate XNOR1, an AND gate AND3, and an inverter INV8.

[0397] Signal shaping circuit 126i further receives signal SigN2 from latch circuit 123b<0> and generates signals Sigαi and Sigβi based on signal SigN2. Signal SigN2 is transmitted to node N2 and represents the voltage at node N2. Signals Sig1 and SigN2 are processed within signal shaping circuit 126i as follows.

[0398] Delay circuit DC3 receives signal SigN2, generates signal SigDN2 based on signal SigN2, and outputs signal SigDN2. Signal SigDN2 is a delayed signal SigN2. For example, signal SigDN2 rises later than signal SigN2, remains at an H level along with signal SigN2 until signal SigN2 falls, and then falls later than signal SigN2.

[0399] AND gate AND2 receives signal SigN2 at its first input terminal and signal SigDN2 at its second input terminal. AND gate AND2 performs an AND operation on these two signals and outputs signal SigNN2 as the result of the operation. Signal SigNN2, for example, rises later than signal SigN2 and remains at an H level along with signal SigN2 until signal SigN2 falls, and falls substantially simultaneously with signal SigN2.

[0400] Exclusive-NOR gate XNOR1 receives signal SigN2 at its first input terminal and signal SigNN2 at its second input terminal. Exclusive-NOR gate XNOR1 performs an exclusive-NOR operation on the two received signals and outputs a signal SigTDi as the result of the operation. Signal SigTDi is at an L level from the moment signal SigN2 rises until the delayed rise of signal SigNN2, and is at an H level otherwise.

[0401] AND gate AND3 receives signal Sig1 at its first input terminal and receives signal SigTDi at its second input terminal. AND gate AND3 performs AND operation on the two received signals and outputs a signal as the result of the operation. The output signal is equivalent to Figure 22 The signal Sigαi is shown as follows. The signal Sigαi is at the same level as the signal Sig1 while the signal SigTDi is at the H level, but is at the L level while the signal SigTDi is at the L level.

[0402] The inverter INV8 receives the signal Sigαi at its input terminal and outputs a signal obtained by inverting the voltage level of the signal Sigαi. The output signal is equivalent to Figure 22 The signal Sigβi is shown.

[0403] [Action Example]

[0404] Figure 28An example of a timing diagram is shown, illustrating the temporal changes of various signals when a local latch circuit LC1b of a semiconductor memory device 1bi according to the fifth embodiment latches a certain bit of data transmitted by a signal DQ<0>. In this timing diagram, the temporal changes of the signals Sig2 and Sigβi are omitted. This is because the signals Sig2 and Sigβi are merely complementary signals of the signals Sig1 and Sigαi, respectively, which exhibit temporal changes.

[0405] Regarding the time variation of the signal Sig1 and the signal Din<0>, Figure 13 In the description of , the contents are still valid even if time T00 is replaced by time T50, time T01 is replaced by time T51, time T02 is replaced by time T52, time T03 is replaced by time T53, time T04 is replaced by time T54, time T01d is replaced by time T51d, and time T02d is replaced by time T52d. The time ΔTb from time T51d to time T52 is longer than the time ΔT from time T01d to time T02. In addition, whether the latch input circuit 1231 and the inverter circuit with release function 12322 are in the on state or the off state, Figure 13 In the description of , the content still holds even after the time is replaced in the above manner. Figure 28 In FIG. 1 , the temporal change of the signal SigN2 only indicates whether the voltage of the node N2 is at an L level or an H level, or whether the voltage changes from one level to another. The same applies to the following similar figures.

[0406] The inverter circuit 12321b is adjusted to an off state while the signal Sigαi is at an L level, and is adjusted to an on state while the signal Sigαi is at an H level.

[0407] From time T50 to time T51d, Figure 13 In the example shown in FIG. 1 , the voltage at node N1 remains at an H level from time T00 to time T01d. During this period, inverter circuit 12321b supplies an L level voltage to node N2 in response to the voltage at node N1 being equal to or greater than threshold value Vth7. Consequently, the voltage at node N2 remains stable at an L level. The H level voltage at node N1 during this period will be described below.

[0408] Since the voltage at node N2 is stable at the L level, signal SigTDi is at the H level. Therefore, similar to signal Sig1, signal Sigαi is at the L level from time T50 to time T51, rises from the L level to the H level at time T51, and remains at the H level from time T51 to time T51d. Inverter circuit 12321b is in an adjusted OFF state from time T50 to time T51 when signal Sigαi is at the L level, and is in an adjusted ON state from time T51 to time T51d when signal Sigαi is at the H level.

[0409] From time T50 to time T51, the inverter circuit 12321b is in the adjustment off state, so the H level voltage of the node N1 is the same as that of the comparative example. Figure 15 As in the example of , no voltage drop occurs. From the moment T51 when the inverter circuit 12321b becomes the adjusted conductive state, the control of the inverter circuit 12321b takes effect. As a result, the voltage of the node N1 is, for example, Figure 13 Similarly to the example of , the voltage at the node N1 is stabilized at the H level after being dropped by the voltage difference ΔVH, and the voltage at the node N1 is stabilized at the H level until time T51d.

[0410] From time T51d to time T52, Figure 13 In the example shown in FIG. 1 , from time T01d to time T02, an L-level voltage, for example, voltage VSS, is supplied to node N1. Consequently, the voltage at node N1 decreases from an H-level. After the voltage value at node N1 decreases below threshold value Vth7 during this period, inverter circuit 12321b supplies an H-level voltage to node N2 in response to the voltage value at node N1 decreasing below threshold value Vth7. Consequently, the voltage at node N2 increases from an L-level. Consequently, for example, the voltage at node N1 reaches an L-level, and the voltage at node N2 reaches an H-level. The voltages at nodes N1 and N2 remain at these levels until time T52. The L-level voltage at node N1 during this period will be described.

[0411] In response to the voltage at node N2 rising from L to H, signal SigTDi falls from H to L at time T51s. Time T51s is after time T51d and before time T52. Later than the voltage at node N2 rises, signal SigNN2 rises from L to H. In response to the rise of signal SigNN2, signal SigTDi rises from L to H at time T52s. The time from time T51s to time T52s depends on the delay amount of delay circuit DC3. Time T52s is, for example, after time T52 and before time T52d. Therefore, signal Sigαi is at H, the same level as signal Sig1, from time T51d to time T51s, falls from H to L at time T51s, and remains L from time T51s to time T52. The inverter circuit 12321b is adjusted to an on state from time T51d to time T51s when the signal Sigαi is at an H level, and is adjusted to an off state from time T51s to time T52 when the signal Sigαi is at an L level.

[0412] From time T51d to time T51s, inverter circuit 12321b is in its regulated on state. Therefore, the voltage at node N1, for example, stabilizes at an L level after rising by a voltage difference ΔVL before time T51s. From time T51s, when inverter circuit 12321b is in its regulated off state, control by inverter circuit 12321b ceases to function. As a result, the voltage at node N1 decreases by the increased voltage difference ΔVL and stabilizes at the L level after this voltage decrease. The voltage at node N1 remains stable at this L level until time T52.

[0413] From time T52 to time T53, Figure 13 Similarly, in the example of the comparative example, from time T02 to time T03, the inverter circuit 12321b supplies an H-level voltage to the node N2 and an L-level voltage to the node N1. As a result, the voltage of the node N1 is stabilized at an L-level, and the voltage of the node N2 is stabilized at an H-level. During this period, since the signal Sig1 is at an L-level, the signal Sigαi is also at an L-level. Therefore, the inverter circuit 12321b is in the adjusted off state. The inverter circuit 12321b is in the adjusted off state, so the L-level voltage of the node N1 is different from that of the comparative example. Figure 15 In the same example, no voltage rise occurs.

[0414] In this way, with Figure 13 Similarly to the example of , the H level of the signal Din<0> immediately before the time T52 when the signal Sig1 falls is reflected in the voltages of the nodes N1 and N2. Figure 12As described above, at the timing when the signal DQS falls, a certain odd-numbered bit of data transmitted by the signal DQ<0> is latched by the local latch circuit LC1b.

[0415] From time T53 to time T54, Figure 13 In the example shown in FIG. 1 , from time T03 to time T04, an H-level voltage is supplied to node N1. Consequently, the voltage at node N1 shifts from an L-level to and stabilizes at an H-level. After the voltage at node N1 becomes equal to or greater than threshold value Vth7 during this period, inverter circuit 12321b supplies an L-level voltage to node N2 in response to the voltage at node N1 becoming equal to or greater than threshold value Vth7. Consequently, the voltage at node N2 shifts from an H-level to and stabilizes at an L-level.

[0416] Although the voltage of the node N2 changes from H level to L level, the signal SigTDi still maintains H level. Therefore, from time T53 to time T54, the signal Sigαi is at H level, the same as the signal Sig1. Therefore, the inverter circuit 12321b is adjusted to the on state. The inverter circuit 12321b is adjusted to the on state, so the voltage of the node N1 at H level is the same as the Figure 13 In the same way as in the example above, the voltage drops by the voltage difference ΔVH.

[0417] [Effect]

[0418] According to the local latch circuit LC1b of the semiconductor memory device 1bi of the fifth embodiment, in addition to the effects similar to those described in the first to third embodiments, the following effects can be achieved.

[0419] Inverter circuit 12321b of local latch circuit LC1b of semiconductor memory device 1bi according to the fifth embodiment is adjusted to an OFF state while signal Sigαi is at an L level, and is adjusted to an ON state while signal Sigαi is at an H level. Signal Sigαi is at the same level as signal Sig1 while signal SigTDi is at an H level, but is at an L level while signal SigTDi is at an L level. Signal SigTDi is at an L level, for example, upon detecting a rising edge of signal SigN2, but is at an H level at other times.

[0420] For example, Figure 28 As an example, the following describes a case where the local latch circuit LC1b of the semiconductor storage device 1bi of the fifth embodiment causes the voltage of the node N1 to drop from the H level, for example, in response to the signal Din<0> rising from the L level to the H level while the signal Sig1 is at the H level.

[0421] The voltage of the node N2 is stabilized at the L level, for example, until the timing of the rise of the signal Din<0>. Therefore, the signal SigTDi is at the H level, so the signal Sigαi is at the same level as the signal Sig1. Therefore, from the time when the signal Sig1 becomes the H level to the time when the signal Din<0> rises, the inverter circuit 12321b is in the adjusted on state. Therefore, at the timing of the rise of the signal Din<0>, the H level voltage of the node N1 drops. This also applies to the time from the rise of the signal Din<0> to the fall of the signal Sig1 as shown in FIG. Figure 13 Therefore, as described in the first embodiment, the local latch circuit LC1b of the semiconductor memory device 1bi of the fifth embodiment can accurately latch a certain bit of data transmitted by the signal Din<0> at the timing of the falling edge of the signal Sig1.

[0422] In response to the rising edge of signal Din<0>, latch input circuit 1231 supplies an L-level voltage to node N1. Consequently, when the voltage value at node N1 falls below threshold Vth7, inverter circuit 12321b supplies an H-level voltage to node N2. Consequently, the voltage at node N2 rises from L to H. In response to the rising edge of the voltage at node N2, signal SigTDi falls from H to L. If signal SigTDi falls while signal Sig1 is H, signal Sigαi falls to L in response to the falling edge. Consequently, inverter circuit 12321b remains in the regulation-off state even while signal Sig1 is H. Since signal Din<0> has already risen while signal Sig1 is H, the level of signal Din<0> does not change further until signal Sig1 falls from H to L.

[0423] As described above, the period during which the inverter circuit 12321b of the local latch circuit LC1b of the semiconductor memory device 1bi according to the fifth embodiment is adjusted to the on-state is similar to that in the fourth embodiment, while the period during which the inverter circuit 12321b is adjusted to the on-state in the third embodiment can be shortened. Therefore, the local latch circuit LC1b of the semiconductor memory device 1bi according to the fifth embodiment can further reduce power consumption compared to the third embodiment.

[0424] <Sixth embodiment>

[0425] Hereinafter, a semiconductor memory device 1bj according to a sixth embodiment will be described.

[0426] [Example of configuration]

[0427] The configuration of the semiconductor storage device 1bj according to the sixth embodiment will be described focusing on differences from the configuration of the semiconductor storage device 1b according to the third embodiment.

[0428] The semiconductor memory device 1bj of the sixth embodiment is obtained by replacing the input / output circuit 12b with an input / output circuit 12bj in the semiconductor memory device 1b of the third embodiment. When describing certain components of the semiconductor memory device 1bj of the sixth embodiment including the input / output circuit 12bj, the components are described using the reference numerals j used in the third embodiment.

[0429] like Figure 22 As described above, the input / output circuit 12bj includes a signal shaping circuit 126j in addition to the configuration of the input / output circuit 12b of the semiconductor memory device 1b according to the third embodiment. Figure 22 , only the differences from those already described are described.

[0430] The input circuit 122 outputs the signal Sig1 to the signal shaping circuit 126j, for example.

[0431] The signal shaping circuit 126 j receives the signal Sig1 from the input circuit 122 , for example, generates a signal Sigαj and a signal Sigβj based on the signal Sig1 , and outputs the signal Sigαj and the signal Sigβj to the latch circuit 123 b <0>.

[0432] Figure 29 An example of the configuration of a local latch circuit LC1b of a semiconductor memory device 1bj according to the sixth embodiment is shown.

[0433] The local latch circuit LC1b includes Figure 24 In addition to the latch input circuit 1231 and the positive feedback circuit 1232b shown in FIG, a flip-flop circuit 1234 is also included. Figure 24 In the description of , the contents still hold true even after the signal Sigαh is replaced by the signal Sigαj and the signal Sigβh is replaced by the signal Sigβj.

[0434] The structure of the trigger circuit 1234 Figure 10 The latch input circuit 1231 and the positive feedback circuit 1232 shown in FIG. 1 are identical in configuration. In other words, the flip-flop circuit 1234 is configured as Figure 10 The local latch circuit LC1 shown in FIG. 1 is configured by removing the voltage adjustment circuit 1233. For example, Figure 8 The primary flip-flop circuit F / F among the multiple flip-flop circuits F / F included in the shift register SR1 shown can be used as Figure 29The trigger circuit 1234 in the circuit functions.

[0435] Figure 29 In the figure, the components of the trigger circuit 1234 that are the same as those of the latch input circuit 1231 are represented by the inverter INV9 and the switch SW6, the components that are the same as those of the inverter circuit 12321 are represented by the inverter INV10, and the components that are the same as those of the inverter circuit 12322 with a release function are represented by the inverter INV11 and the switch SW7.

[0436] Regarding the configuration of flip-flop circuit 1234, in the description of the configuration of latch input circuit 1231 and positive feedback circuit 1232, inverter INV2 is replaced with inverter INV9, switch SW2 is replaced with switch SW6, inverter INV3 is replaced with inverter INV10, inverter INV4 is replaced with inverter INV11, switch SW3 is replaced with switch SW7, node N1 is replaced with node N3, and node N2 is replaced with node N4. Furthermore, the input terminal of inverter INV9 is connected to node N2, signals Sig1 and Sig2 are swapped, and the threshold Vth is appropriately changed. The contents still hold true. Signal Do<0> is generated based on the voltage at node N4.

[0437] Figure 30 An example of the circuit configuration of the local latch circuit LC1b of the semiconductor memory device 1bj according to the sixth embodiment is shown. Figure 30 Except for the Figure 25 The circuit configuration shown is the same as the circuit configuration shown in FIG. Figure 29 The functions implemented by the inverters INV and the switches SW as part of the flip-flop circuit 1234 are similar to those implemented by the inverters INV and the switches SW as described above.

[0438] Regarding the circuit configuration other than the trigger circuit 1234, Figure 25 In the description of , the contents still hold true even after the signal Sigαh is replaced by the signal Sigαj and the signal Sigβh is replaced by the signal Sigβj.

[0439] Figure 30 The circuit structure of the trigger circuit 1234 shown in FIG. Figure 11 The latch input circuit 1231 and the positive feedback circuit 1232 described above have the same circuit configuration.

[0440] The flip-flop circuit 1234 includes, for example, p-channel MOS transistors Tr401 , Tr402 , Tr411 , Tr421 , and Tr422 , and n-channel MOS transistors Tr403 , Tr404 , Tr412 , Tr423 , and Tr424 .

[0441] The connection relationship between transistors Tr401, Tr402, Tr403, and Tr404 will be described. Regarding this connection relationship, in the description of the circuit configuration of latch input circuit 1231, the following applies even if transistor Tr11 is replaced with transistor Tr401, transistor Tr12 is replaced with transistor Tr402, transistor Tr13 is replaced with transistor Tr403, transistor Tr14 is replaced with transistor Tr404, and node N1 is replaced with node N3. Furthermore, signals Sig1 and Sig2 are swapped, and the gates of transistors Tr401 and Tr404 are connected to node N2.

[0442] The connection relationship between transistors Tr411 and Tr412 will be described. Regarding this connection relationship, the description of the circuit configuration of inverter circuit 12321 still holds true even if transistor Tr211 is replaced by transistor Tr411, transistor Tr212 is replaced by transistor Tr412, node N1 is replaced by node N3, and node N2 is replaced by node N4.

[0443] The connection relationship between transistors Tr421, Tr422, Tr423, and Tr424 will be described. Regarding this connection relationship, in the description of the circuit configuration of inverter circuit 12322, the following applies even if transistor Tr221 is replaced by transistor Tr421, transistor Tr222 is replaced by transistor Tr422, transistor Tr223 is replaced by transistor Tr423, transistor Tr224 is replaced by transistor Tr424, node N2 is replaced by node N4, and node N1 is replaced by node N3. Furthermore, even if signals Sig1 and Sig2 are swapped, the contents still hold true.

[0444] Figure 31 An example of the circuit configuration of a signal shaping circuit 126j of a semiconductor memory device 1bj according to the sixth embodiment is shown.

[0445] The signal shaping circuit 126j is similar to the reference Figure 27 The signal shaping circuit 126i shown in the figure also includes an exclusive-NOR gate XNOR1, an AND gate AND3, and an inverter INV8.

[0446] Signal shaping circuit 126j further receives signals SigN2 and SigN4 from latch circuit 123b<0> and generates signals Sigαj and Sigβj based on signals SigN2 and SigN4. Signal SigN4 is transmitted to node N4 and represents the voltage at node N4. Signals Sig1, SigN2, and SigN4 are processed within signal shaping circuit 126j as follows.

[0447] Exclusive-NOR gate XNOR1 receives signal SigN2 at its first input terminal and signal SigN4 at its second input terminal. Exclusive-NOR gate XNOR1 performs an exclusive-NOR operation on the two received signals and outputs signal SigTDj as the result of the operation. Signal SigTDj is at an L level from the time signal SigN2 rises until the delayed rise of signal SigN4, and from the time signal SigN2 falls until the delayed fall of signal SigN4. It is at an H level at all other times.

[0448] AND gate AND3 receives signal Sig1 at its first input terminal and receives signal SigTDj at its second input terminal. AND gate AND3 performs AND operation on the two received signals and outputs a signal as the result of the operation. The output signal is equivalent to Figure 22 The signal Sigαj is shown as follows. The signal Sigαj is at the same level as the signal Sig1 while the signal SigTDj is at the H level, but is at the L level while the signal SigTDj is at the L level.

[0449] The inverter INV8 receives the signal Sigαj at its input terminal and outputs a signal obtained by inverting the voltage level of the signal Sigαj. The output signal is equivalent to Figure 22 The signal Sigβj is shown.

[0450] [Action Example]

[0451] Figure 32 An example of a timing chart is shown, which shows the time changes of various signals when the local latch circuit LC1b of the semiconductor memory device 1bj of the sixth embodiment latches a certain bit of data transmitted by the signal DQ<0>. Figure 28 For the same reason as in the example, the time changes of the signal Sig2 and the signal Sigβj are omitted.

[0452] Regarding the time variation of the signal Sig1 and the signal Din<0>, Figure 13 In the description of , the contents are still valid even if time T00 is replaced by time T60, time T01 is replaced by time T61, time T02 is replaced by time T62, time T03 is replaced by time T63, time T04 is replaced by time T64, time T01d is replaced by time T61d, and time T02d is replaced by time T62d. The time ΔTb from time T61d to time T62 is longer than the time ΔT from time T01d to time T02. In addition, whether the latch input circuit 1231 and the inverter circuit with release function 12322 are in the on state or the off state, Figure 13 Even if the time is replaced in the manner described in the description, the content still holds true.

[0453] Signal Sig1 at time T64 remains at an L level until time T65, at which point it rises from an L level to an H level. Therefore, from time T64 to time T65, latch input circuit 1231 is in an OFF state, while inverter circuit 12322 with a release function is in an ON state. Signal Din<0> remains at an L level from time T64 to time T65.

[0454] The flip-flop circuit 1234 supplies a voltage at the same level as the voltage at the node N2 to the node N4 while the signal Sig1 is at the L level, for example. The flip-flop circuit 1234 supplies a voltage at the same level as the voltage at the node N4 to the node N4 while the signal Sig1 is at the H level, for example, in order to maintain the voltage at the node N4.

[0455] The inverter circuit 12321b is adjusted to an off state while the signal Sigαj is at an L level, and is adjusted to an on state while the signal Sigαj is at an H level.

[0456] From time T60 to time T61d, Figure 28 In the example of , the voltage of the node N1 is at H level from time T50 to time T51d. Figure 28 In the example of FIG5 , the voltage of the node N2 is also stable at the L level from the time T50 to the time T51 d. The H level voltage of the node N1 during this period will be described.

[0457] The flip-flop circuit 1234 supplies a voltage of the same low level as the voltage of the node N2 to the node N4 from time T60 to time T61. As a result, the voltage of the node N4 is stabilized at the low level. The flip-flop circuit 1234 supplies a voltage of the same low level as the voltage of the node N4 to the node N4 from time T61 to time T61d. As a result, the voltage of the node N4 is stabilized at the low level. From time T60 to time T61d, the voltage of the node N2 and the voltage of the node N4 are both low level. Therefore, the signal SigTDj and the Figure 28 In the same way as in the example, it is H level.

[0458] Therefore, regarding the H level voltage of the node N1 during this period, Figure 28 In the description of the voltage from time T50 to time T51d in the example, the content still holds true even if the signal Sigαi is replaced by the signal Sigαj, the time T50 is replaced by the time T60, the time T51 is replaced by the time T61, and the time T51d is replaced by the time T61d.

[0459] From time T61d to time T62, Figure 28In the example shown in FIG5 , from time T51d to time T52, an L-level voltage is supplied to node N1. After the voltage value of node N1 during this period falls below threshold value Vth7, inverter circuit 12321b supplies an H-level voltage to node N2. Consequently, for example, the voltage of node N1 changes from H to L, and the voltage of node N2 changes from L to H. The voltages of node N1 and node N2 maintain their levels until time T62. The L-level voltage of node N1 during this period will be described below.

[0460] The trigger circuit 1234 supplies a voltage of the same L level as the voltage of the node N4 to the node N4 from the time T61d to the time T62. As a result, the voltage of the node N4 is stabilized at the L level. Therefore, even if the voltage of the node N2 rises from the L level to the H level as described above, the voltage of the node N4 will not rise from the L level before the time T62. Therefore, corresponding to the rise of the voltage of the node N2, at the time T61s, the signal SigTDj falls from the H level to the L level, and the L level of the signal SigTDj is maintained until the time T62. The time T61s is after the time T61d and before the time T62. In this way, the signal SigTDj is Figure 28 In the example of the time T51d to time T51s, the H level is maintained from time T61d to time T61s. Figure 28 In the example of FIG, the level is L from time T51s to time T52, and similarly, from T61s to time T62.

[0461] Therefore, regarding the voltage of the node N1 during this period, Figure 28 In the description of the voltage from time T51d to time T52 in the example, the content still holds true even if the signal Sigαi is replaced by the signal Sigαj, the time T51d is replaced by the time T61d, the time T51s is replaced by the time T61s, and the time T52 is replaced by the time T62.

[0462] From time T62 to time T63, Figure 28 In the example of FIG5 , from time T52 to time T53, the voltage of the node N1 is stable at the L level, and the voltage of the node N2 is stable at the H level. Figure 28 Similarly to the example of the comparative example, since the signal Sig1 is at the L level, the signal Sigαj is also at the L level. Therefore, the L level voltage of the node N1 is the same as that of the comparative example. Figure 15 In the same example, no voltage rise occurs.

[0463] In this way, with Figure 13Similarly to the example of , the H level of the signal Din<0> immediately before the time T62 when the signal Sig1 falls is reflected in the voltages of the nodes N1 and N2. Figure 12 As described above, at the timing when the signal DQS falls, a certain odd-numbered bit of data transmitted by the signal DQ<0> is latched by the local latch circuit LC1b.

[0464] Furthermore, from time T62 to time T63, flip-flop circuit 1234 supplies a voltage at the L level, inverting the voltage level of node N2, to node N3. After the voltage value of node N3 falls below the threshold during this period, flip-flop circuit 1234 supplies a voltage at the H level to node N4 in response to the voltage value of node N3 falling below the threshold. Consequently, the voltage of node N4 rises from the L level to the H level and stabilizes at the H level. In response to the rise in the voltage of node N4 while the voltage of node N2 remains stable at the H level, at time T62s, signal SigTDj rises from the L level to the H level. Time T62s is after time T62 and before time T63. Figure 32 In FIG, time T62s is shown to be after time T62d. The signal SigTDj is maintained at the H level until time T63.

[0465] From time T63 to time T64, Figure 28 In the example shown in FIG5 , an H-level voltage is similarly supplied to node N1 from time T53 to time T54. After the voltage value of node N1 during this period reaches or exceeds threshold value Vth7, inverter circuit 12321b supplies an L-level voltage to node N2. Consequently, the voltage of node N1 shifts from L to H, and the voltage of node N2 shifts from H to and stabilizes at L. The voltages of node N1 and node N2 maintain their respective levels until time T64. The H-level voltage of node N1 during this period will be described below.

[0466] From time T63 to time T64, flip-flop circuit 1234 supplies a voltage at the same H level as the voltage level of node N4 to node N4. This stabilizes the voltage of node N4 at the H level. Therefore, even if the voltage of node N2 drops from the H level to the L level as described above, the voltage of node N4 does not drop from the H level until time T64. Therefore, in response to the drop in the voltage of node N2, signal SigTDj drops from the H level to the L level at time T63s, and remains at the L level until time T64. Time T63s is after time T63 and before time T64. Therefore, signal Sigαj is at the same H level as signal Sig1 from time T63 to time T63s, drops from the H level to the L level at time T63s, and remains at the L level from time T63s to time T64. The inverter circuit 12321b is adjusted to an on state from time T63 to time T63s when the signal Sigαj is at H level, and is adjusted to an off state from time T63s to time T64 when the signal Sigαj is at L level.

[0467] From time T63 to time T63s, inverter circuit 12321b is in the regulated on state. Therefore, the voltage at node N1, for example, is stabilized at an H level, which is a voltage drop by a voltage difference ΔVH, before time T63s. From time T63s, when inverter circuit 12321b is in the regulated off state, the control of inverter circuit 12321b ceases to function. As a result, the voltage at node N1 rises by the voltage difference ΔVH and stabilizes at the H level after this voltage increase. The voltage at node N1 remains stable at this H level until time T64.

[0468] From time T64 to time T65, the inverter circuit 12321b supplies an L-level voltage to the node N2, and the inverter circuit 12322 supplies an H-level voltage to the node N1. As a result, the voltage of the node N1 is stabilized at an H level, and the voltage of the node N2 is stabilized at an L level. During this period, the signal Sig1 is at an L level, so the signal Sigαi is also at an L level. Therefore, the inverter circuit 12321b is in the adjustment-off state. The inverter circuit 12321b is in the adjustment-off state, so the H-level voltage of the node N1 is different from that of the comparative example. Figure 15 Again, no voltage drop occurs.

[0469] In this way, the L level of the signal Din<0> immediately before the time T64 at which the signal Sig1 falls is reflected in the voltages of the nodes N1 and N2. Figure 12 As described above, at the timing when the signal DQS falls, a certain odd-numbered bit of data transmitted by the signal DQ<0> is latched by the local latch circuit LC1b.

[0470] Furthermore, from time T64 to time T65, flip-flop circuit 1234 supplies an H-level voltage to node N3, inverting the voltage level of node N2. After the voltage value of node N3 exceeds the threshold value during this period, flip-flop circuit 1234 supplies an L-level voltage to node N4 in response to the voltage value of node N3 exceeding the threshold value. Consequently, the voltage of node N4 drops from H to L and then stabilizes at L. In response to the drop in the voltage of node N4 while the voltage of node N2 remains stable at L, at time T64s, signal SigTDj rises from L to H. Time T64s is after time T64 and before time T65. Signal SigTDj remains at H until time T65.

[0471] [Effect]

[0472] According to the local latch circuit LC1b of the semiconductor memory device 1bj of the sixth embodiment, in addition to the effects similar to those described in the first to third embodiments, the following effects can be achieved.

[0473] Inverter circuit 12321b of local latch circuit LC1b of semiconductor memory device 1bj according to the sixth embodiment is adjusted to an OFF state while signal Sigαj is at an L level, and is adjusted to an ON state while signal Sigαj is at an H level. Signal Sigαj is at the same level as signal Sig1 while signal SigTDj is at an H level, but is at an L level while signal SigTDj is at an L level. Signal SigTDj is at an L level, for example, when detecting a rise or fall of signal SigN2, but is at an H level at other times.

[0474] For example, Figure 32 As an example, the following describes a case where the local latch circuit LC1b of the semiconductor memory device 1bj according to the sixth embodiment causes the voltage of the node N1 to drop from the H level, for example, in response to a rise in the signal Din<0> from the L level to the H level while the signal Sig1 is at the H level.

[0475] The voltage at node N2 remains stable at, for example, an L level until the rising timing of signal Din<0>. Therefore, as described in the fifth embodiment, signal SigTDj is at an H level, and inverter circuit 12321b is in a regulated on state from the time signal Sig1 reaches an H level until the rising timing of signal Din<0>. Therefore, as described in the fifth embodiment, local latch circuit LC1b of semiconductor memory device 1bj in the sixth embodiment can accurately latch a certain bit of data transmitted by signal Din<0> at the falling timing of signal Sig1.

[0476] In response to the rise of signal Din<0>, the voltage at node N2 rises from L level to H level. In response to the rise of the voltage at node N2, signal SigTDj falls from H level to L level. As described in the fifth embodiment, when signal SigTDj falls while signal Sig1 is H level, signal Sigαj falls to L level in response to the fall. Consequently, inverter circuit 12321b enters the regulated-off state even while signal Sig1 is H level. Similarly, in the local latch circuit LC1b of semiconductor memory device 1bj according to the sixth embodiment, when signal Din<0> falls from H level to L level while signal Sig1 is H level, inverter circuit 12321b may enter the regulated-off state even while signal Sig1 is H level.

[0477] As described above, the period during which the inverter circuit 12321b of the local latch circuit LC1b of the semiconductor memory device 1bj according to the sixth embodiment adjusts the conductive state is similar to that in the fifth embodiment, while the period during which the conductive state is adjusted in the third embodiment can be shortened. Therefore, the local latch circuit LC1b of the semiconductor memory device 1bj according to the sixth embodiment can further reduce power consumption compared to the third embodiment.

[0478] <Seventh embodiment>

[0479] Hereinafter, a semiconductor memory device 1bk according to a seventh embodiment will be described.

[0480] [Example of configuration]

[0481] The configuration of the semiconductor storage device 1bk according to the seventh embodiment will be described focusing on differences from the configuration of the semiconductor storage device 1b according to the third embodiment.

[0482] The semiconductor memory device 1bk of the seventh embodiment is the semiconductor memory device 1b of the third embodiment, in which the input / output circuit 12b is replaced with an input / output circuit 12bk. When describing certain components of the semiconductor memory device 1bk of the seventh embodiment including the input / output circuit 12bk, the components are described using the reference numerals used in the third embodiment, k.

[0483] like Figure 22 As described above, the input / output circuit 12bk includes a signal shaping circuit 126k in addition to the configuration of the input / output circuit 12b of the semiconductor memory device 1b according to the third embodiment. Figure 22 , only the differences from those already described are described.

[0484] The input circuit 122 outputs the signal Sig1 to the signal shaping circuit 126k, for example.

[0485] The signal shaping circuit 126 k receives the signal Sig1 from the input circuit 122 , for example, generates a signal Sigαk and a signal Sigβk based on the signal Sig1 , and outputs the signal Sigαk and the signal Sigβk to the latch circuit 123 b <0>.

[0486] Regarding the configuration of the local latch circuit LC1b of the semiconductor memory device 1bk according to the seventh embodiment, Figure 24 and Figure 25 In the description of , the contents still hold true even if the signal Sigαh is replaced by the signal Sigαk and the signal Sigβh is replaced by the signal Sigβk.

[0487] Figure 33 An example of the circuit configuration of a signal shaping circuit 126k of a semiconductor memory device 1bk according to the seventh embodiment is shown. Figure 33 , input circuits 121<0> and 122 are also shown.

[0488] The signal shaping circuit 126 k includes, for example, an inverter INV12 , an XNOR gate XNOR2 , an AND gate AND4 , and an inverter INV13 .

[0489] Signal shaping circuit 126k further receives signal DPin<0>, output by the primary inverter of inverter group INVG1, which consists of three inverters, from input circuit 121<0>. Signal DPin<0> rises a certain time before signal Din<0>, then remains at an H level along with signal Din<0>, and falls the same time before signal Din<0> falls. This relationship between signals DPin<0> and Din<0> is due to the delay of inverter group INVG1. Signal shaping circuit 126k further receives signal SigN2 from latch circuit 123b<0>. Signal shaping circuit 126k also generates signals Sigαk and Sigβk based on signals DPin<0> and SigN2. Signals Sig1, DPin<0>, and SigN2 are processed within signal shaping circuit 126k as follows.

[0490] The inverter INV12 receives the signal SigN2 at an input terminal, and outputs a signal obtained by inverting the voltage level of the signal SigN2.

[0491] XNOR gate XNOR2 receives signal DPin<0> at its first input terminal and the signal output from inverter INV12 at its second input terminal. XNOR gate XNOR2 performs an exclusive-NOR operation on these two signals and outputs a signal SigTDk representing the result of this operation. Signal SigTDk is at an H level from the time signal DPin<0> rises until the delayed rise of signal SigN2, and from the time signal DPin<0> falls until the delayed fall of signal SigN2. It is at an L level at all other times.

[0492] AND gate AND4 receives signal Sig1 at its first input terminal and receives signal SigTDk at its second input terminal. AND gate AND4 performs AND operation on the two received signals and outputs a signal as the result of the operation. The output signal is equivalent to Figure 22 The signal Sigαk is shown as follows. The signal Sigαk is at H level during a period when the signal Sig1 is at H level and the signal SigTDk is also at H level, but is at L level during other periods.

[0493] The inverter INV13 receives the signal Sigαk at its input terminal and outputs a signal obtained by inverting the voltage level of the signal Sigαk. The output signal is equivalent to Figure 22 The signal Sigβk is shown.

[0494] [Action Example]

[0495] Figure 34 An example of a timing chart is shown, which shows the time changes of various signals when the local latch circuit LC1b of the semiconductor memory device 1bk of the seventh embodiment latches a certain bit of data transmitted by the signal DQ<0>. Figure 28 For the same reason as in the example, the time changes of the signal Sig2 and the signal Sigβk are omitted.

[0496] Regarding the time variation of the signal Sig1 and the signal Din<0>, Figure 13 In the description of , the content still holds true even if time T00 is replaced by time T70, time T01 is replaced by time T71, time T02 is replaced by time T72, time T03 is replaced by time T73, time T04 is replaced by time T74, time T01d is replaced by time T71d, and time T02d is replaced by time T72d. In addition, whether the latch input circuit 1231 and the inverter circuit with release function 12322 are in the on state or the off state, Figure 13 Even if the time is replaced in the manner described in the description, the content still holds true.

[0497] Signal DPin<0> is at an L level from time T70 to time T71s, rises from an L level to an H level at time T71s, and remains at an H level from time T71s to time T72s. Time T71s is, for example, after time T71 and before time T71d. Time T72s is after time T72 and before time T72d. Signal DPin<0> falls from an H level to an L level at time T72s, and remains at an L level from time T72s to time T74.

[0498] The inverter circuit 12321b is adjusted to an off state while the signal Sigαk is at an L level, and is adjusted to an on state while the signal Sigαk is at an H level.

[0499] From time T70 to time T71d, Figure 13 In the example shown in FIG. 1 , the voltage at node N1 remains at an H level from time T00 to time T01d. During this period, inverter circuit 12321b supplies an L level voltage to node N2 in response to the voltage at node N1 being equal to or greater than threshold value Vth7. Consequently, the voltage at node N2 remains stable at an L level. The H level voltage at node N1 during this period will be described below.

[0500] Since the voltage at node N2 is stable at the L level, signal SigTDk is L from time T70 to time T71s, when signal DPin<0> is also L. From time T71s to time T71d, when signal DPin<0> is H, signal SigTDk is H. Therefore, signal Sigαk is L from time T70 to time T71s, then rises from L to H at time T71s, remaining H from time T71s to time T71d, similar to signal Sig1. Inverter circuit 12321b is in an adjusted OFF state from time T70 to time T71s, when signal Sigαk is L. From time T71s to time T71s, when signal Sigαk is H, it is in an adjusted ON state.

[0501] From time T70 to time T71s, the inverter circuit 12321b is in the adjustment off state, so the H level voltage of the node N1 is the same as that of the comparative example. Figure 15 As in the example of , no voltage drop occurs. From the moment T71s when the inverter circuit 12321b becomes the adjusted conductive state, the control of the inverter circuit 12321b takes effect. As a result, the voltage of the node N1 is, for example, Figure 13 Similarly to the example of , the voltage of the node N1 is stabilized at the H level after being dropped by the voltage difference ΔVH, and the voltage of the node N1 is stabilized at the H level until time T71d.

[0502] From time T71d to time T72, Figure 13In the example shown above, from time T01d to time T02, an L-level voltage is supplied to node N1. Consequently, the voltage at node N1 decreases from an H-level. After the voltage at node N1 decreases below threshold Vth7 during this period, inverter circuit 12321b supplies an H-level voltage to node N2 in response to the voltage at node N1 decreasing below threshold Vth7. Consequently, the voltage at node N2 increases from an L-level. At time T72, for example, the voltage at node N1 reaches an L-level, but the voltage at node N2 does not reach an H-level. The L-level voltage at node N1 during this period will be described.

[0503] For example, the voltage at node N2 has not risen sufficiently, and signal DPin is at an H level. Therefore, signal SigTDk is at an H level from time T71d to time T72. Therefore, during this period, signal Sigαk is at the same H level as signal Sig1, and inverter circuit 12321b is in a regulated on state. Therefore, the voltage at node N1, for example, remains stable at an L level after rising by voltage difference ΔVL until time T72.

[0504] From time T72 to time T73, Figure 13 In the example shown above, from time T02 to time T03, an L-level voltage is supplied to node N1. Consequently, the voltage at node N1 remains at an L-level. During this period, inverter circuit 12321b supplies an H-level voltage to node N2 in response to the voltage at node N1 falling below threshold Vth7. Consequently, the voltage at node N2 reaches and stabilizes at an H-level. During this period, signal Sig1 is at an L-level, and therefore signal Sigαk is also at an L-level, placing inverter circuit 12321b in a regulated-off state. From time T72, when inverter circuit 12321b enters the regulated-off state, the control of inverter circuit 12321b ceases to function. As a result, the voltage at node N1 decreases by an increasing voltage difference ΔVL and stabilizes at the L-level after this voltage decrease. The voltage at node N1 remains stable at this L-level until time T73.

[0505] Furthermore, the voltage at node N2 reaches H level, for example, before time T72s. In response to the voltage at node N2 rising from L level to H level in this manner, signal SigTDk falls from H level to L level. Thereafter, signal SigTDk remains L level until time T72s, when both the voltage at node N2 and signal DPin<0> are H level. From time T72s, when the voltage at node N2 is H level and signal DPin<0> is L level, to time T73, signal SigTDk remains H level.

[0506] From time T73 to time T74, Figure 13In the example shown in FIG. 1 , from time T03 to time T04, an H-level voltage is supplied to node N1. Consequently, the voltage at node N1 changes from an L-level to and stabilizes at an H-level. After the voltage at node N1 becomes equal to or greater than threshold value Vth7 during this period, inverter circuit 12321b supplies an L-level voltage to node N2 in response to the voltage at node N1 becoming equal to or greater than threshold value Vth7. Consequently, the voltage at node N2 decreases from an H-level to and stabilizes at an L-level.

[0507] Furthermore, in response to the voltage at node N2 dropping from H to L in this manner, signal SigTDk also drops from H to L at time T73s. Time T73s occurs after time T73 and before time T74. Thereafter, signal SigTDk remains L until time T74, when both the voltage at node N2 and signal DPin<0> are L. Therefore, signal Sigαk remains H, similar to signal Sig1, from time T73 to time T73s, and remains L from time T73s to time T74. Inverter circuit 12321b is in an on-state from time T73 to time T73s when signal Sigαk is H, and in an off-state from time T73s to time T74 when signal Sigαk is L.

[0508] From time T73 to time T73s, the inverter circuit 12321b is in the adjusted on state. Therefore, the voltage of the node N1 can be stabilized at the H level after the voltage is dropped by the voltage difference ΔVH before time T73s. From time T73s to time T74, the inverter circuit 12321b is in the adjusted off state. Therefore, the voltage of the node N1 stabilized at the H level during this period is the same as that of the comparative example. Figure 15 Again, no voltage drop occurs.

[0509] [Effect]

[0510] According to the local latch circuit LC1b of the semiconductor memory device 1bk of the seventh embodiment, in addition to the effects similar to those described in the first to third embodiments, the following effects can be achieved.

[0511] The inverter circuit 12321b of the local latch circuit LC1b of the semiconductor memory device 1bk according to the seventh embodiment is adjusted to an off state while the signal Sigαk is at an L level, and adjusted to an on state while the signal Sigαk is at an H level. Signal Sigαk maintains the same level as signal Sig1 while signal SigTDk is at an H level, but remains at an L level while signal SigTDk is at an L level. For example, upon detecting a level change in signal DPin<0>, signal SigTDk becomes H level until a level change in signal SigN2 corresponding to the level change is detected, but remains L level at all other times. For example, signal DPin<0> rises a certain time before the rise of signal Din<0>, then becomes H along with signal Din<0> and falls the certain time before the fall of signal Din<0>.

[0512] For example, Figure 34 As an example, the following describes a case where the local latch circuit LC1b of the semiconductor memory device 1bk of the seventh embodiment causes the voltage of the node N1 to drop from the H level, for example, in response to a rise in the signal Din<0> from the L level to the H level while the signal Sig1 is at the H level.

[0513] For example, the voltage at node N2 remains stable at an L level until the rise of signal Din<0>. Specifically, while the voltage at node N2 remains stable at an L level, the level of signal DPin<0> rises from an L level to an H level. Therefore, signal SigTDk is at an L level before the rise of signal DPin<0> and then rises from an L level to an H level in response to the rise of signal DPin<0>. Signal SigTDk remains at an H level until the voltage at node N2 rises in response to the rise of signal Din<0>. Therefore, from the later of the rise of signal Sig1 or the rise of signal SigTDk (i.e., the rise of signal DPin<0>), until the rise of signal Din<0>, inverter circuit 12321b is in an adjusted on state. Therefore, at the timing of the rise of signal Din<0>, the H level voltage at node N1 decreases. Therefore, as described in the first embodiment, the local latch circuit LC1b of the semiconductor memory device 1bk of the seventh embodiment can accurately latch a certain bit of data transmitted by the signal Din<0> at the timing of the falling of the signal Sig1. Furthermore, when the voltage at the node N2 rises in response to the rising of the signal Din<0>, the signal SigTDk falls from an H level to an L level in response to the rising voltage at the node N2. Therefore, the inverter circuit 12321b switches from a regulated on state to a regulated off state in response to the earlier of the falling of the signal Sig1 and the falling of the signal SigTDk, i.e., the rising voltage at the node N2.

[0514] If the rise of signal DPin<0> is later than the rise of signal Sig1, inverter circuit 12321b remains in the regulated OFF state until signal DPin<0> rises, even while signal Sig1 is at an H level. Furthermore, if the rise of the voltage at node N2 is earlier than the fall of signal Sig1, inverter circuit 12321b remains in the regulated OFF state after the voltage at node N2 rises, even while signal Sig1 is at an H level.

[0515] As described above, the period during which the inverter circuit 12321b of the local latch circuit LC1b of the semiconductor memory device 1bk according to the seventh embodiment is adjusted to its on-state is similar to that in the fourth embodiment, while the period during which the inverter circuit 12321b is adjusted to its on-state in the third embodiment can be shortened. Therefore, the local latch circuit LC1b of the semiconductor memory device 1bk according to the seventh embodiment can further reduce power consumption compared to the third embodiment.

[0516] <Eighth embodiment>

[0517] Hereinafter, a semiconductor memory device 1c according to an eighth embodiment will be described.

[0518] The configuration of the semiconductor memory device 1 c according to the eighth embodiment will be described focusing on differences from the configuration of the semiconductor memory device 1 according to the first embodiment.

[0519] The semiconductor memory device 1c of the eighth embodiment is obtained by replacing the local latch circuit LC1 with a local latch circuit LC1c in the semiconductor memory device 1 of the first embodiment. When describing certain components of the semiconductor memory device 1c of the eighth embodiment that include the local latch circuit LC1c, the components will be described using the reference numeral c used in the first embodiment.

[0520] Figure 35 An example of the configuration of a local latch circuit LC1c of a semiconductor memory device 1c according to the eighth embodiment is shown.

[0521] The local latch circuit LC1c includes Figure 10 In addition to the latch input circuit 1231 and the positive feedback circuit 1232 shown, the system further includes a voltage adjustment circuit 1235 .

[0522] The voltage regulating circuit 1235 includes, for example, an inverter INV14. The input and output terminals of the inverter INV14 are connected to a node N2. For example, when the voltage value of the node N2 connected to the input terminal is greater than or equal to a threshold value Vth14, the inverter INV14 supplies an L-level voltage to the node N2 connected to the output terminal. When the voltage value of the node N2 connected to the input terminal is less than the threshold value Vth14, the inverter INV14 supplies an H-level voltage to the node N2 connected to the output terminal.

[0523] When inverter circuit 12321 supplies an H-level voltage to node N2, the voltage at node N2 may rise. If this voltage exceeds threshold value Vth14, voltage regulator circuit 1235 supplies an L-level voltage to node N2, corresponding to the voltage exceeding threshold value Vth14. As a result, the voltage at node N2 stabilizes at an H level. This H-level voltage is lower than when no voltage is supplied from voltage regulator circuit 1235, but the voltage at node N2 is stabilized by the H-level voltage supplied from inverter circuit 12321. This is because, when the voltage at node N2 stabilizes at an H level, the resistance R14L of the path from the source of the L-level voltage supplied by voltage regulator circuit 1235 to node N2 is greater than the resistance R3H of the path from the source of the H-level voltage supplied by inverter circuit 12321 to node N2. For example, when the voltage of the node N2 is stable at the H level, (the size of the resistor R14L) / (the size of the resistor R3H) is within the range of 5 / 3 or more and 3 or less.

[0524] When inverter circuit 12321 supplies an L-level voltage to node N2, the voltage at node N2 may drop. If the value of this voltage is less than threshold value Vth14, voltage regulator circuit 1235 supplies an H-level voltage to node N2 in response to the voltage being less than threshold value Vth14. As a result, the voltage at node N2 stabilizes at an L-level. This L-level voltage is higher than when no voltage is supplied from voltage regulator circuit 1235, but the voltage at node N2 is stabilized by the L-level voltage supplied from inverter circuit 12321. This is because, when the voltage at node N2 stabilizes at an L-level, the resistance R14H of the path from the source of the H-level voltage supplied by voltage regulator circuit 1235 to node N2 is greater than the resistance R3L of the path from the source of the L-level voltage supplied by inverter circuit 12321 to node N2. For example, when the voltage of the node N2 is stable at the L level, (the size of the resistor R14H) / (the size of the resistor R3L) is within the range of 5 / 3 or more and 3 or less.

[0525] According to the local latch circuit LC1c of the semiconductor memory device 1c of the eighth embodiment, in addition to the effects similar to those described in the first embodiment, the following effects can also be achieved. The voltage regulator circuit 1235 can lower the H-level voltage of the node N2 and raise the L-level voltage of the node N2. Therefore, for example, the voltage of the node N2 can be lowered from the H-level voltage to below the threshold value Vth4 and raised from the L-level voltage to above the threshold value Vth4 in a shorter time than that of the inverter circuit 12321.

[0526] <Ninth embodiment>

[0527] Hereinafter, a semiconductor memory device 1d according to a ninth embodiment will be described.

[0528] The configuration of the semiconductor memory device 1 d according to the ninth embodiment will be described focusing on differences from the configuration of the semiconductor memory device 1 according to the first embodiment.

[0529] The semiconductor memory device 1d of the ninth embodiment is obtained by replacing the local latch circuit LC1 with a local latch circuit LC1d in the semiconductor memory device 1 of the first embodiment. When describing certain components of the semiconductor memory device 1d of the ninth embodiment including the local latch circuit LC1d, the components are described using the reference numeral d used in the first embodiment.

[0530] Figure 36 An example of the configuration of a local latch circuit LC1d of a semiconductor memory device 1d according to the ninth embodiment is shown.

[0531] The local latch circuit LC1d includes Figure 20 In addition to the latch input circuit 1231 and the positive feedback circuit 1232b shown in the figure, it also includes an inverter circuit 1236. Figure 20 The descriptions given are consistent.

[0532] The inverter circuit 1236 includes, for example, an inverter INV15 and a switch SW8 .

[0533] Regarding the configuration of inverter circuit 1236, the same contents apply as described above for the configuration of inverter circuit 12321, except that inverter INV7 is replaced with inverter INV15, switch SW5 is replaced with switch SW8, node N1 is replaced with node N2, node N2 is replaced with node N5, and threshold Vth7 is replaced with threshold Vth15. Signal Do<0> is generated based on the voltage at node N5.

[0534] The function of adjusting the voltage of the node N2 by the inverter circuit 1236 during the period when the signal Sig1 is at H level will be described. During this period, the switch SW8 is in the on state, that is, the inverter circuit 1236 is in the adjusted on state.

[0535] When inverter circuit 12321b supplies an H-level voltage to node N2, the voltage at node N2 may rise. When this voltage exceeds threshold value Vth15, inverter circuit 1236 supplies an L-level voltage to node N2, corresponding to the voltage exceeding threshold value Vth15. As a result, the voltage at node N2 stabilizes at an H level. This H-level voltage is lower than when no voltage is supplied from inverter circuit 1236, but the voltage at node N2 stabilizes based on the H-level voltage supplied from inverter circuit 12321b. This is because, when the voltage at node N2 stabilizes at an H level, the resistance R15L of the path from the source of the L-level voltage supplied by inverter circuit 1236 to node N2 is greater than the resistance R7H of the path from the source of the H-level voltage supplied by inverter circuit 12321b to node N2. For example, when the voltage of the node N2 is stable at the H level, (the size of the resistor R15L) / (the size of the resistor R7H) is within the range of 5 / 3 to 3.

[0536] When inverter circuit 12321b supplies an L-level voltage to node N2, the voltage at node N2 may drop. If the value of this voltage is less than threshold value Vth15, inverter circuit 1236 supplies an H-level voltage to node N2 in response to the voltage being less than threshold value Vth15. As a result, the voltage at node N2 may stabilize at an L-level. This L-level voltage is higher than when no voltage is supplied from inverter circuit 1236, but the voltage at node N2 is stabilized by the L-level voltage supplied from inverter circuit 12321b. This is because, when the voltage at node N2 is stabilized at an L-level, the resistance R15H of the path from the source of the H-level voltage supplied by inverter circuit 1236 to node N2 is greater than the resistance R7L of the path from the source of the L-level voltage supplied by inverter circuit 12321b to node N2. For example, when the voltage of the node N2 is stable at the L level, (the size of the resistor R15H) / (the size of the resistor R7L) is within the range of 5 / 3 to 3.

[0537] The following describes the period when signal Sig1 is at an L level. During this period, switch SW8 is in the OFF state, that is, inverter circuit 1236 is in the regulated OFF state. Therefore, even if the voltage at node N2 is stabilized at an H level or an L level, inverter circuit 1236 does not cause the voltage at node N2 to drop or rise as described above.

[0538] Figure 37 An example of the circuit configuration of a local latch circuit LC1d of a semiconductor memory device 1d according to the ninth embodiment is shown. Figure 37 Except for the Figure 21 The circuit configuration shown is the same as the circuit configuration shown in FIG. Figure 36 The functions of the inverter INV15 and the switch SW8 as part of the inverter circuit 1236 are similar to those of the inverter circuit 1236. Figure 21 The descriptions given are consistent.

[0539] The inverter circuit 1236 includes, for example, p-channel MOS transistors Tr61 and Tr62 , and n-channel MOS transistors Tr63 and Tr64 .

[0540] Regarding the circuit structure of the inverter circuit 1236, in the description of the circuit structure of the inverter circuit 12321b, the content still holds true after the transistor Tr213 is replaced by the transistor Tr61, the transistor Tr214 is replaced by the transistor Tr62, the transistor Tr215 is replaced by the transistor Tr63, the transistor Tr216 is replaced by the transistor Tr64, the node N1 is replaced by the node N2, and the node N2 is replaced by the node N5.

[0541] According to the local latch circuit LC1d of the semiconductor memory device 1d of the ninth embodiment, in addition to the effects similar to those described in the eighth embodiment, the effects described in the third embodiment can also be achieved.

[0542] In the eighth and ninth embodiments, examples have been described in which circuits are provided for supplying voltages to the nodes N1 and N2, respectively, so that the voltage at the H level of the nodes N1 decreases and the voltage at the L level increases. For example, any combination of the circuits described in the first to seventh embodiments can be used as circuits for supplying voltages to the nodes N1 and N2 in this manner.

[0543] <Tenth embodiment>

[0544] Hereinafter, a semiconductor memory device 1eh according to a tenth embodiment will be described.

[0545] [Example of configuration]

[0546] The configuration of the semiconductor storage device 1eh according to the tenth embodiment will be described focusing on differences from the configuration of the semiconductor storage device 1bh according to the fourth embodiment.

[0547] The semiconductor memory device 1eh of the tenth embodiment is obtained by replacing the local latch circuit LC1b with the local latch circuit LC1e in the semiconductor memory device 1bh of the fourth embodiment. When referring to certain components of the semiconductor memory device 1eh of the tenth embodiment that include the local latch circuit LC1e, these components are denoted by the reference numerals used in the fourth embodiment with the reference numerals e replaced with the reference numeral b.

[0548] Figure 38 An example of the configuration of a local latch circuit LC1e of a semiconductor memory device 1eh according to the tenth embodiment is shown.

[0549] Figure 38 The local latch circuit LC1e is constructed in Figure 24 In the configuration of the local latch circuit LC1b shown, the positive feedback circuit 1232b is replaced by a positive feedback circuit 1232e. The positive feedback circuit 1232e is obtained by replacing the inverter circuit 12321b in the positive feedback circuit 1232b with an inverter circuit 12321 and a voltage adjustment circuit 12323. The configuration of the inverter circuit 12321 and the inverter circuit 12322 of the positive feedback circuit 1232e is similar to that of the reference circuit 12321. Figure 10 The descriptions given are consistent.

[0550] The voltage adjustment circuit 12323 includes, for example, a delay circuit DC4 and a switch SW9.

[0551] The input terminal of the delay circuit DC4 is connected to the node N2, and the output terminal of the delay circuit DC4 is connected to the node N6. The first terminal of the switch SW9 is connected to the node N6, and the second terminal of the switch SW9 is connected to the node N1.

[0552] The delay circuit DC4 receives the signal SigN2 at the node N2 connected to the input terminal, generates a signal after the signal SigN2 is delayed, and outputs the generated signal to the node N6 connected to the output terminal. The switch SW9 transmits the signal SigN6 transmitted at the node N6 connected to the first terminal to the node N1 connected to the second terminal while the switch SW9 is in the on state. The signal SigN6 is a signal indicating the voltage of the node N6. The switch SW9 is connected to the reference Figure 24 The switch SW5 is similar to the description above. It is in the off state while the signal Sigαh is at the L level and the signal Sigβh is at the H level, and is in the on state while the signal Sigαh is at the H level and the signal Sigβh is at the L level. Figure 38 , the signals Sigαh and Sigβh are respectively shown as signals Sigα and Sigβ. The same applies to the other drawings in this embodiment.

[0553] The above describes an example of the configuration of the voltage regulating circuit 12323, but the present embodiment is not limited thereto. The voltage regulating circuit 12323 may have another configuration capable of outputting a delayed signal SigN2 to the node N1 while the switch SW9 is in the on state.

[0554] Regarding the voltage regulation function of the voltage regulation circuit 12323 for the node N1, refer to Figure 20 The same explanation as that described above regarding the function of the inverter circuit 12321b to adjust the voltage of the node N1 holds true.

[0555] Figure 39 An example of the circuit configuration of the local latch circuit LC1e of the semiconductor memory device 1eh according to the tenth embodiment is shown.

[0556] Figure 39 The latch input circuit 1231, the inverter circuit 12321, and the inverter circuit 12322 with a release function are shown in FIG. Figure 11 The circuit configuration of the voltage regulating circuit 12323 is described below.

[0557] The voltage regulating circuit 12323 includes, for example, inverters INV16 and INV17, p-channel MOS transistors Tr231 and Tr232, and n-channel MOS transistors Tr233 and Tr234. While the voltage regulating circuit 12323 includes two inverters INV, the number of inverters INV included in the voltage regulating circuit 12323 is not limited thereto.

[0558] The input terminal of the inverter INV16 is connected to the node N2, the output terminal of the inverter INV16 is connected to the input terminal of the inverter INV17, and the output terminal of the inverter INV17 is connected to the node N6.

[0559] Inverter INV16 receives signal SigN2 at node N2 connected to the input terminal and supplies a voltage of an inverted level of signal SigN2 to the input terminal of inverter INV17 connected to the output terminal. Inverter INV17 receives the voltage supplied to the input terminal in the above manner and supplies a voltage of an inverted level of the voltage to node N6 connected to the output terminal of inverter INV17. Although a voltage of the same level as signal SigN2 is supplied to node N6 in this manner, signal SigN6 is delayed by signal SigN2 due to passing through inverters INV16 and INV17. The high-level voltage supplied to node N6 by inverter INV17 is, for example, voltage VDD, and the low-level voltage supplied to node N6 by inverter INV17 is, for example, voltage VSS.

[0560] The first terminal of transistor Tr231 is connected to node N6, and the second terminal of transistor Tr231 is connected to the first terminal of transistor Tr232. The second terminal of transistor Tr232 is connected to node N1. The first terminal of transistor Tr233 is connected to node N1, and the second terminal of transistor Tr233 is connected to the first terminal of transistor Tr234. The second terminal of transistor Tr234 is connected to node N6. For example, voltage VSS is applied to the gate of transistor Tr231, and voltage VDD is applied to the gate of transistor Tr234. Signal Sigβh is input to the gate of transistor Tr232, and signal Sigαh is input to the gate of transistor Tr233.

[0561] When the signal SigN6 is at an H level, the transistor Tr231 is in an on state and the transistor Tr234 is in an off state. Therefore, corresponding to the signal SigN6 being at an H level, the voltage VDD of the signal SigN6 at an H level is supplied to the first terminal of the transistor Tr232. On the other hand, when the signal SigN6 is at an L level, the transistor Tr231 is in an off state and the transistor Tr234 is in an on state. Therefore, corresponding to the signal SigN6 being at an L level, the voltage VSS of the signal SigN6 at an L level is supplied to the second terminal of the transistor Tr233. Here, the transistors Tr231 and Tr234 can play the same role as the reference. Figure 19 The same effects as those mentioned and explained for the transistors Tr303 and Tr304 are achieved.

[0562] While the signal Sigαh is at L level and the signal Sigβh is at H level, the transistors Tr232 and Tr233 are in the OFF state. Therefore, the voltage VDD supplied to the first terminal of the transistor Tr232 and the voltage VSS supplied to the second terminal of the transistor Tr233 are not supplied to the node N1.

[0563] While signal Sigαh is at an H level and signal Sigβh is at an L level, transistors Tr232 and Tr233 are in an on state. During this period, voltage regulator circuit 12323 supplies voltage to node N1 as follows. When signal SigN6 is at an H level, voltage VDD supplied to the first terminal of transistor Tr232 is supplied to node N1. On the other hand, when signal SigN6 is at an L level, voltage VSS supplied to the second terminal of transistor Tr233 is supplied to node N1.

[0564] For example, Figure 39 Inverters INV16 and INV17 are shown as Figure 38 The delay circuit DC4 shown in FIG. Figure 39The p-channel MOS transistors Tr231 and Tr232, and the n-channel MOS transistors Tr233 and Tr234 shown are used as Figure 38 The switch SW9 shown is functional. Figure 39 The other circuit configurations shown, and Figure 38 The composition shown is the same as that of reference Figure 11 The same corresponding relationship as described above holds true.

[0565] Figure 40 FIG. 1 shows another example of the circuit configuration of the local latch circuit LC1e of the semiconductor memory device 1eh according to the tenth embodiment. The circuit configuration of the local latch circuit LC1e is similar to that of FIG. 1 except for the following aspects. Figure 39 Same as the example.

[0566] The voltage adjustment circuit 12323 includes, for example, an inverter INV18, p-channel MOS transistors Tr235 and Tr236, and n-channel MOS transistors Tr237 and Tr238 instead of the reference Figure 39 The circuit configuration described.

[0567] The input terminal of inverter INV18 is connected to node N2. For example, voltage VDD is applied to the first terminal of transistor Tr235. The second terminal of transistor Tr235 is connected to the first terminal of transistor Tr236, and the second terminal of transistor Tr236 is connected to node N1. The first terminal of transistor Tr237 is connected to node N1, and the second terminal of transistor Tr237 is connected to the first terminal of transistor Tr238. ​​For example, voltage VSS is applied to the second terminal of transistor Tr238. ​​The gates of transistors Tr235 and Tr238 are each connected to the output terminal of inverter INV18. Signal Sigβh is input to the gate of transistor Tr236, and signal Sigαh is input to the gate of transistor Tr237.

[0568] While the signal Sigαh is at L level and the signal Sigβh is at H level, transistors Tr236 and Tr237 are off. Therefore, voltage VDD applied to the first terminal of transistor Tr235 and voltage VSS applied to the second terminal of transistor Tr238 are not supplied to node N1.

[0569] While the signal Sigαh is at the H level and the signal Sigβh is at the L level, the transistors Tr236 and Tr237 are in the on state. During this period, the voltage regulating circuit 12323 supplies a voltage to the node N1 as follows.

[0570] Inverter INV18 receives signal SigN2 at node N2 connected to its input terminal and supplies a voltage of an inverted level of signal SigN2 to the gates of transistors Tr235 and Tr238, which are connected to the output terminal. When signal SigN2 is high and inverter INV18 supplies a low-level voltage to the gates of transistors Tr235 and Tr238, transistor Tr235 is turned on and transistor Tr238 is turned off. Therefore, when signal SigN2 is high, voltage VDD applied to the first terminal of transistor Tr235 is supplied to node N1. On the other hand, when signal SigN2 is low and inverter INV18 supplies a high-level voltage to the gates of transistors Tr235 and Tr238, transistor Tr235 is turned off and transistor Tr238 is turned on. Therefore, in response to the L-level signal SigN2 , the voltage VSS applied to the second terminal of the transistor Tr238 is supplied to the node N1 .

[0571] The voltage supplied to the node N1 by the voltage adjustment circuit 12323 is the same level as the signal SigN2. However, the voltage supplied to the node N1 is delayed by the signal SigN2 through the inverter INV18 and the transistors Tr235 and Tr238.

[0572] For example, Figure 40 The inverter INV18, the p-channel MOS transistor Tr235 and the n-channel MOS transistor Tr238 are shown as Figure 38 The delay circuit DC4 shown in FIG. Figure 40 The p-channel MOS transistor Tr236 and the n-channel MOS transistor Tr237 shown are used as Figure 38 The switch SW9 shown is functional. Figure 40 The other circuit configurations shown, and Figure 38 The composition shown is the same as that of reference Figure 11 The same corresponding relationship as described above holds true.

[0573] Figure 39 and Figure 40 In any of the examples, when both the voltage regulating circuit 12323 and the latch input circuit 1231 supply a voltage to the node N1 and stabilize the voltage of the node N1, the relationship between the on-resistance of the transistor Tr through which a current flows between the voltage supply source supplied by the voltage regulating circuit 12323 and the node N1 and the transistor Tr through which a current flows between the voltage supply source supplied by the latch input circuit 1231 and the node N1 is the same as that in the reference circuit. Figure 21The same explanation as that given for the inverter circuit 12321 b and the latch input circuit 1231 applies.

[0574] While the above description describes an example in which the delay circuit DC4 participates in adjusting the voltage of the node N1 and is applied to the semiconductor memory device 1bh of the fourth embodiment, the present embodiment is not limited thereto and the technology disclosed in this embodiment can also be applied to semiconductor memory devices of other embodiments.

[0575] [Action Example]

[0576] Figure 41 An example of a timing chart is shown, which shows the time changes of various signals when the local latch circuit LC1e of the semiconductor memory device 1eh of the tenth embodiment latches a certain bit of data transmitted by the signal DQ<0>. Figure 28 For the same reason as in the example, the time changes of the signal Sig2 and the signal Sigβh are omitted.

[0577] Regarding the time variation of the signal Sig1 and the signal Din<0>, Figure 13 In the description of , the content still holds even if time T00 is replaced by time T80, time T01 is replaced by time T81, time T02 is replaced by time T82, time T03 is replaced by time T83, time T04 is replaced by time T84, time T01d is replaced by time T81d, and time T02d is replaced by time T82d. The time from time T81d to time T82 is the same as the time ΔT from time T01d to time T02, for example. In addition, whether the latch input circuit 1231 and the inverter circuit with release function 12322 are in the on state or the off state, Figure 13 Even if the time is replaced in the manner described in the description, the content still holds true.

[0578] Regarding the time variation of the signal Sigαh, Figure 26 In the description of , the content still holds even if the time T40 is replaced by the time T80, the time T41 is replaced by the time T81, the time T41s is replaced by the time T81s, the time T41d is replaced by the time T81d, the time T42 is replaced by the time T82, the time T43 is replaced by the time T83, the time T43s is replaced by the time T83s, and the time T44 is replaced by the time T84. Therefore, the voltage regulating circuit 12323 is the same as Figure 26 Similarly, the inverter circuit 12321b in the example is in the on state from time T81s to time T82 and from time T83s to time T84, and is in the off state otherwise.

[0579] From time T80 to time T81d, Figure 13In the example shown in FIG. 1 , the voltage at node N1 is also at an H level from time T00 to time T01d. During this period, inverter circuit 12321 supplies an L level voltage to node N2 in response to the H level voltage at node N1. Consequently, the voltage at node N2 is stabilized at an L level. Furthermore, during this period, delay circuit DC4 of voltage adjustment circuit 12323 supplies an L level voltage to node N6 in response to the L level voltage at node N2. Consequently, the voltage at node N6 is also stabilized at an L level. The H level voltage at node N1 during this period will be described.

[0580] From time T80 to time T81s, the voltage regulating circuit 12323 is in the off state, so the H level voltage of the node N1 is the same as that of the comparative example. Figure 15 From time T81s to time 81d, the voltage adjustment circuit 12323 is in the on state, and the L level voltage of the node N6 is transmitted to the node N1. As a result, the voltage of the node N1 is, for example, Figure 13 Similarly to the example of , the voltage of the node N1 is stabilized at the H level after the voltage is dropped by the voltage difference ΔVH, and the voltage of the node N1 is stabilized at the H level until time T81d.

[0581] From time T81d to time T82, Figure 13 In the example shown in FIG. 1 , from time T01d to time T02, an L-level voltage, for example, voltage VSS, is supplied to node N1. Consequently, the voltage at node N1 decreases from an H-level. In response to the decrease in the voltage at node N1, inverter circuit 12321 supplies an H-level voltage to node N2. Consequently, the voltage at node N2 increases from an L-level. In response to the increase in the voltage at node N2, delay circuit DC4 supplies an H-level voltage to node N6. This H-level voltage is supplied to node N6 later than the H-level voltage is supplied to node N2, for example, starting after time T82. In this case, from time T81d to time T82, the voltage at node N6 does not increase but remains constant, for example, at an L-level. During this period, voltage adjustment circuit 12323 is in an on state, transmitting the L-level voltage at node N6 to node N1.

[0582] At time T82, the voltage of node N1 drops to a level where the level change of signal Din<0> can be reliably transmitted in the form of voltage change of node N1. Figure 13 In the example of FIG. 1 , from time T02 to time T03, the inverter circuit 12321 supplies an H-level voltage to the node N2 and an L-level voltage to the node N1. Figure 13Similarly to the example of the comparative example, the voltage of the node N1 reaches and stabilizes at the L level, and the voltage of the node N2 rises and stabilizes at the H level. In addition, the delay circuit DC4 supplies the H level voltage to the node N6 in response to the rise in the voltage of the node N2, so the voltage of the node N6 is also stabilized at the H level. However, during this period, the voltage adjustment circuit 12323 is in the off state, so the L level voltage of the node N1 is different from that of the comparative example. Figure 15 In the same example, no voltage rise occurs.

[0583] In this way, with Figure 13 Similarly to the example of , the H level of the signal Din<0> immediately before the time T82 when the signal Sig1 falls is reflected in the voltages of the nodes N1 and N2. Figure 12 As described above, at the timing when the signal DQS falls, a certain odd-numbered bit of data transmitted by the signal DQ<0> is latched by the local latch circuit LC1e.

[0584] From time T83 to time T84, Figure 13 In the example shown in FIG. 1 , from time T03 to time T04, an H-level voltage is supplied to node N1. Consequently, the voltage at node N1 rises from an L-level voltage, reaches an H-level voltage, and stabilizes there. Inverter circuit 12321 supplies an L-level voltage to node N2 in response to the rise in the voltage at node N1. Consequently, the voltage at node N2 decreases from an H-level voltage. Delay circuit DC4 supplies an L-level voltage to node N6 in response to the decrease in the voltage at node N2. The supply of this L-level voltage to node N6 begins later than the supply of the L-level voltage to node N2.

[0585] From time T83 to time T83s, the voltage regulating circuit 12323 is in the off state. Therefore, if the voltage of the node N1 reaches the H level during this period, the voltage of the H level is the same as that of the comparative example. Figure 15 As in the example, no voltage drop occurs. From time T83s to time T84, the voltage adjustment circuit 12323 is in the on state. As a result, the voltage of the node N1 is equal to Figure 13 Similarly to the example of , the voltage of the node N1 is stabilized at the H level after being dropped by the voltage difference ΔVH, and the voltage of the node N1 is stabilized at the H level until time T84.

[0586] [Effect]

[0587] According to the local latch circuit LC1e of the semiconductor memory device 1eh of the tenth embodiment, in addition to the effects similar to those described in the first to fourth embodiments, the following effects can be achieved.

[0588] Figure 41In the example shown in FIG. 1 , at time T81d, latch input circuit 1231 begins supplying an L-level voltage to node N1 in response to a rise in signal Din<0> from L to H. Consequently, the voltage at node N1 drops from H level, having dropped by a voltage difference ΔVH. Inverter circuit 12321 supplies an H-level voltage to node N2 in response to the drop in node N1 voltage. Consequently, the voltage at node N2 rises from L level. Delay circuit DC4 supplies an H-level voltage to node N6 in response to the rise in node N2 voltage. Due to the delay circuit DC4, the supply of this H-level voltage to node N6 begins later than the supply of the H-level voltage to node N2, for example, after time T82. In this case, from time T81d to time T82, the voltage at node N6 does not rise but remains constant, for example, at a stable L level. Latch input circuit 1231 continues supplying the L-level voltage to node N1 until time T82.

[0589] From time T81d to time T82, voltage adjustment circuit 12323 transmits the L-level voltage of node N6 to node N1. Thus, while the voltage of node N1 decreases from time T81d to time T82, the L-level voltage of node N6, for example, is continuously transmitted to node N1. In other words, during this period, voltage adjustment circuit 12323 can maximize its function of decreasing the voltage of node N1. Therefore, latch input circuit 1231 reliably transmits the voltage change of node N1 from time T81d to time T82, which causes the voltage of node N1 to decrease to the level of signal Din<0>, as a voltage change of node N1.

[0590] As described above, even when the time from the rise of signal Din<0> to the fall of signal Sig1 is as short as time ΔT, the local latch circuit LC1e of the semiconductor memory device 1eh in the tenth embodiment can accurately latch a certain bit of data transmitted by signal Din<0> at the timing of the fall. Therefore, as described with reference to the first embodiment, the local latch circuit LC1e of the semiconductor memory device 1eh can accurately latch each odd-numbered bit of data of signal Din<0> even when the semiconductor memory device 1eh is operating at high speed.

[0591] <Other embodiments>

[0592] In the above description, several D-type latch circuits are cited as examples of latch circuits to which the technology disclosed in this specification can be applied. However, the technology disclosed in this specification can also be applied to various other D-type latch circuits. Furthermore, the technology disclosed in this specification can also be applied to latch circuits other than D-type latch circuits.

[0593] In the first embodiment, an example of implementing the voltage regulating circuit 1233 using a CMOS inverter circuit was described. However, the voltage regulating circuit 1233 can also be implemented using an inverter having another configuration. For example, a NAND gate circuit can be used instead of a CMOS inverter circuit. In this case, by supplying an H-level voltage to one of the two input terminals of the NAND gate circuit, the other input terminal can be used as the input terminal of the inverter. In addition, a clocked inverter circuit can be used instead of a CMOS inverter circuit. More specifically, a clock-synchronized CMOS inverter circuit can also be used. In this way, as an inverter constituting the voltage regulating circuit 1233, circuits with various configurations can be used as long as a voltage having an opposite logic level (L level or H level) to the logic level (H level or L level) of the voltage supplied to the input terminal can be supplied from the output terminal. The same is true for other inverters.

[0594] For example, the fourth, fifth, and sixth embodiments each add a signal shaping circuit based on the configuration of the third embodiment, thereby shortening the period during which the conductive state is adjusted. However, the signal shaping circuits shown in the fourth, fifth, and sixth embodiments can also be applied to the second embodiment to shorten the period during which the conductive state is adjusted.

[0595] In the above description, an inverter, for example, is used to lower and raise the voltage at a node to an H level and an L level, respectively. However, other configurations can also be used to adjust the voltage at the node. For example, a configuration can be used in which a voltage between the H level and the L level, such as the average voltage of the H level and the L level, is supplied to the node.

[0596] In this specification, the term "connected" means electrically connected, and does not exclude the presence of other elements interposed therebetween.

[0597] In this specification, the use of terms such as "identical," "consistent," "fixed," and "maintained" is intended to include situations where there are design errors when implementing the techniques described in the embodiments. This also applies to situations where the term "substantially the same" is used repeatedly in these expressions. Furthermore, the use of the term "applying or supplying a certain voltage" is intended to include both controlling the application or supply of the voltage and actually applying or supplying the voltage. Furthermore, "applying or supplying a certain voltage" may also include applying or supplying a voltage of, for example, 0V.

[0598] The above-described embodiments can be understood in view of the following items.

[0599] [1] A semiconductor device comprising:

[0600] a first circuit configured to receive a first signal, output a first voltage to a first node in response to a voltage of the first signal being at a first level, and output a second voltage to the first node in response to a voltage of the first signal being at a second level, wherein the first voltage is higher than the second voltage;

[0601] a second circuit connected to the first node and configured to latch data generated based on the voltage of the first node; and

[0602] The third circuit is configured to be connected to the first node, output a third voltage to the first node while the first circuit outputs the first voltage to the first node, and output a fourth voltage to the first node while the first circuit outputs the second voltage to the first node, wherein the third voltage is lower than the first voltage and the fourth voltage is higher than the second voltage.

[0603] [2] The device of [1], wherein

[0604] The first circuit is further configured to receive a second signal.

[0605] The first voltage and the second voltage are output to the first node during a period in which the voltage of the second signal is at a third level.

[0606] [3] The device of [1], wherein

[0607] The third circuit includes an inverter.

[0608] The third voltage and the fourth voltage are output by the inverter based on the voltage of the first node.

[0609] [4] The device of [1], wherein

[0610] The third circuit can perform on-off control on output of the third voltage and the fourth voltage at the first node.

[0611] [5] The device of [1], wherein

[0612] The first circuit is connected to a second node to which the first voltage is applied.

[0613] The third circuit is connected to a third node to which the third voltage is applied.

[0614] While the first circuit outputs the first voltage to the first node and the third circuit outputs the third voltage to the first node, resistance of a path from the third node to the first node is greater than resistance of a path from the second node to the first node.

[0615] [6] A semiconductor device comprising:

[0616] a first circuit configured to receive a first signal, output a first voltage to a first node in response to a voltage of the first signal being at a first level, and output a second voltage to the first node in response to a voltage of the first signal being at a second level, wherein the first voltage is higher than the second voltage; and

[0617] a second circuit connected to the first node and the second node and configured to latch data generated based on the voltage of the first node;

[0618] The second circuit includes an inverter, an input terminal of the inverter is connected to the first node, and an output terminal of the inverter is connected to the second node.

[0619] The inverter outputs one of a third voltage and a fourth voltage to the second node based on the voltage of the first node.

[0620] The second circuit is further configured to output the third voltage output by the inverter to the second node to the first node while the first circuit outputs the first voltage to the first node, and to output the fourth voltage output by the inverter to the second node to the first node while the first circuit outputs the second voltage to the first node.

[0621] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in a variety of other ways and can be omitted, replaced, or modified without departing from the spirit of the invention. These embodiments and their variations are intended to be included within the scope and spirit of the invention and within the scope of the invention set forth in the claims and their equivalents.

Claims

1. A semiconductor device comprising: a first circuit configured to receive a first signal whose voltage switches between a first level and a second level, output a first voltage to a first node in response to the voltage of the first signal being at the first level, and output a second voltage to the first node in response to the voltage of the first signal being at the second level, wherein the first voltage is higher than the second voltage; a second circuit connected to the first node and configured to latch data generated based on the voltage of the first node; and The third circuit includes a first inverter having a first input terminal connected to the first node and a first output terminal connected to the first node.

2. The semiconductor device according to claim 1, wherein The first circuit is further configured to receive a second signal whose voltage alternately switches between a third level and a fourth level, The second circuit is further configured to receive the second signal and latch the data generated based on the voltage of the first node in accordance with the second signal.

3. The semiconductor device according to claim 2, wherein The third circuit is further configured to output a third voltage to the first node while the first circuit outputs the first voltage to the first node, and to output a fourth voltage to the first node while the first circuit outputs the second voltage to the first node. The third voltage is lower than the fourth voltage. 4 . The semiconductor device according to claim 3 , wherein the first inverter outputs the third voltage and the fourth voltage based on the voltage of the first node. 5 . The semiconductor device according to claim 3 , wherein a difference between the first voltage and the second voltage is equal to a difference between the fourth voltage and the third voltage. 6 . The semiconductor device according to claim 3 , wherein the third voltage is the same as the second voltage, and the fourth voltage is the same as the first voltage.

7. The semiconductor device according to claim 5, wherein The first circuit is connected to a second node to which the first voltage is applied and a third node to which the second voltage is applied. The third circuit is connected to a fourth node to which the third voltage is applied and a fifth node to which the fourth voltage is applied. During a period in which the first circuit outputs the first voltage to the first node and the third circuit outputs the third voltage to the first node, a resistance of a path from the fourth node to the first node is greater than a resistance of a path from the second node to the first node. While the first circuit outputs the second voltage to the first node and the third circuit outputs the fourth voltage to the first node, resistance of a path from the fifth node to the first node is greater than resistance of a path from the third node to the first node. The semiconductor device according to claim 1 , wherein The third circuit further includes a switch between the first node and the first input terminal or between the first node and the first output terminal. The first circuit is further configured to receive a second signal whose voltage alternately switches between a third level and a fourth level, When the switch is located between the first node and the first input terminal, the switch connects the first node to the first input terminal during a first period when the second signal is at the third level, and disconnects the first node from the first input terminal during a second period when the second signal is at the fourth level. When the switch is located between the first node and the first output terminal, the switch connects the first node and the first output terminal during the first period, and disconnects the first node and the first output terminal during the second period.

9. The semiconductor device according to claim 2, wherein The semiconductor device further includes a fourth circuit, The fourth circuit includes a delay circuit for delaying the second signal, and is configured to output a third signal generated based on the second signal. The third circuit further includes a switch between the first node and the first input terminal or between the first node and the first output terminal. When the switch is located between the first node and the first input terminal, the switch connects the first node to the first input terminal during a first period when the third signal is at the third level, and disconnects the first node from the first input terminal during a second period when the third signal is at the fourth level. When the switch is located between the first node and the first output terminal, the switch connects the first node and the first output terminal during the first period, and disconnects the first node and the first output terminal during the second period.

10. The semiconductor device according to claim 2, wherein The second circuit includes a second inverter having a second input terminal connected to the first node and a second output terminal connected to a second node. The semiconductor device further includes a fourth circuit, The fourth circuit includes a delay circuit for delaying the voltage signal at the second node, and is configured to output a third signal generated based on the second signal. The third circuit further includes a switch between the first node and the first input terminal or between the first node and the first output terminal. When the switch is located between the first node and the first input terminal, the switch connects the first node to the first input terminal during a first period when the third signal is at the third level, and disconnects the first node from the first input terminal during a second period when the third signal is at the fourth level. When the switch is located between the first node and the first output terminal, the switch connects the first node and the first output terminal during the first period, and disconnects the first node and the first output terminal during the second period.

11. The semiconductor device according to claim 2, wherein The second circuit includes a second inverter having a second input terminal connected to the first node and a second output terminal connected to a second node. The semiconductor device further comprises: a fourth circuit connected to the second node and the third node, receiving the second signal and latching data generated based on the voltage of the second node according to the second signal; and a fifth circuit including an XOR gate or an XNOR gate connected to the third node and the second node, and configured to output a third signal generated based on the second signal; The third circuit further includes a switch between the first node and the first input terminal or between the first node and the first output terminal. When the switch is located between the first node and the first input terminal, the switch connects the first node to the first input terminal during a first period when the third signal is at the third level, and disconnects the first node from the first input terminal during a second period when the third signal is at the fourth level. When the switch is located between the first node and the first output terminal, the switch connects the first node and the first output terminal during the first period, and disconnects the first node and the first output terminal during the second period.

12. The semiconductor device according to claim 1, wherein The semiconductor device further comprises: a fourth circuit connected to a preceding stage of the first circuit and having a second node; and a fifth circuit configured to output a second signal generated based on the voltage of the second node; The third circuit further includes a switch between the first node and the first input terminal or between the first node and the first output terminal. When the switch is located between the first node and the first input terminal, the switch connects the first node to the first input terminal during a first period when the second signal is at a third level, and disconnects the first node from the first input terminal during a second period when the second signal is at a fourth level. When the switch is located between the first node and the first output terminal, the switch connects the first node and the first output terminal during the first period, and disconnects the first node and the first output terminal during the second period.

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