Resistive random access memory and method for manufacturing the same

Abstract

A resistive random access memory includes: a memory cell including a resistor element whose resistance changes according to a write operation, and storing data according to the resistance of the resistor element; a reference resistor element whose resistance is set to a first value; a voltage line set to a first voltage during a first write operation, during which the resistance of the resistor element changes from a second value higher than the first value to the first value; and a voltage control circuit arranged between first ends of two resistor elements. During the first write operation, the voltage control circuit adjusts the value of the first voltage supplied from the voltage line to reduce the difference between the currents flowing through the two resistor elements, and supplies the adjusted first voltage to the first ends of the two resistor elements.

Description

Technical Field

[0001] The invention relates to a resistive random access memory and a method for manufacturing the resistive random access memory. Background Art

[0002] Resistive random access memory (sometimes also referred to as "ReRAM") refers to a semiconductor memory or semiconductor memory device having a memory cell that stores data according to resistance. The memory cell of the resistive random access memory has a resistor element including a metal oxide sandwiched between a pair of electrodes. The resistance of the resistor element changes according to the voltage applied to the resistor element. The logic level or value of the data stored in the memory cell is determined according to the current flowing through the resistor element in accordance with the resistance of the resistor element.

[0003] In order to improve the accuracy of the resistance of the resistance element set by writing data, the following write control is performed. For example, data can be written in the following manner: a current from a constant current source is supplied to a resistance element of a replica cell having the same structure as a memory cell, and a voltage is applied to the resistance element of the memory cell, which is the same as the voltage generated at the node connecting the constant current source and the replica cell (for example, see Japanese Patent Gazette No. 2009-093687). In addition, data can be written in the following manner: the resistance is determined by comparing the voltage appearing on the bit line during a confirmation read operation before writing with a plurality of reference voltages, and the write amplifier is controlled according to the determination result of the resistance (for example, see Japanese Patent Gazette No. 2014-203505).

[0004] Generally, a resistive random access memory (chip) has a large number of resistor elements, and the resistance of the resistor elements varies according to process variations in the manufacturing process of the resistive random access memory and the position of the resistor elements on the chip. The change in resistance is manifested as a change in the read current read from the memory cell during the read operation of the resistive random access memory. Therefore, the read current change deteriorates the read margin.

[0005] When the change in resistance of the resistance element is reduced by performing a confirmation read operation before writing data, a circuit for performing the confirmation read operation is required. In addition, since the confirmation read operation is included in the data writing cycle, the data writing cycle is extended. Summary of the invention

[0006] Therefore, an aspect of an embodiment of the present invention is to provide a resistive random access memory and a method for manufacturing the resistive random access memory, which can reduce the change in resistance of the resistor element when writing data into the resistive random access memory without performing a confirmation read operation and improve the read margin.

[0007] According to one aspect of an embodiment of the present invention, a resistive random access memory includes: a storage unit, including a first resistance element whose resistance changes according to a write operation, and the storage unit is configured to store data according to the resistance of the first resistance element; a first reference resistance element, whose resistance is set to a first value; a first voltage line, which is set to a first voltage during a first write operation, during which the resistance of the first resistance element changes from a second value higher than the first value to the first value; and a first voltage control circuit, which is arranged between a first end of the first resistance element and a first end of the first reference resistance element, and is configured to adjust the value of a first voltage supplied from the first voltage line during the first write operation to reduce the difference between currents flowing through the first resistance element and the first reference resistance element, and supply the adjusted first voltage to the first end of the first resistance element and the first end of the first reference resistance element. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating an example of a resistive random access memory according to one embodiment.

[0009] Figure 2 It is shown Figure 1 2 is a characteristic diagram of an example of the current-voltage characteristics of the resistance element of the memory cell shown in FIG.

[0010] Figure 3 It is shown Figure 1 An operation diagram of an example of a set write operation of a memory cell of a resistive random access memory is shown in FIG.

[0011] Figure 4 It is shown Figure 1 0 is a timing diagram of an example of a set write operation of a resistive random access memory shown in .

[0012] Figure 5 It is shown Figure 1 FIG. 4 is a timing diagram of another example of a set write operation of a resistive random access memory shown in FIG.

[0013] Figure 6 Yes Description Figure 1 An example of the effect of a set write operation on a resistive random access memory is shown in FIG.

[0014] Figure 7 is a block diagram illustrating an example of a resistive random access memory according to another embodiment.

[0015] Figure 8 It is shown Figure 7 An operation diagram of an example of a set write operation of a memory cell of a resistive random access memory is shown in FIG.

[0016] Fig. 9is a block diagram illustrating an example of a resistive random access memory according to another embodiment.

[0017] Fig.10 is a block diagram illustrating an example of a resistive random access memory according to another embodiment.

[0018] Fig.11 It is shown Fig.10 An operation diagram of an example of a reset write operation of a memory cell of a resistive random access memory shown in FIG.

[0019] Fig.12 is a block diagram illustrating an example of a resistive random access memory according to another embodiment.

[0020] Fig.13 It is shown Fig.12 0 is a timing diagram of an example of a read operation of a resistive random access memory shown in FIG.

[0021] Fig.14 It is used to illustrate Fig.12 An example of the effect of a read operation on a resistive random access memory is shown in FIG.

[0022] Fig.15 is a block diagram illustrating an example of a resistive random access memory according to another embodiment.

[0023] Fig.16 It is shown Fig.15 An example circuit diagram of a portion of a memory core is shown in FIG.

[0024] Fig.17 is a block diagram showing an example of a resistive random access memory according to yet another embodiment.

[0025] Fig.18 It is shown Fig.17 0 is a timing diagram of an example of a set write operation of a resistive random access memory shown in .

[0026] Fig.19 is a block diagram illustrating an example of a resistive random access memory according to another embodiment.

[0027] Fig. 20 It is shown Fig.19 0 is a timing diagram of an example of a read operation of a resistive random access memory shown in FIG.

[0028] Fig.21 is a block diagram illustrating an example of a resistive random access memory according to another embodiment.

[0029] Fig. 22 It is shown Fig.210 is a timing diagram of an example of a multi-value set write operation of a resistive random access memory shown in .

[0030] Fig.23 is a block diagram illustrating an example of a resistive random access memory according to another embodiment.

[0031] Fig.24 It is shown Fig.23 0 is a timing diagram of an example of a read operation of a resistive random access memory shown in FIG.

[0032] Fig.25 It is shown Fig.23 A circuit diagram of an example of a sense amplifier is shown in .

[0033] Fig.26 is a block diagram illustrating an example of a resistive random access memory according to another embodiment.

[0034] Fig. 27 It is used to illustrate Fig.26 0 is a diagram of an example of a set write operation of a resistive random access memory shown in .

[0035] Fig.28 It is shown Fig.26 0 is a timing diagram of an example of a set write operation of a resistive random access memory shown in .

[0036] Fig.29 It is shown Fig.26 A block diagram of an example of states during a reset write operation of a resistive random access memory shown in FIG.

[0037] Fig.30 It is used to illustrate Fig.26 0 is a diagram of an example of a reset write operation of a resistive random access memory shown in .

[0038] Fig.31 It is shown Fig.26 0 is a timing diagram of an example of a reset write operation of a resistive random access memory shown in .

[0039] Fig.32 It is used to illustrate Fig.26 0 is a diagram of an example of a read operation of a resistive random access memory shown in FIG.

[0040] Fig.33 It is used to illustrate Fig.26 FIG. 4 is a diagram of another example of a read operation of a resistive random access memory shown in FIG. DETAILED DESCRIPTION

[0041] Preferred embodiments of the present invention will be described with reference to the accompanying drawings. A resistive random access memory and a method for manufacturing a resistive random access memory according to an embodiment of the present invention will now be described.

[0042] Hereinafter, a signal line that transmits information (such as a signal) is represented by the same name (or symbol) as the signal name. Similarly, a voltage line is represented by the same name (or symbol) as the voltage name, and a power line is represented by the same name (or symbol) as the power name.

[0043] Figure 1 An example of a resistive random access memory according to an embodiment is shown. Figure 1 The core of the resistive random access memory is shown in FIG. Figure 1 In the following figures, a transistor with a circular mark added to the gate represents a p-channel metal oxide semiconductor (MOS) transistor. A transistor without a circular mark added to the gate represents an n-channel MOS transistor. In the following, a p-channel MOS transistor and an n-channel MOS transistor may also be referred to as a transistor.

[0044] Figure 1 The resistive random access memory 100 shown includes a voltage control circuit VCNT1 for a set write operation, a transfer transistor TB, and a reference resistance element RRB. The resistive random access memory 100 also includes a sense amplifier SA for a read operation, and a voltage generation circuit VGEN for setting the voltage of the bit line BL and the source line SL during a set write operation, a reset write operation, and a read operation. The voltage generation circuit VGEN includes transistors P1, P2, N1, and N2. For example, the reference resistance element RRB is formed of polysilicon or the like, and its resistance is fixed to the resistance of the resistance element R1 in a low resistance state.

[0045] The resistive random access memory 100 further includes a memory cell MC connected between a bit line BL (BL0) and a source line SL. The memory cell MC includes a resistance element R1 and stores data according to the resistance of the resistance element R1, the resistance of which changes according to a write operation. The resistance element R1 is an example of a first resistance element.

[0046] A first end of the resistance element R1 is connected to the bit line BL0 via the transfer transistor T1. The other end (i.e., the second end) of the resistance element R1 is connected to the source line SL. One of the source and the drain of the transfer transistor T1 is connected to the resistance element R1. The other of the source and the drain of the transfer transistor T1 is connected to the bit line BL0. The gate of the transfer transistor T1 is connected to the word line WL.

[0047] The write operation to the memory cell MC includes a set write operation, which sets the resistance of the resistance element R1 from a high resistance state to a low resistance state, and a reset write operation, which sets the resistance of the resistance element R1 from a low resistance state to a high resistance state. The resistance in the low resistance state is an example of a first value. The resistance in the high resistance state is an example of a second value.

[0048] The set write operation is performed by supplying a current from the first end of the resistor element R1 connected to the bit line BL0 via the transfer transistor T1 to the second end of the resistor element R1 connected to the source line SL (i.e., from the bit line BL0 side of the resistor element R1 to the source line SL side). The reset write operation is performed by supplying a current from the source line SL side of the resistor element R1 to the bit line BL0 side. The set write operation is an example of the first write operation. The reset write operation is an example of the second write operation.

[0049] The voltage control circuit VCNT1 includes transistors PB1 and PB2, and an operational amplifier BAMP for a set write operation. The transistor PB1 is arranged between the bit line BL and the bit line BL0. The transistor PB2 is arranged between the bit line BL and the reference bit line RBL. The gates of the transistors PB1 and PB2 are connected to the output terminal of the operational amplifier BAMP and receive a control signal REGB output from the output terminal of the operational amplifier BAMP. The control signal REGB is an example of a first control signal.

[0050] Transistor PB1 is an example of a first variable resistance element having a resistance that varies according to control signal REGB, and forms an example of a first p-channel MOS transistor. Transistor PB2 is an example of a second variable resistance element having a resistance that varies according to control signal REGB, and forms an example of a second p-channel MOS transistor.

[0051] The inverting input terminal (-) of the operational amplifier BAMP is connected to the first end of the resistor element R1 via the bit line BL0 and the transfer transistor T1. The non-inverting input terminal (+) of the operational amplifier BAMP is connected to the first end of the reference resistor element RRB via the reference bit line RBL and the transfer transistor TB. The gate of the transfer transistor TB is connected to the reference word line RBWL, which is set to a high level during the set write operation. The other end (i.e., the second end) of the reference resistor element RRB is connected to the ground line VSS. The reference resistor element RRB is an example of a first reference resistor element.

[0052] During the set write operation, the operational amplifier BAMP operates upon receiving the amplifier enable signal BAMPEN having an effective level (e.g., a high level), and outputs the control signal REGB according to the voltage of the bit line BL0 and the voltage of the reference bit line RBL. During the set write operation, the transfer transistors T1 and TB are set to a conductive state. For this reason, during the set write operation, the operational amplifier BAMP compares the voltage at the first end of the resistor element R1 with the voltage at the first end of the reference resistor element RRB.

[0053] For example, when the voltage at the first end of the resistance element R1 is equal to the voltage at the first end of the reference resistance element RRB, the operational amplifier BAMP outputs a control signal REGB to cause a predetermined current to flow to the transistors PB1 and PB2. The operational amplifier BAMP is an example of a first voltage comparator and also an example of a first operational amplifier. The voltage control circuit VCNT1 is an example of a first voltage control circuit that adjusts the voltages of the bit line BL0 and the reference bit line RBL to reduce the difference between the currents flowing to the resistance element R1 and the reference resistance element RRB during the set write operation.

[0054] The amplifier enable signal BAMPEN supplied to the operational amplifier BAMP is set to a low level during the reset write operation and the read operation to stop the amplification operation of the operational amplifier BAMP and output the high-level control signal REGB. Therefore, the transistor PB1 is turned off, and the connection between the bit line BL and the bit line BL0 is cut off. At the same time, the control signal VSSBL presents a high level, and the bit line BL0 is connected to the ground line VSS via the transistor N1.

[0055] In the voltage generating circuit VGEN, transistor N1 has a drain connected to the bit line BL0, a source connected to the ground line VSS, and a gate receiving a control signal VSSBL. Transistor N2 has a drain connected to the source line SL, a source connected to the ground line VSS, and a gate receiving a control signal VSSSL.

[0056] Transistor P1 has a source connected to power supply line VDD, a drain connected to bit line BL, and a gate receiving control signal SETENB. Transistor P2 has a source connected to power supply line VDD, a drain connected to source line SL, and a gate receiving control signal RSTENB.

[0057] Transistor P1 supplies a voltage (VDD) to bit line BL, which is supplied to a first end of resistor element R1 and a first end of reference resistor element RRB during a set write operation. The voltage VDD supplied to the source of transistor P1 is an example of a first voltage. During a set write operation, transistor N2 generates a voltage (VSS) supplied to a second end of resistor element R1. The voltage VSS supplied to the second end of resistor element R1 is an example of a reference voltage, and the source line SL set to the reference voltage is an example of a reference voltage line.

[0058] The sense amplifier SA is connected to the source line SL and operates during a read operation that reads data from the memory cell MC. During the read operation, the control signals SETENB, RSTENB, and VSSBL are set to a high level, and the control signal VSSSL is set to a low level. The bit line BL0 is connected to the ground line VSS by the control signal VSSBL set to a high level during the read operation. In addition, the first end of the resistor element R1 is connected to the bit line BL0 via the word line WL set to a high level.

[0059] The sense amplifier SA will Figure 2 The read voltage Vread shown is output to the source line SL set to a floating state. The sense amplifier SA determines the logic of the data stored in the memory cell MC by comparing the read current Iread, which flows from the source line SL through the resistor element R1 through the bit line BL0, the transistor N1, and the ground line VSS, with the reference current Iref. The sense amplifier SA outputs a data signal DATA indicating the determined logic.

[0060] During the reset write operation of setting the resistance element R1 from the low resistance state to the high resistance state, the control signals SETENB and VSSBL are set to a high level, and the control signals RSTENB and VSSSL are set to a low level. Therefore, the transistors P2 and N1 are turned on, and the transistors P1 and N2 are turned off. In addition, when the word line WL is set to a high level, the current from the source line SL flows through the resistance element R1, the bit line BL0, the transistor N1 and the ground line VSS, and the resistance element R1 is set to a high resistance state.

[0061] The resistive random access memory 100 may include a plurality of memory cells MC arranged in a matrix. In this case, the resistive random access memory 100 includes Figure 1 A plurality of pairs of bit lines BL and source lines SL arranged in a horizontal direction, and Figure 1 In addition, Figure 1 In the vertical direction, a plurality of memory cells MC are arranged (but Figure 1) are commonly connected to a pair of bit lines BL and source lines SL. Figure 1 A plurality of memory cells MC are arranged horizontally in Figure 1 ) are connected to a common word line WL.

[0062] In addition, control signals SETENB and RSTENB are generated for each pair of bit line BL and source line SL. For example, during a set write operation, among a plurality of memory cells MC connected to a common word line WL, only a control signal SETENB corresponding to a memory cell MC on which a set write operation is performed is set to a low level. A control signal SETENB corresponding to a memory cell MC on which a set write operation is not performed is set to a high level.

[0063] Similarly, during the reset write operation, among the plurality of memory cells MC connected to the common word line WL, only the control signal RSTENB corresponding to the memory cell MC that performs the reset write operation is set to a low level. The control signal RSTENB corresponding to the memory cell MC that does not perform the reset write operation is set to a high level. Therefore, the set write operation or the reset write operation can be selectively performed on any memory cell MC among the plurality of memory cells MC connected to the common word line WL.

[0064] Figure 2 Shows Figure 1 . The current-voltage characteristic of the resistance element R1 of the memory cell MC shown in FIG. 1 represents a so-called hysteresis loop. For example, when a positive voltage (VBL0>VSL) is applied across the resistance element R1, a set write operation is performed, and the resistance element R1 changes from a high resistance state to a low resistance state. In addition, when a negative voltage (VSL>VBL0) is applied across the resistance element R1, a reset write operation is performed, and the resistance element R1 changes from a low resistance state to a high resistance state.

[0065] When a read voltage Vread is applied across the resistor element R1 set to a low resistance state (SET), a read current Iread greater than the reference current Iref flows. When a read voltage Vread is applied across the resistor element R1 set to a high resistance state (RESET), a read current Iread less than the reference current Iref flows. For this reason, by comparing the read current Iread with the reference current Iref, the resistance state of the resistor element R1 can be determined, and the logic of the data stored in the memory cell MC can be determined.

[0066] Figure 3 Shows Figure 1 An example of a set write operation of a memory cell MC of a resistive random access memory 100 is shown in FIG. That is, Figure 3An example of a control method for controlling the resistive random access memory 100 is shown.

[0067] like Figure 3 As shown in the upper right part of FIG. 1 , during the set write operation, the control signals SETENB and VSSBL are set to a low level L, and the control signals RSTENB and VSSSL are set to a high level H. For example, the word line WL and the reference word line RBWL are set to a high level higher than the power supply voltage VDD. The amplifier enable signal BAMPEN is set to a high level.

[0068] During the set write operation, the non-inverting input terminal (+) of the operational amplifier BAMP receives the voltage VRBL of the reference bit line RBL, and the inverting input terminal (-) of the operational amplifier BAMNP receives the voltage VBL0 of the bit line BL0. The operational amplifier BAMP outputs the control signal REGB having the voltage VREGB according to the voltage difference VRBL-VBL0 between the voltages VRBL and VBL0.

[0069] like Figure 3 As shown in the upper left part of FIG. 1 , when the voltage difference VRBL-VBL0 is a positive value, the operational amplifier BAMP outputs a voltage VREGB higher than the equilibrium voltage VEQ. When the voltage difference VRBL-BVL0 is a negative value, the operational amplifier BAMP outputs a voltage VREGB lower than the equilibrium voltage VEQ. When the voltages VRBL and VBL0 are equal to each other, the operational amplifier BAMP sets the voltage VREGB to the equilibrium voltage VEQ.

[0070] like Figure 1 As shown, transistors PB1 and PB2 of voltage control circuit VCNT1 have sources connected to bit line BL and gates receiving control signal REGB. For this reason, during a set write operation in which power supply voltage VDD is supplied to bit line BL, the same voltage is applied to resistor element R1 and reference resistor element RRB.

[0071] like Figure 3 As shown in the current-voltage characteristic shown in the lower left part, since the resistance of the reference resistance element RRB is fixed in the low resistance state, the current IRRB proportional to the increase in the voltage VRBL flows to the reference resistance element RRB, as shown by the dotted line. Figure 2 As shown, as the voltage VBL0 increases, the current IR1 in the high-resistance state flows first, and after changing from the high-resistance state to the low-resistance state, the current IR1 in the low-resistance state flows.

[0072] Due to the control of the voltage control circuit VCNT1, the increase in current IR1 is equal to the increase in current IRRB, and no further increase occurs. For this reason, during the set write operation, the resistance of the resistance element R1 can be set to the resistance of the reference resistance element RRB (low resistance state). Because the resistance of the resistance element R1 can be set to match the resistance of the reference resistance element RRB, the resistance of the resistance element R1 can be set to a predetermined resistance even if the electrical characteristics of the resistance element R1 vary. For example, during the manufacturing process of the resistive random access memory 100, the electrical characteristics of the resistance element R1 may vary depending on the position on the wafer, and may also vary between wafers and batches.

[0073] At the beginning of the set write operation, the resistor element R1 is in a high resistance state, and the reference resistor element RRB is in a low resistance state. Figure 3 As shown on the right side of FIG. 1 , the current IR1 flowing through the resistance element R1 is smaller than the current IRRB flowing through the reference resistance element RB. Since the current IR1 is smaller, the voltage VBL0 becomes higher than the voltage VRBL, and the operational amplifier BAMP sets the voltage of the control signal REGB to be lower than the equilibrium voltage VEQ when the set write operation starts.

[0074] As the resistance element R1 changes from a high resistance state to a low resistance state, the current IR1 flowing through the resistance element R1 increases. When the voltage of the bit line BL0 decreases according to the increase of the current IR1, the operational amplifier BAMP increases the voltage VREGB of the control signal REGB according to the decrease of the voltage of the bit line BL0. Therefore, the on-resistance of the transistors PB1 and PB2 increases, the current IRRB decreases, and the increase of the current IR1 becomes gentle.

[0075] The operational amplifier BAMP controls the voltage VREGB so that the voltages VBL0 and VRBL are equal and the currents IR1 and IRRB are equal to each other. The value of the voltage VREGB in this state changes according to the change in the characteristics of the resistance element R1. When the resistance element R1 changes to the low resistance state at a lower voltage, the voltage VREGB becomes a larger value because both the currents IRRB and IR1 are smaller.

[0076] Figure 4 Shows Figure 1 An example of a set write operation of the resistive random access memory 100 shown in FIG. That is, Figure 4 An example of a control method for controlling the resistive random access memory 100 is shown. Figure 4 In FIG. 1 , after voltage is applied to the bit line BL0 and the reference bit line RBL, the transfer transistors T1 and TB are turned on. Figure 4 At the beginning of the set write operation in , it is assumed that the resistor element R1 is in a high impedance state. Figure 4As shown in (a), the control signals SETENB and VSSBL are set to low level, and Figure 4 As shown in (b), the control signal VSSSL and the amplifier enable signal BAMPEN are set to high level to start Figure 4 When the amplifier enable signal BAMPEN turns to a high level, the operation of the operational amplifier BAMP starts. The control signal RSTENB is set to a high level.

[0077] like Figure 4 As shown in (c) in FIG. 1 , the bit line BL is set to a high level by a low-level control signal SETENB, and the source line SL is set to a low level by a high-level control signal VSSL. Because the control signal REGB is at a low level in the initial state, transistors PB1 and PB2 are turned on, and the voltage of the bit line BL0 and the voltage of the reference bit line RBL both increase, as shown in FIG. Figure 4 As shown in (d) in FIG. 1 , since the voltage of the bit line BL0 is approximately equal to the voltage of the reference bit line RBL, the operational amplifier BAMP increases the control signal REGB to the equilibrium voltage VEQ, as shown in FIG. Figure 4 As shown in (e) in .

[0078] Next, the word line WL and the reference word line RBWL are set to a high level, and the transfer transistors T1 and TB are turned on. Figure 4 As shown in (f) in FIG. 1 , the first end of the resistor element R1 is connected to the bit line BL0 via the transfer transistor T1, and the first end of the reference resistor element RRB is connected to the reference bit line RBL via the transfer transistor TB. In addition, current starts to flow through the resistor element R1 and the reference resistor element RRB.

[0079] like Figure 4 As shown in (g) in FIG. 1 , the current IR1 flowing through the resistor element R1 in the high resistance state is smaller than the current IRRB flowing through the reference resistor element RRB in the low resistance state. For this reason, the voltage of the bit line BL0 gradually decreases from the voltage of the reference bit line RBL, as shown in FIG. Figure 4 As shown in (h) in FIG. 1 , because the voltage of the bit line BL0 becomes higher than the voltage of the reference bit line RBL, the operational amplifier BAMP reduces the voltage of the control signal REGB, as shown in FIG. Figure 4 As shown in (i) in .

[0080] When the resistance of the resistor element R1 changes from a high resistance state to a low resistance state according to the current flowing through the resistor element R1, the voltage of the control signal REGB increases according to the feedback control of the operational amplifier BAMP, such as Figure 4 As shown in (j) in FIG. 1 , the increase of the current IR1 flowing through the resistor element R1 becomes gentle, as shown in FIG. Figure 4 As shown in (k) in FIG. 1 , the current IRB flowing through the reference resistor element RRB decreases, as shown in FIG. Figure 4 As shown in (m), the voltage of the reference bit line RBL increases, as shown in Figure 4 As shown in (l) in .

[0081] Finally, the voltage of the bit line BL0 and the voltage of the reference bit line RBL become equal, as shown in FIG. Figure 4 In this state, the value of the voltage VREGB changes according to the change in the characteristics of the resistor R1. Finally, the smaller the currents IRRB and IR1 are, the larger the voltage VREGB is, as shown in Figure 4 As shown in (o) in .

[0082] Thereafter, the word line WL and the reference word line RBWL are set to a low level, such as Figure 4 As shown in (p) in FIG. 1 , current is prevented from flowing through the resistance element R1 and the reference resistance element RRB, and the voltages of the bit line BL0 and the reference bit line RBL are turned into a high level, as shown in FIG. Figure 4 As shown in (q) in FIG. 1 , the levels of the control signals SETENB, VSSBL, and VSSSL, and the amplifier enable signal BAMPEN return to the levels of the initial states, and the set write operation is completed.

[0083] Figure 5 Shows Figure 1 Another example of the set write operation of the resistive random access memory 100 shown in FIG. That is, Figure 5 Another example of a control method for controlling the resistive random access memory 100 is shown. Figure 4 The same operation is described in detail. Figure 5 In the embodiment, after the transfer transistors T1 and TB are turned on, a voltage is applied to the bit line BL0 and the reference bit line RBL.

[0084] exist Figure 5 In the embodiment, the word line WL and the reference word line RBWL are set to a high level at the same timing as the amplifier enable signal BAMPEN turns to a high level. Figure 5 As shown in (a) in FIG. 1 . When the operational amplifier BAMP starts operating in response to the high-level amplifier enable signal BAMPEN, the bit line BL0 and the reference bit line RBL are at a low level. For this reason, the operational amplifier BAMP increases the control signal REGB to the equilibrium voltage VEQ, as shown in FIG. Figure 5 As shown in (b) in .

[0085] Next, the control signal SETENB is set to a high level, and the transistor P1 is turned on. Figure 5 As shown in (c) in FIG. Therefore, the current starts to flow to the resistor element R1 and the reference resistor element RRB, as shown in FIG. Figure 5As shown in (d) in FIG. 1 , because the resistance element R1 is in the high resistance state, the current IR1 flowing through the resistance element R1 is smaller than the current IRRB flowing through the reference resistance element RRB corresponding to the low resistance state.

[0086] The voltage of the reference bit line RBL through which a relatively large current IRRB flows gradually increases, while the voltage of the bit line BL0 through which a relatively small current IR1 flows increases sharply, as shown in FIG. Figure 5 As shown in (e) in FIG. 1 , as the potential difference between the bit line BL0 and the reference bit line RBL increases, the operational amplifier BAMP reduces the voltage of the control signal REGB, as shown in FIG. Figure 5 As shown in (f) in FIG. Thereafter, as the voltage difference between the bit line BL0 and the reference bit line RBL decreases, the operational amplifier BAMP increases the control signal REGB until the voltage of the bit line BL0 matches the voltage of the reference bit line RBL, as shown in FIG. Figure 5 As shown in (g) in .

[0087] Then the control signal SETENB is set to high level, as Figure 5 As shown in (h) in FIG. 1 , the current supply from the bit line BL stops, and the voltages of the bit lines BL and BL0 and the reference bit line RBL turn to a low level, which is the voltage of the source line SL, as shown in FIG. Figure 5 Therefore, the current no longer flows to the resistor element R1 and the reference resistor element RRB, as shown in (j) and (i) in FIG. Figure 5 Then, the levels of the control signal VSSBL, the word line WL, the reference word line RBWL and the amplifier enable signal BAMPEN return to the levels of the initial state, and the set write operation is completed.

[0088] Figure 6 Shows Figure 1 An example of the effect of a set write operation of the resistive random access memory 100 shown in . In this embodiment, when the resistance of the resistor element R1 becomes equal to the resistance of the reference resistor element RRB, the reduction in the resistance of the resistor element R1 is limited during the set write operation, and the resistance does not decrease further. Therefore, even if the electrical characteristics of the resistor element R1 change, the resistance can be kept constant after the set write operation. For this reason, during the read operation, when the read voltage Vread is applied to both ends of the resistor element R1, the current IR1 flowing through the resistor element R1 can be kept constant. Therefore, it can be ensured that the difference between the current IR1 and the reference current Iref during the read operation is greater than or equal to a predetermined value, and the read margin can be improved.

[0089] In addition, even if the electrical characteristics of the resistor element R1 change, the voltage control circuit VCNT1 controls the reduction of the resistance of the resistor element R1 through resistance, so that overwriting when the resistance of the resistor element R1 is excessively reduced can be prevented. Because the load applied to the resistor element R1 can be reduced during the write operation, and the degradation of the resistor element R1 can be prevented, the reliability of the resistive random access memory 100 can be improved. Because no wasteful current flows during the set write operation, the write power of the resistive random access memory 100 can be reduced.

[0090] In contrast, in other resistive random access memories that perform a set write operation by limiting the current IR1 flowing through the resistor element R1, the resistance in the low resistance state changes according to the change in the electrical characteristics of the resistor element R1. Therefore, the reference current Iref is set according to the resistor element R1 through which the small current IR1 flows during the read operation. Therefore, not only the read margin of the resistor element R1 in the low resistance state is reduced, but also the read margin of the resistor element R1 in the high resistance state is reduced.

[0091] As described above, during the set write operation in the present embodiment, the resistance of the resistor element R1 can be set to the resistance (low resistance state) of the reference resistor element RRB by the control of the voltage control circuit VCNT1. Therefore, even if the electrical characteristics of the resistor element R1 change, the resistance of the resistor element R1 in the low resistance state can be set to a predetermined resistance, and the read margin during the read operation can be improved. Because there is no need to perform a confirmation read operation in advance, the resistance of the resistor element R1 in the low resistance state can be set to a predetermined resistance, and the read margin can be improved without setting a plurality of determination circuits for confirming the read operation in the resistive random access memory 100. For this reason, a resistive random access memory 100 with a reduced chip size can be designed.

[0092] The voltage control circuit VCNT1 includes an operational amplifier BAMP serving as a voltage comparator for comparing the voltages of the bit line BL0 and the reference bit line RBL. In addition, the voltage control circuit VCNT1 includes transistors PB1 and PB2 serving as variable resistance elements having resistances that vary according to the voltage VREGB output from the operational amplifier BAMP.

[0093] Therefore, the voltage control circuit VCNT1 can control the current flowing through the resistance element R1 and the current flowing through the reference resistance element RRB to become equal according to the difference between the voltages of the bit line BL0 and the reference bit line RBL. Therefore, the resistance of the resistance element R1 can be automatically adjusted to the resistance of the reference resistance element RRB by feedback control, which controls the current according to the current flowing through the resistance element R1 and the reference resistance element RRB, without measuring the current or voltage.

[0094] By using p-channel MOS transistors PB1 and PB2 as variable resistance elements, the configuration of the voltage control circuit VCNT1 can be simplified. Therefore, even if the voltage control circuit VCNT1 is provided for each bit line BL, the increase in chip size of the resistive random access memory 100 can be reduced.

[0095] Figure 7 An example of a resistive random access memory according to another embodiment is shown. Figure 7 In, with Figure 1 Like elements are denoted by the same reference numerals, and a detailed description thereof will be omitted. Figure 7 The configuration of the resistive random access memory 102 shown is similar to Figure 1 The configuration of the resistive random access memory 100 shown is similar, except that the second end of the reference resistance element RRB is connected to a voltage line set to an offset voltage Voffset instead of being connected to a ground line VSS. The ground voltage is an example of a reference voltage, and the ground line VSS is an example of a reference voltage line. The offset voltage Voffset is an example of a voltage higher than the reference voltage, and the offset voltage line Voffset is an example of a voltage line higher than the reference voltage.

[0096] In the resistive random access memory 102, the amplification operation of the operational amplifier BAMP is stopped during the reset write operation and the read operation to output the high-level control signal REGB. Therefore, the transistor PB1 is turned off, and the connection between the bit line BL and the bit line BL0 is cut off. At the same time, the control signal VSSBL presents a high level, and the bit line BL0 is connected to the ground line VSS via the transistor N1.

[0097] Figure 8 Shows Figure 7 An example of a set write operation of a memory cell of the resistive random access memory 102 shown in FIG. That is, Figure 8 An example of a control method for controlling the resistive random access memory 102 is shown. Figure 4 The input-output characteristics of the operational amplifier BAMP are similar to those of Figure 3 Same as in.

[0098] Because the second end of the reference resistance element RRB is set to the offset voltage Voffset, no current flows to the reference resistance element RRB until the voltage VRBL of the reference bit line RBL exceeds the offset voltage Voffset. Figure 8 The current-voltage characteristic curve is shown in the lower left part of Figure 3Similarly, as the voltage VBL0 of the bit line BL0 increases, the current IR1 of the resistance element R1 initially flows in the high resistance state, and after changing from the high resistance state to the low resistance state, the current IR1 flows in the low resistance state. By the control of the voltage control circuit VCNT1, the increase of the current IR1 is the same as the increase of the current IRRB, and no longer increases.

[0099] exist Figure 8 During the set write operation shown on the right, the operation until the voltage VREGB of the control signal REGB reaches the equilibrium value is the same as Figure 3 In this embodiment, according to the offset voltage Voffset, the voltage of the reference bit line RBL during the set write operation is Figure 3 For this reason, compared to the voltage during the set write operation shown in Figure 3 In comparison, the current IRRB flowing through the reference resistance element RRB is smaller.

[0100] Next, after the voltage VREGB reaches the equilibrium value, if the current IR1 slightly exceeds the current IRRB and the voltage VREGB becomes higher than the equilibrium value, the current IRRB becomes smaller than the current IR1. Therefore, the voltage of the reference bit line RBL becomes higher than the voltage of the bit line BL0, and the voltage BREGB output from the operational amplifier BAMP increases to the upper limit indicated by the input-output characteristic of the operational amplifier BAMP.

[0101] For this reason, transistors PB1 and PB2 are turned off, and currents IR1 and IRRB no longer flow. Therefore, during the set write operation of the present embodiment, the application of voltage to the resistor element R1 can be automatically terminated without returning the word line WL and the reference word line RBWL to a low level, and without returning the control signal SETENB to a high level. Therefore, the voltage applied to the resistor element R1 can be minimized, and the amount of current flowing to the resistor element R1 during the set write operation can be minimized. In addition, the degradation of the resistor element R1 can be prevented, and the reliability of the resistive random access memory 102 can be improved.

[0102] As described above, the present embodiment can obtain effects similar to those obtainable by the above-described embodiments. For example, even if the electrical characteristics of the resistance element R1 vary, the resistance of the resistance element R1 in the low resistance state can be set to a predetermined resistance, and the read margin during the read operation can be improved.

[0103] Further, during the set write operation of the present embodiment, the second end of the reference resistor element RRB is set to the offset voltage Voffset, so that the voltage applied to the resistor element R1 can be automatically terminated based on setting the resistor element R1 to the low resistance state. Therefore, the voltage applied to the resistor element R1 can be minimized, and the amount of current flowing to the resistor element R1 during the set write operation can be minimized. In addition, the degradation of the resistor element R1 can be prevented, and the reliability of the resistive random access memory 102 can be improved.

[0104] Fig. 9 An example of a resistive random access memory according to another embodiment is shown. Fig. 9 In, with Figure 1 Like elements are denoted by the same reference numerals, and a detailed description thereof will be omitted. Fig. 9 The configuration of the resistive random access memory 104 shown is similar to Figure 1 The configuration of the resistive random access memory 100 shown in FIG. 1 is different in that an n-channel MOS transistor TD having a diode connection is provided instead of the reference resistance element RRB. The transistor TD has a drain and a gate connected to the transfer transistor TB, and a source connected to the ground line VSS. Therefore, the characteristics of the current flowing to the reference bit line RBL can be made similar to those of Figure 8 The lower left portion shows the characteristics of the current IRRB flowing to the reference resistance element RRB.

[0105] During the reset write operation and read operation of the resistive random access memory 104, the operational amplifier BAMP stops the amplification operation and outputs the high-level control signal REGB. Therefore, the transistor PB1 is turned off, and the connection between the bit line BL and the bit line BL0 is cut off. At the same time, the control signal VSSBL presents a high level, and the bit line BL0 is connected to the ground line VSS via the transistor N1.

[0106] As described above, the present embodiment can obtain effects similar to those obtainable by the above-described embodiments. For example, even if the electrical characteristics of the resistance element R1 change, the resistance of the resistance element R1 in the low resistance state can be set to a predetermined resistance, and the read margin during the read operation can be improved. In addition, the voltage applied to the resistance element R1 can be minimized, and the amount of current flowing to the resistance element R1 during the set write operation can be minimized. Therefore, the degradation of the resistance element R1 can be prevented, and the reliability of the resistive random access memory 104 can be improved.

[0107] Fig.10 An example of a resistive random access memory in another embodiment is shown. Fig.10 In, with Figure 1Like elements are denoted by the same reference numerals, and a detailed description thereof will be omitted. Fig.10 The resistive random access memory 106 shown includes a voltage control circuit VCNT2 for controlling a reset write operation, instead of Figure 1 The voltage control circuit VCNT1 shown. The resistive random access memory 106 also includes a transmission transistor TS and a reference resistor element RRS to replace Figure 1 The transfer transistor TB and the reference resistance element RRB are shown. In other aspects, Fig.10 The configuration of the resistive random access memory 106 shown is similar to Figure 1 The configuration of the resistive random access memory 100 is shown. For example, the reference resistor element RRS is made of polysilicon or the like, and its resistance is fixed to the resistance of the resistor element R1 in the high resistance state.

[0108] The voltage control circuit VCNT2 includes transistors PS1 and PS2, and an operational amplifier SAMP for resetting the write operation. The transistor PS1 is arranged between the source line SL and the source line SL0. The transistor PS2 is arranged between the source line SL and the reference source line RSL. The gates of the transistors PS1 and PS2 are connected to the output terminal of the operational amplifier SAMP and receive the control signal REGS output by the operational amplifier SAMP. The control signal REGS is an example of the second control signal.

[0109] Transistor PS1 is an example of a third variable resistance element having a resistance that varies according to control signal REGS, and forms an example of a third p-channel MOS transistor. Transistor PS2 is an example of a fourth variable resistance element having a resistance that varies according to control signal REGS, and forms an example of a fourth p-channel MOS transistor.

[0110] The non-inverting input terminal (+) of the operational amplifier SAMP is connected to the source line SL0 and is connected to the second end of the resistor element R1 via the source line SL0. The inverting input terminal (-) of the operational amplifier SAMP is connected to the first end of the reference resistor element RRS via the transfer transistor TS. The gate of the transfer transistor TS is connected to the reference word line RSWL, which is set to a high level during the reset write operation. The other end (i.e., the second end) of the reference resistor element RRS is connected to the ground line VSS. The reference resistor element RRS is an example of a second reference resistor element.

[0111] During the reset write operation, the operational amplifier SAMP operates upon receiving the amplifier enable signal SAMPEN having an effective level (e.g., a high level), and outputs the control signal REGS according to the voltage of the source line SL0 and the voltage of the reference source line RSL. During the reset write operation, the transfer transistors T1 and TS are set to a conductive state. For this reason, during the reset write operation, the operational amplifier SAMP compares the voltage at the second end of the resistor element R1 with the voltage at the first end of the reference resistor element RRS.

[0112] For example, when the voltage at the second end of the resistance element R1 is equal to the voltage at the first end of the reference resistance element RRS, the operational amplifier SAMP outputs a control signal REGS to supply a predetermined current to the transistors PS1 and PS2. The operational amplifier SAMP is an example of a second voltage comparator and forms an example of a second operational amplifier. The voltage control circuit VCNT2 is an example of a second voltage control circuit, which adjusts the voltages of the source line SL0 and the reference source line RSL to reduce the difference between the currents flowing to the resistance element R1 and the reference resistance element RRS during the reset write operation.

[0113] The amplifier enable signal SAMPEN supplied to the operational amplifier SAMP causes the operational amplifier SAMP to output a high-level control signal REGS during the set write operation and the read operation. Therefore, the transistor PS1 is turned off, and the connection between the source line SL and the source line SL0 is cut off. At the same time, the control signal VSSL presents a high level, and the source line SL0 is connected to the ground line VSS via the transistor N2.

[0114] During the set write operation, the control signals SETENB and VSSBL are set to a low level, the control signals RSTENB and VSSSL are set to a high level, and the word line WL is set to a high level. In addition, the power supply voltage VDD is supplied from the transistor P1 to the bit line BL, and the current flows from the bit line BL to the source line SL0 through the resistor element R1, thereby changing the resistor element R1 from a high resistance state to a low resistance state.

[0115] During the reset write operation, the control signals RSTENB and VSSSL are set to a low level, the control signals SETENB and VSSBL are set to a high level, the word line WL and the reference word line RSWL are set to a high level. In addition, the power supply voltage VDD is supplied from the transistor P2 to the source line SL, and the current flows from the source line SL to the bit line BL through the resistor element R1, thereby changing the resistor element R1 from a low resistance state to a high resistance state.

[0116] Transistor P2 is an example of a second voltage generating circuit that generates a voltage (VDD) supplied to the second end of resistor element R1 and the first end of reference resistor element RRS during a reset write operation. The voltage VDD supplied to the source of transistor P2 is an example of a second voltage. During a reset write operation, transistor N1 generates a voltage (VSS) supplied to the first end of resistor element R1. Fig.11 An example of a reset write operation is described.

[0117] During the read operation, similar to the above embodiment, the control signals SETENB, RSTENB and VSSSL are set to low level, the control signal VSSBL is set to high level, and the word line WL is set to high level. In addition, the sense amplifier SA is set to Figure 2 The read voltage Vread shown is output to the source line SL0, and the logic of the data stored in the memory cell MC is determined by comparing the read current Iread flowing through the resistance element R1 with the reference current Iref. The sense amplifier SA outputs a data signal DATA indicating the determined logic.

[0118] Fig.11 Shows Fig.10 An example of a reset write operation of a memory cell MC of the resistive random access memory 106 shown in FIG. That is, Fig.11 An example of a control method for controlling the resistive random access memory 106 is shown. Figure 3 Detailed description of the same operations in .

[0119] During the reset write operation, the non-inverting input terminal (+) of the operational amplifier SAMP receives the voltage VSL0 of the source line SL0, and the inverting input terminal (-) of the operational amplifier SAMP receives the voltage VRSL of the reference source line RSL. The operational amplifier SAMP outputs a control signal REGS having a voltage VREGS according to the difference VSL0-VRSL between the voltages VSL0 and VRSL.

[0120] like Fig.11 As shown in the upper left part of FIG. 1 , when the voltage difference VSL0-VRSL is a positive value, the operational amplifier SAMP outputs a voltage VREGS higher than the equilibrium voltage VEQ. When the voltage difference VSL0-VRSL is a negative value, the operational amplifier SAMP outputs a voltage VREGS lower than the equilibrium voltage VEQ. When the voltages VSL0 and VRSL are equal to each other, the operational amplifier SAMP sets the voltage VREGS to the equilibrium voltage VEQ.

[0121] like Fig.10As shown, transistors PS1 and PS2 of the voltage control circuit VCNT2 have sources connected to the source line SL and gates receiving the control signal REGS. For this reason, during a reset write operation in which the power supply voltage VDD is supplied to the source line SL, the same voltage is applied to the resistance element R1 and the reference resistance element RRS.

[0122] like Fig.11 As shown in the current-voltage characteristic shown in the lower left part of FIG, since the resistance of the reference resistance element RRS in the high resistance state is fixed, the current IRRS proportional to the increase in the voltage VRSL flows to the reference resistance element RRS, as shown by the dotted line. Figure 2 As shown, as the voltage VSL0 increases, the current IR1 in the low resistance state first flows, and after changing from the low resistance state to the high resistance state, the current IR1 decreases. The direction of the current IR1 flowing through the resistor element R1 during the reset write operation is opposite to the direction of the current IR1 flowing through the resistor element R1 during the set write operation.

[0123] Due to the control of the voltage control circuit VCNT2, the current IR1 flowing through the resistance element R1 that is transitioning to the high-resistance state decreases and becomes equal to the current IRRB. When the current IR1 becomes less than the current IRRS, the transition of the resistance element R1 to the high-resistance state is completed. For this reason, during the reset write operation, the resistance of the resistance element R1 can be set to the resistance of the reference resistance element RRS (high-resistance state). Because the resistance of the resistance element R1 increases according to the resistance of the reference resistance element RRS, the resistance of the resistance element R1 can be set to a predetermined resistance even if the electrical characteristics of the resistance element R1 change.

[0124] At the beginning of the reset write operation, the resistor element R1 is in a low resistance state and the reference resistor element RRS is in a high resistance state. Fig.11 As shown on the right side of , current IR1 is larger than current IRRS. As current IR1 begins to flow through resistance element R1 and resistance element R1 begins to transition from a low resistance state to a high resistance state, current IR1 decreases. As current IR1 decreases, voltage VSL0 of source line SL0 increases, and voltage difference VSL0-VRSL increases.

[0125] When the current IR1 becomes smaller than the current IRRS, the voltage difference becomes VSL0-VRSL>0, and the voltage VREGS of the control signal REGS increases sharply according to the input-output characteristics of the operational amplifier SAMP. Therefore, the currents of the transistors PS1 and PS2 decrease, and the voltage applied to the resistor elements R1 and RRS also decreases. In many cases, the current-voltage characteristic of the resistor element R1 is nonlinear, and the current reduction amount according to the voltage reduction is greater than the current reduction amount of the current flowing through the reference resistor element RR1. For this reason, the voltage difference VSL0-VRSL further increases, and the voltage applied to the resistor elements R1 and RRS continues to decrease according to the operation of the operational amplifier SAMP. Therefore, according to this embodiment, the reset write operation can be ended autonomously.

[0126] As described above, during the reset write operation of the present embodiment, even if the electrical characteristics of the resistance element R1 change, the resistance of the resistance element R1 can be set to correspond to the resistance of the reference resistance element RRS in the high resistance state. Therefore, the read margin during the read operation can be improved. In addition, the reset write operation can be terminated autonomously.

[0127] Fig.12 An example of a resistive random access memory according to another embodiment is shown. Fig.12 In, with Figure 1 and Fig.10 Elements similar to those shown are denoted by the same reference numerals, and detailed description thereof will be omitted. Figure 1 The voltage control circuit VCNT1 shown, Fig.12 The resistive random access memory 108 shown includes a voltage control circuit VCNT3 for controlling a read operation, a transmission transistor TR, a reference resistance element RRR, and a transistor P3. The resistive random access memory 108 also includes a latch LT to replace Figure 1 The sense amplifier SA is shown. In other aspects, Fig.12 The configuration of the resistive random access memory 108 shown is similar to Figure 1 The configuration of the resistive random access memory 100 is shown.

[0128] The voltage control circuit VCNT3 includes an operational amplifier RAMP for read operation and transistors PR1 and PR2. The transistor PR1 is arranged between the source line SL and the source line SL0. The transistor PR2 is arranged between the source line SL and the reference source line RSL. The gates of the transistors PR1 and PR2 are connected to the output terminal of the operational amplifier RAMP and receive the control signal REGR output from the operational amplifier RAMP. The control signal REGR is an example of the third control signal.

[0129] Transistor PR1 is an example of a fifth variable resistance element having a resistance that varies according to control signal REG, and forms an example of a fifth p-channel MOS transistor. Transistor PR2 is an example of a sixth variable resistance element having a resistance that varies according to control signal REGR, and forms an example of a sixth p-channel MOS transistor.

[0130] The inverting input terminal (-) of the operational amplifier RAMP is connected to the source line SL0, and is connected to the second end of the resistor element R1 via the source line SL0. The non-inverting input terminal (+) of the operational amplifier RAMP is connected to the first end of the reference resistor element RRR via the transfer transistor TR. The gate of the transfer transistor TR is connected to the reference word line RRWL, which is set to a high level during the read operation. The other end (i.e., the second end) of the reference resistor element RRR is connected to the ground line VSS. For example, the reference resistor element RRR is formed of polysilicon or the like, and the resistance is set to an intermediate value between the low resistance state of the resistor element R1 and the high resistance state of the resistor element R1. The reference resistor element RRR is an example of a third reference resistor element.

[0131] During the read operation, the operational amplifier RAMP operates upon receiving the amplifier enable signal RAMPEN having an effective level (e.g., a high level), and outputs the control signal REGR according to the voltage of the source line SL0 and the voltage of the reference source line RSL. During the read operation, the transfer transistors T1 and TR are set to a conductive state. For this reason, the operational amplifier RAMP compares the voltage at the second end of the resistance element R1 with the voltage at the first end of the reference resistance element RRR during the read operation.

[0132] For example, when the voltage at the second end of the resistance element R1 is equal to the voltage at the first end of the reference resistance element RRR, the operational amplifier RAMP outputs a control signal REGR to cause a predetermined current to flow to the transistors PR1 and PR2. The operational amplifier RAMP is an example of a third voltage comparator and forms an example of a third operational amplifier. The voltage control circuit VCNT3 is an example of a third voltage control circuit, which adjusts the voltages of the source line SL0 and the reference source line RSL to reduce the difference between the currents flowing to the resistance element R1 and the reference resistance element RRR during the read operation.

[0133] The amplifier enable signal RAMPEN supplied to the operational amplifier RAMP is set to a low level during the set write operation and the reset write operation to stop the amplification operation of the operational amplifier RAMP and output the high-level control signal REGB. Therefore, the transistor PR1 is turned off, and the connection between the source line SL and the source line SL0 is cut off. At the same time, the control signal VSSSL presents a high level, and the source line SL0 is connected to the ground line VSS via the transistor N2.

[0134] The transistor P3 has a source connected to the power supply line VDD, a drain connected to the source line SL, and a gate receiving a read enable signal RDENB which is set to a low level during a read operation and set to a high level during a set write operation and a reset write operation.

[0135] Transistor P3 is an example of a third voltage generating circuit that generates a voltage (VDD) supplied to the second end of the resistor element R1 and the first end of the reference resistor element RRS during a read operation. The voltage VDD supplied to the source of transistor P3 is an example of a third voltage. During a read operation, transistor N1 generates a voltage (VSS) supplied to the first end of the resistor element R1.

[0136] During the set write operation, the control signals SETENB and VSSBL are set to a low level, the control signals RSTENB, VSSSL and RDENB are set to a high level, and the word line WL is set to a high level. In addition, the power supply voltage VDD is supplied from the transistor P1 to the bit line BL, and the current flows from the bit line BL to the source line SL through the resistor element R1, thereby causing the resistor element R1 to change from a high resistance state to a low resistance state.

[0137] During the reset write operation, the control signals RSTENB and VSSSL are set to a low level, the control signals SETENB, VSSBL and RDENB are set to a high level, the word line WL and the reference word line RSWL are set to a high level. In addition, the power supply voltage VDD is supplied from the transistor P2 to the source line SL, and the current flows from the source line SL to the bit line BL through the resistance element R1, thereby causing the resistance element R1 to change from a low resistance state to a high resistance state.

[0138] During the read operation, the control signals SETENB, RSTENB and VSSBL are set to a high level, and the control signals VSSSL and RDENB are set to a low level. In addition, the word line WL is set to a high level. In addition, the latch LT operates in response to the sense amplifier enable signal SAEN activated during the read operation, and compares the voltage of the source line SL0 with the reference voltage VREF to determine the logic of the data stored in the memory cell MC. The latch LT outputs a data signal DATA indicating the determined logic.

[0139] During a read operation, the current flowing through the resistor element R1 in the set state (low resistance state) is greater than the current flowing through the reference resistor element RRR, and the voltage VSL0 of the source line SL0 is lower than the voltage VRSL of the reference source line RSL. During a read operation of the resistive random access memory 108, the current flowing through the resistor element R1 in the reset state (high resistance state) is less than the current flowing through the reference resistor element RRR, and the voltage VSL0 of the source line SL0 is higher than the voltage VRSL of the reference source line RSL.

[0140] During the read operation, similar to the voltage control circuit VCNT1, the voltage control circuit VCNT3 supplies current to the source line SL0 and the reference source line RSL. The voltage control circuit VCNT3 detects the difference between the voltage of the source line SL0 and the voltage of the reference source line RSL through the operational amplifier RAMP. The voltage control circuit VCNT3 performs feedback control so that the current IR1 flowing through the resistance element R1 and the current IRRR flowing through the reference resistance element RRR are equal. In addition, the latch LT receiving the voltage of the source line SL0 outputs a data signal DATA indicating logic according to the resistance set to the resistance element R1.

[0141] Fig.13 Shows Fig.12 An example of a read operation of the resistive random access memory 108 shown in FIG. That is, Fig.13 An example of a control method for controlling the resistive random access memory 108 is shown. First, an operation control circuit (not shown) provided in the resistive random access memory 108 sets the control signal VSSSL to a low level and sets the amplifier enable signal RAMPEN to a high level. Fig.13 The row encoder (not shown) provided in the resistive random access memory 108 sets the word line WL to be read and the reference word line RRWL to a high level, as shown in FIG. Fig.13 As shown in (b) in .

[0142] Because the control signal VSSBL is at a high level, the resistor element R1 is connected to the ground line VSS via the transfer transistor T1, and the source line SL0 is set to 0 V. The reference source line RSL is connected to the ground line VSS via the reference resistor element RRR and the transfer transistor TS, and is set to 0 V. The operational amplifier RAMP starts to operate in response to the high-level amplifier enable signal SAMPEN, and because there is no voltage difference between the inverting input terminal (-) and the non-inverting input terminal (+) of the operational amplifier RAMP, the control signal REGR having the equilibrium voltage VEQ is output, as shown in FIG. Fig.13 As shown in (c) in .

[0143] Next, the operation control circuit sets the read enable signal RDENB to a low level. Fig.13As shown in (d) in FIG. 1 , due to the low-level read enable signal RDENB, the source line SL is set to a high level, as shown in FIG. Fig.13 As shown in (d) in .

[0144] The source-drain resistances of the transistors PR1 and PR2 having gates receiving the equilibrium voltage VEQ are set to predetermined values, and the source line SL, the source line SL0, and the reference source line RSL are electrically connected. For this reason, the voltage of the source line SL is transmitted to the source line SL0 and the reference source line RSL, as shown in FIG. Fig.13 As shown in (f) in .

[0145] When the resistor element R1 is in the set state SET (low resistance state), the voltage of the source line SL0 decreases to a voltage lower than the voltage of the reference source line RSL, and the voltage of the control signal REGR increases. Fig.13 As shown in (g) in FIG. 1 . The voltage control circuit VCNT3 performs feedback control so that the current flowing through the source line SL0 and the reference source line RSL is equal. Fig.14 As shown on the left side of FIG, the currents flowing through the resistor element R1 and the reference resistor element RRR match in a relatively low voltage region. Due to feedback control, the increase in the voltage of the source line SL0 is small, and the current IR1 flowing through the resistor element R1 and the current IRRR flowing through the reference resistor element RRR are also small, as shown in FIG. Fig.13 As shown in (h) in FIG. 1 , because the voltage of the source line SL0 is lower than the reference voltage VREF, the latch LT determines that the resistor element R1 is in the set state SET and outputs a high-level data signal DATA, as shown by Fig.13 As shown in (i) in .

[0146] On the other hand, when the resistor element R1 is in the reset state RESET (high resistance state), the voltage of the source line SL0 increases to a voltage higher than the voltage of the reference source line RSL, such as Fig.13 As shown in (j) in FIG. 1 , the voltage of the control signal REGR decreases, as shown in FIG. Fig.13 As shown in (k) in FIG. 1 . The voltage control circuit VCNT3 performs feedback control so that the current flowing through the source line SL0 and the reference source line RSL is equal. Fig.14 As shown on the left side of FIG, the currents flowing through the resistor element R1 and the reference resistor element RRR match in a relatively high voltage region. Due to feedback control, the voltage of the source line SL0 increases, and the current IR1 flowing through the resistor element R1 and the current IRRR flowing through the reference resistor element RRR become larger, as shown in FIG. Fig.13 As shown in (l) in FIG. 1 , because the voltage of the source line SL0 is higher than the reference voltage VREF, the latch LT determines that the resistor element R1 is in the reset state RESET and outputs a low-level data signal DATA, as shown in FIG. Fig.13As shown in (m) in FIG. Thereafter, the levels of various control signals return to the levels in the initial state, and the reading operation is completed.

[0147] Fig.14 Shows Fig.12 An example of the effect of the read operation of the resistive random access memory 108 is shown in FIG. During the read operation of the present embodiment, data stored in the resistance element R1 is read by comparing a voltage VSL0 appearing on the source line SL0 according to the resistance of the resistance element R1 with a reference voltage VREF. Fig.14 The operation shown on the left side shows an example of a read operation when the resistance element R1 of the RRAM 108 is in a degraded state.

[0148] During the read operation, the voltage control circuit VCNT3 performs feedback control so that the current flowing through the resistance element R1 and the current flowing through the reference resistance element RRR are equal. For example, the voltage control circuit VCNT3 is designed so that the voltage VSL0 of the source line SL0 becomes 0.8V in the set state SET and becomes 2.0V in the reset state RESET.

[0149] During the read operation of the present embodiment, since the current flowing from the source line SL0 side to the bit line BL side of the resistance element R1 in the set state SET can be reduced, the resistance element R1 can be prevented from being changed to the reset state RESET according to the read operation. Therefore, the read operation can be performed without applying a high voltage to the resistance element R1 in the set state SET, and degradation of the resistance element R1 can be prevented.

[0150] On the other hand, during the read operation of the resistor element R1 in the reset state RESET, the current flowing through the resistor element R1 is larger than the current flowing in the set state SET. However, since the direction of the current flowing through the resistor element R1 from the source line SL0 side to the bit line BL side is the direction of the current that causes the transition to the reset state RESET, the reset state RESET of the resistor element R1 is maintained unaffected. Therefore, in the present embodiment, the read operation can be performed without deteriorating the reliability of the resistor element R1.

[0151] On the contrary, during a read operation of another resistive random access memory that reads data stored in the resistor element R1 by comparing the current flowing through the resistor element R1 with the reference current Iref, the following problem occurs. For example, if the electrical characteristics of the resistor element R1 deteriorate, the waveform of the current-voltage characteristic in the set state SET and the waveform of the current-voltage characteristic in the reset state RESET become close to each other. In this case, the read margin with respect to the reference current Iref decreases in both the set state SET and the reset state RESET. In addition, by increasing the voltage VSL applied to the resistor element R1, the reduction in the read margin can be compensated for the degraded read margin. However, because more current flows to the resistor element R1 in the set state SET with low resistance, a transition to the reset state RESET may occur. Therefore, the read operation using the reference current Iref may deteriorate the reliability of the resistor element R1 that is transitioned to the set state SET.

[0152] As described above, in the present embodiment, the resistive random access memory 108 controls the current flowing through the resistance element R1 by the feedback control of the voltage control circuit VCNT3 during the read operation, and reads data from the memory cell MC by comparing the voltage VSL0 of the source line SL0 with the reference voltage VREF. Therefore, during the read operation, the current flowing through the resistance element R in the set state SET from the source line SL0 side to the bit line BL side can be reduced, and the resistance element R1 can be prevented from being changed to the reset state RESET according to the read operation. Therefore, the read operation that does not deteriorate the reliability of the resistance element R1 can be performed.

[0153] Fig.15 An example of a resistive random access memory according to another embodiment is shown. Fig.15 In, with Figure 1 Elements similar to those shown are denoted by the same reference numerals, and detailed descriptions thereof will be omitted. Fig.15 In the example, adding a symbol “ / ” to a signal line indicates that multiple signal lines (eg, multiple bits) are provided. Fig.15 The resistive random access memory 110 shown includes an operation control circuit 10, an address buffer 20 and a memory core 30. The memory core 30 includes a row decoder 40, a memory cell array 50, a sense amplifier (SA) circuit 60, a write amplifier (WA) circuit 70, a column decoder 80 and a data input and output circuit 90.

[0154] The rectangular frame representing the RRAM 110 represents, for example, a semiconductor chip, and the double square marks on the rectangular frame represent external terminals. The external terminals may be pads provided on the periphery of the semiconductor chip, or bumps provided on the back side of the semiconductor chip.

[0155] The operation control circuit 10 receives a control signal CNT such as a chip selection signal, a write command signal, a read command signal, etc. supplied to an external terminal, and outputs various control signals for operating the memory core 30 according to the received control signal CNT.

[0156] The address buffer 20 receives the address signal AD supplied to the address terminal and outputs the received address signal AD to the row decoder 40 and the column decoder 80. If the address signal AD includes a row address signal and a column address signal, the row address signal AD is output to the row decoder 40, and the column address signal is output to the column decoder 80.

[0157] The row decoder 40 decodes the address signal AD and drives the word line WL and the reference word line (not shown) at a high level. The column decoder 80 decodes the address signal AD and controls the connection between the memory cell array 50 and the data input / output circuit 90 according to the decoded address signal AD.

[0158] The memory cell array 50 includes Fig.15 The memory cell array 50 includes a plurality of memory cells MC arranged in a matrix and arranged in the vertical and horizontal directions. Fig.15 In addition, the memory cell array 50 includes a plurality of word lines WL, which are arranged in the vertical direction and in the horizontal direction. Fig.15 The memory cells MC are arranged in the horizontal direction and in the vertical direction. The memory cells MC arranged in the vertical direction are connected to a common bit line BL and a common source line SL. The memory cells MC are arranged in the horizontal direction and connected to a common word line WL. Figure 1 The same as the memory cell MC shown in the figure.

[0159] The sense amplifier circuit 60 includes a plurality of sense amplifiers SA connected to the source lines SL, respectively. For example, the sense amplifiers SA may be Figure 1 Alternatively, the sense amplifier SA may include Fig.12 The voltage control circuit VCNT3, the transmission transistor TR, the reference resistance element RRR and the latch LT are shown.

[0160] The write amplifier circuit 70 includes a plurality of write amplifiers WA connected to the bit line BL and the source line SL pair, respectively. For example, the write amplifier WA includes Figure 1 or Figure 7 The voltage control circuit VCNT1, the transmission transistor TB, the reference resistance element RRB and the voltage generation circuit VGEN are shown. The write amplifier WA may include Fig. 9The voltage control circuit VCNT1, the transmission transistor TB, the transistor TD and the voltage generation circuit VGEN are shown. The write amplifier WA may include Fig.10 The voltage control circuit VCNT2, the transmission transistor TS, the reference resistance element RRS and the voltage generating circuit VGEN are shown.

[0161] The data input-output circuit 90 outputs the write data supplied to the data terminal DT to the column decoder 80, and outputs the read data output from the column decoder 80 to the data terminal DT. For example, the resistive random access memory 110 may include data terminals DT corresponding to 64 bits, and includes a memory cell array 50 for each data terminal DT.

[0162] Fig.16 Shows Fig.15 An example of the core of the memory core 30 is shown in FIG. For example, the memory core 30 includes Figure 1 The voltage control circuit VCNT1, the transmission transistor TB, the reference resistance element RRB and the voltage generating circuit VGEN are shown. Fig.16 In, omitted Figure 1 , and is supplied to the amplifier enable signal BAMPEN of the operational amplifier BAMP of the voltage control circuit VCNT1. The memory core 30 can set the second end of the reference resistance element RRB to the offset voltage Voffset, such as Figure 7 As shown, a transistor TD may be included to replace the reference resistance element RRB, such as Fig. 9 shown.

[0163] In addition, the memory core 30 includes Fig.10 The voltage control circuit VCNT2, the transmission transistor TS and the reference resistance element RRS shown, and Fig.12 The voltage control circuit VCNT3, the transmission transistor TR, the reference resistance element RRR, the latch LT and the transistor P3 are shown. The resistive random access memory 110 performs a set write operation, a reset write operation and a read operation, as described above in conjunction with the embodiment. Fig.16 In, omitted Fig.10 , and is supplied to the amplifier enable signal SAMPEN of the operational amplifier SAMP of the voltage control circuit VCNT2. Fig.12 , and is a diagram of the amplifier enable signal RAMPEN supplied to the operational amplifier RAMP of the voltage control circuit VCNT3.

[0164] The operational amplifiers BAMP, SAMP, and RAMP stop the amplification operation in their disabled state and output high-level control signals REGB, REGS, and REFR, respectively. Therefore, by turning off transistor PB1 or transistors PS1 and PR2, operations other than the intended target operation can be prevented from affecting the intended target operation during the set write operation, reset write operation, and read operation.

[0165] As described above, the present embodiment can obtain effects similar to those obtainable by the above-described embodiment.

[0166] In the example of the above embodiment, a current having the same amplitude is supplied to the resistance element R1 and the reference resistance element RRB, RRS or RRR. However, the resistance of the reference resistance element RRB, RRS or RRR can be set to n times the resistance of the resistance element R1, and the gate width of the transistor PB2, PS2 or PR2 can be set to 1 / n times its original gate width. In this case, the current consumption of the voltage control circuit VCNT1, VCNT2 or VCNT3 can be reduced.

[0167] In addition, a plurality of reference resistance elements RRB having mutually different resistances may be connected in parallel to the voltage control circuit VCNT1, and one of the plurality of reference resistance elements RRB may be selectively used during a set write operation, thereby enabling a plurality of resistances to be set for the resistance element R1. In this case, during a read operation, the logic of the multi-valued data stored in the memory cell MC may be determined by comparing the read voltage appearing on the source line SL with a plurality of reference voltages. The comparison of the read voltage with the plurality of reference voltages may be performed sequentially (i.e., one after the other) or in parallel. Therefore, a multi-valued resistive random access memory capable of reducing the reduction of the read margin may be obtained.

[0168] Fig.17 An example of a resistive random access memory according to another embodiment is shown. Fig.17 , elements similar to those shown in the above-described embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted. Fig.17 The resistive random access memory 112 shown includes a voltage control circuit VCNT4 to replace Figure 1 The voltage control circuit VCNT1 shown. In addition, the voltage generating circuit VGEN includes transistors P11 and P12 instead of transistor P1. In other aspects, Fig.17 The configuration of the resistive random access memory 112 is similar to Figure 1 The configuration of the resistive random access memory 100 is shown.

[0169] The voltage control circuit VCNT4 has a current mirror circuit including transistors PB3 and PB4 and a current mirror circuit including transistors NB3 and NB4. Transistor NB3 has a source connected to the first end of the resistor element R1 via the bit line BL and the transmission transistor T1, and a gate and a drain connected to each other. Transistor NB4 has a source connected to the first end of the reference resistor element RRB via the transmission transistor TB and a gate connected to the gate of transistor NB3.

[0170] Transistor PB3 has a drain connected to the drain of transistor NB3 and a source connected to power supply line VDD via transistor P11, which is turned on during the set write operation. Transistor PB4 has a drain connected to the drain of transistor NB4, a gate connected to the gate of transistor PB3, and a source connected to power supply line VDD via transistor P12, which is turned on during the set write operation.

[0171] When the control signal SETENB is set to a low level during the set write operation, the voltage control circuit VCNT4 adjusts the bit line BL and the reference bit line RBL to the same voltage. That is, the voltage control circuit VCNT4 performs control to supply the same current to the bit line BL and the reference bit line RBL. Because the voltage control circuit VCNT4 including the current mirror circuit does not have a feedback system including the operational amplifier BAMP, etc., when Figure 1 Compared with the voltage control circuit VCNT1 shown, the current flowing to the bit line BL and the reference bit line RBL can be controlled at high speed.

[0172] Similar to Figure 7 , the reference resistance element RRB may be connected to a voltage line set to an offset voltage Voffset. Alternatively, a Fig. 9 The transistors TB and TD shown are used instead of the reference resistance element RRB.

[0173] Fig.18 Shows Fig.17 An example of a set write operation of the resistive random access memory 112 shown in FIG. That is, Fig.18 An example of a control method for controlling the resistive random access memory 112 is shown. Figure 4 Detailed description of the same operation.

[0174] By setting the control signals SETENB and VSSBL to low level (such as Fig.18 ) and set the control signal VSSSL and the amplifier enable signal BAMPEN to a high level (as shown in (a) in FIG. Fig.18As shown in (b) in FIG. 1 , the set write operation starts. When the amplifier enable signal BAMPEN changes to a high level, the operation of the operational amplifier BAMP starts. The control signal RSTENB is set to a high level.

[0175] Due to the low level control signal SETENB, the current flows to Fig.17 In the double-layer current mirror circuit of the voltage control circuit VCNT4 shown in FIG. 1 , the voltage of the bit line BL0 and the voltage of the reference bit line RBL increase, as shown in FIG. Fig.18 As shown in (c) in .

[0176] Next, the word line WL and the reference word line RBWL are set to a high level, and current begins to flow through the resistor element R1 and the reference resistor element RRB, respectively. Fig.18 As shown in (d) and (e) in FIG. 1 , the current IR1 flowing through the resistance element R1 in the high resistance state is smaller than the current IRRB flowing through the reference resistance element RRB having a resistance corresponding to the low resistance state. For this reason, the voltage of the bit line BL0 drops more slowly than the voltage of the reference bit line RBL, as shown in FIG. Fig.18 As shown in (f) in .

[0177] Due to the current flowing through the resistance element R1, the resistance element R1 changes from a high resistance state to a low resistance state. Then, when the current IR1 becomes equal to the current IRRB, the resistance of the resistance element R1 becomes equal to the resistance of the reference resistance element RRB, and the voltage of the bit line BL0 becomes equal to the voltage of the reference bit line RBL.

[0178] Thereafter, the word line WL and the reference word line RBWL are set to a low level, such as Fig.17 As shown in (g) in FIG. 1 . Therefore, the current no longer flows to the resistor element R1 and the reference resistor element RRB, and the voltages of the bit line BL0 and the reference bit line RBL are turned into a high level. In addition, the levels of the control signals SETENB, VSSBL and VSSSL and the amplifier enable signal BAMPEN return to the levels of the initial state, and the set write operation ends.

[0179] As described above, the present embodiment can obtain effects similar to those obtainable by the above-described embodiments. For example, even if the electrical characteristics of the resistance element R1 vary, the resistance of the resistance element R1 in the low resistance state can be set to a predetermined resistance, and the read margin during the read operation can be improved.

[0180] Furthermore, in the present embodiment, the voltage control circuit VCNT4 including the current mirror circuit controls the current flowing to the resistance element R1 and the reference resistance element RRB during the set write operation. Figure 1 The operational amplifier BAMP shown in the feedback system is Figure 1 Compared with the voltage control circuit VCNT1 shown in FIG. 1 , the current flowing to the bit line BL and the reference bit line RBL can be controlled at high speed and the current consumption is low. Figure 1 Compared with the resistive random access memory 100 shown in FIG. 1 , the set write operation can be performed at a high speed, and the current consumption during the set write operation can be reduced.

[0181] Fig.19 An example of a resistive random access memory according to another embodiment is shown. Fig.19 Components similar to those of the above-described embodiment are denoted by the same reference numerals, and detailed descriptions thereof will be omitted. Fig.19 The resistive random access memory 114 shown includes a voltage control circuit VCNT5 to replace Fig.12 The voltage control circuit VCNT3 shown. The resistive random access memory 114 also includes transistors P31 and P32 to replace Fig.12 The transistor P3 is shown. In other aspects, Fig.19 The configuration of the resistive random access memory 114 shown is similar to Fig.12 The configuration of the RRAM 108 is shown.

[0182] The voltage control circuit VCNT5 has a current mirror circuit including transistors PB5 and PB6 and a current mirror circuit including transistors NB5 and NB6. The transistor NB5 has a source connected to the second end of the resistor element R1 and a gate and a drain connected to each other. The transistor NB6 has a source connected to the first end of the reference resistor element RRR via the transmission transistor TR and a gate connected to the gate of the transistor NB5.

[0183] Transistor PB5 has a drain connected to the drain of transistor NB5, a source connected to power supply line VDD via transistor P31, which is turned on during the read operation. Transistor PB6 has a gate connected to the gate of transistor PB5 and a drain connected to the drain of transistor NB6, and a source connected to power supply line VDD via transistor P32, which is turned on during the read operation.

[0184] When the read enable signal RDENB is set to a low level during a read operation, the voltage control circuit VCNT5 performs control so that the same current flows to the source line SL and the reference source line RRSL. Fig.12 The operational amplifier shown in the RAMP feedback system is Fig.12Compared with the voltage control circuit VCNT3 shown in FIG. 1 , the voltage control circuit VCNT5 can control the current flowing to the source line SL and the reference source line RSL at high speed and has low current consumption. Fig.12 Compared with the resistive random access memory 108 shown, the read operation can be performed at a high speed and the current consumption during the read operation can be reduced.

[0185] Fig.19 The lower right portion of shows an example of the transient response of the current mirror circuit of the voltage control circuit VCNT5 during the read operation of the resistance element R1. For example, when the current IR1 flowing through the resistance element R1 is less than the current IRRR flowing through the reference resistance element RRR, the current mirror circuit exhibits a transient response, so that the voltage VSL of the source line SL and the voltage VRRSL of the reference source line RRSL become the same voltage. Therefore, the voltages VSL and VRRSL increase. On the other hand, when the current IR1 flowing through the resistance element R1 is greater than the current IRRR flowing through the reference resistance element RRR, the current mirror circuit exhibits a transient response, so that the voltages VSL and VRRSL become the same voltage, and the voltages VSL and VRRSL decrease.

[0186] Fig. 20 Shows Fig.19 An example of a read operation of the resistive random access memory 114 shown in FIG. That is, Fig. 20 An example of a control method for controlling the resistive random access memory 114 is shown. Fig.13 First, the read enable signal RDENB and the control signal VSSSL are set to a low level, and the control signal VSSBL is set to a high level. Fig. 20 As shown in (a) in the figure. Due to the low level of the read enable signal RDENB, the current flows to Fig.19 In the double-layer current mirror circuit of the voltage control circuit VCNT5 shown in FIG. 1 , the voltage of the source line SL and the reference source line RRSL are both increased to the voltage of the power supply voltage line VDD, as shown in FIG. Fig. 20 As shown in (b) in .

[0187] Next, the word line WL to be read and the reference word line RRWL are set to a high level, and current flows to the resistance element R1 and the reference resistance element RRR according to the resistance of the resistance element R1 and the reference resistance element RRR, respectively. Fig. 20 The voltage of the source line SL and the reference source line RRSL is set to a voltage according to the resistance of the resistor element R1 (in the set state SET or the reset state RESET), as shown in (c) and (d) in FIG. Fig. 20As shown in (e) in FIG. 1 , the voltage of the source line SL and the reference source line RRSL in the set state SET (low impedance state) becomes lower than the reference voltage VREF. The voltage of the source line SL and the reference source line RRSL in the reset state RESET (high impedance state) becomes higher than the reference voltage VREF.

[0188] Next, the sense amplifier enable signal SAEN is activated, as shown in FIG. Fig. 20 As shown in (f) in FIG. 1 . The latch LT operates when the sense amplifier enable signal SAEN is activated and compares the voltage of the source line SL with the reference voltage VREF. Then, the latch LT outputs the logic data signal DATA according to the comparison result, as shown in FIG. Fig. 20 As shown in (g) in FIG. 1 , the data held in the resistor element R1 is thus read out.

[0189] As described above, this embodiment can obtain effects similar to those obtainable in the above-described embodiment. In this embodiment, the current flowing to the resistance element R1 and the reference resistance element RRR during the read operation is controlled by the voltage control circuit VCNT5 including the current mirror circuit. Fig.12 Compared with the resistive random access memory 108 shown, the read operation can be performed at a high speed and the current consumption during the read operation can be reduced.

[0190] Fig.21 An example of a resistive random access memory according to another embodiment is shown. Fig.21 , elements similar to those shown in the above-described embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted. Fig.21 The resistive random access memory 116 shown is a multi-value memory that stores 4-value data (2 bits) in each resistor element R1. For this reason, the resistive random access memory 116 includes three pairs of transfer transistors TB and reference resistor elements RRB. The gates of the transfer transistors TB are connected to different reference word lines RBWL.

[0191] For example, each resistance element R1 is set to one of the resistance states corresponding to the logic values ​​"00", "01", "10", and "11", respectively. The resistance of the resistance element R1 decreases in the order of "00", "01", "10", and "11". The logic value "00" corresponds to the reset state. The logic value "01" corresponds to the first set state. The logic value "10" corresponds to the second set state. The logic value "11" corresponds to the third set state.

[0192] In addition, the RRAM 116 further includes precharge transistors PP1 and PP2 having gates for receiving a precharge signal PRCB, so as to replace Figure 1The transistor P1 shown is used to receive the control signal SETENB. In addition, the resistive random access memory 116 includes a first write control circuit 117. The sources of the precharge transistors PP1 and PP2 receive the set voltage VSET. For example, the set voltage VSET is slightly lower than the power supply voltage VDD (for example, the threshold voltage of the low transistor). The drain of the precharge transistor PP1 is connected to the reference bit line RBL. The drain of the precharge transistor PP2 is connected to the bit line BL. Instead of the set voltage VSET, the power supply voltage VDD can be supplied to the voltage control circuit VCNT1 and the precharge transistors PP1 and PP2.

[0193] In other respects, Fig.21 The configuration of the resistive random access memory 116 shown is similar to Figure 1 The configuration of the resistive random access memory 100 is shown. Figure 7 , the reference resistance element RRB can be connected to a voltage line set to an offset voltage Voffset. In addition, it can be arranged Fig. 9 Transistors TB and TD are shown to replace reference resistance element RRB.

[0194] For example, the first write control circuit 117 generates a voltage to be supplied to three reference word lines RBWL, which are connected to the gates of three transfer transistors TB. When the resistor element R1 is set to the first set state during the set write operation, the first write control circuit 117 sets one reference word line RBWL to a high level and turns on one transfer transistor TB. When the resistor element R1 is set to the second set state during the set write operation, the first write control circuit 117 sets two reference word lines RBWL to a high level and turns on two transfer transistors TB. When the resistor element R1 is set to the third set state during the set write operation, the first write control circuit 117 sets three reference word lines RBWL to a high level and turns on three transfer transistors TB. Therefore, by changing the number of reference resistor elements RRB connected to the reference bit line RBL according to the logical value of the data to be written into the resistor element R1, multi-valued data can be written into the resistor element R1.

[0195] Similar to Figure 1, only one reference resistance element RRB can be connected to the reference bit line RBL via one transfer transistor TB. In this case, the voltage control circuit VCNT1 includes three transistors PB2 connected in parallel. The gates of the three transistors PB2 receive the control signal REGB. The sources of the three transistors PB2 are connected to the set voltage line VSET via the switch transistors, respectively. The drains of the three transistors PB2 are connected to the reference bit line RBL. As the number of transistors PB2 increases, the current flowing through the reference resistance element RRB increases at the current mirror ratio PB2 / PB1, and the voltage generated at one end of the reference resistance element RRB increases, thereby showing an effect equivalent to increasing the resistance of the reference resistance element RRB.

[0196] When the resistance element R1 is set to the first set state during the set write operation, the first write control circuit 117 turns on three switch transistors. When the resistance element R1 is set to the second set state during the set write operation, the first write control circuit 117 turns on two switch transistors. When the resistance element R1 is set to the third set state during the set write operation, the first write control circuit 117 turns on one switch transistor. Therefore, by changing the number of transistors PB2 that supply current according to the logic value of the data to be written to the resistance element R1, multi-valued data can be written to the resistance element R1.

[0197] Fig. 22 Shows Fig.21 An example of a multi-value set write operation of the resistive random access memory 116 shown in FIG. That is, Fig. 22 An example of a control method for controlling the resistive random access memory 116 is shown. Figure 4 Detailed description of the same operation. Fig. 22 The waveforms of n=1 and n=2 on the lower side respectively represent the waveforms when the resistor element R1 is set to the first set state and the second set state. Except for different voltage values ​​and different current values, the characteristics of the waveform change are similar for the operation set to the first set state and the operation set to the second set state.

[0198] exist Fig. 22 In the set write operation shown in FIG. 1 , the precharge signal PRCB temporarily becomes a low level as the control signal VSSBL becomes a low level. Fig. 22 As shown in (a) in FIG. 1 , the precharge signal PRCB precharges the bit line BL and the reference bit line RBL. Fig. 22 Thereafter, the amplifier enable signal BAMPEN is set to a high level, as shown in (b) and (c) of FIG. Fig. 22 As shown in (d) in .

[0199] The operation of the operational amplifier BAMP starts in response to the amplifier enable signal BAMPEN of a high level. Since the voltages of the precharged bit line BL and the reference bit line RBL are equal to each other, the control signal REGB output from the operational amplifier BAMP decreases to an equilibrium voltage, as shown in FIG. Fig. 22 As shown in (e) and (f) in .

[0200] Next, the word line WL and the reference word line RBWL are set to a high level, the transfer transistors T1 and TB are turned on, and the current starts to flow to the resistor element R1 and the reference resistor element RRB, as shown in FIG. Fig. 22 As shown in (g), (h) and (i) in Figure 4 Similarly, the operational amplifier BAMP generates a control voltage REGB which reduces the difference between the voltage of the bit line BL which varies according to the current and the voltage of the reference bit line RBL, as shown in FIG. Fig. 22 As shown in (j) and (k) in .

[0201] The current IR1 of the resistance element R1 increases until the current IR1 becomes equal to the current IRRB, wherein the current IRRB flows according to the number n of reference resistance elements RRB connected to the reference bit line RBL, as shown in FIG. Fig. 22 As shown by the dotted line inside the box on the left. Therefore, when a logic value according to the number n of reference resistance elements RRB having a fixed resistance and connected to the reference bit line RBL is set to the resistance element R1, a change in the resistance of the resistance element R1 after the setting of this logic value can be minimized. Therefore, during a read operation, when a read voltage is set to the word line WL and multi-value data is read from the resistance element R1, a decrease in a read margin can be reduced.

[0202] In the case where the voltage control circuit VCNT1 includes three transistors PB2 connected in parallel instead of three reference resistance elements RRB, the number n may represent the number of transistors PB2 supplying current. However, in this case, the larger the number n is, the smaller the current set to the resistance element R1 is.

[0203] As described above, the present embodiment can obtain an effect similar to that obtainable in the above-described embodiment. In addition, in the present embodiment, during the multi-value set write operation of writing multi-value data to the resistance element R1, the change in the resistance of the resistance element R1 can be minimized. Therefore, when reading multi-value data from the resistance element R1, the reduction in the read margin can be reduced.

[0204] Fig.23 An example of a resistive random access memory according to another embodiment is shown. Fig.23 Components similar to those of the above-described embodiment are denoted by the same reference numerals, and detailed descriptions thereof will be omitted. Fig.23The RRAM 118 shown is a multi-value memory that stores 4-value data (2 bits) in each resistor element R1. For example, the RRAM 118 includes a Fig.21 The circuit shown performs a multi-valued set write operation and writes multi-valued data into the memory cell MC.

[0205] The RRAM 118 includes a precharge transistor PRS having a source connected to a source line SL and a precharge transistor PRS having a source connected to a reference source line RRL. The precharge transistor PRS connected to the source line SL and the reference source line RRL has a gate receiving a precharge signal PRCS and a drain receiving a precharge voltage VPRC.

[0206] replace Fig.12 , the resistive random access memory 118 includes three sense amplifiers SA for determining the logic values ​​"00", "01", "10" and "11" held by the resistor element R1. During a read operation, each sense amplifier SA compares a reference voltage VREF (VREF0, VREF1 or VREF2) with a voltage generated on a source line SL and generates a data signal DATA (DATA0, DATA1 or DATA2). The data determination circuit (not shown) of the resistive random access memory 118 determines the logic value of the data stored in the memory cell MC according to the logic values ​​of the three data signals DATA0, DATA1 and DATA2, and outputs the result of the determination. Fig.24 The data signal DATA shown in FIG.

[0207] Fig.24 Shows Fig.23 An example of a read operation of the resistive random access memory 118 shown in FIG. That is, Fig.24 An example of a control method for controlling the resistive random access memory 118 is shown. Fig.13 Detailed description of the same operation.

[0208] First, as the control signal VSSBL changes to a low level, the precharge signal PRCS temporarily changes to a high level. Fig.24 As shown in (a) in FIG. 1 . The precharge signal PRCS precharges the source line SL and the reference source line RRL. Fig.24 Thereafter, the amplifier enable signal RAMPEN is set to a high level, as shown in (b) of FIG. Fig.24 As shown in (c) in .

[0209] The operation of the operational amplifier RAMP starts in response to the amplifier enable signal RAMPEN of a high level. Since the voltages of the precharged source line SL and the reference source line RRL are equal to each other, the control signal REGR output from the operational amplifier RAMP decreases to a balanced voltage, as shown in FIG. Fig.24 As shown in (d) in .

[0210] Next, the word line WL and the reference word line RRWL are set to a high level, and the transfer transistors T1 and TR are turned on. Fig.24 As shown in (e) in FIG. 1 . The conduction of the transfer transistors T1 and TR causes current to flow to the resistance element R1 and the reference resistance element RRR, and the operational amplifier RAMP generates a control voltage REGR that reduces the difference between the voltage of the source line SL and the voltage of the reference source line RRL that vary according to the current. Therefore, the voltage of the source line SL and the voltage of the reference source line RRL change to a voltage corresponding to the logic value stored in the memory cell MC, as shown in FIG. Fig.24 As shown in (f) in .

[0211] Next, the sense amplifier enable signal SAEN is activated, as shown in FIG. Fig.24 As shown in (g) in FIG. 3 . The three sense amplifiers SA operate when the sense amplifier enable signal SAEN is activated to compare the voltage of the source line SL with each of the reference voltages VREF0, VREF1, and VREF2. Each sense amplifier SA outputs one of the logic data signals DATA0, DATA1, and DATA2 (not shown) according to the comparison result. Thereafter, the data determination circuit outputs a 2-bit data signal DATA[1:0] based on the data signals DATA0, DATA1, and DATA2 from the sense amplifiers SA, as shown in FIG. Fig.24 As shown in (h) in .

[0212] Examples of voltages generated on the source line SL during a read operation and reference voltages VREF0, VREF1, and VREF2 are shown in FIG. Fig.24 As shown in the box on the left. The reference voltage VREF0 is set between voltages V0 and V1, wherein V0 is the voltage generated on the source line SL when the resistor element R1 maintains a logic value of "00" (in the reset state), and V1 is the voltage generated on the source line SL when the resistor element R1 maintains a logic value of "01" (in the first set state). The reference voltage VREF1 is set between voltage V1 in the first set state and voltage V2, wherein V2 is the voltage generated on the source line SL when the resistor element R1 maintains a logic value of "10" (in the second set state). The reference voltage VREF2 is set between voltage V2 in the second set state and voltage V3, wherein V3 is the voltage generated on the source line SL when the resistor element R1 maintains a logic value of "11" (in the third set state).

[0213] Fig.25 It is shown Fig.23 1 is a circuit diagram of an example of a sense amplifier SA (SA0, SA1, and SA2) shown in FIG. Since the sense amplifiers SA0, SA1, and SA2 have the same circuit configuration, the sense amplifier SA0 will be described as an example. The sense amplifier SA0 includes a latch LT. When the complementary sense amplifier enable signals SAEN and SAENB are activated, the latch LT latches a logic corresponding to the difference between the voltage of the source line SL and the reference voltage VREF0, and outputs the latched logic as the data signal DATA0.

[0214] The source line SL and the latch LT are connected via the transfer transistor TT1. The gate of the transfer transistor TT1 receives the switch control signal SW. The reference voltage line VREF0 and the latch LT are connected via the transfer transistor TT2. The gate of the transfer transistor TT2 receives the switch control signal SW. For example, after the amplifier enable signal RAMPEN is set to a high level and before the sense amplifier enable signal SAEN is set to a high level, the switch control signal SW is set to a high level.

[0215] As described above, this embodiment can obtain effects similar to those obtainable by the above-described embodiments. In addition, in this embodiment, when reading multi-valued data written to the resistance element R1, the voltage control circuit VCNT3 generates a read voltage on the source line SL, thereby reducing the reduction in the read margin.

[0216] Fig.26 An example of a resistive random access memory according to another embodiment is shown. Fig.26 The resistive random access memory 120 shown is a cross-point resistive random access memory. The resistive random access memory 120 includes a memory cell array ARY. The memory cell array ARY has a plurality of resistor elements R arranged in a matrix arrangement. The resistor element R is arranged at the intersection of the word line WL and the bit line BL, and has a first end connected to the word line WL (WL0 to WL3) and a second end connected to the bit line BL (BL0 to BL3). The 2-bit number added to the "R" representing the resistor element R represents the number assigned to the word line WL connected to the resistor element R and the number assigned to the bit line BL connected to the resistor element R.

[0217] A write control circuit for a set write operation of the resistance element R is connected to the bit line BL0. Although illustration is omitted, the same circuit is also connected to the bit lines BL1, BL2, and BL3. Fig.26 An overview of a case where a set write operation is performed on the resistance elements R00 and R01 is shown.

[0218] In the cross-point resistive random access memory, when the word line WL is in a suspended state, the bit lines BL0 to BL3 become the same voltage according to the sneak current. To prevent this, during the generation period of the control signal SETEN, the word line WL0 is set to the ground voltage VSS, and the word lines WL1 to WL3 are set to the unselected (or non-selected) WL bias VWLU. During the generation period of the control signal SETEN, the bit lines BL2 and BL3 are set to the unselected (or non-selected) BL bias VBLU. During the set write operation, the control signal SETEN is activated.

[0219] During the set write operation and the reset write operation of the cross-point resistive random access memory, control is performed to reduce the change in resistance due to the parasitic current of the resistance element R1 other than the resistance element R1 that is the target of the set write operation. For example, during the set write operation, the unselected WL bias VWLU and the unselected BL bias VBLU are set to values ​​within the range of about one-half to about one-third of the maximum value of the voltage of the bit line BL.

[0220] The set write control circuit includes transistors PM1 and S0B connected in series between the set voltage line VSET and the ground line VSS and a reference resistance element RR. The resistance of the reference resistance element RR is fixed to the resistance of the resistance element R1 in the low resistance state. The set write control circuit includes transistors PM2 and S0A connected in series between the set voltage line VSET and the bit line BL0. Transistors PM1 and S0B are connected via the bit line BL0B, and transistors PM2 and S0A are connected via the bit line BL0A. During the period when the gates of transistors S0B and S0A receive the high-level selection signal SEL0, transistors S0B and S0A are turned on. The set write control circuit is an example of a first voltage control circuit.

[0221] The bit lines BL0B and BL0A are connected to a precharge circuit PRE. During the high level period of the precharge signal PRC, the precharge circuit PRE sets the bit lines BL0B and BL0A to the unselected BL bias VBLU. The operational amplifier AMP and the transistors PM1 and PM2 have Figure 1 The voltage control circuit VCNT1 shown has the same circuit configuration and operates similarly to the voltage control circuit VCNT1 , wherein the operational amplifier AMP receives the amplifier enable signal AMPEN, and the gates of the transistors PM1 and PM2 receive the control signal REG output from the operational amplifier AMP.

[0222] Fig. 27 Shows Fig.26 An example of a set write operation of the resistive random access memory 120 is shown in FIG. Fig. 27Part (1) of shows an example of a setting circuit for setting the resistance of the reference resistance element RR2 for each bit line BL, wherein the current flowing through the reference resistance element RR2 is equal to the sum of the currents flowing through the unselected resistance elements R1 that are not the target of the set write operation. That is, the resistance of the reference resistance element RR2 corresponds to the combined resistance of the unselected resistance elements R1.

[0223] The setting circuit includes a reference operational amplifier REFAMP and resistance elements, which are arranged between the adjustment voltage line VTEST and the inverting and non-inverting input terminals of the reference operational amplifier REFAMP, respectively. Fig. 27 The illustrated reference resistance element RR2 is an example of a fourth reference resistance element. Fig. 27 The setting circuit shown is an example of a first resistance setting circuit. Fig. 27 The reference operational amplifier REFAMP shown is an example of a fourth voltage comparator.

[0224] The reference resistance element RR2 is used as a variable resistance element whose resistance varies according to the control signal VCTRL. The sum of the currents flowing through the unselected resistance element R1 which is not the target of the set write operation is different according to the write state of the unselected resistance element R1. For this reason, the setting operation of the setting circuit is performed at the beginning of each set write operation to set the resistance of the reference resistance element RR2. In the following, for convenience, it is assumed that the resistance element R1 which is the target of the set write operation is connected between the word line WL0 and the bit line BL0.

[0225] During the set operation, the word line WL0 is set to the adjustment voltage VTEST so that no current flows to the resistance element R1 that is the target of the set write operation. In addition, the resistance of the reference resistance element RR2 is determined so that the same current flows between the adjustment voltage line VTEST and the word line WL connected to the unselected resistance element R1 (in this example, WL1-WL3=VSS). The resistance of the reference resistance element RR2 is determined by the control signal VCTRL output by the reference operational amplifier REFAMP.

[0226] The reference operational amplifier REFAMP receives a differential input of the voltage of the reference resistor element RR2 on the side closer to the higher adjustment voltage line VTEST and the voltage of the bit line BL0. The reference operational amplifier REFAMP outputs a control signal VCTRL that makes the voltages received by the differential inputs equal. In order to generate the voltage of the differential input, the inverting input terminal and the non-inverting input terminal of the reference operational amplifier REFAMP are connected to the adjustment voltage line VTEST via the resistor element, respectively. For example, the adjustment voltage line VTEST is set to be similar to Figure 2 The voltage value of the read voltage VREAD is shown.

[0227] Fig. 27 Part (2) of shows the circuit state during the set write operation. During the set write operation, the reference resistance element RR2 is maintained at the resistance set by the above-mentioned set operation. The unselected WL bias VWLU is supplied to the reference resistance element RR2 and the unselected resistance element R1. For this reason, during the set write operation, the current flowing through the unselected resistance element R1 can be offset by the current flowing through the reference resistance element RR2. Therefore, during the set write operation, the selected resistance element R1 (or R00) can be set to the desired resistance (low resistance state) without being affected by the current flowing through the unselected resistance element R1.

[0228] Fig. 27 Part (3) shows an example of a circuit of a reference resistance element RR2. The reference resistance element RR2 includes transistors NM11, NM12, and NM13 and resistance elements RRa and RRb. Transistor NM11 has a drain connected to a power supply line VDD, a gate connected to an input IN (i.e., a bit line BL0B), and a source connected to the first end of resistance elements RRa and RRb. The other end (i.e., the second end) of resistance element RRa is connected to a ground line VSS. The other end (i.e., the second end) of resistance element RRb is connected to the drain of transistor NM12 and the gate of transistor NM13. The sources of transistors NM12 and NM13 are connected to a ground line VSS. The drain of transistor NM13 is connected to input IN.

[0229] The transistor NM11 and the resistor element RRa are used as a source follower, and a voltage is applied to the gate of the transistor NM13 via the second end of the resistor element RRb, which voltage is based on the voltage of the input IN. Therefore, the transistor NM13 is a diode-connected transistor. The transistor NM12 reduces the gate voltage of the transistor NM13, the higher the control voltage VCTRL. Therefore, the current-voltage characteristic of the diode-connected transistor NM13 can be continuously changed by the control voltage VCTRL, and the reference resistor element RR2 can be operated as a variable resistor element.

[0230] Fig.28 Shows Fig.26 An example of a set write operation of the resistive random access memory 120 is shown in FIG. That is, Fig.28 An example of a control method for controlling the resistive random access memory 120 is shown. Figure 4 The same operation is described in detail. Fig.28 During the set write operation shown, the resistor elements R00 and R01 connected between the word line WL0 and the bit lines BL0 and BL1, respectively, are set to a low resistance state. Fig.28 The set write operation shown is performed before Fig. 27 In the set operation shown, the reference resistance element RR2 for the set write operation is set to the parallel resistance of the unselected resistance element R. In addition, the voltage of the control signal VCTRL for the set write operation is maintained during the set write operation, which voltage is determined by the set operation. Hereinafter, the set write operation of the resistance element R1 connected to the bit line BL0 will be described.

[0231] exist Fig.28 In the example, when the set write operation starts, the control signal SETEN and the selection signals SEL0 and SEL1 are set to high level H, and the precharge signal PRC is temporarily set to high level H. Fig.28 The word lines WL1 to WL3 not related to the set write operation are set to the unselected WL bias VWLU in response to the high-level control signal SETEN, as shown in (a) of FIG. Fig.28 In addition, the bit lines BL2 and BL3 that are not related to the set write operation are set to the unselected BL bias VBLU, as shown in FIG. Fig.28 As shown in (c) in .

[0232] The bit lines BL0A and BL0B are set to the unselected BL bias VBLU in response to the precharge signal PRC of the high level, and the voltage of the bit line BL0 increases by following the voltage variation of the bit line BL0A, as shown in FIG. Fig.28 Then, current flows from the precharge circuit PRE to the resistance element R1 and the reference resistance element RR as the target of the set write operation via the bit lines BL0A and BL0B, respectively, as shown in FIG. Fig.28 As shown in (e) in .

[0233] Thereafter, the amplifier enable signal AMPEN is set to a high level, and the operation of the operational amplifier AMP starts, as shown in FIG. Fig.28 As shown in (f) in FIG. 1 . However, during the high level period of the precharge signal PRC, the bit lines BL0A and BL0B remain at the unselected BL bias VBLU. Thereafter, the precharge signal PRC is set to a low level. Therefore, the current from the precharge circuit PRE to the bit lines BL0B and BL0A stops, and the currents IBL0A and IBL0B flow to the bit lines BL0A and BL0B according to the resistance of the resistance element R1 and the reference resistance element RR, as shown by Fig.28 As shown in (g) in .

[0234] The operational amplifier AMP controls the gate voltages of the transistors PM1 and PM2 so that the voltages of the bit lines BL0B and BL0A, which vary according to the currents IBL0A and IBL0B, become equal to each other. Fig.28 The following operations are the same as Figure 4Then, the resistance element R1 which is the target of the set write operation changes from the high resistance state to the low resistance state.

[0235] Fig.29 shows the reset write operation during Fig.26 An example of the state of the resistive random access memory 120 is shown in FIG. Fig.29 In, with Fig.26 Components similar to those shown are denoted by the same reference numerals, and their detailed description will be omitted. The circuit for resetting the write operation is similar to that for Fig.26 The circuit for setting operation shown in FIG. 1 is different in that transistors NM1 and NM2 are arranged to replace transistors PM1 and PM2. The sources of transistors NM1 and NM2 are connected to the ground line VSS, and the drains of transistors NM1 and NM2 are respectively connected to the inverting input terminal (or negative input terminal) and the non-inverting input terminal (or positive input terminal) of the operational amplifier AMP. The gates of transistors NM1 and NM2 receive the output (control signal REG) of the operational amplifier AMP. The reference resistance element RR is connected to the reset voltage line VRESET. The resistance of the reference resistance element RR is fixed to the resistance of the resistance element R1 in the high-resistance state. The voltage of the reset voltage line VRESET is slightly lower than the power supply voltage VDD (for example, the threshold voltage of the transistor is lower).

[0236] Fig.29 The reset write control circuit shown is used during a reset write operation of causing the resistance element R connected to the bit line BL0 to change from a low resistance state to a high resistance state. The reset write control circuit is an example of a second voltage control circuit. Fig.29 An overview of the case where a reset write operation is performed on the resistor elements R00 and R01 is shown. In this case, the word line WL0 is set to the reset voltage VRESET, and the word lines WL1 to WL3 are set to the unselected WL bias VWLU during the generation period of the control signal SETEN. During the generation period of the control signal SETEN, the bit lines BL2 and BL3 are set to the unselected BL bias VBLU. During the reset write operation, the control signal SETEN is activated.

[0237] Fig.30 Shows Fig.26 The reset write operation example of the resistive random access memory 120 shown in FIG. Fig. 27 The same operations are described in detail in Fig.30 In the following figures, a triangular mark shown at the end of a signal line represents a ground line VSS.

[0238] Fig.30Part (1) of shows an example of a setting circuit that sets the resistance of a reference resistance element RR2 through which a current equals the sum of currents flowing through unselected resistance elements R1 that are not targets of a set write operation for each bit line BL. The setting circuit includes a reference operational amplifier REFAMP, and resistance elements that are respectively arranged between a ground line VSS and inverting and non-inverting input terminals of the reference operational amplifier REFAMP. Fig.30 The illustrated reference resistance element RR2 is an example of a fifth reference resistance element. Fig.30 The illustrated setting circuit is an example of a second resistance setting circuit. Fig.30 The reference operational amplifier REFAMP shown is an example of a fifth voltage comparator. Fig.30 The setup circuit shown is similar to Fig. 27 The setting circuit is similar to that shown in part (1) of , except that the connection between the ground line VSS and the adjustment voltage line VTEST connected to the reference resistance element RR2 is reversed, and the inverting and non-inverting input terminals of the reference operational amplifier REFAMP are reversed.

[0239] Further, similar to Fig. 27 , the setting circuit determines the resistance of the reference resistance element RR2 so that the current flowing through the reference resistance element RR2 and the current flowing through the word line WL (in this example, WL1-WL3=VSS) become equal to each other, and the word line WL is connected to the unselected resistance element R1. Fig. 27 The setup circuit for the set write operation and Fig.30 The setting circuit for reset writing operation is shown connected in parallel to each of the bit lines BL0 to BL3.

[0240] Fig.30 Part (2) shows the state of the circuit during a reset write operation. Fig.30 The circuit in part (2) is similar to Fig. 27 The circuit of part (2) is different in that the voltage set to each circuit element is set for the reset write operation. The reference resistance element RR2 for the reset write operation is maintained by Fig.30 The setting circuit shown in part (1) sets the resistance. The reference resistance element RR2 and the unselected resistance element R1 are set to the unselected WL bias VWLU. For this reason, during the reset write operation, the current flowing through the unselected resistance element R1 can be offset by the current flowing through the reference resistance element RR2. Therefore, during the reset write operation, the resistance element R1 or R00 can be reset to the desired resistance (high resistance state) without being affected by the current flowing through the unselected resistance element R1.

[0241] Fig.31Shows Fig.26 An example of a reset write operation of the resistive random access memory 120 shown in FIG. That is, Fig.31 An example of a control method for controlling the resistive random access memory 120 is shown. Fig.28 The same operation is described in detail. Fig.31 During the reset write operation shown, the resistor elements R00 and R01 connected between the word line WL0 and the bit lines BL0 and BL1, respectively, are set to a high impedance state. Fig.31 The reset write operation shown is performed before Fig.30 In the set operation shown, the reference resistance element RR2 for the reset write operation is set to the parallel resistance of the unselected resistance element R. In addition, during the reset write operation, the voltage of the control signal VCTRL for the reset write operation determined by the set operation is maintained. Hereinafter, the reset write operation of the resistance element R1 connected to the bit line BL0 will be described.

[0242] and Fig.28 Similarly, at the beginning of the reset write operation, the control signal SETEN and the selection signals SEL0 and SEL1 are set to high level, and the precharge signal PRC is temporarily set to high level, such as Fig.31 In response to the high-level control signal SETEN, the word lines WL1 to WL3 and the bit lines BL2 and BL3 that are not related to the reset write operation are set to the unselected WL bias VWLU and the unselected BL bias VBLU, respectively, as shown in FIG. Fig.31 As shown in (b) and (c) in .

[0243] The bit lines BL0A and BL0B are set to the unselected BL bias VBLU in response to the precharge signal PRC of a high level, and the voltage of the bit line BL0 increases by following the voltage variation of the bit line BL0A, as shown in FIG. Fig.31 Then, current flows from the precharge circuit PRE to the resistance element R1 and the reference resistance element RR as the target of the reset write operation via the bit lines BL0A and BL0B, respectively, as shown in FIG. Fig.31 As shown in (e) in .

[0244] Thereafter, the amplifier enable signal AMPEN is set to a high level, and the operation of the operational amplifier AMP starts, as shown in FIG. Fig.31 As shown in (f) in FIG. 1 . When the precharge signal PRC is at a low level, the current from the precharge circuit PRE to the bit lines BL0B and BL0A stops. Therefore, according to the resistance of the resistor element R1 and the reference resistor element RR, the currents IBL0A and IBL0B flow to the bit lines BL0A and BL0B, as shown in FIG. Fig.31 As shown in (g) in .

[0245] The operational amplifier AMP controls the gate voltages of the transistors PM1 and PM2 so that the voltages of the bit lines BL0B and BL0A, which vary according to the currents IBL0A and IBL0B, become equal to each other. Fig.31 Then, the resistance element R1 which is the target of the reset writing operation changes from the low resistance state to the high resistance state.

[0246] Fig.32 Shows Fig.26 An example of a read operation of the resistive random access memory 120 shown in FIG. That is, Fig.32 An example of a control method for controlling the resistive random access memory 120 is shown. For example, the resistive random access memory 120 includes a read control circuit for each bit line BL. Fig.32 In the figure, for convenience, only the read control circuit connected to the bit line BL0 is shown. The read control circuits connected to the other bit lines BL have the same Fig.32 The read control circuit has the same configuration as shown.

[0247] The read control circuit includes a current integration circuit, switches SW1, SW2, and SW3, capacitive elements CR1 and CR2, and a sense amplifier SA. The current integration circuit includes an operational amplifier having a non-inverting input terminal (or positive input terminal) receiving a read voltage Vread, and an output terminal and an inverting input terminal (or negative input terminal) connected via a capacitive element C, wherein the inverting input terminal is connected to the bit line BL0. The switch SW3 is arranged between the output terminal of the operational amplifier of the current integration circuit and the bit line BL0, and connects both ends of the capacitive element C. The switch SW1 is an example of a first switch, and the switch SW2 is an example of a second switch.

[0248] The capacitive element CR1 and the switch SW1 are connected in series between the read voltage line Vread and the output terminal of the operational amplifier of the current integration circuit. The capacitive element CR2 and the switch SW2 are connected in series between the read voltage line Vread and the output terminal of the operational amplifier of the current integration circuit. The inputs of the sense amplifier SA providing a differential input are respectively connected to a node CN1 and a node CN2, the node CN1 connecting the capacitive element CR1 and the switch SW1, and the node CN2 connecting the capacitive element CR2 and the switch SW2.

[0249] The resistive random access memory 120 is Fig.26 The memory cell array ARY shown includes a read reference resistor element RREF connecting a reference word line WLR and each bit line BL. Switches SW1 and SW2 connected to the reference word line WLR and the word line WL0 are added to illustrate the setting of the voltage values ​​of the reference word line WLR and the word line WL0.

[0250] During the read operation, the word line WL0 connected to the reference word line WLR and the resistance element R0 as the target of the read operation is set to the read voltage Vread or the ground voltage VSS. The word lines WL1 to WL3 connected to the resistance element R1 other than the resistance element R1 as the target of the read operation are set to the read voltage Vread.

[0251] Fig.32 The right side of shows the waveform during the read operation. For example, during the read operation, the data held by the resistance element R0 connected between the word line WL0 and the bit line BL0 is read. First, the switch control signal SCNT1 for controlling the switch SW1 is set to a high level, and the switch control signal SCNT3 for controlling the switch SW3 is temporarily set to a high level. Therefore, the switches SW1 and SW3 are turned on (in a closed state).

[0252] In response to the switch SW1 being turned on, the output of the operational amplifier of the current integration circuit is connected to the ground line VSS via the bit line BL0, the read reference resistance element RREF and the reference word line WLR. When the switch SW3 is turned off (in an open circuit state), the inverting input of the operational amplifier receives the voltage of the bit line BL0, which decreases according to the current flowing from the reference resistance element RREF to the ground line VSS, and the operational amplifier increases the voltage of the bit line BL0 to the read voltage Vread. Therefore, the charge corresponding to the current flowing through the reference resistance element RREF is accumulated in the capacitor element C, thereby increasing the voltage of the node CN1 in proportion to the current flowing through the reference resistance element RREF. When the switch SW1 is turned off, the voltage of the node CN1 is maintained on the capacitor element CR1.

[0253] After the switch control signal SCNT1 is set to a low level, the switch control signal SCNT2 that controls the switch SW2 is set to a high level, and the switch control signal SCNT3 is temporarily set to a high level. Therefore, the switches SW2 and SW3 are turned on (in a closed state).

[0254] In response to the switch SW2 being turned on, the output terminal of the operational amplifier of the current integration circuit is connected to the ground line VSS via the bit line BL0, the resistor element R0, and the word line WL0. When the switch SW3 is turned off (in an open state), the inverting input terminal of the operational amplifier receives the voltage of the bit line BL0, which decreases according to the current flowing from the resistor element R0 to the ground line VSS, and the operational amplifier increases the voltage of the bit line BL0 to the read voltage Vread. The on period of the switch SW1 is an example of the first period, and the on period of the switch SW2 is an example of the second period. The order of the on period of the switch SW1 and the on period of the switch SW2 can be reversed.

[0255] Therefore, the charge corresponding to the current flowing through the resistance element R0 is accumulated in the capacitance element C, thereby increasing the voltage of the node CN2 in proportion to the current flowing to the resistance element R0. The voltage of the node CN1 is maintained on the capacitance element CR2. In this state, when the resistance element R0 is in the low-resistance state, the voltage at the node CN2 is relatively high, and when the resistance element R0 is in the high-resistance state, the voltage at the node CN2 is relatively low. In addition, the voltage at the node CN1 is an intermediate voltage between the voltage at the node CN2 in the low-resistance state and the voltage at the node CN2 in the high-resistance state.

[0256] After the switch control signal SCNT2 is set to a low level, the sense amplifier enable signal SAEN is set to a high level, and the operation of the sense amplifier SA starts. The sense amplifier SA outputs the logic value stored in the resistance element R0 as the output data signal DATAOUT by differentially amplifying the voltages at the nodes CN1 and CN2. Thus, the read operation is completed.

[0257] exist Fig.32 During the read operation shown, even if current flows to the reference resistance element RREF and the resistance element R0, by connecting the current integration circuit to the bit line BL0, the voltage of the bit line BL0 can be maintained at the read voltage line Vread. For this reason, during the read operation, current can be prevented from flowing to the resistance element R1 other than the resistance element R1 that is the target of the read operation.

[0258] Fig.33 Shows Fig.26 Another example of a read operation of the resistive random access memory 120 is shown in FIG. That is, Fig.33 An example of a control method for controlling the resistive random access memory 120 is shown. Fig.32 The same operation is described in detail. Fig.33 In the embodiment, multi-value data (for example, 4-value data) is stored in each resistance element R (R0 and R1). For example, the resistive random access memory 120 includes a read control circuit for each bit line BL. Fig.33 In the figure, for convenience, only the read control circuit connected to the bit line BL0 is shown. The read control circuits connected to the other bit lines BL have the same Fig.33 The read control circuit has the same configuration as shown.

[0259] exist Fig.33 In the read control circuit shown in Fig.32 The read control circuit shown in FIG. 1 additionally includes switches SW41 and SW42. Fig.33 The RRAM 120 shown does not have Fig.21The reference word line WLR and the read reference resistance element RREF are shown. The switch SW41 connects the switches SW1 and SW2, and the switch SW42 connects the node CN1 to the read voltage line Vread. The switch SW41 is an example of a third switch. The output voltage VOUT output from the node CN2 is supplied to the Fig.25 Sense amplifiers SA0 to SA2 are shown as similar circuits to determine the logic of the data held in the resistor element R0.

[0260] Fig.33 The right side of shows the waveform during the read operation. For example, during the read operation, the data held by the resistor element R0 connected between the word line WL0 and the bit line BL0 is read. The waveforms of the switch control signals SCNT1 to SCNT3 are similar to Fig.32 The waveform of the switch control signal SCNT4 used to control the switches SW41 and SW42 is similar to Fig.32 The waveform of the sense amplifier enable signal SAEN is shown in FIG. The order of the on-period of the switch SW1 and the on-period of the switch SW2 may be reversed.

[0261] When the switches SW1 and SW3 are turned on and then the switch SW3 is turned off, charges corresponding to the currents flowing through the resistance element R1 and the resistance element R0 as the target of the read operation are accumulated in the capacitance element C. The voltage across the capacitance element CR1 is proportional to the charges accumulated in the capacitance element C. Next, when the switches SW2 and SW3 are turned on and then the switch SW3 is turned off, charges corresponding to the currents flowing through the resistance element R0 as the target of the read operation are accumulated in the capacitance element C.

[0262] Then, after the switch control signal SCNT2 is set to a low level, the switch control signal SCNT4 is set to a high level, and switches SW41 and SW42 are turned on (in a closed state). Therefore, capacitance elements CR1 and CR2 are connected in series, and the charge accumulated in capacitance elements CR1 and CR2 is redistributed. That is, the result of performing subtraction between the charge accumulated in capacitance elements CR1 and CR2 is generated as an output voltage VOUT. That is, an output voltage VOUT is generated, which corresponds to the multi-valued data retained in the resistance element R0 as the target of the read operation. When the resistance element R0 is in a low-resistance state, the output voltage VOUT is higher, and when the resistance element R0 is in a high-resistance state, the output voltage VOUT is lower. The on period of switches SW41 and SW42 is an example of the third period.

[0263] exist Fig.33 During the illustrated read operation, even if multi-valued data is stored in the memory cell (resistance element R) of the cross-point RRAM 120, the multi-valued data can be read by reducing the influence of the parasitic current.

[0264] As described above, the present embodiment can obtain an effect similar to that obtainable in the above-described embodiment. In addition, in the present embodiment, the cross-point resistive random access memory 120 can perform a set write operation, a reset write operation, and a read operation by reducing the influence of parasitic current. In addition, data can be read from the resistance element R that holds multi-value data.

[0265] According to an embodiment, a resistive random access memory and a method for manufacturing the resistive random access memory can be provided, which can reduce the change in resistance of a resistive random access element when writing data to the resistive random access memory, eliminate the need to perform a confirmation read operation, and improve the read margin.

[0266] The order in which the embodiments are described in this specification does not imply priority of the embodiments.Many other variations and modifications will be apparent to those skilled in the art.

[0267] All examples and conditional language recorded herein are intended for teaching purposes to help readers understand the present invention and the concepts contributed by the inventor to further promote the technical field, and should be interpreted as not being limited to these specifically described examples and conditions, and the organization of these examples in the specification is also irrelevant to the advantages and disadvantages of the present invention. Although the embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A resistive random access memory, comprising: a memory cell including a first resistance element and configured to store data according to a resistance of the first resistance element, wherein the resistance of the first resistance element changes according to a write operation; a first reference resistor element having a resistance set to a first value; a first voltage line set to a first voltage during a first write operation, wherein during the first write operation, the resistance of the first resistance element changes from a second value higher than the first value to the first value; and A first voltage control circuit is arranged between the first end of the first resistance element and the first end of the first reference resistance element, and is configured to: compare the voltage of the first end of the first resistance element with the voltage of the first end of the first reference resistance element, and when the voltage of the first end of the first resistance element becomes higher than the voltage of the first end of the first reference resistance element, adjust the value of the first voltage supplied from the first voltage line to reduce the difference between the currents flowing through the first resistance element and the first reference resistance element during the first write operation; and supply the adjusted first voltage to the first end of the first resistance element and the first end of the first reference resistance element.

2. The resistive random access memory according to claim 1, wherein: The first voltage control circuit comprises: a first variable resistance element disposed between the first voltage line and a first end of the first resistance element, and the resistance of the first variable resistance element varies according to a first control signal; a second variable resistance element disposed between the first voltage line and the first end of the first reference resistance element, and the resistance of the second variable resistance element varies according to the first control signal, and A first voltage comparator is configured to compare the voltage at the first end of the first resistance element with the voltage at the first end of the first reference resistance element and output the first control signal. When the voltage at the first end of the first resistance element becomes higher than the voltage at the first end of the first reference resistance element, the first control signal reduces the resistance of the first variable resistance element and the second variable resistance element.

3. The resistive random access memory according to claim 2, wherein The first variable resistance element includes a first p-channel MOS transistor having a source coupled to the first voltage line, a drain coupled to the first end of the first resistance element, and a gate receiving the first control signal. The second variable resistance element includes a second p-channel MOS transistor having a source coupled to the first voltage line, a drain coupled to the first end of the first reference resistance element, and a gate receiving the first control signal, and The first voltage comparator includes a first operational amplifier having: an inverting input terminal coupled to a first terminal of the first resistance element; a non-inverting input terminal coupled to a first terminal of the first reference resistance element; and an output terminal for outputting the first control signal, Wherein, the first operational amplifier is configured to amplify the difference between the voltage at the first end of the first resistance element and the voltage at the first end of the first reference resistance element, and output the first control signal, which causes feedback control of the source-drain current of the first p-channel MOS transistor and the source-drain current of the second p-channel MOS transistor.

4. The resistive random access memory according to any one of claims 1, 2 and 3, further comprising: a plurality of first reference resistance elements; as well as a first write control circuit configured to couple a first end of at least one of the plurality of first reference resistance elements to the first voltage control circuit during the first write operation, Wherein, the resistance of the first resistance element set by the first writing operation is set to one of a plurality of first values ​​according to the number of first reference resistance elements coupled to the first voltage control circuit.

5. The resistive random access memory according to claim 3, wherein The second variable resistance element includes a plurality of second p-channel MOS transistors, and The resistance of the first resistance element set by the first writing operation is set to one of a plurality of first values ​​according to the number of second p-channel MOS transistors coupled between the first voltage line and the first reference resistance element.

6. The resistive random access memory according to any one of claims 1, 2, 3 and 5, wherein The other second end of the first resistance element is coupled to a reference voltage line set to a reference voltage, and The other second end of the first reference resistance element is coupled to a voltage line set to a voltage higher than the reference voltage.

7. The resistive random access memory according to claim 1, wherein: The first voltage control circuit comprises: a first n-channel MOS transistor having: a source coupled to the first end of the first resistor element; and a gate and a drain coupled to each other, a second n-channel MOS transistor having: a source coupled to the first end of the first reference resistor element; and a gate coupled to the gate of the first n-channel MOS transistor, a seventh p-channel MOS transistor having: a drain coupled to the drain of the first n-channel MOS transistor; and a source coupled to the first voltage line set to a first voltage during the first write operation, and an eighth p-channel MOS transistor having a drain and a gate coupled to the drain of the second n-channel MOS transistor and the gate of the seventh p-channel MOS transistor, and a source coupled to the first voltage line set to a first voltage during the first write operation.

8. The resistive random access memory according to any one of claims 1, 2, 3, 5 and 7, further comprising: a second reference resistor element having a resistance set to a second value; as well as a second voltage control circuit disposed between a second voltage line and first ends of the first resistance element and the second reference resistance element, wherein during a second write operation in which the resistance of the first resistance element changes from the first value to a second value, the second voltage line is set to the first voltage, and the second voltage control circuit is configured to: adjust the value of a second voltage supplied from the second voltage line during the second write operation to reduce a difference between currents flowing through the first resistance element and the second reference resistance element; The adjusted second voltage is supplied to the other second end of the first resistance element and the first end of the first reference resistance element.

9. The resistive random access memory according to claim 8, wherein: The second voltage control circuit comprises: a third variable resistance element disposed between the second voltage line and the other second end of the first resistance element, and the resistance of the third variable resistance element changes according to a second control signal, a fourth variable resistance element disposed between the second voltage line and the first end of the second reference resistance element, and the resistance of the fourth variable resistance element varies according to the second control signal, and A second voltage comparator is configured to compare the voltage at the other second end of the first resistance element with the voltage at the first end of the second reference resistance element, and output the second control signal, wherein when the voltage at the other second end of the first resistance element becomes lower than the voltage at the first end of the second reference resistance element, the second control signal reduces the resistance of the third variable resistance element and the fourth variable resistance element.

10. The resistive random access memory according to claim 9, wherein The third variable resistance element includes a third p-channel MOS transistor having a source coupled to the second voltage line, a drain coupled to the other second end of the first resistance element, and a gate receiving the second control signal. The fourth variable resistance element includes a fourth p-channel MOS transistor having a source coupled to the second voltage line, a drain coupled to the first end of the second reference resistance element, and a gate receiving the second control signal, and The second voltage comparator includes a second operational amplifier having a non-inverting input terminal coupled to the other second end of the first resistance element, an inverting input terminal coupled to the first end of the second reference resistance element, and an output terminal outputting the second control signal. in, The second operational amplifier is configured to amplify a difference between a voltage at the other second end of the first resistance element and a voltage at the first end of the second reference resistance element, and output a second control signal causing feedback control of a source-drain current of the third p-channel MOS transistor and a source-drain current of the fourth p-channel MOS transistor.

11. The resistive random access memory according to any one of claims 1, 2, 3, 5 and 7, further comprising: a third reference resistance element having a resistance set between the first value and the second value; a third voltage control circuit disposed between a third voltage line and the other second end of the first resistance element and the first end of the third reference resistance element, the third voltage line being set to a third voltage during a read operation that reads data stored in a memory cell, and the third voltage control circuit being configured to: adjust a value of a third voltage supplied from the third voltage line during the read operation to reduce a difference between currents flowing through the first resistance element and the third reference resistance element; and supplying the adjusted third voltage to the first end of the first resistance element and the first end of the third reference resistance element; as well as A sense amplifier is configured to determine data stored in the memory cell based on a voltage at the other second end of the first resistance element and a reference voltage.

12. The resistive random access memory according to claim 11, wherein: The third voltage control circuit comprises: a fifth variable resistance element, arranged between the third voltage line and the other second end of the first resistance element, and the resistance of the fifth variable resistance element changes according to a third control signal, a sixth variable resistance element disposed between the third voltage line and the first end of the third reference resistance element, and the resistance of the sixth variable resistance element varies according to the third control signal, and a third voltage comparator configured to compare the voltage at the other second end of the first resistance element with the voltage at the first end of the third reference resistance element and output the third control signal, wherein when the voltage at the other second end of the first resistance element becomes higher than the voltage at the first end of the third reference resistance element, the third control signal causes the resistance of the fifth variable resistance element and the sixth variable resistance element to decrease, and when the voltage at the other second end of the first resistance element becomes lower than the voltage at the first end of the third reference resistance element, the third control signal causes the resistance of the fifth variable resistance element and the sixth variable resistance element to increase.

13. The resistive random access memory according to claim 12, wherein The fifth variable resistance element includes a fifth p-channel MOS transistor having a source coupled to the third voltage line, a drain coupled to the first end of the first resistance element, and a gate receiving the third control signal. The sixth variable resistance element includes a sixth p-channel MOS transistor having a source coupled to the third voltage line, a drain coupled to the first end of the third reference resistance element, and a gate receiving the third control signal, and The third voltage comparator comprises a third operational amplifier having a non-inverting input terminal coupled to the first end of the first resistor element, an inverting input terminal coupled to the first end of the third reference resistor element, and an output terminal for outputting the third control signal. in, The third operational amplifier is configured to amplify a difference between a voltage at a first end of the first resistance element and a voltage at a first end of the third reference resistance element, and output the third control signal, which causes feedback control of a source-drain current of the fifth p-channel MOS transistor and a source-drain current of the sixth p-channel MOS transistor.

14. The resistive random access memory according to claim 11, wherein: The third voltage control circuit comprises: a third n-channel MOS transistor having a source coupled to the first end of the first resistance element, and a gate and a drain coupled to each other, a fourth n-channel MOS transistor having a source coupled to the first end of the first reference resistance element and a gate coupled to the gate of the third n-channel MOS transistor, a seventh p-channel MOS transistor having: a drain coupled to the drain of the third n-channel MOS transistor; and a source coupled to the third voltage line set to a third voltage during the read operation, and an eighth p-channel MOS transistor having a drain and a gate coupled to the drain of the fourth n-channel MOS transistor and the gate of the seventh p-channel MOS transistor, and a source coupled to the third voltage line set to a third voltage during the read operation.

15. The resistive random access memory according to claim 1, further comprising: a plurality of first resistance elements; a plurality of word lines coupled to the first ends of the plurality of first resistance elements; as well as a plurality of bit lines coupled to the other second ends of the plurality of first resistor elements, and the plurality of bit lines intersect the plurality of word lines, The plurality of first resistance elements are respectively arranged at intersections of the plurality of word lines and the plurality of bit lines, and The first reference resistance element and the first voltage control circuit are coupled to each bit line of the plurality of bit lines.

16. The resistive random access memory according to claim 15, further comprising: a fourth reference resistance element coupled in parallel to the first reference resistance element disposed on each bit line of the plurality of bit lines; as well as A first resistance setting circuit is arranged on each bit line of the multiple bit lines and is configured to: during the first write operation, before setting the resistance of a first resistance element among the multiple first resistance elements coupled to one of the multiple bit lines to the first value, set the resistance of the fourth reference resistance element to a resistance that is the same as the combined resistance of the other first resistance elements coupled to the multiple bit lines.

17. The resistive random access memory according to claim 8, further comprising: a plurality of first resistance elements; a plurality of word lines coupled to the first ends of the plurality of first resistance elements; as well as a plurality of bit lines coupled to the other second ends of the plurality of first resistor elements, and the plurality of bit lines intersect the plurality of word lines, The plurality of first resistance elements are respectively arranged at intersections of the plurality of word lines and the plurality of bit lines, and The second reference resistance element and the second voltage control circuit are coupled to each bit line of the plurality of bit lines.

18. The resistive random access memory according to claim 17, further comprising: a fifth reference resistance element coupled in parallel to the second reference resistance element disposed on each of the plurality of bit lines; as well as A second resistance setting circuit is provided for each of the multiple bit lines, and the second resistance setting circuit is configured to: during the second write operation, before setting the resistance of a first resistance element among the multiple first resistance elements coupled to one of the multiple bit lines to the second value, set the resistance of the fifth reference resistance element to a resistance that is the same as the combined resistance of the other first resistance elements coupled to the multiple bit lines.

19. The resistive random access memory according to claim 15 or 16, further comprising: Reference word line; a sixth reference resistance element disposed at each intersection of the reference word line and the plurality of bit lines; as well as a read control circuit coupled to each of the plurality of bit lines and configured to perform a read operation in which data is read from a first resistance element that is a target of the read operation and is coupled to one of the plurality of bit lines, Wherein, the reading control circuit comprises: The first capacitive element, The second capacitive element, a first switch disposed between one end of the first capacitive element and a corresponding bit line among the plurality of bit lines, and configured to be turned on during a first period of the read operation, in which a current from the corresponding bit line flows only to the sixth reference resistance element, and to be turned off during a second period of the read operation, in which a current from the corresponding bit line flows only to the first resistance element as a target of the read operation, a second switch disposed between one end of the second capacitive element and a corresponding bit line among the plurality of bit lines and configured to be turned off during the first period and turned on during the second period, a current integrating circuit configured to generate a voltage according to a current flowing through the bit line, and A sense amplifier is configured to determine data stored in a first resistance element as a target of the read operation based on a voltage according to the charge accumulated in the first capacitance element and a voltage according to the charge accumulated in the second capacitance element.

20. A method for controlling a resistive random access memory, the resistive random access memory comprising: a memory cell including a first resistance element whose resistance varies according to a write operation, and the memory cell is configured to store data according to the resistance of the first resistance element; and a first reference resistance element, the resistance of the first reference resistance element being set to a first value, the method comprising: setting a first voltage line to a first voltage during a first write operation in which the resistance of the first resistive element changes from a second value higher than the first value to the first value; generating the first voltage during the first write operation, the first voltage being supplied to a first end of the first resistance element and a first end of the first reference resistance element; as well as The voltage at the first end of the first resistance element is compared with the voltage at the first end of the first reference resistance element, and when the voltage at the first end of the first resistance element becomes higher than the voltage at the first end of the first reference resistance element, the value of the first voltage supplied from the first voltage line is adjusted to reduce the difference between the currents flowing through the first resistance element and the first reference resistance element during the first write operation, thereby supplying the adjusted first voltage to the first end of the first resistance element and the first end of the first reference resistance element.

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