Semiconductor memory device

Abstract

An embodiment of the present application provides a semiconductor storage device that shortens the time for energization readout processing. The semiconductor storage device of an embodiment has a memory plane (P0) that can store user data and system information, a memory plane (P1) that can store user data and system information, a latch circuit (ADL) of the memory plane (P0) that can store one of even bit data or odd bit data of the system information read out from the memory plane (P0), a latch circuit (ADL) of the memory plane (P1) that can store the other of the even bit data or the odd bit data of the system information read out from the memory plane (P1), and a sequencer (27). The sequencer (27) performs in parallel a first process of reading out the even bit data and storing into the latch circuit (ADL) of the memory plane (P0) and a second process of reading out the odd bit data and storing into the latch circuit (ADL) of the memory plane (P1).

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2020-157807 (filed on September 18, 2020). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0004] Non-volatile memories such as NAND (Not-And) flash memory perform power-on readout processes when the memory system boots up, reading system information such as setting parameters from a specified memory area. If the amount of system information increases, the time to read the system information increases, and the power-on readout process itself becomes longer. Summary of the Invention

[0005] One embodiment of the present invention aims to provide a semiconductor memory device that shortens the time required for power-on readout processing.

[0006] One embodiment of a semiconductor memory device includes: a first memory cell array capable of storing user data and system information, wherein the system information is information used for writing and reading the user data; a second memory cell array capable of storing the user data and the system information; a first latch circuit capable of storing one of the even-numbered bits or odd-numbered bits of the system information read from the first memory cell array, namely, a first bit data; a second latch circuit capable of storing the other of the even-numbered bits or odd-numbered bits of the system information read from the second memory cell array, namely, a second bit data; and a control circuit that performs in parallel a first process of reading the first bit data and storing it in the first latch circuit and a second process of reading the second bit data and storing it in the second latch circuit. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating a configuration example of the memory system according to the first embodiment.

[0008] Figure 2 This is a block diagram illustrating a configuration example of the non-volatile memory in the first embodiment.

[0009] Figure 3 This is a diagram illustrating an example of the circuit configuration of a block of a three-dimensional NAND memory according to the first embodiment.

[0010] Figure 4This is a cross-sectional view of a block of a three-dimensional NAND memory according to the first embodiment.

[0011] Figure 5 This is a diagram showing the configuration of blocks in a memory cell array when viewed from the multiple bit line side in the first embodiment.

[0012] Figure 6 This is a diagram illustrating an example of the threshold region in the first embodiment.

[0013] Figure 7 This is a circuit diagram illustrating an example of the specific configuration of the sensing amplifier in the first embodiment.

[0014] Figure 8A This is a diagram showing the operating waveform of the sensing amplifier in the first embodiment.

[0015] Figure 8B This is a diagram showing an example of the operating waveform of the sensing amplifier in the voltage sensing method of the first embodiment.

[0016] Figure 9 This is a waveform diagram showing the voltage change during the readout of the current sensing method in the first embodiment.

[0017] Figure 10 This is a waveform diagram showing the voltage change during readout of the voltage sensing method of the first embodiment.

[0018] Figure 11 This is a diagram schematically illustrating the arrangement of the even-numbered bit line and the odd-numbered bit line among the plurality of bit lines in the first embodiment.

[0019] Figure 12 This is a diagram used to illustrate the case where data is read out for the even-numbered bit line and the odd-numbered bit line in the first embodiment.

[0020] Figure 13 This is a diagram illustrating the processing flow of reading system information from two memory surfaces in the first embodiment.

[0021] Figure 14 This is a graph showing a comparison of the readout times of system information in the first embodiment.

[0022] Figure 15 This is a graph showing the time of peak current generation in a variation of the first embodiment.

[0023] Figure 16 This is a diagram illustrating the processing flow of reading system information from two memory surfaces in the second embodiment.

[0024] Figure 17 This is a graph showing the readout time of system information in the second embodiment.

[0025] Figure 18 This is a diagram illustrating the processing flow of reading system information from two memory surfaces in the third embodiment.

[0026] Figure 19 This is a graph showing the readout time of system information in the third embodiment. Detailed Implementation

[0027] The embodiments will now be described with reference to the accompanying drawings.

[0028] (First Embodiment)

[0029] (The structure of a memory system)

[0030] Figure 1 This is a block diagram illustrating a configuration example of the memory system according to the first embodiment. The memory system of this embodiment includes a memory controller 1 and non-volatile memory 2. The memory system can be connected to a host computer. The host computer is, for example, an electronic device such as a personal computer or a portable terminal.

[0031] Non-volatile memory 2 is a semiconductor storage device that stores data non-volatilely, such as NAND flash memory. In this embodiment, non-volatile memory 2 is a NAND memory with memory cell transistors, each capable of storing 3 bits, i.e., a 3-bit / Cell (TLC: Triple Level Cell) NAND memory. Non-volatile memory 2 is three-dimensional.

[0032] In addition, the non-volatile memory 2 can also be a NAND memory with a storage cell transistor that can store 2 bits per storage cell transistor, i.e., a 2-bit / Cell (MLC: Multi Level Cell) NAND memory, or a NAND memory with a storage cell transistor that can store 4 bits per storage cell transistor, i.e., a 4-bit / Cell (QLC: Quad Level Cell) NAND memory.

[0033] Furthermore, the non-volatile memory 2 can also be a NAND memory with a storage cell transistor that can store 1 bit per storage cell transistor, i.e., a 1-bit / Cell (SLC: Single Level Cell) NAND memory.

[0034] The memory controller 1 controls the writing of data to the non-volatile memory 2 according to write requests from the host. Additionally, the memory controller 1 controls the reading of data from the non-volatile memory 2 according to read requests from the host. The memory controller 1 includes RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC (Error Checking and Correction) circuit 14, and a memory interface 15. The RAM 11, processor 12, host interface 13, ECC circuit 14, and memory interface 15 are interconnected via an internal bus 16.

[0035] The host interface 13 outputs requests received from the host, user data (write data), etc., to the internal bus 16. In addition, the host interface 13 sends user data read from the non-volatile memory 2, responses from the processor 12, etc., to the host.

[0036] The memory interface 15 controls, based on instructions from the processor 12, the processes of writing user data, etc., to the non-volatile memory 2 and the processes of reading user data, etc., from the non-volatile memory 2.

[0037] Processor 12 provides overall control over memory controller 1. Processor 12 may be, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), or the like. Upon receiving a request from the host via host interface 13, processor 12 performs control according to that request. For example, based on a request from the host, processor 12 instructs memory interface 15 to write user data and parity data to non-volatile memory 2. Additionally, based on a request from the host, processor 12 instructs memory interface 15 to read user data and parity data from non-volatile memory 2.

[0038] Processor 12 determines a storage region (hereinafter referred to as a memory region) on non-volatile memory 2 for user data stored in RAM 11. User data is stored in RAM 11 via internal bus 16. Processor 12 determines the memory region for page data, which is written in page units. In this specification, user data stored in one page of non-volatile memory 2 is defined as cell data. Cell data is stored in non-volatile memory 2, for example, in the form of encoded codewords.

[0039] Furthermore, encoding is not mandatory. Memory controller 1 can also store cell data in non-volatile memory 2 without encoding, but... Figure 1The diagram shows an example of an encoding configuration. When the memory controller 1 does not perform encoding, the page data is identical to the cell data. Alternatively, a codeword can be generated based on a single cell data unit, or based on segmented data formed from the cell data unit. Furthermore, a codeword can also be generated using multiple cell data units.

[0040] Processor 12 determines the memory region of non-volatile memory 2 as the destination for each unit of data. The memory region of non-volatile memory 2 is assigned a physical address. Processor 12 uses the physical address to manage the memory region as the destination for writing unit data. Processor 12 specifies the physical address of the determined memory region and instructs memory interface 15 to write user data into non-volatile memory 2. Processor 12 manages the mapping between logical addresses (logical addresses managed by the host) and physical addresses of user data. Upon receiving a read request containing a logical address from the host, processor 12 identifies the physical address corresponding to the logical address, specifies the physical address, and instructs memory interface 15 to read the user data.

[0041] ECC circuit 14 encodes user data stored in RAM 11 to generate codewords. Additionally, ECC circuit 14 decodes codewords read from non-volatile memory 2.

[0042] RAM 11 temporarily stores user data received from the host before storing it in non-volatile memory 2, or temporarily stores data read from non-volatile memory 2 before sending it to the host. RAM 11 is, for example, a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0043] Figure 1 The diagram shows an example configuration where the memory controller 1 includes an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 can also be integrated into the memory interface 15. Alternatively, the ECC circuit 14 can also be integrated into the non-volatile memory 2.

[0044] Upon receiving a write request from the host, the memory controller 1 operates as follows: The processor 12 temporarily stores the write data in RAM 11. The processor 12 reads the data stored in RAM 11 and inputs it to the ECC circuit 14. The ECC circuit 14 encodes the input data and provides the codeword to the memory interface 15. The memory interface 15 writes the input codeword to the non-volatile memory 2.

[0045] Upon receiving a read request from the host, the memory controller 1 operates as follows: The memory interface 15 provides the codeword read from the non-volatile memory 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in the RAM 11. The processor 12 sends the data stored in the RAM 11 to the host via the host interface 13.

[0046] (The structure of non-volatile memory)

[0047] Figure 2 This is a block diagram illustrating an example of the configuration of the non-volatile memory according to this embodiment. The non-volatile memory 2 includes a logic control circuit 21, an input / output circuit 22, a two-cell array 23, two sense amplifiers 24, two line decoders 25, a register circuit 26, a sequencer 27, a voltage generation circuit 28, an input / output pad group 32, a logic control pad group 34, and a power input terminal group 35.

[0048] Non-volatile memory 2 is a NAND memory with two memory planes P0 and P1. Each memory plane P0 and P1 contains a memory cell array 23, a sense amplifier 24, and a row decoder 25. Each memory plane P0 and P1 is a unit capable of independently performing read, write, and erase operations.

[0049] The memory cell array 23 comprises multiple blocks. The memory cell array 23 can store user data and system information (SI). Each of the multiple blocks (BLKs) has multiple memory cell transistors (memory cells). In order to control the voltage applied to the memory cell transistors, the memory cell array 23 is equipped with multiple bit lines, multiple word lines, and source lines. The specific structure of the block (BLK) will be described below.

[0050] The input / output pad group 32 has multiple terminals (pads) corresponding to the signals DQ<7:0> and the data strobe signals DQS and / DQS in order to transmit and receive signals containing data with the memory controller 1.

[0051] The logic control pad group 34 has multiple terminals (pads) corresponding to the chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, and write protect signal / WP in order to transmit and receive various signals with the memory controller 1.

[0052] The / CE signal enables selection of non-volatile memory 2. The CLE signal latches the instruction sent as the DQ signal into the instruction register. The ALE signal latches the address sent as the DQ signal into the address register. The WE signal enables writing. The RE signal enables reading. The WP signal disables writing and erasing. The R / B signal indicates whether non-volatile memory 2 is in a ready state (able to receive commands from external sources) or a busy state (unable to receive commands from external sources). Memory controller 1 can know the state of non-volatile memory 2 by receiving the R / B signal.

[0053] The power input terminal group 35 provides various operating power supplies to the non-volatile memory 2 from the outside, and includes multiple terminals for input power supply voltages Vcc, VccQ, Vpp, and ground voltage Vss. The power supply voltage Vcc is the circuit power supply voltage that is typically supplied externally as the operating power supply, for example, a voltage of approximately 3.3V. The power supply voltage VccQ is, for example, a voltage of 1.2V. The power supply voltage VccQ is used for transmitting and receiving signals between the memory controller 1 and the non-volatile memory 2. The power supply voltage Vpp is a power supply voltage higher than the power supply voltage Vcc, for example, a voltage of 12V.

[0054] The logic control circuit 21 and the input / output circuit 22 are connected to the memory controller 1 via a NAND bus. The input / output circuit 22 and the memory controller 1 communicate via the NAND bus to transmit and receive signals DQ (e.g., DQ0 to DQ7).

[0055] The logic control circuit 21 receives external control signals (e.g., chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, and write protect signal / WP) from the memory controller 1 via the NAND bus. The " / " in the signal name indicates active low. Additionally, the logic control circuit 21 sends the ready / busy signal / RB to the memory controller 1 via the NAND bus.

[0056] Register circuit 26 includes an instruction register, an address register, and a status register. The instruction register temporarily stores instructions. The address register temporarily stores addresses. The status register temporarily stores data required for the operation of non-volatile memory 2. Register circuit 26 may include, for example, SRAM.

[0057] The sequencer 27 receives instructions from the register circuit 26 and controls the control circuit of the non-volatile memory 2 according to the sequence of instructions. The sequencer 27 includes a register R.

[0058] The voltage generation circuit 28 receives a power supply voltage from the external source of the non-volatile memory 2 and uses this power supply voltage to generate multiple voltages required for write, read, and erase operations. The voltage generation circuit 28 provides the generated voltages to the two memory cell arrays 23, the two sense amplifiers 24, and the two line decoders 25, etc.

[0059] The row decoder 25 of each memory plane P0 and P1 receives the row address from the register circuit 26 and decodes the row address. Based on the decoded row address, the row decoder 25 performs word line selection. Then, the row decoder 25 transmits the multiple voltages required for write, read, and erase operations to the selected block.

[0060] The sense amplifiers 24 of each memory plane P0 and P1 receive the column address from the register circuit 26 and decode the column address. Based on the decoded column address, the sense amplifier 24 selects any bit line. Furthermore, when reading data, the sense amplifier 24 detects and amplifies the data read from the memory cell transistor to the bit line. Additionally, when writing data, the sense amplifier 24 writes the data to the bit line.

[0061] The sensing amplifier 24 includes a sensing amplifier unit group 24A and a data register 24B. When reading data, the data register 24B temporarily stores the data detected by the sensing amplifier 24 and serially transmits it to the latch circuit XDL in the sensing amplifier unit group 24A of the input / output circuit 22. Additionally, when writing data, the data register 24B temporarily stores the data serially transmitted from the input / output circuit 22 and transmits it to the sensing amplifier 24. The data register 24B is composed of SRAM or the like.

[0062] (Composition of a memory cell array)

[0063] The storage cell array 23 of the three-dimensional NAND memory contains multiple blocks. Figure 3 This is a diagram illustrating an example of the circuit configuration of a block of three-dimensional NAND memory. Figure 4 This is a cross-sectional view of a block of a three-dimensional NAND memory. Other blocks of the memory cell array 23 also have similar characteristics. Figure 3 Same circuit configuration, and with Figure 4 The same cross-sectional structure.

[0064] like Figure 3 As shown, a block BLK, for example, contains four string cells SU (SU0 to SU3). Each string cell SU contains multiple NAND strings NS. Each NAND string NS, for example, contains eight memory cell transistors MT (MT0 to MT7) and select gate transistors ST1 and ST2. The memory cell transistors MT have a gate and a charge storage layer, and non-volatilely store data.

[0065] Furthermore, the number of memory cell transistors MT is not limited to 8; for example, it can be 32, 48, 64, or 96. The select-gate transistors ST1 and ST2 are shown as a single transistor in the circuit, but they can also be structurally identical to the memory cell transistors. Additionally, for example, to improve critical characteristics, multiple select-gate transistors can be used as select-gate transistors ST1 and ST2 respectively. Furthermore, dummy cell transistors can be provided at locations where the periodicity of the memory cell transistor MT is disordered, such as between the memory cell transistor MT and the select-gate transistors ST1 and ST2.

[0066] The memory cell transistor MT is configured in series between the select gate transistors ST1 and ST2. The memory cell transistor MT7 on one side is connected to one end of the select gate transistor ST1, and the memory cell transistor MT0 on the other side is connected to one end of the select gate transistor ST2.

[0067] The gates of the select gate transistors ST1 for each of the serial cells SU0 to SU3 are all connected to the select gate lines SGD0 to SGD3. On the other hand, the gates of the select gate transistors ST2 are all connected to the same select gate line SGS across multiple serial cells SU within the same BLK. Furthermore, the control gates of the memory cell transistors MT0 to MT7 within the same BLK are all connected to the word lines WL0 to WL7. That is, the word lines WL0 to WL7 and the select gate line SGS are all connected across multiple serial cells SU0 to SU3 within the same BLK. In contrast, the select gate line SGD is independent for each of the serial cells SU0 to SU3, even within the same BLK.

[0068] The control gate electrodes of the memory cell transistors MT0 to MT7 constituting the NAND string NS are respectively connected to word lines WL0 to WL7. Furthermore, the memory cell transistors MTi (i = 0 to n) in each NAND string NS are interconnected via the same word line WLi (i = 0 to n). That is, the corresponding ( Figure 4 In the NAND flash memory, the control gate electrodes of the memory cell transistors MTi (which are at the same height in the D3 direction) are connected to the same word line WLi. Furthermore, in the following description, the NAND flash memory NS may sometimes be simply referred to as "flash".

[0069] The other end of the select gate transistor ST1 of the NAND string NS (the end not connected to the memory cell transistor MT7) is connected to any one of the m bit lines. Bit line BL is commonly connected to the NAND string NS at any location within each string cell SU0 to SU3 in the same BLK block. Furthermore, bit line BL is connected to the corresponding NAND string NS across multiple BLK blocks. Additionally, the other end of the select gate transistor ST2 (the end not connected to the memory cell transistor MT0) is connected to the source line CELSRC. The source line CELSRC is connected to multiple NAND strings NS across multiple BLK blocks.

[0070] As described above, the data in the memory cells (memory cell transistors MT) within the same BLK is erased in a comprehensive manner. On the other hand, data reading and writing are performed in memory cell groups MG (or page units). In this specification, multiple memory cells connected to one word line WLi and belonging to one serial unit SU are defined as memory cell groups MG. During read and write operations, one word line WLi and one select gate line SGD are selected according to the physical address to select the memory cell group MG.

[0071] Each memory plane, P0 and P1, contains a user data area and a ROM (Read Only Memory) area. The user data area stores user data and is accessible to the user of the memory system. The ROM area stores system information (SI) and is typically inaccessible to the user of the memory system.

[0072] like Figure 2 As shown, a portion of the memory cell array 23 in each memory plane P0 and P1 is used as a ROM region. Here, the ROM region is a storage region of at least a portion of one of the multiple blocks BLK contained in the memory cell array 23. Hereinafter, the block BLK having a ROM region will be referred to as a ROM block ROMBLK. In each memory plane P0 and P1, more than two blocks BLK can be used as ROM regions. That is, each memory plane P0 and P1 can contain more than two ROM blocks ROMBLK.

[0073] The ROM area stores, for example, system information required for the operation of the non-volatile memory 2. This system information includes, for example, information used to control the write and read operations of user data. The system information required for the operation of the non-volatile memory 2 includes various setting parameters, such as bad block (unusable block) information, timing information, column redundancy information, and trimming information. Trimming information includes, for example, parameters used to generate a specified voltage.

[0074] After manufacturing, the non-volatile memory 2 is evaluated, and information such as defective blocks (unusable blocks), column redundancy information, and trimming information are stored as system information in the ROM area. System information SI is sent from the non-volatile memory 2 to the memory controller 1 and stored in RAM 11.

[0075] Power-on readout is a read process performed after the memory system or non-volatile memory 2 is booted, used to read system information (SI) from the ROM region. Power-on readout is, for example, the initial data readout process performed after the memory system boots up. Non-volatile memory 2 uses the system information read from the ROM region via power-on readout to control the write and read operations of user data.

[0076] That is, the system information required for the operation of the non-volatile memory 2 is pre-written into the ROM block ROMBLK. The system information is read from the ROM block ROMBLK by power-on readout.

[0077] Figure 4 In this diagram, direction D1 corresponds to the direction in which bit line BL extends, direction D2 corresponds to the direction in which word line WL and select gate lines SGD and SGS extend, and direction D3 corresponds to the stacking direction of word line WL and select gate lines SGD and SGS. Furthermore, direction D1 is parallel to the surface of semiconductor substrate 100, direction D2 is perpendicular to the surface of semiconductor substrate 100 and orthogonal to direction D1, and direction D3 is perpendicular to the surface of semiconductor substrate 100 and orthogonal to both directions D1 and D2.

[0078] like Figure 4 As shown, multiple NAND strings NS are formed on the p-type well region (P-well). That is, on the p-type well region, multiple wiring layers 333 that function as select gate line SGS, multiple wiring layers 332 that function as word line WLi, and multiple wiring layers 331 that function as select gate line SGD are stacked.

[0079] Furthermore, a memory via 334 is formed, penetrating these wiring layers 333, 332, and 331 to reach the p-type well region. On the side of the memory via 334, a barrier insulating film 335, a charge storage layer 336, and a gate insulating film 337 are sequentially formed, thereby embedding a conductive pillar 338 within the memory via 334. The conductive pillar 338, for example, comprises polysilicon and functions as a region forming a channel when the memory cell transistor MT and the select gate transistors ST1 and ST2 contained in the NAND string NS are operated.

[0080] In each NAND string NS, a select gate transistor ST2, multiple memory cell transistors MT, and a select gate transistor ST1 are formed on the p-type well region. A wiring layer, functioning as a bit line BL, is formed above the conductor pillar 338. A contact plug 339, connecting the conductor pillar 338 to the bit line BL, is formed above the conductor pillar 338.

[0081] Furthermore, an n+ type impurity diffusion layer and a p+ type impurity diffusion layer are formed within the surface of the p-type well region. A contact plug 340 is formed on the n+ type impurity diffusion layer, and a wiring layer that functions as a source line CELSRC is formed on the contact plug 340. Additionally, a contact plug 341 is formed on the p+ type impurity diffusion layer, and a wiring layer that functions as a well line CPWELL is formed on the contact plug 341.

[0082] The above Figure 4 The configuration shown is in Figure 4 Multiple NAND strings are arranged along the depth direction (D2 direction) of the paper. A single string unit SU is formed by a collection of multiple NAND strings arranged in a row along the depth direction.

[0083] Figure 5 This is a diagram showing the configuration of blocks in the memory cell array 23 when viewed from the top side of multiple bit lines BL.

[0084] When viewing the memory cell array 23 from the D3 direction, multiple bit lines BL are arranged parallel to each other. Multiple blocks BLK are arranged consecutively in the direction in which the bit lines BL extend. Each block BLK is formed in a direction orthogonal to the bit lines BL.

[0085] Here, the memory cell array 23 of each memory plane P0 and P1 has n blocks BLK.

[0086] The ROM block ROMBLK is the block located approximately at the center of a plurality of BLK blocks arranged in the D1 direction. Figure 5 The block BLK(n / 2) that is approximately in the center of the blocks BLK0 to BLK(n-1) arranged in the D1 direction is the ROM block ROMBLK with the ROM region.

[0087] If n is, for example, 2000, then it is block BLK0 to block BLK1999, and ROM block ROMBLK is the 1000th block BLK1000.

[0088] (Threshold distribution of memory cell transistors)

[0089] The writing operation to the memory cell transistor MT generally includes programming and verification operations. The programming operation is the process of increasing the threshold voltage Vth of the memory cell transistor MT by injecting electrons into the charge accumulation layer 336 (or maintaining the threshold voltage Vth by disabling injection). During the programming operation, the sequencer 27 controls the row decoder 25 to apply the programming voltage Vpgm to the word line WL connected to the target memory cell transistor MT, and controls the sense amplifier 24 to apply the bit line voltage corresponding to the data to be written to the bit line BL connected to the target memory cell transistor MT.

[0090] Figure 6 This is a diagram illustrating an example of the threshold region in this embodiment. Figure 6 The figure above shows an example of the threshold distribution of a 3-bit / cell memory cell transistor MT. In the non-volatile memory 2, information is stored by the amount of charge accumulated in the charge storage film of the memory cell. Each memory cell has a threshold voltage Vth corresponding to the amount of charge. Furthermore, the multiple data values ​​stored in the memory cell are respectively associated with multiple regions (threshold regions) of the threshold voltage Vth.

[0091] Figure 6 The diagram above shows eight distributions (mountain-shaped) labeled Er, A, B, C, D, E, F, and G, representing the threshold distributions within eight threshold regions. Thus, a 3-bit / cell memory cell transistor MT has a threshold distribution separated by seven boundary zones. Figure 12 The horizontal axis represents the threshold voltage Vth, and the vertical axis represents the distribution of the number of storage cells (cell count).

[0092] In this embodiment, the region where the threshold voltage Vth becomes below Vr1 is called region Er; the region where the threshold voltage Vth is greater than Vr1 and becomes below Vr2 is called region A; the region where the threshold voltage Vth is greater than Vr2 and becomes below Vr3 is called region B; and the region where the threshold voltage Vth is greater than Vr3 and becomes below Vr4 is called region C. Furthermore, in this embodiment, the region where the threshold voltage Vth is greater than Vr4 and becomes below Vr5 is called region D; the region where the threshold voltage Vth is greater than Vr5 and becomes below Vr6 is called region E; the region where the threshold voltage Vth is greater than Vr6 and becomes below Vr7 is called region F; and the region where the threshold voltage Vth is greater than Vr7 is called region G.

[0093] In addition, the threshold distributions corresponding to regions Er, A, B, C, D, E, F, and G are respectively called distributions Er, A, B, C, D, E, F, and G (distributions 1 to 8). Vr1 to Vr7 are the threshold voltages Vth that form the boundaries between each region.

[0094] Figure 6The figure below shows an example of the threshold distribution of a 1-bit / cell memory cell transistor MT. Figure 6 The diagram below shows two distributions (mountain-shaped) labeled Er and A, representing the threshold distributions within two threshold regions. Thus, a 1-bit / cell memory transistor MT has a threshold distribution separated by a single boundary.

[0095] In the non-volatile memory 2, multiple data values ​​are respectively mapped to multiple threshold regions (i.e., threshold distributions) of the memory cell. This mapping is called data encoding. This data encoding is predetermined, and when writing data (programming), the memory cell is injected with charge so that it corresponds to a threshold region of the data value stored according to the data encoding. Furthermore, during reading, a read voltage is applied to the memory cell, and the data is determined based on whether the threshold of the memory cell is higher or lower than the read voltage.

[0096] The non-volatile memory 2 has, for example, two operating modes: a first mode and a second mode. The first mode is, for example, the TLC mode applied when the memory cell transistor MT stores 3 bits of data, and the second mode is the SLC mode applied when the memory cell transistor MT stores 1 bit of data.

[0097] For example, in the user data regions of each memory plane P0 and P1, the memory cell transistor MT has a threshold distribution of 3 bits / cell. The actions of writing data to and reading data from the user data regions of each memory plane P0 and P1 are performed in Mode 1. Furthermore, in the user data regions of each memory plane P0 and P1, the memory cell transistor MT can have any of the following threshold distributions: 4 bits / cell, 3 bits / cell, 2 bits / cell, or 1 bit / cell, or a combination of these threshold distributions.

[0098] For example, in the ROM regions of each memory plane P0 and P1, the memory cell transistor MT has a threshold distribution of 1 bit / cell. Writing data to and reading data from the ROM regions of each memory plane P0 and P1 is performed in the second mode. Furthermore, in the ROM regions of each memory plane P0 and P1, the memory cell transistor MT can have any of the following threshold distributions: 4 bit / cell, 3 bit / cell, 2 bit / cell, or 1 bit / cell, or a combination of these threshold distributions. However, compared to the user data region, the ROM region requires higher reliability. Therefore, it is preferable to use a 1 bit / cell or 2 bit / cell memory cell transistor MT.

[0099] In mode 2, such as Figure 6As shown in the figure below, the threshold level is 1, and binary data 0 or 1 is stored in each memory cell transistor MT.

[0100] (Sensing amplifier)

[0101] In the non-volatile memory 2, a sense amplifier 24 is used when writing data to and reading data from the memory cell transistor MT.

[0102] In non-volatile memory 2, data is read from the memory cell transistor MT using either current sensing or voltage sensing. Current sensing involves sensing the current flowing in the bit line BL. Voltage sensing involves sensing changes in the voltage across the bit line BL.

[0103] In the current sensing method, for example, to ensure high-speed operation, data is read out to the sensing amplifier 24 for all bit lines BL of the select word line WL. In the voltage sensing method, for example, to ensure readout accuracy, data is read out to the sensing amplifier 24 for the even-numbered bit line BLe and the odd-numbered bit line BLo of all bit lines BL of the select word line WL. Furthermore, in the current sensing method, the sensing amplifier 24 may also read out only the even-numbered bit line BLe, or only the odd-numbered bit line BLo.

[0104] For example, in the first mode, data readout from the memory cell transistor MT in the user data area is performed by current sensing. Conversely, in the second mode, data readout from the memory cell transistor MT in the ROM area is performed by voltage sensing. Furthermore, data readout in the first mode can be performed by voltage sensing, and data readout in the second mode can also be performed by current sensing. However, the first mode readout of the user data area requires high speed. Therefore, the first mode readout of the user data area is preferably performed by current sensing. Furthermore, the second mode readout of the ROM area requires higher reliability compared to the first mode readout of the user data area. Therefore, the second mode readout of the ROM area is preferably performed by voltage sensing.

[0105] Figure 7 It means Figure 2 The circuit diagram shows an example of the specific configuration of the sensing amplifier 24.

[0106] The sensing amplifier 24 includes multiple sensing amplifier units SAU that correspond to the bit lines BL0 to BL(m-1). Figure 7 This shows the detailed circuit configuration of a single sense amplifier unit (SAU).

[0107] like Figure 7As shown, the sense amplifier unit SAU includes a sense amplifier section SA and latch circuits SDL, ADL, BDL, CDL, and XDL. The sense amplifier section SA and the latch circuits SDL, ADL, BDL, CDL, and XDL are connected via a bus LBUS to allow them to receive data from each other. The latch circuits SDL, ADL, BDL, CDL, and XDL temporarily store read and write data. The latch circuit XDL is connected to the sequencer 27 and is used to input and output data between the sense amplifier unit SAU and the sequencer 27.

[0108] The latch circuit SDL includes, for example, inverters 50 and 51 and n-channel MOS (Metal Oxide Semiconductor) transistors 52 and 53. The input node of inverter 50 and the output node of inverter 51 are connected to node LAT. The input node of inverter 51 and the output node of inverter 50 are connected to node INV. Inverters 50 and 51 store data in nodes INV and LAT. Write data from sequencer 27 is provided to node LAT. The data stored in node INV is the inverted version of the data stored in node LAT.

[0109] One end of the drain-source path of transistor 52 is connected to node INV, and the other end is connected to the bus LBUS. Similarly, one end of the drain-source path of transistor 53 is connected to node LAT, and the other end is connected to the bus LBUS. A control signal STL is input to the gate of transistor 53, and a control signal STI is input to the gate of transistor 52.

[0110] Furthermore, the circuit configurations of latch circuits ADL, BDL, CDL, and XDL are the same as those of latch circuit SDL, therefore their descriptions are omitted. Additionally, the various control signals provided to the sense amplifier unit SAU are supplied by the sequencer 27.

[0111] The sensing amplifier section SA includes, for example, a p-channel MOS transistor 40, n-channel MOS transistors 41-48, and a capacitor 49.

[0112] During the readout operation, the sensing amplifier section SA senses the data read into the corresponding bit line BL and determines whether the read data is "0" or "1". Additionally, during the programming operation, the sensing amplifier section SA sets the corresponding bit line BL to the voltage value corresponding to the data to be written, "0" or "1".

[0113] In the sensing amplifier section SA, transistors 40 to 44 are connected during programming. The source-drain path of transistor 40 and the drain-drain path of transistor 41 are connected in series between the power supply line supplying the internal power supply voltage VDD and node COM. Additionally, the drain-drain path of transistor 44 is connected between node COM and node SRC supplying the ground voltage VSS. Furthermore, the drain-drain path of transistor 42 and the drain-drain path of transistor 43 are connected in series between node COM and bit line BL.

[0114] The gates of transistors 40 and 44 are connected to node INV. Therefore, when node LAT is low (hereinafter referred to as "L") corresponding to data "0", INV is maintained at a high level (hereinafter referred to as "H"), transistor 40 is off, and transistor 44 is on. Conversely, when node LAT is "H" corresponding to data "1", node INV is maintained at "L", transistor 40 is on, and transistor 44 is off.

[0115] During programming, the control signals HLL and XXL provided to the gates of transistors 45 and 46 are "L", respectively, turning transistors 45 and 46 off. The control signal provided to transistor 41 is "H", turning transistor 41 on. Additionally, during programming, transistors 42 and 43 are typically turned on via the control signals BLC and BLS.

[0116] Therefore, if data "0" is stored in node LAT, transistor 40 is turned off and transistor 44 is turned on, and a bit line voltage Vbl_L, such as the voltage VSS (e.g., 0V) from node SRC, is provided to bit line BL. Conversely, if data "1" is stored in node LAT, transistor 40 is turned on and transistor 44 is turned off, and a bit line voltage Vbl_H, such as 2.5V, is provided to bit line BL according to the control signals BLC and BLS assigned to transistors 42 and 43.

[0117] When a programming voltage Vpgm is applied to the word line WL of the programmable object, electrons are accumulated in the charge accumulation layer 336 of the write-to-memory cell transistor MT according to the potential of the corresponding bit line BL. When the data is "0", a voltage VSS is applied to the bit line BL, so electrons are accumulated in the charge accumulation layer 336 of the write-to-memory cell transistor using the programming voltage Vpgm applied to the select word line WL. When the data is "1", a bit line voltage Vbl_H of 2.5V or similar is applied to the bit line BL, so electrons are not accumulated in the charge accumulation layer 336 of the write-to-memory cell transistor using the programming voltage Vpgm applied to the select word line WL.

[0118] The verification process determines whether the threshold voltage Vth of each unit has reached the target level. The verification process is the same as the readout process.

[0119] During the readout operation, all transistors 40-48 and capacitor 49 in the sense amplifier section SA are interconnected. The drain-source paths of transistors 45 and 46 are connected in series between the drain of transistor 40 and node COM. Additionally, the drain-source paths of transistors 48 and 47 are connected in series between the bus LBUS and the reference potential. The sources of transistors 45 and 46 are connected to the sense node SEN, which is connected to the gate of transistor 47. Control signals HLL, XXL, the voltage of sense node SEN, or control signal STB are applied to the gates of transistors 45-48, respectively. The sense node SEN is clocked via capacitor 49.

[0120] Data is read out by applying a readout voltage to the select word line WL using the line decoder 25 and sensing the data read out to the bit line BL using the sensing amplifier 24, thus determining whether the readout data is "0" or "1". Furthermore, to turn on the memory cell transistors connected to the non-select word line WL, the line decoder 25 applies a sufficiently high voltage VREAD to the non-select word line WL to enable the transistors to conduct. Additionally, to facilitate the conduction of memory cell transistors connected to adjacent word lines, a voltage VREADK slightly higher than VREAD can be applied to the adjacent word lines.

[0121] In current-sensing readout, the row decoder 25 applies a readout voltage to the select word line WL and a voltage VREAD or VEREDK to the non-select word line WL. During readout, the sense amplifier 24 holds the bit line BL at a fixed voltage (e.g., 0.5V) and charges the sense node SEN to a specified precharge voltage Vpre higher than the voltage of the bit line BL. In this state, the sequencer 27 connects the sense node SEN to the bit line BL. As a result, current flows from the sense node SEN to the bit line BL, and the voltage of the sense node SEN gradually decreases.

[0122] The voltage at the sensing node SEN varies depending on the state of the threshold voltage Vth of the memory cell transistor connected to the corresponding bit line BL. Specifically, when the threshold voltage Vth of the memory cell transistor is lower than the read voltage, the memory cell transistor is in the on state, a large cell current flows to it, and the voltage at the sensing node SEN decreases more rapidly. Conversely, when the threshold voltage Vth of the memory cell transistor is higher than the read voltage, the memory cell transistor is in the off state, a small cell current flows to it, or no cell current flows to it at all, and the voltage at the sensing node SEN decreases more slowly.

[0123] By utilizing the difference in the rate of voltage drop at the sensing node SEN, the write state of the memory cell transistor is determined, and the result is stored in the data latch circuit. For example, at the first point in time (t4) after a specified first period following the start of discharge from the beginning of releasing the charge at the sensing node SEN (t3 below), it is determined whether the voltage of the sensing node SEN is low (hereinafter referred to as "L") or high (hereinafter referred to as "H"). For example, if the threshold voltage Vth of the memory cell transistor is lower than the read voltage, the memory cell transistor is fully turned on, and a large cell current flows to the memory cell transistor. Therefore, the voltage of the sensing node SEN drops rapidly, and the voltage drop is relatively large. At the first point in time, the sensing node SEN becomes "L".

[0124] Furthermore, when the threshold voltage Vth of the memory cell transistor is higher than the read voltage, the memory cell transistor is in the off state, and the cell current flowing to the memory cell transistor is very small, or the cell current does not flow to the memory cell transistor. Therefore, the voltage of the sensing node SEN decreases very slowly, and the voltage drop is relatively small. At point 1, the sensing node SEN remains "H".

[0125] In this way, by applying a readout voltage to the select word line using the line decoder 25 while monitoring the state of the sense node SEN using the sense amplifier unit group 24A, it is determined whether the threshold voltage Vth of the memory cell transistor is higher or lower than the readout voltage. Therefore, by applying the voltage between each level as the readout voltage to the select word line WL, the level of each memory cell transistor can be determined, and the data assigned to each level can be read out.

[0126] Figure 8A This is a diagram illustrating an example of the operating waveform of the sensing amplifier 24 in a current sensing mode. First, the line decoder 25 applies a readout voltage Vv corresponding to the target state to the select word line WL, and applies a non-select readout voltage Vpass (e.g., 5-7V) higher than the readout voltage Vv to the non-select word line WL.

[0127] During the readout operation, sequencer 27 first sets node INV to "L", turning on transistor 40. Additionally, transistor 41 is turned on via control signal BLX, while control signals BLC and BLS are set to specified voltages, thereby fixing bit line BL at a fixed voltage (e.g., 0.5V). Furthermore, by setting control signal HLL to a specified voltage, sensing node SEN is charged to a specified precharge voltage Vpre, higher than the voltage of bit line BL. In this state, if control signal XXL is set to "H" (t3), current flows from sensing node SEN through transistors 46, 42, and 43 to bit line BL, and the voltage of sensing node SEN gradually decreases.

[0128] The voltage of the sensing node SEN varies depending on the state of the threshold voltage Vth of the memory cell to be read (the selected memory cell). Specifically, when the threshold voltage Vth of the selected memory cell is lower than the read voltage Vv, the selected memory cell is in the ON state, a large cell current flows to it, and the voltage of the sensing node SEN decreases more rapidly. Conversely, when the threshold voltage Vth of the selected memory cell is higher than the read voltage Vv, the selected memory cell is in the OFF state, a small cell current flows to it, or no cell current flows to it, and the voltage of the sensing node SEN decreases more slowly.

[0129] Therefore, if at point t4, after the first period following the start of the discharge of charge from the sensing node SEN (i.e., after the first period following the setting of control signal XXL to "H"), control signal XXL is set to "L" and control signal STB is set to "H" to turn on transistor 48, then transistor 47 will turn on or off depending on whether the voltage of sensing node SEN is "L" or "H". When control signal STB is set to "H" to turn on transistor 48, transistor 47 will turn on or off depending on the potential of sensing node SEN, and the bus LBUS will be updated. Furthermore, the voltage of bit line BL, whether connected to a memory cell transistor in the on state or in the off state, is maintained at a fixed voltage corresponding to control signal BLC (the voltage hardly drops).

[0130] Data is read out in the sensing amplifier 24 by changing the readout voltage while determining the level of each memory cell transistor.

[0131] In voltage-sensing readout, the row decoder 25 applies a readout voltage to the select word line WL and applies voltage VREAD or VREADK to the non-select word line WL. Additionally, the row decoder 25 applies voltage VREAD to the select gate line SGD corresponding to the select string SU, and simultaneously applies voltage VSS to both the select gate line SGD and the select gate line SGS corresponding to the non-select string SU. Then, the sense amplifier 24 charges the bit line BL. After these voltages are applied, the sense amplifier 24 sets the bit line BL to a floating state, and the row decoder 25 applies voltage VREAD to the select gate line SGS. In this way, the bit line BL connected to the on-state memory cell transistor is discharged to voltage VSS, while the bit line BL connected to the off-state memory cell transistor maintains its voltage (without discharging to VSS).

[0132] Figure 8B This is a diagram illustrating an example of the operating waveform of the sensing amplifier 24 in a voltage sensing mode. If, after the bit line BL is charged, a voltage VREAD is applied to the select gate line SGS at time t12 after the time point t11 ​​when it becomes a floating state, the bit line BL connected to the memory cell transistor in the on state is discharged to the voltage VSS, while the bit line BL connected to the memory cell transistor in the off state maintains the voltage (without discharging to VSS).

[0133] Then, if at the second time point t14 after the second period following the start of the discharge of the charge of the sensing node SEN (i.e., after the second period following the start of the discharge of the control signal XXL to “H”), the control signal XXL is set to “L” and the control signal STB is set to “H”, and the transistor 48 is turned on, then the transistor 47 is turned on or off depending on whether the voltage of the sensing node SEN is “L” or “H”.

[0134] Figure 9 This is a waveform diagram showing the voltage change during the readout of the current sensing method. The horizontal axis represents time, and the vertical axis represents voltage. Figure 9 This indicates the case where the voltage of the word line WLn of the read object changes three times when a certain page is read.

[0135] In current-sensing readout, at the start of a series of readouts, a readout spike period is established by applying a specified voltage, such as VREAD (5V), to the select gate line SGS, SGD, and all word lines WL. Then, after the readout spike period ends, in order to reduce the voltage of the select gate line SGD corresponding to the non-select string cell SU to about VSS and to read the data of the memory cell transistor, a voltage of about VREAD is continuously applied to the select gate line SGD and select gate line SGS corresponding to the select string cell SU, while the readout voltage VCGRV is transitioned in the positive direction.

[0136] Figure 10 This is a waveform diagram showing the voltage change during readout in a voltage sensing mode. The horizontal axis represents time, and the vertical axis represents voltage.

[0137] For example, system information is written to the ROM area at 1 bit / cell. That is, system information is written to the ROM area as binary data (i.e., 1 bit data).

[0138] In voltage-sensing readout, a readout voltage VCGRV is applied to the select word line WL. Additionally, except for the select gate line SGD corresponding to the select string cell SU and the select word line WL, a voltage of approximately VREAD is applied to all word lines WL, and a voltage of approximately VSS is applied to the select gate lines SGD and SGS corresponding to the non-select string cells SU. Furthermore, after these voltages are applied, a voltage of approximately VREAD is applied to the select gate line SGS.

[0139] Regarding the multiple bit lines BL, within the block BLK, counting sequentially from the end, there are even-numbered bit lines BLe and odd-numbered bit lines BLo. To ensure the accuracy of system information reading, even-numbered bits and odd-numbered bits of system information are read separately.

[0140] In this embodiment, the system information is stored in the system information area by comparing the even-numbered data (of the even-numbered bit line BLe) of the two data sections (df1, df2) with each other and comparing the odd-numbered data (of the odd-numbered bit line BLo) with each other, in order to check whether there are any errors in the system information.

[0141] Figure 11 This is a diagram that schematically illustrates the configuration of the even-numbered bit line BLe and the odd-numbered bit line BLo in a plurality of bit lines BL.

[0142] Figure 12 This diagram illustrates the data read from the even-numbered bit line BLe and the odd-numbered bit line BLo.

[0143] Can Figure 12 As shown on the upper side, the sensing amplifier 24 first reads the data of the even-numbered bit line BLe (represented by slashes), and then, as... Figure 12 As shown below, read the data for the odd-numbered bit line BLo (represented by a slash). Alternatively, you can first read the data for the odd-numbered bit line BLo (represented by a slash), and then read the data for the even-numbered bit line BLe (represented by a slash).

[0144] When reading data from an even-numbered bit line BLe, a voltage VSS is applied to the odd-numbered bit line BLo. This is to shield each even-numbered bit line BLe from the two odd-numbered bit lines BLo on either side.

[0145] Similarly, when reading data from the odd-numbered bit line BLo, a voltage VSS is applied to the even-numbered bit line BLe. This is to shield each odd-numbered bit line BLo from the two even-numbered bit lines BLe on either side.

[0146] Thus, the sequencer 27 can independently read out the even-numbered bit line BLe and the odd-numbered bit line BLo by controlling the sensing amplifier 24.

[0147] (Reading system information)

[0148] Next, we will explain how to read system information.

[0149] As mentioned above, the system information includes bad block (unusable block) information, column redundancy information, and trimming information. The system information is required for the operation of the non-volatile memory 2.

[0150] Therefore, the system information contains identical data in two separate data sections, in a way that allows for error checking of the read information. The system information is stored on one page. In this case, the two data sections on one page store identical data. Errors in the system information are determined by checking whether the two data sections are identical. This check will be described below.

[0151] In this embodiment, in order to quickly read system information, the data of the even-numbered bit line BLe is read in one of the two memory planes P0 and P1, and the data of the odd-numbered bit line BLo is read in the other of the two memory planes P0 and P1.

[0152] Figure 13 This is a diagram showing the processing flow of reading system information from two memory planes, P0 and P1.

[0153] System information SI includes even-numbered bits of data E read from the even-numbered bit line BLe and odd-numbered bits of data O read from the odd-numbered bit line BLo. As described above, the system information SI stored in memory plane P0 is the same data as the system information SI stored in memory plane P1. System information SI has two data sections df1 and df2. The data in data section df1 is the same as the data in data section df2.

[0154] Even-numbered bit data E is the data read from the selected bit line BLe. Odd-numbered bit data O is the data read from the selected bit line BLo. For example... Figure 13 As shown, even-numbered bit data E is stored in the latch circuit ADL of memory plane P0, and odd-numbered bit data O is stored in the latch circuit ADL of memory plane P1. That is, the latch circuit ADL of each memory plane P0 and P1 can store either the even-numbered bit data E or the odd-numbered bit data O of system information SI read from the memory cell array 23 of memory planes P0 and P1. The latch circuit ADL of memory plane P0 stores one of the even-numbered bit data E or the odd-numbered bit data O of system information SI, and the latch circuit ADL of memory plane P1 stores the other of the even-numbered bit data E or the odd-numbered bit data O of system information SI.

[0155] The processes of reading even-numbered bits of data E from the system information SI of memory plane P0 and transmitting it to the latch circuit ADL, and reading odd-numbered bits of data O from the system information SI of memory plane P1 and transmitting it to the latch circuit ADL, are performed in parallel. The reading process of the system information SI in each memory plane P0 and P1 is performed by the sequencer 27. That is, the sequencer 27, as a control circuit, performs in parallel the first process of reading one of the even-numbered bits of data E or the odd-numbered bits of data O and storing it in the latch circuit ADL of memory plane P0, and the second process of reading the other of the even-numbered bits of data E or the odd-numbered bits of data O and storing it in the latch circuit ADL of memory plane P0.

[0156] Sequencer 27 transfers the even-numbered bits of data E from latch circuit ADL of memory plane P0 to latch circuit XDL of memory plane P0. Similarly, sequencer 27 transfers the odd-numbered bits of data O from latch circuit ADL of memory plane P1 to latch circuit XDL of memory plane P1.

[0157] Figure 2 In the diagram, the double-dotted line d0 indicates that an even number of bits of data E are read from the ROM block ROMBLK of the memory cell array 23 of memory surface P0 and stored in the latch circuit XDL. Similarly, Figure 2 In the diagram, the double-dotted line d1 indicates that odd-bit data O is read from the ROM block ROMBLK of the memory cell array 23 of the memory surface P1 and stored in the latch circuit XDL.

[0158] The even-numbered bits E of the latch circuit XDL of memory plane P0 and the odd-numbered bits O of the latch circuit XDL of memory plane P1 are transmitted to the sequencer 27 via register circuit 26. A complementarity check is performed on the even-numbered bits E and the odd-numbered bits O in the sequencer 27. For example, the sequencer 27 performs a complementarity check on the received even-numbered bits E, and then performs a complementarity check on the received odd-numbered bits O.

[0159] Figure 2 In the diagram, the double-dotted line d01 indicates that the even-numbered bits of data E stored in the latch circuit XDL of memory plane P0 are transferred to the sequencer 27. Similarly, Figure 2 In the diagram, the double-dotted line d11 indicates that the odd-bit data O stored in the latch circuit XDL of memory plane P1 is transmitted to the sequencer 27.

[0160] When the even-numbered bit data E and the odd-numbered bit data O are found to be error-free through the complement check, the sequencer 27 combines the even-numbered bit data E and the odd-numbered bit data O, and then stores the system information SI in the register R.

[0161] As described above, regarding the system information SI stored in the ROM area, in a way that allows for data error checking when storing to or reading from the ROM area, two identical data entries are included in the two data sections df1 and df2, which are divided into two parts. By comparing the even-numbered data entries with each other and the odd-numbered data entries with each other for the two identical data entries in the two data sections df1 and df2, errors in the transmitted system information SI can be checked complementaryly.

[0162] Complementarity checking is performed by comparing the two data units df1 and df2 in 2-byte units to see if they match. For even-numbered bit data E, the two data units df1 and df2 are compared in 2-byte units to determine if they match. For odd-numbered bit data O, the two data units df1 and df2 are also compared in 2-byte units to determine if they match. Therefore, when the data size of system information SI is set to L bytes, data comparison is performed only once, using the number of comparisons (k) obtained by dividing (L / 2) bytes by 2.

[0163] Furthermore, while the complementarity check is performed in sequencer 27, it can also be performed by a dedicated circuit. That is, in the embodiment, the determination of whether the even-numbered bit data E and the odd-numbered bit data O are erroneous is performed by sequencer 27, but it can also be performed by a circuit different from sequencer 27.

[0164] For example, such as Figure 2As shown by the dashed lines, it can also be configured such that complementary checking circuits 24C are provided within each sensing amplifier 24 to perform complementary checks on even-numbered bit data E and odd-numbered bit data O in parallel. That is, the complementary checking circuit 24C of the sensing amplifier 24 on memory plane P0 functions as the first determination circuit for determining whether there is an error in the even-numbered bit data E, and the complementary checking circuit 24C of the sensing amplifier 24 on memory plane P1 functions as the second determination circuit for determining whether there is an error in the odd-numbered bit data O. In this case, since the complementary checks are performed in parallel, the power-on readout processing time is shorter. The results of the two complementary checks are notified to the sequencer 27.

[0165] According to this embodiment, since the processing of reading even-numbered bit data E from the ROM region of memory surface P0 and transmitting it to the latch circuit ADL, and the processing of reading odd-numbered bit data O from the ROM region of memory surface P1 and transmitting it to the latch circuit ADL are executed in parallel, the system information SI can be read quickly.

[0166] As a comparative example, the following method is used: Even-numbered bits of data E are read from the ROM region of memory plane P0 and transmitted to latch circuit ADL; then, odd-numbered bits of data O are read from the ROM region of memory plane P0 and transmitted to latch circuit BDL. In this method, the even-numbered bits of data E and the odd-numbered bits of data O are combined and transmitted as system information to latch circuit XDL. The data stored in latch circuit XDL is then checked for errors.

[0167] However, in this case, if either the even-numbered data E or the odd-numbered data O is faulty, the same operation is then performed using memory plane P1. Therefore, the process of reading the even-numbered data E from the ROM region of memory plane P1 and transferring it to latch circuit ADL, and then reading the odd-numbered data O from the ROM region of memory plane P1 and storing it in latch circuit BDL, needs to be repeated, which is time-consuming.

[0168] Figure 14 This is a graph showing a comparison of the readout times of system information SI in the described embodiment.

[0169] The implementation method ( Figure 14 In the example shown by solid lines, the even-numbered bits of data E are read out in parallel with the odd-numbered bits of data O. In the comparative example, as shown by dashed lines, the even-numbered bits of data E are read out sequentially with the odd-numbered bits of data O.

[0170] Therefore, in the first embodiment, since the processes of reading the even-numbered bit data E of memory surface P0 and storing it in latch circuit XDL and reading the odd-numbered bit data O of memory surface P1 and storing it in latch circuit XDL are performed in parallel, the time taken to read the even-numbered bit data E and the odd-numbered bit data O of system information SI is halved compared to the comparative example.

[0171] As described above, according to the embodiment, a semiconductor memory device that shortens the time required for power-on readout processing can be provided.

[0172] (Example of variation)

[0173] In this configuration, the first process reads even-numbered bits of system information SI from the ROM block ROMBLK of memory plane P0 and transmits them to the latch circuit ADL, and the second process reads odd-numbered bits of system information SI from the ROM block ROMBLK of memory plane P1 and transmits them to the latch circuit ADL in parallel. However, since the first and second processes start simultaneously, the peak current in the non-volatile memory 2 increases. Because the word line WL and bit line BL are charged and configured to read the data, a peak current is generated at the start of reading the even-numbered bits of data E and the odd-numbered bits of data O.

[0174] Therefore, in this variation, in order to prevent the peak current from increasing, a time difference is set between the start time of the first process and the start time of the second process. That is, the two time points are staggered so that the start time of the first process is not the same as the start time of the second process.

[0175] Figure 15 This is a diagram showing the timing of the peak current generation in this variation example. The timing te, when the even-numbered bits of system information SI are read from the ROM block ROMBLK of memory plane P0, and the timing to, when the odd-numbered bits of system information SI are read from the ROM block ROMBLK of memory plane P1, are offset by a time td.

[0176] Therefore, the generation time of the peak current Ip based on time point te does not coincide with the generation time of the peak current Ip based on time point toto. Figure 15 In the diagram, the peak current Ip is represented by a dashed line in the shape of a mountain.

[0177] According to this variation, the peak current in the first process of reading even-numbered bits of data E does not coincide with the peak current in the second process of reading odd-numbered bits of data O. Therefore, the peak current in the non-volatile memory 2 can be reduced.

[0178] (Second Implementation)

[0179] In the first embodiment, even-numbered bit data E is read from one memory plane and odd-numbered bit data O is read from another memory plane. However, in the second embodiment, it is assumed that when there is an error in the even-numbered bit data E or the odd-numbered bit data O read from one memory plane, the erroneous even-numbered bit data E or the odd-numbered bit data O is read from the other memory plane.

[0180] Since the memory system of the second embodiment has the same structure as the memory system of the first embodiment, the same symbols are used for the same constituent elements and the description is omitted. Only the different structures are described.

[0181] Figure 16 This is a diagram illustrating the processing flow of reading system information from two memory surfaces P0 and P1 in the second embodiment. Figure 17 This is a graph showing a comparison of the readout times of system information SI in the second embodiment.

[0182] For example, the even-numbered bits E of system information SI are read from the ROM block ROMBLK of memory plane P0 and stored in the latch circuit ADL. The odd-numbered bits O of system information SI are read from the ROM block ROMBLK of memory plane P1 and stored in the latch circuit ADL. In this case, when the result of the complementary check is that the even-numbered bits E is incorrect (indicated by the × symbol), the sequencer 27 reads the even-numbered bits E from the ROM block ROMBLK of memory plane P1 and stores them in the latch circuit BDL.

[0183] Then, a complementary check is performed on the even-numbered bit data E read from the ROM region of memory plane P1. If the complementary check finds that the even-numbered bit data E is error-free, the even-numbered bit data E read from the ROM block ROMBLK of memory plane P1 is combined with the odd-numbered bit data O to generate system information SI, which is then stored in register R.

[0184] According to this embodiment, only data with errors (even-bit data E or odd-bit data O) resulting from the complementary check are read from the error-free memory surface (memory surface P1 in this example), so system information can be read quickly.

[0185] Figure 17 The dashed lines in the diagram indicate that, in the comparative example described, after reading even-numbered bits of data E and odd-numbered bits of data O from the ROM block ROMBLK of memory plane P0, a complementarity check is performed. Furthermore, if the complementarity check reveals an error in either even-numbered bits of data E or odd-numbered bits of data O, then even-numbered bits of data E and odd-numbered bits of data O are read from the ROM block ROMBLK of memory plane P1, and a complementarity check is performed. Therefore, in the comparative example, power-on readout time is consumed.

[0186] In contrast, in this embodiment, when either the even-numbered bit data E or the odd-numbered bit data O is erroneous in one of the two memory planes, only the erroneous even-numbered or odd-numbered bit data is read from the other memory plane. That is, based on the determination of whether the even-numbered bit data E or the odd-numbered bit data O is erroneous, the sequencer 27 performs a third process—reading one of the even-numbered bit data E or the odd-numbered bit data O from the memory cell array 23 of the memory plane where the other of the even-numbered bit data E or the odd-numbered bit data O was not determined to be erroneous—when it determines that one of the even-numbered bit data E or the odd-numbered bit data O is erroneous. The determination of whether the even-numbered bit data E or the odd-numbered bit data O is erroneous can also be performed by a circuit different from the sequencer 27.

[0187] Therefore, in the second embodiment, in addition to the effects of the first embodiment, system information can also be read quickly even if there are errors in the even-numbered bit data E or the odd-numbered bit data O read.

[0188] Furthermore, variations of the first embodiment can also be applied in this embodiment. That is, the peak current Ip generated when reading even-numbered bit data E is not coincident with the peak current Ip generated when reading odd-numbered bit data O.

[0189] (Third Implementation)

[0190] In the second embodiment, when it is determined that the even-numbered bit data E or odd-numbered bit data O read from one memory surface is erroneous, the erroneous even-numbered bit data E or odd-numbered bit data O is read from the other memory surface that is error-free. In the third embodiment, instead of waiting for the determination of whether the even-numbered bit data E or odd-numbered bit data O read from the two memory surfaces P0 and P1 is erroneous, the unread odd-numbered bit data O and even-numbered bit data E are read from the two memory surfaces P0 and P1 respectively during the complementary check. That is, in the third embodiment, in order to prevent the even-numbered bit data E and odd-numbered bit data O read from the two memory surfaces P0 and P1 from being erroneous, both even-numbered bit data E and odd-numbered bit data O are read from each memory surface P0 and P1 in advance.

[0191] The memory system of the third embodiment has the same configuration as the memory systems of the first and second embodiments. Therefore, the same symbols are used for the same constituent elements and the description is omitted. Only the different configurations are described.

[0192] Figure 18 This is a diagram illustrating the processing flow of reading system information from two memory surfaces P0 and P1 in the third embodiment. Figure 19 This is a graph showing the readout time of system information SI in the third embodiment.

[0193] like Figure 18 As shown, even-numbered bit data E and odd-numbered bit data O are read from memory planes P0 and P1, respectively. Then, a complementarity check is performed on the read even-numbered bit data E and odd-numbered bit data O. During this complementarity check, odd-numbered bit data O and even-numbered bit data E are read from memory planes P0 and P1, respectively.

[0194] If one of the even-numbered bit data E and the odd-numbered bit data O read from the two memory planes P0 and P1 is erroneous, the sequencer 27 can immediately perform a complementary check using data read from the other memory plane other than the one with the erroneous data after the error has been identified.

[0195] Figure 18 In the process, after reading the even-numbered bit data E from memory plane P0 and storing it in latch circuit ADL, and reading the odd-numbered bit data ODD from memory plane P1 and storing it in latch circuit ADL, a complementarity check is performed on the even-numbered bit data E and the odd-numbered bit data O.

[0196] During the complement check, odd-numbered bits of data O are read from memory plane P0 and stored in latch circuit BDL. Similarly, during the complement check, even-numbered bits of data E are read from memory plane P1 and stored in latch circuit BDL. That is, without waiting for the result of the complement check to be clear, sequencer 27 begins to read odd-numbered bits and even-numbered bits from memory planes P0 and P1 that are the opposite of the already read even-numbered bits of data E and odd-numbered bits of data O.

[0197] Figure 19 The diagram illustrates the case where, when an even-numbered bit data E read from memory plane P0 is determined to be erroneous, a complementary check is performed on the even-numbered bit data E already read from memory plane P1.

[0198] As described above, when the sequencer 27 determines whether there is an error in the even-numbered bit data E or the odd-numbered bit data O, it performs a third process of reading the odd-numbered bit data O from the memory cell array 23 of memory plane P0 and reading the even-numbered bit data E from the memory cell array 23 of memory plane P1. The determination of whether there is an error in the even-numbered bit data E or the odd-numbered bit data O can also be performed by a circuit different from the sequencer 27.

[0199] According to this embodiment, in order to prevent errors from being detected in the results of the complementary check, both even-numbered bit data E and odd-numbered bit data O are read in advance in each memory plane, so the system information SI can be read quickly.

[0200] Therefore, in addition to the effects of the first embodiment, the third embodiment can also quickly read system information even if there are errors in the even-numbered bit data E or the odd-numbered bit data O read.

[0201] Furthermore, variations of the first embodiment can also be applied in this embodiment. That is, the generation time of the peak current Ip when reading even-numbered bits of data E may not coincide with the generation time of the peak current Ip when reading odd-numbered bits of data O.

[0202] As described above, according to the various embodiments, a semiconductor memory device that shortens the time required for power-on readout processing can be provided.

[0203] Several embodiments of the present invention have been described, but these embodiments are illustrative by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

[0204] [Explanation of Symbols]

[0205] 1. Memory controller

[0206] 2. Non-volatile memory

[0207] 11 RAM

[0208] 12 processors

[0209] 13 Host Interface

[0210] 14 ECC Circuit

[0211] 15. Memory Interface

[0212] 16 Internal Bus

[0213] 21 Logic Control Circuit

[0214] 22 Input / Output Circuit

[0215] 23-cell storage array

[0216] 24 Sensing Amplifier

[0217] 24A Sensing Amplifier Unit Group

[0218] 24B Data Register

[0219] 24C Complementary Check Circuit

[0220] 25-line decoder

[0221] 26 Register Circuit

[0222] 27 Sequencer

[0223] 28 Voltage Generation Circuit

[0224] 32 Input / Output Pad Group

[0225] 34 Logic Control Pad Group

[0226] 35 Power input terminal blocks

[0227] 40, 41, 42, 43, 44, 45, 46, 47, 48 Transistors

[0228] 49 Capacitors

[0229] 50, 51 inverters

[0230] 52 and 53 transistors

[0231] 100 Semiconductor Substrate

[0232] 331, 332, 333 wiring layers

[0233] 334 memory hole

[0234] 335 Barrier Insulating Film

[0235] 336 Charge Accumulation Layer

[0236] 337 Gate insulating film

[0237] 338 Conductor Column

[0238] 339 Contact plug

[0239] 340 Contact plug

[0240] 341 Contact plug.

Claims

1. A semiconductor memory device having The first storage unit array can store user data and system information, wherein the system information is the information used for writing and reading user data. The second storage unit array is capable of storing the user data and the system information; The first latch circuit can store one of the even-numbered bits or odd-numbered bits of the system information read from the first memory cell array, namely the first bit data; The second latch circuit is capable of storing either the even-numbered bit data or the odd-numbered bit data of the system information read from the second memory cell array, namely, the second bit data; and The control circuit performs, in parallel, a first process of reading the first bit of data and storing it in the first latch circuit, and a second process of reading the second bit of data and storing it in the second latch circuit.

2. The semiconductor memory device according to claim 1, wherein, based on a determination result of whether the first bit data or the second bit data has an error, the control circuit performs a third process of reading the first bit data from the second memory cell array when it determines that the first bit data has an error.

3. The semiconductor memory device according to claim 2, wherein the determination of whether the first bit data and the second bit data are each erroneous is performed by the control circuit.

4. The semiconductor memory device according to claim 2, wherein the determination of whether the first bit data and the second bit data are each erroneous is performed by a circuit different from the control circuit.

5. The semiconductor memory device according to claim 4, wherein the different circuits include a first determination circuit for determining whether the first bit data has an error, and a second determination circuit for determining whether the second bit data has an error.

6. The semiconductor memory device according to claim 1, wherein when determining whether the first bit data or the second bit data is erroneous, the control circuit performs a third process of reading the second bit data from the first memory cell array and reading the first bit data from the second memory cell array.

7. The semiconductor memory device according to claim 6, wherein the determination of whether the first bit data and the second bit data are each erroneous is performed by the control circuit.

8. The semiconductor memory device according to claim 6, wherein the determination of whether the first bit data and the second bit data are each erroneous is performed by a circuit different from the control circuit.

9. The semiconductor memory device of claim 8, wherein the different circuits include a first determination circuit for determining whether the first bit data has an error, and a second determination circuit for determining whether the second bit data has an error.

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