Circuits and methods for capturing and transmitting data errors.

Abstract

Circuitry and methods for capturing and transmitting data errors are disclosed. In one embodiment, a method includes: receiving a first memory error packet associated with a first memory using a first buffer of a first error compressor unit (ECU); receiving a second memory error packet associated with a second memory using the first buffer; sending a first read request for reading the first memory error packet; receiving the first read request using an arbitrator of an error aggregator unit (EAU) of a central memory error management unit (MEMU); in response to receiving the first read request, reading the first memory error packet from the first buffer, sending the first memory error packet to a controller of the central MEMU, and sending a first acknowledgment to the first ECU; receiving the first acknowledgment using the first ECU; and in response to receiving the first acknowledgment, sending a second read request for reading the second memory error packet.

Description

Technical Field

[0001] This disclosure generally relates to an electronic system and method, and in certain embodiments to a circuit and method for capturing and transmitting data errors. Background Technology

[0002] The complexity of integrated circuits (ICs) has steadily increased in recent years. Some ICs include multiple circuits. For example, a system-on-a-chip (SoC) can integrate all components of a computer or other electronic system onto a single chip to perform many functions, such as receiving and sending data, making and receiving phone calls, playing virtual games, etc. For example, a microcontroller IC, in addition to a central processing unit (CPU) and associated registers, may include multiple memories for, for example, software memory, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other circuits such as SPI and I / O. 2 C's communication interface module, internal oscillator, and other digital and analog circuits. Other examples of complex integrated circuits include field-programmable gate arrays (FPGAs), power management ICs (PMICs), processors (such as ARM or x86 processors), digital signal processors (DSPs), etc.

[0003] Some applications are considered safety-critical and require self-testing and / or real-time monitoring of their circuitry during mission mode (normal operation) or during start-up / shutdown of field applications. An example is automotive-grade applications controlling safety mechanisms such as braking, stopping, and lane changing.

[0004] Complex ICs may include built-in self-test (BIST) circuitry. BIST circuitry (also known as built-in test circuitry or BIT circuitry) is test circuitry included within a complex IC that allows the complex IC to perform its own tests. BIST circuitry can be used, for example, to assist automated test equipment (ATE) by testing logic or memory functions, or to improve coverage or other test performance during IC manufacturing (production).

[0005] BIST circuits can also be used in the field (e.g., during start / stop). For example, automotive-grade microcontrollers can use BIST to test different components of the microcontroller each time the car is started and report any detected faults to the car's central processing unit.

[0006] During normal operation, circuits, such as complex ICs, can use error correction codes (ECC) to detect and correct errors. Summary of the Invention

[0007] According to one embodiment, a method for capturing memory errors includes: receiving a first memory error packet associated with a first memory using a first buffer of a first error compressor unit (ECU) circuit; receiving a second memory error packet associated with a second memory using the first buffer; sending a first read request for reading the first memory error packet; receiving the first read request using an arbitrator circuit of an error aggregator unit (EAU) circuit of a central memory error management unit (MEMU) circuit; in response to receiving the first read request, reading the first memory error packet from the first buffer, sending the first memory error packet to a controller of the central MEMU circuit, and sending a first acknowledgment to the first ECU circuit; receiving the first acknowledgment using the first ECU circuit; and in response to receiving the first acknowledgment, sending a second read request for reading the second memory error packet.

[0008] According to one embodiment, a circuit includes: a central memory error management unit (MEMU) circuit including an error aggregator unit (EAU) circuit; an error compressor unit (ECU) circuit coupled to the EAU circuit, the ECU circuit having a buffer; and a first memory and a second memory coupled to the ECU circuit, wherein the ECU circuit is configured to: receive a first memory error packet from the first memory using the buffer, receive a second memory error packet from the second memory using the buffer, make the first memory error packet available in a parallel bus and send a first read request to the EAU circuit for reading the first memory error packet, after sending the first read request, receive a first acknowledgment, and in response to receiving the first acknowledgment, make the second memory error packet available in the parallel bus and send a second read request to the EAU for reading the second memory error packet.

[0009] According to one embodiment, an integrated circuit includes: a central memory error management unit (MEMU) circuit, including an error aggregator unit (EAU) circuit; a plurality of error compressor unit (ECU) circuits, each of the plurality of ECU circuits including a respective first-in-first-out (FIFO) buffer coupled to a respective parallel bus, the respective parallel bus being coupled to the EAU; and a plurality of memories divided into respective subgroups, each subgroup being coupled to a respective ECU circuit in the plurality of ECU circuits, wherein each of the plurality of ECU circuits is configured to: receive memory error packets from one or more memories in the respective subgroups; store the memory error packets in the respective FIFO buffers; when the respective FIFO buffers are not empty, make the next memory error packet stored in the FIFO buffers available in the respective parallel buses and send a read request to the EAU; after sending the read request, receive an acknowledgment; and in response to receiving the acknowledgment, make the next memory error packet stored in the FIFO buffers available in the respective parallel buses and send a new read request to the EAU. Attached Figure Description

[0010] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0011] Figure 1 An exemplary plan view of a SoC according to an embodiment of the present invention is shown;

[0012] Figure 2 An embodiment according to the present invention is shown. Figure 1 A schematic diagram of the SoC;

[0013] Figure 3A and Figure 3B Error grouping according to an embodiment of the present invention is shown;

[0014] Figure 4 An embodiment according to the present invention is shown. Figure 2 Possible implementations of the error compressor unit (ECU) and error aggregator unit (EAU);

[0015] Figure 5 A flowchart of an embodiment method for capturing memory errors according to an embodiment of the present invention is shown;

[0016] Figure 6A An embodiment according to the present invention is shown. Figure 4 Possible implementation of the ECU's handshake circuit;

[0017] Figure 6B An embodiment of the invention is shown with Figure 6A Exemplary waveforms associated with the handshake circuit;

[0018] Figure 7A An embodiment according to the present invention is shown. Figure 4 Possible implementations of the handshake circuit for the EAU;

[0019] Figure 7B An embodiment of the invention is shown with Figure 7A Exemplary waveforms associated with the handshake circuit of the EAU;

[0020] Figure 8A An embodiment according to the present invention is shown. Figure 4 Possible implementations of a multi-write shared FIFO;

[0021] Figure 8B An embodiment of the invention is shown with Figure 8A Exemplary waveforms associated with multiple write FIFOs;

[0022] Figure 9 and Figure 10 A schematic diagram of a memory according to an embodiment of the present invention is shown;

[0023] Figure 11 An embodiment of the invention is shown. Figure 2 Automotive SoCs and central processing units; and

[0024] Figure 12 A schematic diagram of a SoC according to an embodiment of the present invention is shown.

[0025] Unless otherwise stated, the numbers and symbols corresponding to different figures generally refer to the corresponding parts. These figures are drawn to clearly illustrate relevant aspects of the preferred embodiments and are not necessarily drawn to scale. Detailed Implementation

[0026] The making and use of the disclosed embodiments will now be discussed in detail. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of particular ways of making and using the invention and do not limit the scope of the invention.

[0027] The following description illustrates various specific details to provide a thorough understanding of several exemplary embodiments according to the description. Embodiments may be obtained without one or more specific details, or by utilizing other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been shown or described in detail so as not to obscure different aspects of the embodiments. References to "embodiment" in this specification indicate that a specific configuration, structure, or feature described with respect to at least one embodiment is included. Therefore, phrases such as "in one embodiment" that may appear at different points in this specification do not necessarily refer exactly to the same embodiment. Furthermore, in one or more embodiments, particular constructions, structures, or features may be combined in any suitable manner.

[0028] Embodiments of the invention, circuitry, and methods for capturing and transmitting memory errors in safety-critical applications, such as automobiles, will be described in a specific context. Embodiments of the invention can be used in other types of safety-critical applications, such as industrial applications, as well as non-safety-critical applications, such as smartphones or desks. Some embodiments can also be used to capture errors other than memory errors.

[0029] In embodiments of the invention, an IC having multiple memories uses a central memory error management unit (MEMU) circuitry to store and process error data packets received from the multiple memories. Data flow control is performed via an asynchronous handshake between a multi-write shared first-in-first-out (FIFO) buffer and the central MEMU circuitry to facilitate the transfer of error data packets to the MEMU circuitry. In some embodiments, the asynchronous handshake advantageously allows error data packet flows across different clock domains.

[0030] In some embodiments, a synchronous handshake between a FIFO buffer and an error packet generator (e.g., one or more in-memory BISTs or integrity checkers) is used to prevent the error source from performing further tests until the previous error packet has been confirmed to have been processed (e.g., stored in the MEMU).

[0031] In some safety-critical applications, the memory of an IC may need to be field-tested at different times. For example, microcontrollers for automotive applications compliant with ISO 26262, such as those compliant with Automotive Safety Integrity Level (ASIL) D, need to be tested for faults in the integrated memory every time the vehicle is started and while the vehicle is in motion (e.g., while driving). The memory tested at startup and during operation can be volatile and / or non-volatile.

[0032] At startup, the executable memory BIST (MBIST) detects correctable and uncorrectable error locations in each memory. Since it is generally desirable to minimize the time required to start the car, MBIST typically runs at high speed (maximum speed) and covers multiple (or all) memories in parallel.

[0033] During runtime, error correction codes (ECC) stored along with the data are decoded to detect and report memory-related faults.

[0034] In some embodiments, MBIST also runs during runtime. For example, in some embodiments, MBIST may run in response to the detection of one or more ECC errors. For example, upon detecting an ECC error associated with a memory, processing associated with that memory may be stopped, and MBIST may be executed on that memory.

[0035] All memory errors and their characteristics, such as error type (correctable / uncorrectable), error bit location, error address location, and memory identifier, are sent to the central memory error management unit (MEMU) circuitry in the form of error data packets (also known as error packets) for logging (storage) and further processing. Errors can also be logged and made available, for example, via the onboard diagnostic (OBD) 2 port.

[0036] Error packets can be sent from memories operating in different clock domains, such as from 50MHz to 500MHz, and can be tens of bits in size. For example, in a 32-bit system, the error packet width can be, for example, 42 to 52 bits.

[0037] In some embodiments, more than one type of error grouping may exist. For example, some embodiments may have two types of error grouping: one for startup memory testing (e.g., MBIST) and one for runtime memory testing (e.g., ECC). Some embodiments may also have different types of error grouping for non-volatile memory and volatile memory. In some embodiments, all error grouping may be of the same type. For example, embodiments may have four types of error grouping associated with non-volatile memory (e.g., single / double / triple error correction, and multiple error detection).

[0038] Upon receiving an error during startup, the MEMU circuitry can report the error to the user (e.g., via one or more lights and / or noise in the dashboard) and / or prevent the car from starting. When an error is received during operation, the MEMU circuitry can report the error to the user and take other actions.

[0039] Complex SoCs can include hundreds of volatile memories such as random access memory (RAM) (e.g., associated system and peripheral modules) and multiple non-volatile memory types. These memories are placed in different locations within the SoC. For example, Figure 1 An exemplary plan view of a SoC 100 according to an embodiment of the present invention is shown. The SoC 100 is implemented as an integrated circuit and includes a MEMU circuitry 102 and a plurality of memories 104 disposed on a (e.g., monolithic) semiconductor substrate. The plurality of memories 104 may have different sizes and types (e.g., volatile or non-volatile). For clarity, Figure 1 The other circuitry of the SoC 100 is not shown.

[0040] although Figure 1 Nine memory units 104 are shown, but some embodiments have hundreds of memory units 104. For example, in some embodiments, the SoC 100 may include, for example, more than 300 volatile memories of the RAM type and, for example, more than 10 non-volatile memories of the EEPROM type. Different numbers of memories and other memory types, such as flash, OTP, ROM, PCM, etc., may also be used.

[0041] In some embodiments, SoC 100 may be, for example, a microcontroller, processor, DSP, FPGA, or PMIC.

[0042] Routing dedicated wiring from each memory 104 to the MEMU circuitry 102 can be challenging. For example, placing interconnects across the various metal layers of the SoC 100 to route signals from the memory 104 to the MEMU circuitry 102 itself can be challenging. For instance, routing 84 to 104 error bits (e.g., two types of error packets, each between 42 and 52 bits in size) from each of, for example, more than 300 memories 104 can be challenging. Furthermore, performing timing closure (the process of modifying the logic design to meet timing requirements) can also be challenging.

[0043] In embodiments of the invention, the memory management unit (MEMU) circuitry includes an error aggregator unit (EAU) for processing error packets from multiple memories of the SoC. An error compressor unit (ECU) captures concurrent error packets from a subset of the SoC's multiple memories and sequentially transmits the error packets to the EAU using a multi-write first-in-first-out (FIFO) buffer. The EAU arbitrates and captures error data packets from the multiple ECUs for further processing using a handshake mechanism.

[0044] Figure 2A schematic diagram of a SoC 100 according to an embodiment of the present invention is shown. The SoC 100 includes a MEMU 102 and an ECU 206. The MEMU 102 includes a controller 202 and an EAU 204.

[0045] like Figure 2 As shown, multiple memories 104 are grouped into subgroups 208. The number of memories 104 in each subgroup 208 may be the same or different. In some embodiments, each ECU 206 is customized for the number of input sources it supports.

[0046] ECU 206 is configured to, for example, simultaneously capture erroneous packets and sequentially transmit them to EAU 204 using a handshake mechanism, which can be synchronous or asynchronous. In some embodiments, the ECU also reports to a central fault collection unit when erroneous packets are lost.

[0047] The EAU is configured to arbitrate and capture error data packets from multiple ECUs for further processing.

[0048] During startup, a startup memory test is performed on each memory 104. For example, MBIST can be performed on each volatile type memory 104, and an integrity test can be performed on each non-volatile type memory 104. Errors detected during the startup memory test are recorded using bus D. error_packet Error packets are sent from each fault memory 104 to the corresponding ECU 206. Each ECU 206 receives error packets from multiple corresponding memories 104 and stores them in a multi-write shared FIFO. The error packets are then sent from each ECU 206 to the EAU 204 using a handshake mechanism and arbitration processing (e.g., polling scheduling). The EAU 204 then sends the error packets to the controller 202. The controller 202 then sends the error packets to external circuitry, such as the vehicle's central processing unit (e.g., a central fault handling unit or safety fault collection and controller).

[0049] During operation, error correction codes (ECC codes) are used to detect faults in each memory 104. This is achieved using bus D. error_packet The fault detected in each memory 104 is sent as an error packet to the corresponding ECU 206. Each ECU 206 receives the error packets from multiple corresponding memories 104 and stores them in a multi-write shared FIFO. The error packets are then sent from each ECU 206 to the EAU 204 using a handshake mechanism and arbitration processing. The EAU 204 then sends the error packets to the controller 202, which in turn sends them to the external circuitry.

[0050] In some embodiments, bus D error_packet They are shared for transmitting error packets during startup and operation. In other embodiments, different buses are used for transmitting error packets during startup and operation.

[0051] In some applications, it may be desirable to minimize startup time by, for example, performing startup memory tests at (as fast as possible) speed and by testing multiple (or all) memories 104 in parallel. Performing so many tests in parallel and so quickly can result in multiple error packets being sent to each ECU 206 simultaneously. In some cases, the transmission rate of error packets from each subgroup 206 exceeds the processing capacity of ECU 206 and EAU 204. For example, in some embodiments, MEMU 102 can be used at clock CLK. MEMU One error packet is read / processed per clock cycle.

[0052] In some embodiments, ECU 206 may pause the execution of boot memory tests on the corresponding subgroup 208 when, for example, the corresponding shared FIFO buffer is full or nearly full. In some embodiments, ECU 206 uses signal S flow_control Signals are sent to the corresponding subgroup 208 to pause or resume the execution of the start memory test. In some embodiments, each ECU 206 generates an independent signal S. flow_control In other embodiments, a single signal S flow_control This is used to pause or resume the execution of the entire IC. Other implementations are also possible.

[0053] In some embodiments, stopping the execution of the startup test when the shared FIFO buffer is full or nearly full advantageously allows for the prevention of erroneous packet loss, while still executing the startup test as quickly as possible.

[0054] In some embodiments, each bus D error_packet It is implemented as an independent serial bus from each memory 104. In other embodiments, each bus D error_packet It is implemented as a parallel bus independent of each memory 104. Other implementations are also possible.

[0055] In some embodiments, controller 202 is configured to process error packets and send them to external circuitry or a security controller, maintain an internal record of memory faults to prevent the same fault from being stored multiple times, and / or count errors from a specific memory range / module. Controller 202 can be implemented, for example, using custom logic, which may include, for example, a state machine coupled to the memory and / or combinational logic. Some embodiments can be implemented using a general-purpose core such as an ARM core. Other implementations are also possible.

[0056] MBIST and memory integrity tests can be performed in any manner known in the art, for example, by using a state machine to run the memory in a predetermined mode.

[0057] ECC testing can be performed in any manner known in the art. For example, in some embodiments, ECC is capable of correcting single-bit errors and detecting double-bit errors. In some embodiments, ECC is capable of correcting double-bit errors and detecting triple-bit errors. Other implementations are also possible. In some embodiments, ECC checks are also performed automatically by any other functional unit during the functional use of the memory, such as a CPU that reads its cache memory during code execution.

[0058] Each memory 104 of the non-volatile memory type includes test circuitry (not shown) for performing memory integrity tests and ECC tests. Each memory 104 of the volatile memory type includes test circuitry (not shown) for performing MBIST tests and ECC tests. Such test circuitry may also be referred to as a security monitor. The security monitor may be implemented in any manner known in the art.

[0059] In some embodiments, error grouping may be based on the characteristics of memory 104. For example, Figure 3A An error packet 300 according to an embodiment of the present invention is shown. The error packet 300 is suitable, for example, for a 32-bit system having 64 bits of data.

[0060] As shown in the figure, error packet 300 has 32 bits for the address location of the detected error, 8 bits for the location of the error at the error address ERR ADDRESS, and 2 bits for the error type (e.g., error type, such as single or double error, and whether the error is correctable). In some embodiments, the error packet may have a size other than 42 bits, for example, a size between 42 bits and 52 bits. Other sizes of error data packets are also possible.

[0061] In some embodiments, error packets may take different forms. For example, in some embodiments, different numbers of bits may be assigned to ERR ADDRESS (e.g., different from 32 bits), ERR LOC (e.g., different from 8 bits), and ERR type (e.g., different from 2 bits). In some embodiments, the error packet may also include an additional ERR SRC field to identify the source memory 104 that caused the error packet to be generated. In some embodiments, the ERR SRC field may assist in debugging as an alternative to processing the error address to identify the source memory.

[0062] Figure 3B Error grouping 320 according to an embodiment of the present invention is shown. For example... Figure 3BAs shown, the ERR SRC field can have m bits, and the ERR ADDRESS field can have n bits, such that m+n is less than or equal to 32. Embodiments implementing error grouping 320 can advantageously reduce the group length when the SoC 100 has a relatively small number of memories 104 and / or the size of the memories 104 is small.

[0063] In some embodiments, some memories 104 may be larger than others (e.g., such as...). Figure 1 (as shown), or larger words (e.g., 64, 32, 16, or 8-bit words) can be used compared to other memories. For example, in some embodiments, some memories 104 may have 500 kB or more, such as 1 MB, while other memories may have only a few kB, such as 10 kB or less. In some embodiments, all error packets sent by each memory 104 have the same form (e.g., an error packet form that meets the requirements of the largest memory 104 present in the SoC 100).

[0064] In some embodiments, different memories 104 may send error packets of different forms (e.g., different sizes). For example, a small memory 104 may send smaller error packets (e.g., 42 bits), while a large memory 104 may send larger error packets (e.g., 52 bits).

[0065] In some embodiments, some memories 104 may operate in different clock domains. For example, in some embodiments, some memories 104 may operate in a first clock domain (e.g., at a frequency of 200 MHz), while other memories 104 may operate in a second clock domain (e.g., at a frequency of 400 MHz). In some embodiments, all memories 104 of a particular subgroup 208 operate in the same clock domain.

[0066] In some embodiments, all memories in a particular subgroup 208 are of the same type. For example, in some embodiments, all memories in the first subgroup 208 are of type EEPROM; and all memories in the second subgroup 208 are of type RAM.

[0067] Figure 4 Possible implementations of ECU 206 and EAU 204 according to embodiments of the present invention are shown. For example... Figure 4 As shown, SoC 100 includes n ECUs 206, where n is greater than 1. Each ECU 206 includes a multi-write shared FIFO 402 and a handshake circuit 404. EAU 204 includes multiple handshake circuits 422 coupled to the corresponding ECU 206, arbitrator 424, and selector circuit 426.

[0068] Figure 5A flowchart of an embodiment method 500 for capturing memory errors according to an embodiment of the present invention is shown. Method 500 can be executed at startup or during operation.

[0069] Figure 4 and Figure 5 They can be understood together. Although regarding ECU 206 i Explained Figure 4 and Figure 5 However, it should be understood that ECU 206 i It can be any ECU of SoC 100.

[0070] During step 502, when subgroup 208 i When the memory 104 detects a fault / error, such memory 104 writes the corresponding error packet (e.g., in the form of error packet 300 or 320) into the multi-write shared FIFO 402. i In some embodiments, subgroup 208 i Multiple memory modules 104 simultaneously write each error group to the multi-write shared C.

[0071] In some embodiments, FIFO 402 may be a dedicated (non-shared FIFO). For example, in some embodiments, dedicated FIFO 402 may be used when an error source (e.g., a particular memory 104) is physically or clockwise different from other error sources.

[0072] During step 512, the shared FIFO 402 is executed. i Determining whether it is empty. When sharing FIFO 402 i When not empty, share FIFO 402 i During step 514, the next error packet is made on bus S. DATA_i The bus is available (e.g., in a first-in-first-out manner), and during step 516, the EAU 204 is requested to read the bus S. DATA_i .

[0073] In some embodiments, bus S DATA_i It is a parallel bus (e.g., having 42 parallel lines for error grouping 300). In other embodiments, bus S DATA_i It is a serial bus.

[0074] In some embodiments, when sharing FIFO 402 i If not empty, signal S is released during step 512. empty Assertions (e.g., high-to-low transitions). In other embodiments, a shared FIFO 402 is used. i It can be signaled in other ways that it is not empty, for example, by asserting S.non-empty Signal (e.g., from low to high).

[0075] In some embodiments, ECU 206 i By using handshake circuit 404 i Assertion signal S REQ_i (For example, by using signal S) REQ_i (From low to high) to request a read of bus S during step 516 DATA_i .

[0076] During step 532, the scheduling bus S DATA_i The EAU 204 receives the signal S using a corresponding handshake circuit 422 in some embodiments. REQ_i Upon receiving signal S REQ_i When (for example, when S) REQ_i When asserted, the handshake circuit 422 sends a signal to the arbitrator 424 to indicate that on bus S... DATA_i Error packets are available (e.g., by asserting the signal REQi, for example, by transitioning the signal REQi from low to high). Arbitrator 424 schedules the bus S based on read requests REQ received from other handshake circuits 422, for example, in a polling-based or priority-based manner (e.g., if REQi is set to the highest priority, all its errors are read before moving to REQ(i+1)). DATA_i Reading.

[0077] When it's time to read bus S DATA_i When an error packet is available, EAU 204 reads bus S during step 534. DATA_i Error grouping at the location. For example, in some embodiments, the arbitrator uses selector circuitry 426 to select the bus S for reading. DATA_i and using bus S ERR The selected error packets are sent to controller 202. In some embodiments, bus S ERR It is a parallel bus. In other embodiments, bus S ERR It is a serial bus. In some embodiments, the arbitrator 424 can be connected to the clock CLK. MEMU Each clock cycle processes and acknowledges requests from ECU 206.

[0078] Once the bus S is read DATA_i If an incorrect group is found, step 512 is executed again, repeating the sequence. For example, in some embodiments, once the bus S is read... DATA_i In case of an erroneous packet, arbitrator 424 asserts the signal ACKi (e.g., by transitioning the signal ACKi from low to high). When the assertion signal ACKi... i At that time, handshake circuit 422i Assertion signal S ACK_i When signal S ACK_i When asserted, handshake circuit 404 i Assertion signal S ack To indicate bus S DATA_i The erroneous group at that location has been read.

[0079] In some embodiments, FIFO 402 is shared after step 534. i When not empty, switch signal S empty To enable handshake circuit 404 i Assertion (e.g., switching, or causing a rising edge, or causing a falling edge) signal S REQ_i In some embodiments, FIFO 402 is shared each time. i Make new error groups on bus S DATA_i The signal S can be used without switching. empty At that time, the handshake circuit 404i asserts S REQ_i .

[0080] Some embodiments may also perform steps 542, 544, and 546 for flow control. For example, in some embodiments, when it is determined during step 542 that the shared FIFO is full, an error source (e.g., memory 104 associated with shared FIFO 402) is stopped (e.g., MBIST pause) to prevent the FIFO buffer from overflowing.

[0081] In some embodiments, when the shared FIFO overflows (e.g., when the FIFO buffer discards an erroneous packet because, for example, the FIFO buffer receives an erroneous packet when it is full), an error signal (e.g., S) is asserted. overflow ), to indicate that erroneous groups are lost.

[0082] In some embodiments, step 502 is executed by one or more memories 104 of subgroup 208i, by ECU 206. i Perform steps 512, 514 and 516, and EAU 204 performs steps 532 and 534.

[0083] Multiple write shared FIFO 402 i This can be implemented in any manner known in the art. For example, in some embodiments, the shared FIFO 402i operates synchronously, and the read and write clocks are the same (e.g., CLK). MEM_i In some embodiments, the multi-write shared FIFO 402 i It is implemented as multiple write ports (e.g., one for each memory 104 of subgroup 208i) and a single read port (e.g., bus S). DATA_iIn some embodiments, other types of buffers may be used, such as Last-In-First-Out (LIFO).

[0084] Arbitrator 424 can be implemented, for example, using a state machine, and can implement a round-robin scheduling scheme. Some embodiments can implement other scheduling schemes, such as First-Come, First-Served (FCFS), priority scheduling, or other types of scheduling schemes.

[0085] In some embodiments, the handshake mechanism (e.g., as shown in steps 512, 514, 516, 632, and 534) results in variable execution time, for example, because memory tests may be paused and / or the flow of error packets may be asynchronous and based on a scheduling scheme that may change based on when error packets are issued.

[0086] like Figure 4 As shown, the memory 104 and ECU 206 of subgroup 208i i Operating in the first clock domain (e.g., based on clock CLK) MEM_i And EAU 204 operates in the second clock domain (e.g., based on CLK). MEMU In some embodiments, the clock CLK MEM_i and CLK MEMU Equal. In other embodiments, the clock CLK MEM_i and CLK MEMU They are different.

[0087] In some embodiments, the handshake mechanism (e.g., as shown in steps 512, 514, 516, 632, and 534) advantageously allows erroneous packetization in the clock CLK. MEM_i and CLK MEMU The data does not flow from the first clock domain to the second clock domain simultaneously.

[0088] In some embodiments, the handshake mechanism also advantageously allows for minimizing or eliminating the loss of erroneous packets, since erroneous packets can accumulate in the shared FIFO 402. i In the middle, until MEMU 102 is read to read them.

[0089] The selector circuit 426 can be implemented using a multiplexer (MUX). In some embodiments, the selector circuit 426 is implemented via bus S ERR Error packets are sampled and (e.g., temporarily) stored in a table before being sent. In some embodiments, a shared FIFO 402 is maintained. i On bus S DATA_i Errors in the packet can be addressed until the handshake circuit 422. i Issue confirmation (e.g., by asserting S) ACK_i Advantageously allows for bus SDATA_i When stable, on bus S DATA_i The system samples erroneous groups to avoid metastability issues.

[0090] When subgroup 208 i The memory 104 continues to attempt to write the erroneous packets to the shared FIFO 402. i At that time, share FIFO402 i It may become full. In some embodiments, such a scenario may be more likely to occur, for example during startup (because all memory 104 is tested in parallel, for example). In some embodiments, when the shared FIFO 402 i When packets are lost (e.g., when sharing FIFO 402) i When full, memory 104 attempts to write erroneous packets into shared FIFO 402. i (Time), Shared FIFO 402 i Assertion signal S overflow In some embodiments, when the signal S from any ECU 206 overflow When asserted (e.g., when signal S) overflow When switching from low to high, the test can be restarted (e.g., at a lower speed).

[0091] In some embodiments, each ECU 206 is advantageously placed as close as possible to the memory 104 of the corresponding subgroup 208 to, for example, avoid long interconnects and routing congestion.

[0092] In some embodiments, the use of ECU 206 allows for a tree structure for routing of error groups, which advantageously allows MEMU 102 to be placed in a desired physical location (e.g., in a corner of SoC 100) because the number of interconnects between ECU 206 and MEMU 102 is significantly less than the number of interconnects from all memory 104.

[0093] Advantages of some embodiments include ease of implementation, such as clock trees and timing closures, and improved routing congestion. For example, in some embodiments, the number of MEMU channels can be reduced by more than 80% compared to an architecture that routes erroneous packets directly from each memory to the MEMU.

[0094] Some embodiments can advantageously result in a smaller area, for example, due to a reduction in interconnect routes and, for example, a reduction in the degrees of freedom for MEMU placement without affecting performance. Some embodiments can advantageously result in potentially lower erroneous packet loss, thereby leading to better security and reliability of the product / application.

[0095] Some embodiments can also implement a distributed MEMU unit with multiple local MEMUs responsible for local cluster memory, which can advantageously increase performance and response time.

[0096] Figure 6A A handshake circuit 404 according to an embodiment of the present invention is shown. i One possible implementation is possible. Other implementations are also possible.

[0097] Figure 6B An embodiment of the invention is shown with Figure 6A 404 handshake circuit i Associated exemplary waveforms. This can be based on... Figure 6B To understand Figure 6A .

[0098] like Figure 6A As shown, handshake circuit 404 i It includes flip-flops 604 and 616, AND gate 612, inverters 610 and 614, XOR gate 606, XOR NOT gate 608, and synchronous logic 602.

[0099] During normal operation, when sharing FIFO 402 i When empty (for example, in) Figure 6B At time t0, trigger 616 is disabled.

[0100] When sharing FIFO 402 i When not empty (e.g., when signal S) empty When the signal S is low, whenever the signal S is low ACK_i When asserted (e.g., when signal S) ACK_i When pulsed), signal S REQ_i Switching (as asserted). For example, in Figure 6B in, signal S REQ_i Assertions are made at times t1 and t3.

[0101] Similarly, Figure 6A As shown, when the signal S ACK_i When asserted (e.g., switching), signal S ack It is also asserted (e.g., impulse). For example... Figure 6B As shown, each assertion signal S ack At that time, bus S DATA_i A new erroneous grouping will then occur (e.g., at time t2).

[0102] When from shared FIFO 402 i When reading the last erroneous packet, the assertion signal S empty (For example, at time t4).

[0103] Figure 7AA handshake circuit 422 according to an embodiment of the present invention is shown. i This is one possible implementation. Other implementations are also possible. For example, some embodiments may use a 4-level handshake scheme instead of a 2-level handshake scheme (as described by handshake circuit 422). i (Achieved)

[0104] Figure 7B An embodiment of the invention is shown with Figure 7A Handshake circuit 422 i Associated exemplary waveforms. This can be based on... Figure 7B To understand Figure 7A .

[0105] like Figure 7A As shown, handshake circuit 422 i It includes a flip-flop 708, an inverter 706, an XOR gate 704, and a synchronous logic 702.

[0106] During normal operation, when signal S REQ_i When asserted (e.g., switched), signal REQi is also asserted (e.g., pulsed), for example, at times t6 and t8, thereby signaling to arbitrator 424 that data is on bus S. DATA_i It is available online.

[0107] Once on bus S DATA_i Read error packets at the location (or with the bus S) DATA_i (While reading the erroneous packet), arbitrator 424 causes signal S to be read. ACK_i Assertion is made (e.g., by switching), for example, at times t7 and t9. In some embodiments, the arbitrator 424 may initiate an assertion signal S upon receiving REQi via an assertion (e.g., pulse) signal ACKi (e.g., depending on the scheduling algorithm and load of the arbitrator 424). ACK_i The process.

[0108] from Figure 6A , Figure 6B , Figure 7A and Figure 7B It can be seen from this that Figure 6A and Figure 7A The implementation shown is suitable for operation together.

[0109] Figure 8A A multi-write shared FIFO 402 according to an embodiment of the present invention is shown. i The possibility of its realization. For example... Figure 8A As shown, multi-write shared FIFO 402 i It can be implemented as a 4-deep FIFO. FIFO buffers of different sizes (e.g., sizes of 2, 3, 5, 8, 10 or higher) can also be used.

[0110] Figure 8B An embodiment of the invention is shown with Figure 8A Multiple FIFO 402 i Associated exemplary waveforms.

[0111] At time t 10 , Figure 8A FIFO 402 i Empty, such as signal S empty As shown.

[0112] At time t 11 Memory MEM1 and MEM2 simultaneously begin writing FIFO_ENTRY[0] and FIFO_ENTRY[1] respectively. The written data is recorded at time t. 12 It is latched into the register.

[0113] At time t 12 MEM1 started writing to FIFO 402 again. i (Now at position FIFO_ENTRY[2]).

[0114] At time t 14 Both MEM1 and MEM2 have started writing to FIFO 402 again. i Because a FIFO can only store four erroneous packets, and at time t... 15 At this point, the FIFO changed from having 3 erroneous packets to having 4 erroneous packets (full) and lost 1 erroneous packet (the second packet from MEM2 was not stored in FIFO 402). i (in the middle), therefore at time t 15 All assertion signals S full and S overflow .

[0115] In some embodiments, such as from FIFO 402 i signal S overflow It can be used to pause the generation of erroneous packets from the error source to avoid reaching assertion S. overflow Conditions. In some embodiments, for example, when asserting S full At that time, it can be asserted that S overflow .

[0116] Figure 9 and Figure 10 A schematic diagram of memories 900 and 1000 according to an embodiment of the present invention is shown. Memory 104 can be implemented as memory 900 or 1000.

[0117] like Figure 9As shown, memory 900 is a volatile memory type and includes memory plane 902 and security monitor 904. The security monitor is configured to test memory plane 902 using MBIST circuitry 906 during startup and ECC circuitry 908 during operation.

[0118] like Figure 10 As shown, memory 1000 is a non-volatile memory (NVM) type and includes memory plane 1002 and security monitor 1004. The security monitor is configured to test memory plane 902 using integrity test circuitry 1006 during startup and ECC circuitry 1008 during operation.

[0119] MBIST circuit 906 is configured to perform MBIST tests and can be implemented in any manner known in the art. Integrity test circuit 1006 is configured to perform memory integrity tests and can be implemented in any manner known in the art. ECC circuits 908 and 1008 are configured to perform ECC tests and can be implemented in any manner known in the art.

[0120] Figure 11 An automobile 1100 having a SoC 100 and a central processing unit 1102 according to an embodiment of the present invention is shown.

[0121] When the vehicle 1100 is started (e.g., when the ignition key is inserted and turned), the memory 104 is tested (e.g., with MBIST and integrity tests). Any faults detected in any memory 104 of the SoC 100 are sent from the corresponding ECU 206 to the MEMU 102 in the form of error packets. The MEMU 102 then sequentially sends information about the detected faults to the central processing unit 1102. The central processing unit 1102 can then take action based on the received information, such as preventing the vehicle 1100 from starting, turning on lights in the dashboard, or triggering an audible sound.

[0122] During operation (e.g., when the vehicle 1100 is driven), ECC tests are performed on memory 104 (e.g., when data is read from and written to memory 104). When a fault is detected (e.g., an uncorrectable error such as one or more errors in memory 104), the fault is sent from the corresponding ECU 206 to MEMU 102 in the form of error packets. MEMU 102 then sequentially sends information about the detected fault to central processing unit 1102. Central processing unit 1102 can then take action based on the received information, such as turning on lights in the dashboard or triggering an audible signal.

[0123] Figure 12A schematic diagram of a SoC 1200 according to an embodiment of the present invention is shown. Figure 12 As shown, SoC 1200 includes multiple local clusters 1202. Each local cluster 1202 includes a local MEMU 102, multiple ECUs 206, and multiple memories 104 arranged in multiple subgroups 208. SoC 100 can be implemented as SoC 1200.

[0124] In some embodiments, each local cluster 1202 has a MEMU 102 and multiple ECUs 206 and subgroups 208 to communicate with respect to... Figure 2 The operation is similar to that described. Some embodiments advantageously achieve local MEMU control and response by having multiple local MEMUs 102, and further optimize wiring and response time (e.g., by optimizing the physical locations of memory 104, ECU 206, and MEMU 102 in the substrate to minimize wiring, for example). In some embodiments, component separation is achieved by implementing separate components in a particular cluster 1202.

[0125] This document outlines exemplary embodiments of the invention. Other embodiments can also be understood from the full description and claims provided herein.

[0126] Example 1. A method for capturing memory errors, the method comprising: receiving a first memory error packet associated with a first memory using a first buffer of a first error compressor unit (ECU) circuit; receiving a second memory error packet associated with a second memory using the first buffer; sending a first read request for reading the first memory error packet; receiving the first read request using an arbitrator circuit of an error aggregator unit (EAU) circuit of a central memory error management unit (MEMU) circuit; in response to receiving the first read request, reading the first memory error packet from the first buffer, sending the first memory error packet to a controller of the central MEMU circuit, and sending a first acknowledgment to the first ECU circuit; receiving the first acknowledgment using the first ECU circuit; and in response to receiving the first acknowledgment, sending a second read request for reading the second memory error packet.

[0127] Example 2. The method according to Example 1 further includes: receiving a third memory error packet associated with a third memory using a second buffer of a second ECU circuit; sending a third read request for reading the third memory error packet; receiving a second read request using an arbitrator circuit; receiving a third read request using an arbitrator circuit; and sequentially reading the second memory error packet and the third memory error packet based on a sequence determined by the arbitrator circuit.

[0128] Example 3. The method of one of Examples 1 and 2, wherein the determined sequence is based on a round-robin scheduling scheme.

[0129] Example 4. The method of one of Examples 1 and 2, wherein the determined sequence is based on a priority-based arbitration scheme.

[0130] Example 5. The method of one of Examples 1 to 4, wherein the first buffer is a multi-write buffer.

[0131] Example 6. According to one of Examples 1 to 5, the method further includes simultaneously writing the first memory error packet and the second memory error packet to the first buffer.

[0132] Example 7. The method of one of Examples 1 to 6, wherein the first buffer is a first-in-first-out (FIFO) buffer.

[0133] Example 8. The method according to one of Examples 1 to 7 further includes: performing a memory built-in self-test (MBIST) on the first memory; and generating a first memory error group based on the result of the MBIST.

[0134] Example 9. The method according to one of Examples 1 to 8 further includes: starting the vehicle; and performing MBIST on the first memory during vehicle startup.

[0135] Example 10. The method according to one of Examples 1 to 9 further includes: performing an error correction code (ECC) test on the first memory; and generating a first memory error group based on the result of the ECC test.

[0136] Example 11. The method according to one of Examples 1 to 10 further includes: operating the vehicle; and performing an ECC test on the first memory while operating the vehicle.

[0137] Example 12. According to one of Examples 1 to 11, wherein reading a first memory error packet from a first buffer includes using a parallel bus.

[0138] Example 13. According to one of Examples 1 to 11, wherein reading a first memory error packet from a first buffer includes using a serial bus.

[0139] Example 14. A method according to one of Examples 1 to 12, wherein a parallel bus is coupled between a first buffer and a selector circuit, the method further comprising a controller controlled by an arbitrator circuit to sequentially send erroneous packets to a central MEMU circuit.

[0140] Example 15. According to one of Examples 1 to 14, sending the first read request includes switching the first request signal and sending the first confirmation switch first confirmation signal.

[0141] Example 16. The method according to one of Examples 1 to 15 further includes: operating a first ECU circuit with a first clock; and operating an arbitrator circuit with a second clock, wherein the first clock and the second clock have different frequencies.

[0142] Example 17. The method according to any one of Examples 1 to 15 further includes: operating a first ECU circuit with a first clock; and operating an arbitrator circuit with a second clock, wherein the first clock and the second clock have the same frequency.

[0143] Example 18. According to one of Examples 1 to 17, wherein the first memory error group has between 42 and 52 bits.

[0144] Example 19. A circuit comprising: a central memory error management unit (MEMU) circuit including an error aggregator unit (EAU) circuit; an error compressor unit (ECU) circuit coupled to the EAU circuit, the ECU circuit having a buffer; and a first memory and a second memory coupled to the ECU circuit, wherein the ECU circuit is configured to: receive a first memory error packet from the first memory using the buffer; receive a second memory error packet from the second memory using the buffer; make the first memory error packet available in a parallel bus and send a first read request to the EAU circuit for reading the first memory error packet; after sending the first read request, receive a first acknowledgment; and in response to receiving the first acknowledgment, make the second memory error packet available in the parallel bus and send a second read request to the EAU for reading the second memory error packet.

[0145] Example 20. The circuit according to Example 19, wherein the ECU circuit includes a first terminal and a second terminal and a first handshake circuit coupled between a buffer and the first and second terminals, wherein the ECU circuit is configured to send a first read request via the first terminal and receive a first acknowledgment via the second terminal.

[0146] Example 21. A circuit according to one of Examples 19 or 20, wherein the first handshake circuit comprises: a logic gate having a first input and an output, the first input being configured to receive a first signal indicating whether the buffer is empty from a buffer, the output being coupled to a first terminal; and a flip-flop having an input coupled to a second terminal and an output coupled to the buffer.

[0147] Example 22. A circuit according to one of Examples 19 to 21, wherein the EAU includes an arbitrator circuit and a second handshake circuit coupled between a first handshake circuit and the arbitrator circuit, the second handshake circuit including a flip-flop having an output coupled to a second terminal, and a logic gate having a first input having an output coupled to the flip-flop of the second handshake circuit, a second input coupled to the first terminal, and an output coupled to the arbitrator circuit.

[0148] Example 23. An integrated circuit comprising: a central memory error management unit (MEMU) circuit including an error aggregator unit (EAU) circuit; a plurality of error compressor unit (ECU) circuits, each of the plurality of ECU circuits including a respective first-in-first-out (FIFO) buffer coupled to a respective parallel bus, the respective parallel bus being coupled to the EAU; and a plurality of memories divided into respective subgroups, each subgroup being coupled to a respective ECU circuit in the plurality of ECU circuits, wherein each of the plurality of ECU circuits is configured to: receive a memory error packet from one or more memories in the respective subgroup; store the memory error packet in a respective FIFO buffer; when the respective FIFO buffer is not empty, make the next memory error packet stored in the FIFO buffer available in a respective parallel bus and send a read request to the EAU; after sending the read request, receive an acknowledgment; and in response to receiving the acknowledgment, make the next memory error packet stored in the FIFO buffer available in a respective parallel bus and send a new read request to the EAU.

[0149] Example 24. An integrated circuit according to Example 23, wherein the MEMU circuit includes a controller, and the EAU circuit includes an arbitrator circuit configured to: receive read requests from multiple ECU circuits; sequentially read memory error packets from a parallel bus coupled to a FIFO buffer of the multiple ECU circuits; and sequentially transmit the memory error packets to the controller of the MEMU circuit.

[0150] Example 25. The integrated circuit according to one of Examples 23 or 24 further includes: an additional MEMU circuit including additional EAU circuitry; a plurality of additional ECU circuits, each of the plurality of additional ECU circuits including a respective first-in-first-out (FIFO) buffer coupled to a respective parallel bus coupled to the additional EAU circuitry; and a plurality of additional memories divided into respective additional subgroups, each additional subgroup coupled to the respective additional ECU circuitry, wherein each of the plurality of additional ECU circuits is configured to: receive data from the respective additional... One or more additional memories in the subgroup receive memory error packets, store the memory error packets in their respective FIFO buffers, and when each FIFO buffer is not empty, make the next memory error packet stored in the FIFO buffer available on each parallel bus and send a read request to another EAU circuit. After sending the read request to the other EAU circuit, receive an acknowledgment from the other EAU circuit, and in response to receiving the acknowledgment from the other EAU circuit, make the next memory error packet stored in the FIFO buffer available on each parallel bus and send a new read request to the other EAU circuit.

[0151] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of the illustrative embodiments and other embodiments of the invention will be apparent to those skilled in the art from the description. Therefore, the appended claims cover any such modifications or embodiments.

Claims

1. A method for capturing memory errors, the method comprising: The first buffer of the first error compressor unit circuit receives the first memory error packet associated with the first memory. The first buffer is used to receive second memory error packets associated with the second memory; Send a first read request for reading the first memory error packet; The arbitrator circuit of the error aggregator unit circuit of the central memory error management unit circuit receives the first read request; In response to receiving the first read request, the first memory error packet is read from the first buffer, the first memory error packet is sent to the controller of the central memory error management unit circuit, and a first acknowledgment is sent to the first error compressor unit circuit. The first confirmation is received using the first error compressor unit circuit; as well as In response to receiving the first confirmation, a second read request for reading the second memory error packet is sent.

2. The method according to claim 1, further comprising: The second buffer of the second error compressor unit circuit receives the third memory error packets associated with the third memory; Send a third read request for reading the third memory error packet; The second read request is received using the arbitrator circuit. The third read request is received using the arbitrator circuit. as well as The second memory error group and the third memory error group are read sequentially based on the sequence determined by the arbitrator circuit.

3. The method of claim 2, wherein the determined sequence is based on a round-robin scheduling scheme.

4. The method of claim 2, wherein the determined sequence is based on an arbitration scheme, the arbitration scheme being based on priority.

5. The method of claim 1, wherein the first buffer is a write-multiple buffer.

6. The method according to claim 1, further comprising: The first memory error packet and the second memory error packet are written to the first buffer simultaneously.

7. The method of claim 1, wherein the first buffer is a first-in-first-out buffer.

8. The method according to claim 1, further comprising: Perform a built-in memory self-test on the first memory; as well as Based on the results of the built-in self-test of the memory, the first memory error group is generated.

9. The method according to claim 8, further comprising: Start the car; as well as During the start-up of the vehicle, the built-in self-test of the first memory is performed.

10. The method according to claim 1, further comprising: Perform an error correction code test on the first memory; as well as Based on the results of the error correction code test, the first memory error group is generated.

11. The method of claim 10, further comprising: Operating a car; as well as While operating the vehicle, the error correction code test is performed on the first memory.

12. The method of claim 1, wherein reading the first memory error packet from the first buffer comprises: Use a parallel bus.

13. The method of claim 12, wherein the parallel bus is coupled between the first buffer and the selector circuit, the method further comprising: The arbitrator circuit controls the selector circuit to sequentially send error packets to the controller of the central memory error management unit circuit.

14. The method of claim 1, wherein reading the first memory error packet from the first buffer comprises: Use a serial bus.

15. The method of claim 1, wherein sending the first read request includes switching the first request signal, and wherein sending the first confirmation switch first confirmation signal.

16. The method according to claim 1, further comprising: The first faulty compressor unit circuit is operated using the first clock; as well as The arbitrator circuit is operated with a second clock, wherein the first clock and the second clock have different frequencies.

17. The method according to claim 1, further comprising: The first faulty compressor unit circuit is operated using the first clock; as well as The arbitrator circuit is operated with a second clock, wherein the first clock and the second clock have the same frequency.

18. The method of claim 1, wherein the first memory error group has between 42 and 52 bits.

19. A circuit comprising: The central memory error management unit circuit includes an error aggregator unit circuit; An error compressor unit circuit is coupled to the error aggregator unit circuit, the error compressor unit circuit having a buffer; as well as A first memory and a second memory are coupled to the error compressor unit circuit, wherein the error compressor unit circuit is configured to: The buffer is used to receive the first memory error packet from the first memory. The buffer is used to receive second memory error packets from the second memory. Make the first memory error packet available on the parallel bus, and send a first read request to the error aggregator unit circuit for reading the first memory error packet. After sending the first read request, a first confirmation is received, and In response to receiving the first confirmation, the second memory error packet becomes available on the parallel bus, and a second read request for reading the second memory error packet is sent to the error aggregator unit circuit.

20. The circuit of claim 19, wherein the error compressor unit circuit includes a first terminal and a second terminal and a first handshake circuit coupled between the buffer and the first terminal and the second terminal, wherein the error compressor unit circuit is configured to send the first read request via the first terminal and receive the first acknowledgment via the second terminal.

21. The circuit of claim 20, wherein the first handshake circuit comprises: A logic gate having a first input and an output, the first input being configured to receive a first signal from the buffer, the first signal indicating whether the buffer is empty, and the output being coupled to a first terminal; as well as A trigger having an input and an output, the input being coupled to the second terminal and the output being coupled to the buffer.

22. The circuit of claim 20, wherein the error aggregator unit comprises an arbiter circuit and a second handshake circuit, the second handshake circuit being coupled between the first handshake circuit and the arbiter circuit, the second handshake circuit comprising a flip-flop and a logic gate, the flip-flop having an output coupled to a second terminal, the logic gate having a first input, a second input, and an output, the first input being coupled to the output of the flip-flop of the second handshake circuit, the second input being coupled to the first terminal, and the output of the logic gate being coupled to the arbiter circuit.

23. An integrated circuit, comprising: The central memory error management unit circuit includes an error aggregator unit circuit; Multiple error compressor unit circuits, each of the multiple error compressor unit circuits including a respective first-in-first-out buffer, the respective first-in-first-out buffer being coupled to a respective parallel bus, the respective parallel bus being coupled to the error aggregator unit; as well as Multiple memories are divided into subgroups, each subgroup being coupled to a specific error compressor unit circuit within the plurality of error compressor unit circuits, wherein each error compressor unit circuit is configured to: Receive memory error packets from one or more memories of each of the subgroups. The memory error groups are stored in each of the first-in-first-out buffers. When each of the aforementioned FIFO buffers is not empty, the next memory error packet stored in the FIFO buffer becomes available on each of the aforementioned parallel buses, and a read request is sent to the error aggregator unit. After sending the read request, receive confirmation, and In response to receiving the acknowledgment, the next memory error packet stored in the first-in-first-out buffer becomes available on each of the parallel buses, and a new read request is sent to the error aggregator unit.

24. The integrated circuit of claim 23, wherein the memory error management unit circuit includes a controller, and wherein the error aggregator unit circuit includes an arbitrator circuit configured to: Receive read requests from the plurality of faulty compressor unit circuits; From the parallel bus coupled to the first-in-first-out buffer of the plurality of error compressor unit circuits, memory error packets are read sequentially; as well as The memory error packets are sequentially sent to the controller of the memory error management unit circuit.

25. The integrated circuit according to claim 23, further comprising: Additional memory error management unit circuitry, including additional error aggregator unit circuitry; Multiple additional error compressor unit circuits, each of the multiple additional error compressor unit circuits including a respective first-in-first-out buffer, the respective first-in-first-out buffer being coupled to a respective parallel bus, the respective parallel bus being coupled to the additional error aggregator unit circuit. as well as Multiple additional memories are divided into multiple additional subgroups, each additional subgroup being coupled to multiple additional error compressor unit circuits, wherein each additional error compressor unit circuit is configured as follows: Receive memory error packets from one or more additional memories of each of the additional subgroups. The memory error groups are stored in each of the first-in-first-out buffers. When each of the aforementioned FIFO buffers is not empty, the next memory error packet stored in the FIFO buffer becomes available on each of the aforementioned parallel buses, and a read request is sent to the additional error aggregator unit circuit. After sending the read request to the other error aggregator unit circuit, an acknowledgment is received from the other error aggregator unit circuit, and In response to receiving the acknowledgment from the additional error aggregator unit circuit, the next memory error packet stored in the first-in-first-out buffer becomes available on each parallel bus, and a new read request is sent to the additional error aggregator unit circuit.

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