A method for improving chipping edge of wafer

Abstract

The present invention discloses a method for improving chipping edge of dicing, comprising the following steps: Step 1: Wafer preparation: Select MCZ silicon single crystal wafer, 5-inch crystal orientation <111> , resistivity 5.0‑6.5Ω / cm, thickness 220μm±10%; Step 2: Slice road doping: Phosphorus liquid source deposition is performed under the conditions of furnace temperature 1120°C, oxygen 2L / min, nitrogen 3L / min, and source-carrying nitrogen 1.2L / min; Phosphorus source advancement is performed under the conditions of furnace temperature 1140°C, oxygen 2.5L / min, and nitrogen 4L / min; Four-probe test is used to test the diffusion block resistance of 0.6Ω±10%, and the junction depth is 12μm±10%. In the present invention, a high-concentration impurity doping process is performed on the scribe road area to make the scribe road "loose", thereby reducing the severity of scribe edge collapse and the resulting lattice damage, and improving the scribe quality of the wafer.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chip design and manufacturing, and in particular to a method for improving chipping edges during dicing. Background Art

[0002] The typical structure of the commonly planned strip is as follows: Figure 1 As shown in the figure, after the semiconductor wafer is manufactured, it is necessary to separate the chips one by one by using a grinding wheel. The grinding wheel used for cutting is composed of hard diamond and adhesive. The grinding wheel rotates at high speed to grind and cut the wafer cutting path. Since the wafer is made of silicon material, it has high hardness and high brittleness, so it will break during the cutting process. Figure 2 As shown, the industry calls this phenomenon "edge collapse".

[0003] Since silicon atoms in single crystal silicon are arranged continuously in lattice order, the edge collapse phenomenon will extend the lattice damage to the inside of the silicon chip. If it extends to the effective working area of ​​the chip, it will cause the electrical parameters of the chip to fail. Therefore, edge collapse is a major factor leading to chip loss after dicing. Summary of the invention

[0004] The purpose of the present invention is to provide a method for improving chipping edges, in which a doping process is performed on the chip functional area while a doping process is performed on the dicing lane area at the same time. When designing the photolithography pattern, a doping region can also be designed for the dicing lane, that is, no separate doping process for the dicing lane is added and the product cost is not increased.

[0005] The technical problems solved by the present invention are:

[0006] How to reduce the impact of wafer edge chipping during cutting, thereby improving chip yield.

[0007] The purpose of the present invention can be achieved through the following technical solutions:

[0008] A method for improving chipping edge of a slice comprises the following steps:

[0009] Step 1: Wafer preparation

[0010] Select MCZ silicon single crystal, 5-inch crystal orientation <111> , resistivity 5.0-6.5Ω / cm, thickness 220μm±10%;

[0011] Step 2: Slice doping

[0012] Phosphorus liquid source deposition was carried out at a furnace temperature of 1120°C, oxygen 2L / min, nitrogen 3L / min, and source nitrogen 1.2L / min;

[0013] After deposition, the phosphorus source was advanced at a furnace temperature of 1140°C, oxygen at 2.5 L / min, and nitrogen at 4 L / min;

[0014] The diffusion square resistance is 0.6Ω±10% and the junction depth is 12μm±10% using four-probe test.

[0015] As a further solution of the present invention: in step 2, phosphorus doping is used for doping the scribe line.

[0016] As a further solution of the present invention: the time for depositing the phosphorus liquid source in step 2 is 25 minutes.

[0017] As a further solution of the present invention: the time for advancing the phosphorus source in step 2 is 150 minutes.

[0018] Beneficial effects of the present invention:

[0019] (1) The present invention performs a high-concentration impurity doping process on the scribe line area to make the scribe line "loose", thereby reducing the severity of scribe edge collapse and the resulting lattice damage, and improving the scribe quality of the wafer;

[0020] (2) In the present invention, the doping process is performed on the chip functional area while the doping process is performed on the scribe line area at the same time. When designing the photolithography pattern, the doping area can also be designed for the scribe line. There is no need to add a separate doping process for the scribe line and the product cost is not increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention will be further described below in conjunction with the accompanying drawings.

[0022] Figure 1 It is a schematic diagram of the structure of the commonly planned slice channel in the prior art;

[0023] Figure 2 It is a schematic diagram of the structure of wafer edge collapse damage in the prior art;

[0024] Figure 3 It is a schematic diagram of the structure of the scribe line doping of the present invention;

[0025] Figure 4 It is a schematic diagram of the structure of the scribing road of the present invention;

[0026] Figure 5 is a three-dimensional diagram of the bidirectional cutting table of the present invention;

[0027] Figure 6 It is a front view of the bidirectional cutting table of the present invention.

[0028] Figure 7 It is a schematic diagram of the internal structure of the driving cavity of the present invention.

[0029] In the figure: 1. Bidirectional cutting table; 101. Wafer cutting table; 102. Y-axis lead screw; 103. Moving base; 2. Gantry; 201. Horizontal guide block; 202. X-axis lead screw; 203. Driving cavity; 204. Z-axis lead screw; 205. Longitudinal guide block; 206. Cutting mounting plate; 207. Cutting motor. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] See also Figure 3 As shown, the present invention is a method for improving chipping edge of dicing, comprising the following steps:

[0032] Step 1: Wafer preparation

[0033] Select MCZ silicon single crystal, 5-inch crystal orientation <111> , resistivity 5.0-6.5Ω / cm, thickness 220μm±10%;

[0034] Step 2: Slice doping

[0035] Phosphorus doping was adopted, and phosphorus liquid source deposition was carried out under the conditions of furnace temperature 1120℃, oxygen 2L / min, nitrogen 3L / min, and source-carrying nitrogen 1.2L / min, and the phosphorus liquid source deposition time was 25min; phosphorus source advancement was carried out under the conditions of furnace temperature 1140℃, oxygen 2.5L / min, and nitrogen 4L / min, and the phosphorus source advancement time was 150min; and four-probe test was used to show that the diffused block resistance was 0.6Ω±10%, and the junction depth was 12μm±10%.

[0036] The wafer can be oxidized before doping the scribe line. The oxidation conditions are to produce a field oxygen masking layer at a furnace temperature of 1100° C., oxygen 4 L / min, and hydrogen 5 L / min. The thickness of the oxide layer is 1.5 μm±10%.

[0037] The basis of this scheme is that when single crystal silicon is not doped with impurities, its lattice structure is the most perfect, its hardness is the highest, and its brittleness is also the highest. With the incorporation of impurity atoms, impurity defects will be formed, and the impurity defects will reduce the brittleness of the single crystal silicon material and become the termination point when the lattice damage expands. Therefore, high concentration of impurity doping can make the dicing path "loose", thereby reducing the severity of the dicing edge collapse and the resulting lattice damage.

[0038] See also Figure 5-Figure 7, step 1: the wafer is prepared for bidirectional cutting by the bidirectional cutting table 1, the bidirectional cutting table 1 is in a U-shaped structure, which is convenient for the installation of the block support plate, and the block support plates are vertically arranged on the side plates on both sides of the U-shaped structure of the bidirectional cutting table 1, and the wafer cutting table 101 for placing the wafer raw material is fixedly arranged on the top of the support plates on both sides;

[0039] The width of the block support plate is consistent with the width of the side plate of the bidirectional cutting table 1, making the overall structure more beautiful.

[0040] A Y-direction screw rod 102 is arranged between the side plates on both sides of the bidirectional cutting table 1, and guide slide bars are arranged on both sides of the Y-direction screw rod 102. A movable base 103 inside the bidirectional cutting table 1 is threadedly connected to the Y-direction screw rod 102, and the movable base 103 is slidably arranged on the guide slide bars, and a gantry 2 is fixedly arranged on the movable base 103;

[0041] The guide slides on both sides of the Y-axis screw rod 102 are symmetrical about the center line of the Y-axis screw rod 102. The movable base 103 is provided with through holes compatible with the guide slides on both sides of the threaded hole. The movable base 103 is slidably connected to the guide slides through the through holes on both sides, so that the sliding of the movable base 103 inside the bidirectional cutting table 1 is more stable, thereby improving the cutting accuracy of the cutting mechanism for the wafer material.

[0042] The wafer cutting table 101 is arranged through the gantry 2, and cutting mechanisms are respectively arranged on both sides of the wafer cutting table 101 inside the gantry 2. The two cutting mechanisms are symmetrical in the vertical direction about the midline of the wafer cutting table 101 in the horizontal direction, so that the two cutting mechanisms can realize synchronous cutting of the wafer material, thereby improving the cutting stability.

[0043] The cutting mechanism includes a transverse guide block 201 fixedly arranged inside the gantry 2, and a strip-shaped slot penetrating therein is provided inside the transverse guide block 201 in the vertical direction. A driving cavity 203 is slidably connected to the strip-shaped slot of the transverse guide block 201, and the driving cavity 203 is a rectangular cavity structure with a certain wall thickness, and the wall thickness is adapted to the width of the strip-shaped slot, so as to facilitate the sliding of the driving cavity 203 in the strip-shaped slot;

[0044] The driving cavity 203 has a rectangular slot extending therethrough in the horizontal direction. The driving cavity 203 slides in a cross-over manner with the strip slot of the transverse guide block 201. The rectangular slot and the strip slot are mutually locked to achieve steady sliding of the driving cavity 203 on the transverse guide block 201.

[0045] An X-direction screw rod 202 is arranged inside the strip-shaped slot, and a threaded hole matching the X-direction screw rod 202 is opened in the portion of the drive cavity 203 located inside the strip-shaped slot, and the drive cavity 203 is threadedly connected to the X-direction screw rod 202 through the threaded hole;

[0046] A Z-axis screw rod 204 is vertically arranged inside the driving cavity 203, and a longitudinal guide block 205 is threadedly connected to the Z-axis screw rod 204. Connecting plates are arranged on both sides of the front of the longitudinal guide block 205. The connecting plates on both sides pass through the sliding groove on the front of the driving cavity 203 and are connected to a cutting mounting plate 206. A cutting motor 207 is arranged on the cutting mounting plate 206.

[0047] When cutting the wafer, the cutting mechanisms on the upper and lower sides of the gantry 2 are adjusted synchronously, and the cutting knives of the two cutting mechanisms are collinear in the vertical direction to achieve cutting of the wafer material;

[0048] The specific adjustment is to drive the X-direction lead screw 202 to rotate by the motor in the X direction, so that the X-direction lead screw 202 drives the driving cavity 203 to move in the X direction, and drive the Z-direction lead screw 204 to rotate by the motor in the Z direction, so that the Z-direction lead screw 204 drives the longitudinal guide block 205 to move in the Z direction, thereby realizing the adjustment of the position of the cutting motor 207. After the cutting mechanisms on both sides of the gantry 2 are adjusted, the Y-direction lead screw 102 is driven to rotate by the motor in the Y direction, so that the Y-direction lead screw 102 drives the gantry 2 to move in the Y direction, so that the two cutting structures can synchronously cut the top and bottom surfaces of the wafer material, which can improve the cutting stability of the wafer material and effectively avoid edge collapse during cutting.

[0049] The wafer cutting table 101 is provided with cutting notches for cutting common wafer materials.

[0050] See also Figure 4 As shown, combining the edge smoothness of the undoped scribe lines and the doped scribe lines, it can be seen that the smoothness consistency of the scribe lines through the phosphorus doping process is better than that of the undoped scribe lines. It can be concluded that the present invention optimizes the morphology quality of the scribe lines and improves the impact of scribe edge chipping.

[0051] It is specifically reflected in two aspects:

[0052] A1: It can reduce the brittleness of the dicing line, so that it is not easy to produce chipping during dicing, and improve the yield rate of the dicing process;

[0053] A2: It can curb the stress transfer during the dicing process, making it difficult for the damaged layer to be transferred to the active area of ​​the chip. Active area damage is one of the main reasons for chip reliability failure. The present invention can effectively improve the overall reliability of the chip.

[0054] That is, by optimizing chip design, the chip manufacturing process is greatly improved and the chip performance is improved without increasing manufacturing costs or adding additional processes.

[0055] When the above-mentioned doped scribing lines are used for scribing, feed speeds of 60 mm / s, 80 mm / s, and 100 mm / s are tested respectively. Among them, the process condition of 80 mm / s can also obtain the scribing line morphology that meets the quality requirements. Therefore, the present invention can adapt to higher feed speeds to improve the production efficiency of the scribing process.

[0056] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A method for improving chipping of dicing, characterized in that: The following steps are involved: Step 1: Wafer preparation Select MCZ silicon single wafer, 5-inch crystal orientation <111> , resistivity 5.0-6.5Ω / cm, thickness 220μm±10%; Step 2: The scribe line is doped with phosphorus liquid source deposition at a furnace temperature of 1120°C, oxygen 2L / min, nitrogen 3L / min, and source nitrogen 1.2L / min; After deposition, the phosphorus source was advanced at a furnace temperature of 1140°C, oxygen at 2.5 L / min, and nitrogen at 4 L / min; The diffusion square resistance is 0.6Ω±10% and the junction depth is 12μm±10% using four-probe test; In step 2, phosphorus doping is used for doping the scribe line; The time for the deposition of the phosphorus liquid source in step 2 is 25 min; The time for advancing the phosphorus source in step 2 is 150 min; The wafer preparation in step 1 is to perform bidirectional synchronous cutting on both sides of the wafer material by using a bidirectional cutting table (1); The bidirectional cutting platform (1) is in a U-shaped structure as a whole, and a wafer cutting platform (101) is fixedly arranged above the bidirectional cutting platform (1), a movable base (103) is arranged inside the bidirectional cutting platform (1) via a Y-direction screw rod (102), a gantry (2) is arranged on the movable base (103), and cutting mechanisms for wafer cutting are arranged on upper and lower sides of the two parts of the gantry (2); The two cutting mechanisms have exactly the same structure.

2. A method for improving chipping of dicing according to claim 1, characterized in that: The cutting mechanism comprises a transverse guide block (201) fixedly arranged inside the gantry (2), a strip-shaped slot penetrating the inside of the transverse guide block (201) being provided in the vertical direction, a driving cavity (203) being slidably connected to the strip-shaped slot of the transverse guide block (201), a Z-direction screw rod (204) being vertically arranged inside the driving cavity (203), a longitudinal guide block (205) being threadedly connected to the Z-direction screw rod (204), the longitudinal guide block (205) penetrating the sliding groove on the front side of the driving cavity (203) through the connecting plates on both sides to connect to the cutting installation plate (206), and a cutting motor (207) being arranged on the cutting installation plate (206).

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