Method of manufacturing a semiconductor device

Abstract

Embodiments of the present invention provide a method for manufacturing a semiconductor device with a low on-resistance. The embodiment is a method for manufacturing a semiconductor device, in which a trench is formed in a semiconductor layer of a first conductivity type, a first silicon-containing layer is formed in the trench, and then a second layer containing a first oxide or nitride is formed on the first layer, or the first layer is formed on the second layer after the second layer is formed, and the first layer is thermally oxidized.

Description

[0001] Related Application

[0002] This application claims priority based on Japanese Patent Application No. 2020-156928 (filing date: September 18, 2020). By reference to this basic application, this application incorporates the entire content of the basic application. Technical Field

[0003] An embodiment of the present implementation relates to a method for manufacturing a semiconductor device. Background Art

[0004] Semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used in applications such as power conversion. For such semiconductor devices, a low on-resistance is preferred. Summary of the Invention

[0005] An embodiment of the present invention provides a method for manufacturing a semiconductor device with a low on-resistance.

[0006] The method for manufacturing a semiconductor device according to the embodiment is to form a trench in a semiconductor layer of a first conductivity type, and in the trench, after forming a first silicon-containing layer, form a second layer containing a first oxide or nitride on the first layer, or after forming the second layer, form the first layer on the second layer, and thermally oxidize the first layer. Brief Description of the Drawings

[0007] Figure 1 It is a schematic cross-sectional view of a semiconductor device according to an embodiment.

[0008] Figure 2 It is a schematic cross-sectional view of a semiconductor device according to another mode of the embodiment.

[0009] Figure 3 (a) and (b) are schematic cross-sectional views of a semiconductor device according to an embodiment.

[0010] Figures 4 to 6 It is a schematic cross-sectional view showing the manufacturing process of a first mode of a semiconductor device according to an embodiment.

[0011] Figure 7 and 8 It is a schematic cross-sectional view showing the manufacturing process of a second mode of a semiconductor device according to an embodiment.

[0012] Figures 9 to 14 It is a schematic cross-sectional view showing the manufacturing process of a third mode of a semiconductor device according to an embodiment.

[0013] Figure 15Schematic cross-sectional view of a semiconductor device of a comparison method.

[0014] Figure 16 Schematic cross-sectional view for explaining a manufacturing method of a semiconductor device of a comparison method.

[0015] Figure 17 Schematic cross-sectional view for explaining a manufacturing method of a semiconductor device of a comparison method.

[0016] Figure 18 Schematic cross-sectional view for explaining the operation and effect of a semiconductor device of an embodiment. Detailed implementation mode

[0017] Hereinafter, embodiments of the present invention will be described with reference to the accompanying Figure 1 drawings. In addition, in the following description, the same components etc. are denoted by the same reference numerals, and the description of the components etc. that have been described will be appropriately omitted.

[0018] In this specification, the concepts of "upper" and "lower" are not necessarily terms indicating the relationship with the direction of gravity.

[0019] Hereinafter, the case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example.

[0020] In the following description, n + , n, n - and p + , p, p - expressions represent the relative levels of the impurity concentrations of each conductivity type. That is, n + means that the impurity concentration of the n-type is relatively high compared to n, and n - means that the impurity concentration of the n-type is relatively low compared to n. In addition, p + means that the impurity concentration of the p-type is relatively high compared to p, and p - means that the impurity concentration of the p-type is relatively low compared to p. In addition, there are cases where the n + type and the n - type are only recorded as the n-type, and the p + type and the p - type are only recorded as the p-type.

[0021] (Embodiment)

[0022] In the manufacturing method of the semiconductor device of the embodiment, a trench is formed in a semiconductor layer of the first conductivity type, and after forming a first layer containing silicon in the trench, a second layer containing a first oxide or nitride is formed on the first layer, or after forming the second layer, the first layer is formed on the second layer, and the first layer is thermally oxidized.

[0023] Figure 1Schematic cross-sectional view of the semiconductor device 100 of the embodiment. The semiconductor device 100 is, for example, a vertical MOSFET.

[0024] The semiconductor device 100 includes a drain layer 10, a drift layer 12, a base region 14, a source region 16, a p + region 20, a barrier layer metal 36, a drain electrode 38, a source electrode 42, a first trench 50, a third layer 52a, a first layer 52b, a second layer 52c, an insulating layer 52d, a first field plate electrode 54, a first gate electrode 58, an interlayer insulating film 60, a second trench 70, a sixth layer 72a, a fourth layer 72b, a fifth layer 72c, an insulating layer 72d, a second field plate electrode 74, and a second gate electrode 78.

[0025] In addition, the drift layer 12 is an example of a semiconductor layer. The base region 14 is an example of a first semiconductor region. The source region 16 is an example of a second semiconductor region. The first gate electrode 58 is an example of a first electrode. The drain electrode 38 is an example of a third electrode. The source electrode 42 is an example of a second electrode.

[0026] The drain layer 10 is a layer that functions as the drain of the MOSFET. The drain layer 10 contains, for example, an n + -type semiconductor material.

[0027] The drain electrode 38 is provided under the drain layer 10 and is electrically connected to the drain layer 10. The drain layer 10 is provided between the drain electrode 38 and the drift layer 12. The drain electrode 38 is an electrode that functions as the drain electrode of the MOSFET.

[0028] The drift layer 12 is provided above the drain layer 10. The drift layer 12 is a layer that functions as the drift layer of the MOSFET. The drift layer 12 contains, for example, an n - -type semiconductor material.

[0029] Here, the X direction, the Y direction that intersects the X direction perpendicularly, and the Z direction that intersects the X direction and the Y direction perpendicularly are defined. The drain electrode 38, the drain layer 10, and the drift layer 12 are layers provided parallel to the XY plane parallel to the X direction and the Y direction. The Z direction is the direction in which the drain electrode 38, the drain layer 10, and the drift layer 12 are stacked. Figure 1 Schematic cross-sectional view in the YZ plane of the semiconductor device 100 showing the embodiment.

[0030] The base region 14 is provided above the drift layer 12. The base region 14 is a region that functions as the base of the MOSFET. The base region 14 is a region that forms a channel when a voltage is applied to the first gate electrode 58 or the second gate electrode 78 and allows carriers to flow between the source region 16 and the drain layer 10. The base region 14 contains, for example, p -Type semiconductor material. In the semiconductor device 100, the base region 14 includes base regions 14a, 14b, and 14c.

[0031] The source region 16 is provided above the base region 14. The source region 16 is a region that functions as the source of the MOSFET. When an appropriate voltage is applied to the first gate electrode 58 or the second gate electrode 78, carriers flow into the source region 16 and the drain layer 10. The source region 16, for example, includes an n + Type semiconductor material. In the semiconductor device 100, the source region 16 includes source regions 16a, 16b, 16c, and 16d.

[0032] The first trench 50 is provided so as to reach from the upper end of the base region 14 to the drift layer 12.

[0033] The second trench 70 is provided so as to reach from the upper end of the base region 14 to the drift layer 12.

[0034] The third layer 52a is provided in the first trench 50. The third layer 52a includes a second oxide. Here, the second oxide is, for example, silicon oxide.

[0035] The first layer 52b is provided above the third layer 52a in the first trench 50. The first layer 52b includes a material in which silicon such as polysilicon or amorphous silicon is oxidized. When the polysilicon includes a plurality of particles, the first layer 52b includes a plurality of silicon oxide particles.

[0036] The second layer 52c is provided above the first layer 52b in the first trench 50. The second layer 52c includes a first oxide or a nitride. Here, the first oxide is, for example, silicon oxide. Further, here, the nitride is, for example, silicon nitride.

[0037] Figure 1 In, the first layer 52b and the second layer 52c are each provided with one layer. However, for example, above the third layer 52a, the stacked structure of the first layer 52b and the second layer 52c may be provided repeatedly multiple times. In other words, another first layer 52b may be further provided above the second layer 52c. Further, another second layer 52c may be further provided above the other first layer 52b.

[0038] In addition, the third layer 52a may not be provided.

[0039] The sixth layer 72a is provided in the second trench 70. The sixth layer 72a includes a second oxide. Here, the second oxide is, for example, silicon oxide.

[0040] The fourth layer 72b is disposed above the sixth layer 72a within the second trench 70. The fourth layer 72b contains materials such as polysilicon and amorphous silicon that are oxidized silicon. When the polysilicon contains a plurality of grains, the fourth layer 72b contains a plurality of grains of silicon oxide.

[0041] The fifth layer 72c is disposed above the fourth layer 72b within the second trench 70. The fifth layer 72c contains a first oxide or nitride. Here, the first oxide is, for example, silicon oxide. Additionally, here the nitride is, for example, silicon nitride.

[0042] Figure 1 In this case, one layer of the fourth layer 72b and the fifth layer 72c is respectively provided. However, for example, above the sixth layer 72a, the stacked structure of the fourth layer 72b and the fifth layer 72c may be provided repeatedly multiple times. In other words, another fourth layer 72b may be further provided above the fifth layer 72c. Additionally, another fifth layer 72c may be further provided above another fourth layer 72b.

[0043] Furthermore, the sixth layer 72a may not be provided.

[0044] The first field plate electrode 54 is disposed within the first trench 50 facing the drift layer 12 via the third layer 52a, the first layer 52b, and the second layer 52c. The first field plate electrode 54 is provided, for example, to mitigate the concentration of the reverse electric field between the first gate electrode 58 and the drain electrode 38 and increase the breakdown voltage. Additionally, the first field plate electrode 54 may not be provided.

[0045] The second field plate electrode 74 is disposed within the second trench 70 facing the drift layer 12 via the sixth layer 72a, the fourth layer 72b, and the fifth layer 72c. The second field plate electrode 74 is provided, for example, to mitigate the concentration of the reverse electric field between the second gate electrode 78 and the drain electrode 38 and increase the breakdown voltage. Additionally, as long as the first field plate electrode 54 is not used, the second field plate electrode 74 may not be provided.

[0046] The first gate electrode 58 is disposed within the first trench 50 facing the base region 14. Figure 1 In this case, the first gate electrode 58a is disposed facing the base region 14a via the third layer 52a, the first layer 52b, and the second layer 52c. Additionally, the first gate electrode 58b is disposed facing the base region 14b via the third layer 52a, the first layer 52b, and the second layer 52c. The first gate electrode 58 is an electrode that functions as the gate of the MOSFET.

[0047] For example, the third layer 52a, the first layer 52b, and the second layer 52c between the first gate electrode 58a and the base region 14a function as a gate insulating film of the MOSFET. For example, the third layer 52a, the first layer 52b, and the second layer 52c between the first gate electrode 58b and the base region 14b function as a gate insulating film of the MOSFET.

[0048] The second gate electrode 78 is disposed in the second trench 70 facing the base region 14. Figure 1 In, the second gate electrode 78a is disposed facing the base region 14b via the sixth layer 72a, the fourth layer 72b, and the fifth layer 72c. In addition, the second gate electrode 78b is disposed facing the base region 14c via the sixth layer 72a, the fourth layer 72b, and the fifth layer 72c. The second gate electrode 78 is an electrode that functions as a gate of the MOSFET.

[0049] For example, the sixth layer 72a, the fourth layer 72b, and the fifth layer 72c between the second gate electrode 78a and the base region 14b function as a gate insulating film of the MOSFET. For example, the sixth layer 72a, the fourth layer 72b, and the fifth layer 72c between the second gate electrode 78b and the base region 14c function as a gate insulating film of the MOSFET.

[0050] The interlayer insulating film 60a as the interlayer insulating film 60 is disposed above the first gate electrode 58 and the first field plate electrode 54. The interlayer insulating film 60b as the interlayer insulating film 60 is disposed above the second gate electrode 78 and the second field plate electrode 74.

[0051] In addition, an insulating layer 52d may be appropriately disposed between the second layer 52c and the first field plate electrode 54 in the first trench 50, between the first gate electrode 58 and the first field plate electrode 54, and between the interlayer insulating film 60a and the first gate electrode 58 and the first field plate electrode 54.

[0052] In addition, an insulating layer 72d may be appropriately disposed between the fifth layer 72c and the second field plate electrode 74 in the second trench 70, between the second gate electrode 78 and the second field plate electrode 74, and between the interlayer insulating film 60b and the second gate electrode 78 and the second field plate electrode 74.

[0053] The source electrode 42 has a first electrode portion 42a, a second electrode portion 42b, a third electrode portion 42c, a fourth electrode portion 42d, a fifth electrode portion 42e, a sixth electrode portion 42f, and a seventh electrode portion 42g. The seventh electrode portion 42g is provided over the interlayer insulating film 60. The fourth electrode portion 42d, the fifth electrode portion 42e, and the sixth electrode portion 42f are provided under the seventh electrode portion 42g. The first electrode portion 42a is provided under the fourth electrode portion 42d so as to reach the base region 14a. The second electrode portion 42b is provided under the fifth electrode portion 42e so as to reach the base region 14b. The third electrode portion 42c is provided under the sixth electrode portion 42f so as to reach the base region 14c. The source electrode 42 is an electrode that functions as the source of the MOSFET.

[0054] p + The region 20a is provided in the base region 14a between the first electrode portion 42a and the drain layer 10. p + The region 20b is provided in the base region 14b between the second electrode portion 42b and the drain layer 10. p + The region 20c is provided in the base region 14c between the third electrode portion 42c and the drain layer 10. p + The p-type impurity concentration of the region 20 is higher than that of the base region 14. When a reverse voltage is applied to the MOSFET, if a potential difference is generated between the potential of the base region 14 and the potential of the source electrode 42, the parasitic bipolar transistor formed by the source region 16, the base region 14, and the drift layer 12 operates, resulting in device breakdown. Therefore, by providing p + The region 20 is a region having a Hall conductivity higher than that of the base region 14, so that no potential difference is generated between the potential of the base region 14 and the potential of the source electrode 42, suppressing device breakdown.

[0055] The barrier metal 36 is provided between the base region 14, the source region 16, p + The region 20, and the interlayer insulating film 60 and the source electrode 42. The barrier metal 36 is a film used to prevent the reaction between the source electrode 42 and the semiconductor material used in the semiconductor device 100. The barrier metal 36 contains, for example, Ti (titanium), TiN (titanium nitride), Ta (tantalum), or TaN (tantalum nitride).

[0056] The semiconductor material used for the drain layer 10, the drift layer 12, the base region 14, the source region 16, and p + is, for example, silicon (Si). However, the semiconductor material used for the drain layer 10, the drift layer 12, the base region 14, the source region 16, and p +The semiconductor material used in Region 20 may also be other semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), or gallium arsenide (GaAs).

[0057] When silicon is used as the semiconductor material, arsenic (As), phosphorus (P), or antimony (Sb) can be used as the n-type impurity, and B (boron) can be used as the p-type impurity, for example.

[0058] The first gate electrode 58, the second gate electrode 78, the first field plate electrode 54, and the second field plate electrode 74 include a conductive material such as doped polysilicon.

[0059] The insulating layer 52d, the insulating layer 72d, and the interlayer insulating film 60 include an insulating material such as silicon oxide or silicon nitride.

[0060] The drain electrode 38 and the source electrode 42 include a metal such as aluminum (Al), for example.

[0061] Figure 2 Schematic cross-sectional view of the semiconductor device 110 of another embodiment. In the first trench 50, the second layer 52c is provided above the third layer 52a. In addition, the first layer 52b is provided above the second layer 52c. In addition, in the second trench 70, the fifth layer 72c is provided above the sixth layer 72a. In addition, the fourth layer 72b is provided above the fifth layer 72c. The rest is the same as Figure 1 the semiconductor device 100 shown. In addition, the third layer 52a and the sixth layer 72a may not be provided.

[0062] Figure 3 Schematic cross-sectional view of the semiconductor device of the embodiment. Figure 3 (a) Schematic cross-sectional view of the semiconductor device 100 of the embodiment in the XZ plane. Figure 3 (b) is Figure 3 (a) Schematic cross-sectional view of the semiconductor device 100 of the embodiment in the A-A' cross-section shown. Figure 3 (b) The schematic cross-sectional view in the A-A' cross-section shown corresponds to, for example, Figure 1 the schematic cross-sectional view shown. Figure 3 (a) In the B-B' cross-section, the first field plate electrode 54 has a portion extending upward. Further, using this portion, the first field plate electrode 54 is electrically connected to the source electrode 42 via the barrier layer metal 36, for example. In addition, Figure 3 (b) In (b), the first layer 52b, the second layer 52c, the third layer 52a, and the insulating layer 52d are shown as the insulating layer 52. In addition, the first field plate electrode 54 may also be electrically connected to the first gate electrode 58 in the first trench 50, for example.

[0063] Similarly, the second field plate electrode 74 is electrically connected to the source electrode 42. Further, the second field plate electrode 74 may also be electrically connected to the second gate electrode 78 in the second trench 70, for example.

[0064] Figures 4 to 6 FIG. is a schematic cross-sectional view of a manufacturing process of a first mode of a semiconductor device according to an embodiment. Figures 4 to 6 To represent Figure 1 a schematic cross-sectional view of a manufacturing process of the semiconductor device 100 according to the embodiment shown.

[0065] First, on the drain layer 10, a drift layer 12 is formed by epitaxial growth, for example. For example, with the drain layer 10 as a semiconductor substrate, the drift layer 12 is formed by epitaxial growth on the drain layer 10. Next, for example, using photolithography and RIE (Reactive Ion Etching), a first trench 50 and a second trench 70 are formed in the drift layer 12.

[0066] Next, using a thermal oxidation method, a layer 102a containing a second oxide is formed in the first trench 50 and the second trench 70 on the drift layer 12. Here, the second oxide is, for example, silicon oxide ( Figure 4 ).

[0067] Next, a silicon-containing layer 102b is formed on the layer 102a. For example, when forming the polysilicon-containing layer 102b, it is preferable to form the layer 102b using a reduced-pressure CVD (Chemical Vapor Deposition) method. In addition, when forming the polysilicon-containing layer 102b, the layer 102b contains a plurality of polysilicon grains.

[0068] Next, a layer 102c containing a first oxide or nitride is formed on the layer 102b. Here, the first oxide is, for example, silicon oxide. In addition, the nitride is, for example, silicon nitride. When the first oxide is silicon oxide, for example, it is preferable to form the layer 102c using a plasma CVD method (an example of a CVD method). When the nitride is silicon nitride, for example, it is preferable to form the layer 102c using a reduced-pressure CVD method (an example of a CVD method).

[0069] Next, the layer 102b is thermally oxidized. When the layer 102b contains particles of polysilicon, the thermally oxidized layer 102b contains particles of silicon oxide. Here, the fact that the layer 102b contains particles of silicon oxide can be confirmed by microscopic observation using a microscope such as an SEM (Scanning Electron Microscope) or a TEM (Transmission Electron Microscope). In addition, through thermal oxidation, the film thickness of the polysilicon-containing layer expands to about twice, for example. Therefore, in consideration of this expansion, it is preferable to determine the film thickness for forming the polysilicon-containing layer 102b.

[0070] In addition, the size of the polysilicon particles and the size of the silicon oxide particles are not particularly limited, and are, for example, about several hundred nm.

[0071] In addition, the layer 102a is an example of the third layer. The layer 102b is an example of the first layer. The layer 102c is an example of the second layer.

[0072] Next, the first field plate electrode 54, the second field plate electrode 74, the base region 14, the source region 16, the insulating layer 52d, the insulating layer 72d, the first gate electrode 58, the second gate electrode 78, the interlayer insulating film 60, the barrier layer metal 36, the source electrode 42, and the drain electrode 38 are appropriately formed to obtain the semiconductor device 100 of the embodiment. For example, the semiconductor device 100 of the embodiment is manufactured using the manufacturing method described in Japanese Patent Laid-Open Publication No. 2018-46253. In addition, the layers 102a, 102b, and 102c in the first trench 50 become the third layer 52a, the first layer 52b, and the second layer 52c, respectively. In addition, the layers 102a, 102b, and 102c in the second trench become the sixth layer 72a, the fourth layer 72b, and the fifth layer 72c, respectively.

[0073] In addition, the layer 102a may not be formed.

[0074] Figure 7 and Figure 8 is a schematic cross-sectional view showing the manufacturing process of the second mode of the semiconductor device of the embodiment. Figure 7 and Figure 8 is for showing Figure 2 a schematic cross-sectional view of the manufacturing process of the semiconductor device 110 of the embodiment shown. Up to the formation of the first trench 50 and the second trench 70 in the drift layer 12 and the formation of the layer 102a containing the second oxide in the first trench 50 and the second trench 70 above the drift layer 12 using the thermal oxidation method, it is the same as the manufacturing process of the first mode of the semiconductor device of the embodiment shown in Figures 4 to 6 shown.

[0075] Next, a layer 102c containing a first oxide or nitride is formed over the layer 102a. Here, the first oxide is, for example, silicon oxide. Additionally, the nitride is, for example, silicon nitride. Next, a layer 102b containing silicon is formed over the layer 102c( Figure 7 ).

[0076] Next, the layer 102b is thermally oxidized( Figure 8 ). After that, it is the same as the manufacturing process of the first mode of the semiconductor device in the Figures 4 to 6 illustrated embodiment.

[0077] In addition, the layer 102a may not be formed.

[0078] Figures 9 to 14 FIG. is a schematic cross-sectional view showing the manufacturing process of the third mode of the semiconductor device of the embodiment. Up to before forming the first trench 50 and the second trench 70 in the drift layer 12 and forming a layer 102a containing a second oxide in the first trench 50 and the second trench 70 over the drift layer 12 using thermal oxidation, it is the same as the manufacturing process of the first mode of the semiconductor device in the Figures 4 to 6 illustrated embodiment, and Figure 7 and Figure 8 the manufacturing process of the second mode of the semiconductor device in the illustrated embodiment.

[0079] Next, a layer 102b containing silicon such as polysilicon or amorphous silicon is formed over the layer 102a( Figure 9 ).

[0080] Next, a layer 104 containing silicon nitride is formed over the layer 102b in the first trench 50 and the second trench 70 and over the layer 102b on the drift layer 12( Figure 10 ).

[0081] Next, the layer 104 formed on the drift layer 12 is removed, for example, by wet etching using hot phosphoric acid( Figure 11 ). The layer 104 in the first trench 50 becomes the layer 104a, and the layer 104 in the second trench 70 becomes the layer 104b.

[0082] Next, a part of the layer 102b is removed, for example, by CDE (Chemical Dry Etching). The layer 102b in the first trench 50 becomes the layer 102b1, and the layer 102b in the second trench 70 becomes the layer 102b2( Figure 12 ).

[0083] Next, a part of the layer 102a is removed, for example, by wet etching using BHF (buffered hydrofluoric acid). The layer 102a in the first trench 50 becomes the layer 102a1, and the layer 102a in the second trench 70 becomes the layer 102a2(Figure 13 )。

[0084] Next, for example, by wet etching using hot phosphoric acid, layers 104a and 104b are removed ( Figure 14 ). After that, for example, an insulating layer 52d and an insulating layer 72d are respectively formed over layers 102b1 and 102b2. After that, layers 102b1 and 102b2 are thermally oxidized. After that, a first field plate electrode 54, a second field plate electrode 74, a base region 14, a source region 16, a first gate electrode 58, a second gate electrode 78, an interlayer insulating film 60, a barrier layer metal 36, a source electrode 42, and a drain electrode 38 are appropriately formed to obtain the semiconductor device 100 of the embodiment. For example, the semiconductor device 100 of the embodiment is manufactured using the manufacturing method described in Japanese Patent Laid-Open Publication No. 2018-46253. Furthermore, portions in contact with layer 102b1 of layer 102a1, layer 102b1, and insulating layer 52d in the first trench 50 respectively become a third layer 52a, a first layer 52b, and a second layer 52c. In addition, portions in contact with layer 102b2 of layer 102a2, layer 102b2, and insulating layer 72d in the second trench 70 respectively become a sixth layer 72a, a fourth layer 72b, and a fifth layer 72c.

[0085] Next, the effects of the manufacturing method of the semiconductor device of the embodiment are described.

[0086] Figure 15 FIG. is a schematic cross-sectional view of a semiconductor device 800 of a comparative method. In the first trench 50, a third layer 52a, a first layer 52b, a second layer 52c, and an insulating layer 52d are not provided. In the first trench 50, an insulating layer 52 containing silicon oxide formed, for example, by plasma CVD method or thermal oxidation method is provided. In the second trench 70, a sixth layer 72a, a fourth layer 72b, a fifth layer 72c, and an insulating layer 72d are not provided. In the second trench 70, an insulating layer 72 containing silicon oxide formed, for example, by plasma CVD method or thermal oxidation method is provided.

[0087] For example, by introducing strain into the Si contained in the drift layer 12, if the carrier mobility can be increased, the on-resistance can be reduced. Here, for example, when the carriers are electrons, for example, in Figure 15 the region indicated by the dashed line in the drift layer 12, a tensile stress is preferably applied in the Z direction, which is the carrier movement direction.

[0088] Therefore, it is considered that an insulating layer, such as an oxide layer, for applying such tensile stress to the drift layer 12 is formed in the first trench 50 and the second trench 70. The insulating layer has a different coefficient of thermal expansion from other semiconductor layers. Therefore, by forming the insulating layer on the surface of the semiconductor layer, stress can be applied to the semiconductor layer. Thus, when the insulating layer becomes a stress application source, tensile stress can be applied to the region indicated by the dotted line in the drift layer 12 adjacent to the insulating layer, and the on-resistance can be reduced.

[0089] Figure 16 FIG. for explaining a manufacturing method of a semiconductor device of a comparative method. For example, as a source for applying such tensile stress, it is considered that an oxide layer 106 formed by plasma CVD is formed in the first trench 50 and the second trench 70. When forming the oxide layer 106 by plasma CVD, the residual stress in the oxide layer 106 can be controlled by controlling the LF (Low Frequency) power. However, when forming the oxide layer 106 by plasma CVD, since the burying property is low, it is difficult to form a uniform oxide layer 106 on the inner walls of the first trench 50 and the second trench 70 as shown in Figure 16 , and there is a problem that a portion 107 where the oxide layer is not formed is generated at the bottoms of the first trench 50 and the second trench 70.

[0090] Figure 17 FIG. for explaining a manufacturing method of a semiconductor device of a comparative method. For example, as a source for applying such tensile stress, it is considered that an oxide layer 108 formed by thermal oxidation is formed in the first trench 50 and the second trench 70. In the case of thermal oxidation, the semiconductor material (e.g., Si) on the inner wall of the first trench 50 and the semiconductor material (e.g., Si) on the inner wall of the second trench 70 are oxidized to form the oxide layer 108. Therefore, compared with the oxide layer 106 formed by plasma CVD, the oxide layer 108 is more easily formed with a uniform film thickness on the inner walls of the first trench 50 and the second trench 70. In addition, by controlling the formation parameters such as the temperature used in thermal oxidation, the stress applied to the oxide layer 108 can be controlled. However, when forming the oxide layer 108 by thermal oxidation, as described above, since the semiconductor material on the inner wall of the trench is oxidized, the width of the drift layer 12 between adjacent trenches becomes narrow. Therefore, especially when the number of trenches is increased and the integration degree is improved, there is a problem that it is difficult to control the width of the drift layer 12.

[0091] Therefore, in the method of manufacturing a semiconductor device according to an embodiment, a trench is formed in a semiconductor layer of a first conductivity type, and a layer 102b containing silicon such as polysilicon and amorphous silicon or a layer 102c containing a first oxide or nitride is formed in the trench. When forming the layer 102b, the layer 102c is formed on the layer 102b. When forming the layer 102c, the layer 102b is formed on the layer 102c, and the layer 102b is thermally oxidized.

[0092] Figure 18 It is a schematic cross-sectional view for explaining the effect of the method of manufacturing a semiconductor device according to an embodiment.

[0093] When the layer 102b is thermally oxidized, a tensile stress can be applied from the thermally oxidized layer 102b to the region indicated by the dashed line in the drift layer 12 via the inner wall of the trench. Thereby, the on-resistance of the MOSFET can be reduced.

[0094] For example, when the layer 102c is formed on the layer 102b and the layer 102b is thermally oxidized, the layer 102b is enclosed between the inner wall of the trench and the layer 102c. Therefore, compared with the case where the layer 102b is open at the top, the tensile stress is more likely to propagate to the drift layer.

[0095] Before forming the layer 102b or the layer 102c, when forming the layer 102a containing a second oxide by a thermal oxidation method, only the amount for forming the layer 102b and the layer 102c can reduce the amount of the layer formed by the thermal oxidation method. Therefore, it is difficult to cause the problem that the width of the drift layer 12 between adjacent trenches becomes narrow, so it is easy to increase the number of trenches and improve the integration degree. In addition, since the second oxide is easy to manufacture, silicon oxide is preferred.

[0096] As described above, when polysilicon is oxidized, for example, the film thickness expands to about twice. Therefore, since a large stress is generated along with this expansion, it is easy to apply stress to the drift layer 12. In addition, by oxidizing the polysilicon particles, silicon oxide particles are formed.

[0097] The layer 102c preferably contains silicon oxide as the first oxide or silicon nitride as the nitride. The reason is that either of them is easy to manufacture.

[0098] By repeatedly forming the layer 102b and the layer 102c, a greater tensile stress can be applied to the drift layer 12.

[0099] According to the method of manufacturing a semiconductor device according to an embodiment, a method of manufacturing a semiconductor device with a low on-resistance can be provided.

[0100] Several embodiments of the present invention have been described, but these embodiments and examples are presented by way of illustration and not to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments or their modifications are included in the scope or gist of the invention and are also included in the invention described in the claims and its equivalents.

Claims

1. A method of manufacturing a semiconductor device, wherein, Form a trench in a semiconductor layer of a first conductivity type containing silicon; In the trench, form a first layer containing polysilicon and then form a second layer containing silicon oxide as a first oxide thereon, or form the first layer thereon after forming the second layer; Thermally oxidize the first layer.

2. The method of manufacturing a semiconductor device according to claim 1, wherein, Before forming the first layer or the second layer after forming the trench, form a third layer containing a second oxide in the trench using thermal oxidation.

3. The method of manufacturing a semiconductor device according to claim 1, wherein, The first layer that is thermally oxidized contains particles of silicon oxide.

4. The method of manufacturing a semiconductor device according to claim 1, wherein, Form the second layer using CVD.

5. The method of manufacturing a semiconductor device according to claim 1, wherein, Repeat the formation of the first layer and the second layer.

6. The method of manufacturing a semiconductor device according to any one of claims 1 to 5, wherein, After thermally oxidizing the first layer, form a first electrode in the trench, form a first semiconductor region of a second conductivity type above the semiconductor layer, form a second semiconductor region of a first conductivity type above the first semiconductor region, form a second electrode above the second semiconductor region, and form a third electrode below the semiconductor layer.

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