A semi-floating gate transistor with stable threshold voltage and a method for manufacturing the same

Abstract

The present invention discloses a semi-floating gate transistor with a stable threshold voltage and a preparation method thereof. The semi-floating gate transistor with a stable threshold voltage comprises: a substrate, which is formed with a P-well region, an N-well region and a U-shaped groove, wherein the N-well region is located above the P-well region, and the U-shaped groove runs through the N-well region; a first gate oxide layer, which is formed on the surface of the U-shaped groove and extends to cover part of the surface of the N-well region, and a window is formed on one side; a semi-floating gate, which covers the first gate oxide layer and completely fills the U-shaped groove, and contacts the N-well region at the window; a channel of the semi-floating gate transistor is close to the bottom of the U-shaped groove; a control gate dielectric layer, a control gate and a second silicon nitride layer are formed on the semi-floating gate in sequence; a separation gate dielectric layer and a separation gate, the separation gate dielectric layer covers the tunneling transistor channel region, and extends to cover part of the second silicon nitride layer, and the separation gate covers the separation gate dielectric layer and fills the separation gate region; a source region and a drain region are respectively formed in the N-well regions on both sides.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor memory, and in particular relates to a semi-floating gate transistor with a stable threshold voltage and a preparation method thereof. Background Art

[0002] As the device size becomes smaller and smaller, the 1T1C structure DRAM devices used in integrated circuit chips are facing more and more problems, such as the refresh time of 64ms, and the capacitance value of the capacitor must be kept above a certain value to ensure a sufficiently long charge retention time. However, as the feature size of integrated circuits shrinks, the manufacture of large capacitors becomes more and more difficult and occupies a huge manufacturing cost. As a new type of memory device, the semi-floating gate transistor is different from the traditional 1T1C structure DRAM device. It integrates an embedded tunneling transistor in the CMOS process. Under the appropriate operating voltage, the charge programming and erasing of the semi-floating gate area are completed through the channel of the embedded tunneling transistor and the semi-floating gate window. The entire erasing process can realize all the functions of the traditional 1T1C structure DRAM without capacitors, greatly reducing the cost and faster reading and writing speed. It is one of the most competitive devices in the future DRAM field.

[0003] From the manufacturing process of U-groove semi-floating gate transistors, the depth of the U-groove is greatly affected by the process deviation. If the U-groove is dug too deep relative to the target depth, the threshold voltage will be too high, which will cause the read current of the semi-floating gate transistor to decrease; if the groove is dug too shallow, the threshold voltage will be too low, causing the leakage risk of the semi-floating gate transistor to increase. Therefore, how to improve the manufacturing process of semi-floating gate transistors and improve the uniformity of the performance of semi-floating gate transistor devices is an important issue. Summary of the invention

[0004] The present invention discloses a method for preparing a semi-floating gate transistor with a stable threshold voltage, comprising the following steps: forming a P-well region and an N-well region in a device manufacturing region of a substrate, wherein the N-well region is located above the P-well region; etching to form a U-shaped groove, so that the U-shaped groove penetrates the N-well region; performing P-type impurity channel threshold adjustment injection, so that the channel of the formed semi-floating gate transistor is closely attached to the bottom of the U-shaped groove, so that the influence of the channel threshold adjustment injection on the threshold voltage of the device plays a dominant role; forming a first gate oxide layer and a semi-floating gate, wherein the first gate oxide layer forms a window on the surface of the N-well region on one side of the U-shaped groove, and the semi-floating gate covers the first gate oxide layer and completely Fill the U-shaped groove and contact the N-well region at the window; deposit a second gate oxide layer, a second polysilicon layer and a second silicon nitride layer, and then perform edge etching to expose part of the N-well region surface on one side of the window to form a channel of the tunneling transistor; form a separation gate dielectric layer and a separation gate, the separation gate dielectric layer covers the channel region of the tunneling transistor and extends to cover part of the second silicon nitride layer, the separation gate covers the separation gate dielectric and fills the separation gate region; perform edge etching to expose part of the N-well region surface on both sides to form side walls, perform ion implantation to form a source region and a drain region, and complete the preparation of a semi-floating gate transistor with a stable threshold voltage.

[0005] In the method for preparing a semi-floating gate transistor with a stable threshold voltage of the present invention, preferably, the steps of forming a first gate oxide layer and a semi-floating gate specifically include: growing a first gate oxide layer, depositing a first polysilicon layer, and then chemically and mechanically polishing the first polysilicon layer to a certain height, and etching a window of a semi-floating gate area on the surface of an N-well region on one side of a U-shaped groove; backfilling the first polysilicon layer, and then performing P-type ion implantation in the semi-floating gate area, and chemically and mechanically polishing the first polysilicon layer to a certain height to form a semi-floating gate.

[0006] In the method for preparing a semi-floating gate transistor with a stable threshold voltage of the present invention, preferably, the separation gate dielectric layer includes an oxide layer and a silicon nitride layer, and the separation gate is N-type polysilicon.

[0007] In the method for preparing a semi-floating gate transistor with a stable threshold voltage of the present invention, preferably, the steps of forming a separation gate dielectric layer and a separation gate include: depositing a third silicon oxide layer and a third silicon nitride layer to form a separation gate dielectric layer, so that it covers the surface of the N-well region and the second silicon nitride layer; then depositing a third polysilicon layer to cover the separation gate dielectric layer and fill the separation gate region; performing edge etching to expose part of the surface of the N-well region on both sides, and at the same time etching and removing part of the third polysilicon layer and the separation gate dielectric layer to expose part of the second silicon nitride layer; performing N-type ion implantation on the third polysilicon layer to form an independent separation gate.

[0008] In the method for preparing a semi-floating gate transistor with a stable threshold voltage of the present invention, preferably, the separation gate dielectric layer includes an oxide layer and a high-K dielectric layer, and the separation gate is metal.

[0009] The present invention also discloses a semi-floating gate transistor with a stable threshold voltage, comprising: a substrate, which is formed with a P-well region, an N-well region and a U-shaped groove, wherein the N-well region is located above the P-well region and the U-shaped groove runs through the N-well region; a first gate oxide layer, which is formed on the surface of the U-shaped groove and extends to cover a portion of the surface of the N-well region, and is formed with a window on one side; a semi-floating gate, which covers the first gate oxide layer and completely fills the U-shaped groove, and contacts the N-well region at the window; a channel of the semi-floating gate transistor is close to the bottom of the U-shaped groove; a control gate dielectric layer, a control gate and a second silicon nitride layer are formed in sequence on the semi-floating gate; a separation gate dielectric layer and a separation gate, the separation gate dielectric layer covers the channel region of the tunneling transistor and extends to cover a portion of the second silicon nitride layer, and the separation gate covers the separation gate dielectric layer and fills the separation gate region; a source region and a drain region are respectively formed in the N-well regions on both sides.

[0010] In the semi-floating gate transistor with a stable threshold voltage of the present invention, preferably, the separation gate dielectric layer includes an oxide layer and a silicon nitride layer, and the separation gate is N-type polysilicon.

[0011] In the semi-floating gate transistor with a stable threshold voltage of the present invention, preferably, the separation gate dielectric layer includes an oxide layer and a high-K dielectric layer, and the separation gate is a metal

[0012] The present invention makes the boundary of the channel of the semi-floating gate transistor close to the bottom of the U-shaped groove through the channel threshold adjustment injection, so that the influence of the channel threshold adjustment injection on the threshold voltage plays a leading role, thereby reducing the influence of the depth deviation of the U-shaped groove on the channel length and concentration of the device, and improving the stability of the threshold voltage of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a flow chart of a method for preparing a semi-floating gate transistor with a stable threshold voltage.

[0014] Figure 2 to Figure 13 It is a schematic diagram of the staged structure of each step of a method for preparing a semi-floating gate transistor with a stable threshold voltage. DETAILED DESCRIPTION

[0015] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. The described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0016] In the description of the present invention, it should be noted that the terms "upper", "lower", "vertical", "horizontal", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0017] In addition, many specific details of the present invention are described below, such as the structure, materials, dimensions, processing technology and techniques of the device, so that the present invention can be more clearly understood. However, as can be understood by those skilled in the art, the present invention can be implemented without following these specific details. Unless otherwise specified below, the various parts of the device can be made of materials known to those skilled in the art, or can be made of materials with similar functions developed in the future.

[0018] Figure 1 It is a flow chart of a method for preparing a semi-floating gate transistor with a stable threshold voltage. Figure 1 As shown, the following steps are included:

[0019] Step S1, in the device manufacturing area of ​​the substrate, first deposit a pad oxide layer 103, then perform P-type impurity ion implantation and N-type impurity ion implantation in sequence and perform annealing to form a P-well region 101 and an N-well region 102, wherein the N-well region 102 is located above the P-well region 101. The resulting structure is as shown in FIG. Figure 2 Then, a first silicon nitride layer 104 is deposited to form a hard mask, and then a U-shaped groove is formed by etching. The U-shaped groove runs through the N-well region 102. The resulting structure is as shown in FIG. Figure 3 shown.

[0020] Step S2, after the U-shaped groove is etched, a dose range of 8e 11 cm -2 ~2e 13 cm -2 The p-type impurity channel threshold adjustment injection is performed between the two layers to make the channel 103 of the formed semi-floating gate transistor close to the bottom of the U-shaped groove. The resulting structure is as follows: Figure 4 As shown, the influence of the channel threshold adjustment injection on the device threshold voltage plays a dominant role, reducing the influence of the trench depth process deviation on the device channel length and concentration. After the channel threshold adjustment injection is completed, the hard mask is removed and annealing is performed.

[0021] Step S3, such as Figure 5 to Figure 7As shown, the first gate oxide layer 104 is subsequently grown, the first polysilicon layer 106 is deposited, and then the first polysilicon layer 106 is chemically and mechanically polished to a certain height, and a window of the semi-floating gate region is etched on the surface of the N-well region on one side of the U-shaped groove. Then, the first polysilicon layer 106 is backfilled with a certain thickness, and then P-type ions are implanted in the semi-floating gate region, and the first polysilicon layer 106 is chemically and mechanically polished to a certain height to form a semi-floating gate.

[0022] Step S4, depositing a second gate oxide layer 107, a second polysilicon layer 108 and a second silicon nitride layer 109, the resulting structure is as follows: Figure 8 Then, edge etching is performed to expose the surface of part of the N-well region 102 on one side of the window, forming a channel and a separation gate region of the tunneling transistor. The resulting structure is shown in FIG. Fig. 9 shown.

[0023] Step S5, deposit a third silicon oxide layer 110 of a certain thickness, and then deposit a third silicon nitride layer 111 thereon to form a separation gate dielectric layer. Then, deposit a third polysilicon layer 112 to fill the separation gate region, and chemically and mechanically polish the third polysilicon layer 112 to a certain height. The resulting structure is as shown in FIG. Fig.10 In addition, the separation gate dielectric layer can also be silicon oxide and high-K dielectric, and the separation gate is made of metal.

[0024] Step S6, then Figure 11 to Figure 13 As shown, edge etching is performed to expose the surface of part of the N-well region 102 on both sides of the control gate, and at the same time, part of the third polysilicon layer 112 and the separation gate dielectric layer are etched away to expose part of the second silicon nitride layer 109, forming an independent separation gate and source and drain region. After that, silicon oxide and silicon nitride are isotropically deposited and anisotropically etched to form a sidewall 113, and N-type ion implantation is performed on the second polysilicon layer 108, the third polysilicon layer 112 and the substrate surface to form a control gate, a separation gate, a source region 114 and a drain region 115, completing the preparation of a semi-floating gate transistor with a stable threshold voltage.

[0025] like Fig.13As shown, the semi-floating gate transistor with a stable threshold voltage of the present invention comprises: a substrate, which is formed with a P-well region 101, an N-well region 102 and a U-shaped groove, wherein the N-well region 102 is located above the P-well region 101, and the U-shaped groove runs through the N-well region 102; a first gate oxide layer 104, which is formed on the surface of the U-shaped groove and extends to cover a portion of the surface of the N-well region 102, and has a window formed on one side; a semi-floating gate 106, which covers the first gate oxide layer 104 and completely fills the U-shaped groove, and contacts the N-well region 102 at the window; a semi-floating gate crystal The channel 103 of the tube is close to the bottom of the U-shaped groove; the control gate dielectric layer 107, the control gate 108 and the second silicon nitride layer 109 are formed on the semi-floating gate 106 in sequence; the separation gate dielectric layer includes a silicon oxide layer 110 and a silicon nitride layer 111, and the separation gate dielectric layer is formed on the surface of the N-well region 102 (covering the tunneling transistor channel region) and extends to cover part of the second silicon nitride layer 109, and the separation gate 112 covers the separation gate dielectric and fills the separation gate region; the source region 114 and the drain region 115 are respectively formed in the N-well regions on both sides.

[0026] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for preparing a semi-floating gate transistor with a stable threshold voltage, characterized in that: The following steps are involved: Forming a P-well region and an N-well region in a device manufacturing region of the substrate, wherein the N-well region is located above the P-well region; Etching to form a U-shaped groove, so that the U-shaped groove runs through the N-well region; Performing P-type impurity channel threshold adjustment injection, the channel of the formed semi-floating gate transistor is close to the bottom of the U-shaped groove, so that the influence of the channel threshold adjustment injection on the device threshold voltage plays a dominant role; Forming a first gate oxide layer and a semi-floating gate, wherein the first gate oxide layer forms a window on the surface of the N-well region on one side of the U-shaped groove, and the semi-floating gate covers the first gate oxide layer and completely fills the U-shaped groove, and contacts the N-well region at the window; Depositing a second gate oxide layer, a second polysilicon layer and a second silicon nitride layer, and then performing edge etching to expose a portion of the surface of the N-well region on one side of the window to form a channel of the tunneling transistor; forming a separation gate dielectric layer and a separation gate, wherein the separation gate dielectric layer covers the tunneling transistor channel region and extends to cover a portion of the second silicon nitride layer, and the separation gate covers the separation gate dielectric layer and fills the separation gate region; Edge etching is performed to expose the surface of part of the N-well region on both sides to form sidewalls, and ion implantation is performed to form source and drain regions, completing the preparation of a semi-floating gate transistor with a stable threshold voltage.

2. The method for preparing a semi-floating gate transistor with a stable threshold voltage according to claim 1, characterized in that: The steps of forming the first gate oxide layer and the semi-floating gate specifically include: Growing a first gate oxide layer, depositing a first polysilicon layer, and then chemically mechanically polishing the first polysilicon layer to a certain height, and etching a window of a semi-floating gate region on the surface of the N-well region on one side of the U-shaped groove; The first polysilicon layer is backfilled, and then P-type ion implantation is performed in the semi-floating gate region. The first polysilicon layer is chemically and mechanically polished to a certain height to form a semi-floating gate.

3. The method for preparing a semi-floating gate transistor with a stable threshold voltage according to claim 1, characterized in that: The separation gate dielectric layer includes an oxide layer and a silicon nitride layer, and the separation gate is N-type polysilicon.

4. The method for preparing a semi-floating gate transistor with a stable threshold voltage according to claim 3, characterized in that: The steps of forming a separation gate dielectric layer and a separation gate include: Depositing a third silicon oxide layer and a third silicon nitride layer to form a separation gate dielectric layer so as to cover the surface of the N-well region and the second silicon nitride layer; Then, a third polysilicon layer is deposited to cover the separation gate dielectric layer and fill the separation gate region; Perform edge etching to expose the surface of part of the N-well region on both sides, and simultaneously etch and remove part of the third polysilicon layer and the separation gate dielectric layer to expose part of the second silicon nitride layer; N-type ion implantation is performed on the third polysilicon layer to form an independent separation gate.

5. The method for preparing a semi-floating gate transistor with a stable threshold voltage according to claim 1, characterized in that: The separation gate dielectric layer includes an oxide layer and a high-K dielectric layer, and the separation gate is metal.

6. A semi-floating gate transistor with a stable threshold voltage, characterized in that: include: A substrate having a P-well region, an N-well region and a U-shaped groove, wherein the N-well region is located above the P-well region and the U-shaped groove runs through the N-well region; The channel of the semi-floating gate transistor is closely attached to the bottom of the U-shaped groove and is formed by performing a P-type impurity channel threshold adjustment injection so that the influence of the channel threshold adjustment injection on the device threshold voltage plays a dominant role; A first gate oxide layer is formed on the surface of the U-shaped groove and extends to cover a portion of the surface of the N-well region, and a window is formed on one side; a semi-floating gate covers the first gate oxide layer and completely fills the U-shaped groove, and contacts the N-well region at the window; a channel of the semi-floating gate transistor is closely attached to the bottom of the U-shaped groove; A control gate dielectric layer, a control gate and a second silicon nitride layer are sequentially formed on the semi-floating gate; A separation gate dielectric layer and a separation gate, wherein the separation gate dielectric layer covers the channel region of the tunneling transistor and extends to cover a portion of the second silicon nitride layer, and the separation gate covers the separation gate dielectric layer and fills the separation gate region; The source region and the drain region are formed in the N-well regions on both sides respectively.

7. The semi-floating gate transistor with a stable threshold voltage according to claim 6, characterized in that: The separation gate dielectric layer includes an oxide layer and a silicon nitride layer, and the separation gate is N-type polysilicon.

8. The semi-floating gate transistor with a stable threshold voltage according to claim 6, characterized in that: The separation gate dielectric layer includes an oxide layer and a high-K dielectric layer, and the separation gate is metal.

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