A multi-layer stacked memory packaging method and packaging structure

Abstract

The application provides a multi-layer stacked memory packaging method and packaging structure, which comprises the following steps: providing a buffer chip, a plurality of false tablets and a plurality of first memory chips, the false tablet is provided with a groove, the buffer chip is provided with a plurality of first conductive through holes, and the first memory chip is provided with a plurality of second conductive through holes corresponding to the plurality of first conductive through holes; fixing each first memory chip in the groove of the corresponding false tablet respectively to form a plurality of memory micro modules; and stacking the plurality of memory micro modules on the buffer chip in sequence through hybrid bonding, wherein the orthographic projection of the memory micro module on the buffer chip coincides with the buffer chip. The method adjusts the two different sizes of the first memory chip and the buffer chip to the same size through the false tablet, that is, the size of the memory micro module is the same as that of the buffer chip, wafer-level hybrid bonding can be realized, mass production can be realized, and the yield is high. The hybrid bonding is performed between every two adjacent memory micro modules, and the data throughput is improved under the same density.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor packaging, and particularly relates to a multi-layer stacked memory packaging method and packaging structure. BACKGROUND

[0002] For enterprise-level applications such as data centers, high-capacity high-speed storage is necessary. To meet this demand, high-bandwidth memory (HBM) has emerged. As shown in FIG. 1, HBM uses through silicon vias (TSVs) 12 to vertically interconnect several memory chips 11, and interacts with the outside world through a bottom buffer chip 10. Due to the high density and short vertical interconnection distance of TSVs, the data transmission speed is greatly improved. Figure 1

[0003] Currently, the multi-layer chip stacking of HBM adopts a thermal compression bonding (TCB) process. By rapidly heating, micro-bumps 14 are connected to the back pads 13 of the chips, and the back pads 13 of the chips are connected to the TSVs 12 of the chips. The composition of the micro-bumps 14 is mainly copper-tin structure, and the main component of the back pads 13 of the chips is nickel-gold structure. The final stacked structure is protected by a plastic encapsulation layer 15.

[0004] In the case of using copper-tin micro-bumps, due to the deformation of tin during reflow, in order to prevent short circuit between micro-bumps, the spacing between micro-bumps and the height of tin need to be strictly controlled. Currently, the spacing is more than 40 um. When the spacing is reduced to less than 25 um, due to the small amount of tin, it is fully converted to intermetallic compound under thermal load conditions, resulting in reliability failure.

[0005] In view of the above problems, it is necessary to provide a multi-layer stacked memory packaging method and packaging structure which is reasonable in design and can effectively solve the above problems. SUMMARY

[0006] The present application aims to at least solve one of the technical problems existing in the prior art, and provides a multi-layer stacked memory packaging method and packaging structure.

[0007] One aspect of the present application provides a multi-layer stacked memory packaging method, which comprises:

[0008] A buffer chip, a plurality of dummy chips and a plurality of first memory chips are provided, the dummy chips are provided with a groove, the buffer chip is provided with a plurality of first conductive vias, and the first memory chips are provided with a plurality of second conductive vias corresponding to the plurality of first conductive vias;

[0009] ​respectively fixing each of the first memory chips in the corresponding groove of the dummy wafer to form a plurality of memory micro-modules;

[0010] sequentially hybrid bonding and stacking the plurality of memory micro-modules on the buffer chip, wherein a normal projection of the memory micro-module on the buffer chip coincides with the buffer chip.

[0011] Optionally, a first surface of the first memory chip is provided with a first passivation layer and a first metal pad, and a second surface of the first memory chip is provided with a second passivation layer and a second metal pad.

[0012] The respectively fixing each of the first memory chips in the corresponding groove of the dummy wafer to form a plurality of memory micro-modules comprises:

[0013] forming a first adhesive between the groove bottom wall and the first surface of the first memory chip to fix the first memory chip in the groove;

[0014] forming a second adhesive between the dummy wafer and the second surface of the first memory chip, and allowing part of the second adhesive to fill into a gap between the groove side wall and the first memory chip;

[0015] removing the second adhesive of the second surface of the first memory chip to expose the second passivation layer and the second metal pad;

[0016] removing the first adhesive of the first surface of the first memory chip to expose the first passivation layer and the first metal pad, to form the memory micro-module.

[0017] Optionally, the removing the second adhesive of the second surface of the first memory chip to expose the second passivation layer and the second metal pad comprises:

[0018] polishing and chemically cleaning the dummy wafer and the second surface of the first memory chip to completely remove the second adhesive of the second surface of the first memory chip, while retaining part of the second adhesive on the surface of the dummy wafer.

[0019] Optionally, a side of the buffer chip facing the memory micro-module is provided with a third passivation layer and a third metal pad,

[0020] The sequentially hybrid bonding and stacking the plurality of memory micro-modules on the buffer chip comprises:

[0021] bonding a second passivation layer of a first layer of memory micro-modules to a third passivation layer on the buffer chip, and bonding a second metal pad of the first layer of memory micro-modules to a third metal pad on the buffer chip;

[0022] sequentially stacking the remaining layers of memory micro-modules on the first layer of memory micro-modules, wherein the first passivation layer of each adjacent two layers of memory micro-modules is bonded to the second passivation layer, and the first metal pad of each adjacent two layers of memory micro-modules is bonded to the second metal pad.

[0023] Optionally, after the plurality of memory micro-modules are sequentially mixed and bonded to the buffer chip, the method further comprises:

[0024] forming a plurality of bumps on a surface of the buffer chip facing away from the memory micro-modules, the plurality of bumps corresponding to the plurality of first conductive vias.

[0025] Another aspect of the present application provides a multi-layer stacked memory package structure, comprising a buffer chip and a plurality of memory micro-modules;

[0026] The buffer chip is provided with a plurality of first conductive vias;

[0027] The plurality of memory micro-modules are sequentially stacked on the buffer chip, and the memory micro-modules are in the same projection as the buffer chip; wherein,

[0028] Each of the memory micro-modules comprises a dummy wafer and a first memory chip, the dummy wafer is provided with a slot, the slot is provided with the first memory chip, and the first memory chip is provided with a plurality of second conductive vias corresponding to and electrically connected to the plurality of first conductive vias.

[0029] Optionally, the first memory chip is provided with a first passivation layer and a first metal pad on a first surface facing away from the buffer chip, and is provided with a second passivation layer and a second metal pad on a second surface facing the buffer chip;

[0030] The first passivation layer of each adjacent two layers of memory micro-modules is bonded to the second passivation layer, and the first metal pad of each adjacent two layers of memory micro-modules is bonded to the second metal pad.

[0031] The first metal pad of each adjacent two layers of memory micro-modules is bonded to the second metal pad.

[0032] Optionally, the buffer chip is provided with a third passivation layer and a third metal pad on a surface facing the memory micro-modules;

[0033] The third passivation layer is bonded to the second passivation layer in the first layer of memory micro-module, and the third metal pad is bonded to the second metal pad in the first layer of memory micro-module.

[0034] Optionally, an adhesive is arranged between the two adjacent pseudo tablets and between the groove sidewall and the first memory chip.

[0035] Optionally, a plurality of bumps are arranged on the surface of the buffer chip away from the memory micro-module, and the plurality of bumps correspond to the plurality of first conductive vias.

[0036] The present application provides a multi-layer stacked memory packaging method and packaging structure. In the packaging method, each first memory chip is fixed in the corresponding groove of the pseudo tablet to form a plurality of memory micro-modules. The plurality of memory micro-modules are sequentially mixed and bonded on the buffer chip, wherein the orthographic projection of the memory micro-module on the buffer chip coincides with the buffer chip. The present application adjusts the two different sizes of the first memory chip and the buffer chip to the same size through the pseudo tablet, i.e., the size of the memory micro-module and the buffer chip is the same, which can realize wafer-level mixed bonding. The efficiency of mixed bonding is greatly improved compared with single-chip bonding, which realizes mass production and high yield. In addition, the mixed bonding is also performed between each adjacent two memory micro-modules, which can realize a smaller pitch, increase the number of vertical interconnections under the same density, and increase the number of data channels to improve data throughput. The packaging structure of the present application realizes ultra-fine pitch interconnection through the mixed bonding between each adjacent two memory micro-modules and the mixed bonding between the memory micro-module and the buffer chip, greatly improves the output efficiency, and reduces the production cost. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 A structural schematic diagram of a typical conventional multi-layer memory packaging structure of the prior art;

[0038] Figure 2 A flowchart of a multi-layer stacked memory packaging method according to an embodiment of the present application;

[0039] Figures 3 to 10 A packaging process schematic diagram of a multi-layer stacked memory packaging method according to another embodiment of the present application. DETAILED DESCRIPTION

[0040] In order for those skilled in the art to better understand the technical solutions of the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0041] As shown in the drawings, Figure 2 An aspect of the present application provides a multi-layer stacked memory packaging method S100, which comprises:

[0042] S110. A buffer chip, multiple dummy chips, and multiple first memory chips are provided. The dummy chips are provided with a slot, the buffer chips are provided with multiple first conductive vias, and the first memory chips are provided with multiple second conductive vias corresponding to the multiple first conductive vias.

[0043] Specifically, such as Figure 10 As shown, a buffer chip 110, multiple dummy chips 120, and multiple memory chips 130 are provided. The dummy chips 120 have grooves (not shown in the figure). The buffer chip 110 has multiple conductive vias 111. The first memory chip 130 has multiple second conductive vias 131 corresponding to the first conductive vias 111. Both the first conductive vias 111 and the second conductive vias 131 can be through-silicon vias (TSVs). Using TSV technology to achieve vertical electrical interconnection of TSVs reduces the package height.

[0044] S120. Each of the first memory chips is fixed in the slot of the corresponding dummy chip to form a plurality of memory micro-modules.

[0045] Specifically, such as Figure 3 As shown, each first memory chip 130 is fixed in the slot of the corresponding dummy chip 120 to form multiple memory micro-modules 140. It should be noted that the size of the slot is slightly larger than the size of the first memory chip 130, and the depth of the slot is less than the height of the first memory chip 130. That is to say, the surface of the first memory chip 130 protrudes from the surface of the dummy chip 120.

[0046] For example, such as Figure 3 As shown, a first passivation layer 132 and a first metal pad 133 are disposed on the first surface of the first memory chip 130, and a second passivation layer 134 and a second metal pad 135 are disposed on the second surface of the first memory chip 130. In this embodiment, the first surface of the first memory chip 130 is the back side, and the second surface of the first memory chip 130 is the front side. It should be noted that in this embodiment, the materials of the first passivation layer 132 and the second passivation layer 134 can both be silicon dioxide or silicon nitride, and the first metal pad 133 and the second metal pad 135 can be copper pads.

[0047] Each of the first memory chips is fixed in the slot of the corresponding dummy chip to form multiple memory micro-modules, and the process further includes the following steps:

[0048] First, a first adhesive is formed between the bottom wall of the tank and the first surface of the first memory chip to fix the first memory chip in the tank.

[0049] Specifically, such as Figure 3 As shown, a first adhesive 150 is formed between the bottom wall of the tank and the back of the first memory chip 130. The first adhesive 150 is pressed onto the bottom wall of the tank to fix the first memory chip 130 in the tank.

[0050] Secondly, a second adhesive is formed on the surface of the dummy chip and the second surface of the first memory chip, and a portion of the second adhesive fills the gap between the sidewall of the tank and the first memory chip.

[0051] Specifically, such as Figure 4 As shown, a second adhesive 160 is formed on the surface of the dummy chip 120 and the front side of the first memory chip 130, and a portion of the second adhesive 160 fills the gap between the side wall of the tank and the first memory chip 130, further fixing the first memory chip 130 in the tank.

[0052] Next, the second adhesive on the second surface of the first memory chip is removed to expose the second passivation layer and the second metal pad.

[0053] Specifically, such as Figure 5 As shown, the second surfaces of the dummy die 120 and the first memory chip 130 are polished and chemically cleaned to completely remove the second adhesive 160 from the second surface of the first memory chip 130, exposing the second passivation layer 134 and the second metal pad 135. Simultaneously, a portion of the second adhesive 160 on the surface of the dummy die 120 is retained; in this embodiment, the retained second adhesive 160 on the surface of the dummy die 120 is flush with the second passivation layer.

[0054] Finally, the first adhesive on the first surface of the first memory chip is removed to expose the first passivation layer and the first metal pad, forming the memory micromodule.

[0055] Specifically, such as Figure 6 As shown, the side of the dummy chip 120 away from the first memory chip 130, that is, the back side of the dummy chip 120, is ground and polished to remove the silicon on the back side of the dummy chip 120 and the first adhesive 150 on the first surface of the first memory chip 130. In other words, the back side of the dummy chip 120 is thinned to completely expose the first passivation layer 132 and the first metal pad 133 to form a memory micromodule 140.

[0056] S130. Multiple memory micro-modules are sequentially mixed, bonded, and stacked on the buffer chip, wherein the orthographic projection of the memory micro-modules on the buffer chip coincides with the buffer chip.

[0057] Specifically, such as Figure 7As shown, the buffer chip 110 is provided with a third passivation layer 112 and a third metal pad 113 on one side facing the memory micro-module 140. In this embodiment, the third passivation layer 112 can be silicon dioxide or silicon nitride, and the third metal pad 113 can be a copper pad.

[0058] The plurality of memory micro-modules are sequentially mixedly bonded and stacked on the buffer chip, specifically including the following steps:

[0059] First, the second passivation layer of the first layer of memory micro-modules is bonded with the third passivation layer on the buffer chip, and the second metal pad of the first layer of memory micro-modules is bonded with the third metal pad on the buffer chip.

[0060] Specifically, as shown in Figure 7 and Figure 8 The second passivation layer 134 of the first layer of memory micro-modules 141 is mixedly bonded with the third passivation layer 112 on the buffer chip 110 by heating and pressing, and the second metal pad 135 of the first layer of memory micro-modules 140 is aligned with the third metal pad 113 on the buffer chip 110, and the bonding is achieved by the thermal expansion of copper through high-temperature pressing. The second adhesive 160 reserved on the surface of the dummy sheet 120 in the first layer of memory micro-modules 141 can paste the first layer of memory micro-modules 141 on the buffer chip 110.

[0061] Secondly, the remaining layers of memory micro-modules are sequentially mixedly bonded and stacked on the first layer of memory micro-modules, wherein the first passivation layer of each adjacent two layers of memory micro-modules is bonded with the second passivation layer, and the first metal pad of each adjacent two layers of memory micro-modules is bonded with the second metal pad.

[0062] Specifically, as shown in Figure 8 The remaining layers of memory micro-modules 142 are sequentially mixedly bonded and stacked on the first layer of memory micro-modules 141, wherein the first passivation layer 132 of one of each adjacent two layers of memory micro-modules 140 is mixedly bonded with the second passivation layer 134 of the other under the condition of heating and pressing, and the first metal pad 133 of one of each adjacent two layers of memory micro-modules 140 is mixedly bonded with the second metal pad 135 of the other under the condition of heating and pressing.

[0063] That is, as shown in Figure 9As shown, the first layer of memory micro-modules 141 is mixedly bonded with the buffer chip 110, the second layer of memory micro-modules is arranged on the first layer of memory micro-modules and mixedly bonded with the first layer of memory micro-modules 141, the third layer of memory micro-modules is arranged on the second layer of memory micro-modules and mixedly bonded with the second layer of memory micro-modules, and so on, and each layer of memory micro-modules is sequentially mixedly bonded and stacked on the buffer chip 110.

[0064] As shown in FIG. 1, the first memory chip 130 is mixedly bonded with the buffer chip 110, and the second memory chip 130 is arranged on the first memory chip 130 and mixedly bonded with the first memory chip 130. Figure 10 As shown in FIG. 1, the first memory chip 130 is mixedly bonded with the buffer chip 110, and the second memory chip 130 is arranged on the first memory chip 130 and mixedly bonded with the first memory chip 130.

[0065] As shown in FIG. 1, the first memory chip 130 is mixedly bonded with the buffer chip 110, and the second memory chip 130 is arranged on the first memory chip 130 and mixedly bonded with the first memory chip 130. Figure 7 、 Figure 8 、 Figure 9 and Figure 10 As shown in FIG. 1, the first memory chip 130 is mixedly bonded with the buffer chip 110, and the second memory chip 130 is arranged on the first memory chip 130 and mixedly bonded with the first memory chip 130.

[0066] As shown in FIG. 1, the first memory chip 130 is mixedly bonded with the buffer chip 110, and the second memory chip 130 is arranged on the first memory chip 130 and mixedly bonded with the first memory chip 130. Figure 10 As shown in FIG. 1, the first memory chip 130 is mixedly bonded with the buffer chip 110, and the second memory chip 130 is arranged on the first memory chip 130 and mixedly bonded with the first memory chip 130.

[0067] A plurality of bumps are formed on the surface of the buffer chip away from the memory micro-module, and the plurality of bumps correspond to the plurality of first conductive vias.

[0068] As shown in FIG. 1, the first memory chip 130 is mixedly bonded with the buffer chip 110, and the second memory chip 130 is arranged on the first memory chip 130 and mixedly bonded with the first memory chip 130. Figure 10 As shown in FIG. 1, the first memory chip 130 is mixedly bonded with the buffer chip 110, and the second memory chip 130 is arranged on the first memory chip 130 and mixedly bonded with the first memory chip 130.

[0069] After forming the plurality of bumps 170, cutting is performed to form a plurality of independent memory package structures.

[0070] The application provides a multi-layer stacked memory packaging method, each first memory chip is fixed in a corresponding slot of a dummy wafer to form a plurality of memory micro-modules, and the plurality of memory micro-modules are sequentially mixed and bonded on a buffer chip, wherein a projection of the memory micro-module on the buffer chip coincides with the buffer chip. The first memory chip and the buffer chip of two different sizes are adjusted to the same size by the dummy wafer, that is, the size of the memory micro-module and the buffer chip is adjusted to be the same, wafer-level mixed bonding can be realized, the efficiency of mixed bonding is greatly improved compared with single-chip bonding, mass production is realized, and the yield is high. In addition, mixed bonding is also performed between each adjacent two memory micro-modules, a smaller pitch can be realized, the number of vertical interconnections is increased under the same density, and the number of data channels is increased, so that the data throughput is improved.

[0071] As shown in Figure 10 Another aspect of the application provides a multi-layer stacked memory packaging structure 100, which comprises a buffer chip 110 and a plurality of memory micro-modules 140.

[0072] The buffer chip 110 is provided with a plurality of first conductive vias 111.

[0073] The plurality of memory micro-modules 140 are sequentially stacked on the buffer chip 110, and the projection of the memory micro-module 140 on the buffer chip 110 coincides with the buffer chip 110; wherein,

[0074] Each memory micro-module 140 comprises a dummy wafer 120 and a first memory chip 130, the dummy wafer 120 is provided with a slot, the slot is provided with the first memory chip 130, and the first memory chip 130 is provided with a plurality of second conductive vias 131 corresponding to and electrically connected to the plurality of first conductive vias 111.

[0075] As shown in Figure 10 The first surface of the first memory chip 130 away from the buffer chip 110 is provided with a first passivation layer 132 and a first metal pad 133, and the second surface of the first memory chip 130 towards the buffer chip is provided with a second passivation layer 134 and a second metal pad 135.

[0076] The first passivation layer 132 and the second passivation layer 134 in each adjacent two layers of memory micro-modules 140 are bonded and connected; and,

[0077] The first metal pad 133 and the second metal pad 135 in each adjacent two layers of memory micro-modules 140 are bonded and connected.

[0078] It should be noted that in the embodiment, the material of the first passivation layer 132 and the second passivation layer 134 can be silicon dioxide material or silicon nitride material, and the first metal pad 133 and the second metal pad 135 can be copper pads.

[0079] As shown in the figure, the buffer chip 110 is provided with a third passivation layer 112 and a third metal pad 113 on the surface facing the memory micro module 140. Figure 10

[0080] The third passivation layer 112 is bonded to the second passivation layer 134 in the first layer memory micro module 141, and the third metal pad 113 is bonded to the second metal pad 135 in the first layer memory micro module 141.

[0081] It should be noted that in the embodiment, the material of the third passivation layer 112 can be silicon dioxide material or silicon nitride material, and the third metal pad 113 can be a copper pad.

[0082] As shown in the figure, the buffer chip 110 is provided with a third passivation layer 112 and a third metal pad 113 on the surface facing the memory micro module 140. Figure 10

[0083] As shown in the figure, the buffer chip 110 is provided with a third passivation layer 112 and a third metal pad 113 on the surface facing the memory micro module 140. ​ In the embodiment, the bump 170 can be a copper-tin bump.

[0084] The packaging structure of the present application realizes the interconnection of ultra-fine pitch through the mixed bonding between each adjacent two memory micro modules and the mixed bonding between the memory micro module and the buffer chip, greatly improves the output efficiency, and reduces the production cost. By adjusting the two first memory chips of different sizes and the buffer chip to the same size through the dummy chip, i.e., the size of the memory micro module and the buffer chip is the same, wafer-level mixed bonding can be realized, and the efficiency of mixed bonding is greatly improved compared with single-chip bonding, which realizes mass production and high yield.

[0085] It can be understood that the above embodiments are only exemplary embodiments for illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and essence of the present application, and these modifications and improvements are also considered as the protection scope of the present application.​​

Claims

1. A method of multi-tier stacked memory packaging, the method comprising: The method comprises: providing a buffer chip, a plurality of dummy chips and a plurality of first memory chips, the dummy chips are provided with a plurality of grooves, the buffer chip is provided with a plurality of first conductive vias, and the first memory chips are provided with a plurality of second conductive vias corresponding to the plurality of first conductive vias; fixing each of the first memory chips in the groove of the corresponding dummy chip respectively, so as to adjust the two different sizes of the first memory chips and the buffer chip to the same size through the dummy chip, and form a plurality of memory micro-modules, wherein the surface of the first memory chip protrudes from the surface of the dummy chip; stacking the plurality of memory micro-modules on the buffer chip in sequence through wafer-level hybrid bonding, wherein the orthographic projection of the memory micro-module on the buffer chip coincides with the buffer chip.

2. The method of claim 1, wherein, The first surface of the first memory chip is provided with a first passivation layer and a first metal pad, and the second surface of the first memory chip is provided with a second passivation layer and a second metal pad; The fixing of each of the first memory chips in the groove of the corresponding dummy chip to form a plurality of memory micro-modules comprises: forming a first adhesive between the groove bottom wall and the first surface of the first memory chip to fix the first memory chip in the groove; forming a second adhesive on the dummy chip and the second surface of the first memory chip, and allowing part of the second adhesive to fill into the gap between the groove side wall and the first memory chip; removing the second adhesive on the second surface of the first memory chip to expose the second passivation layer and the second metal pad; removing the first adhesive on the first surface of the first memory chip to expose the first passivation layer and the first metal pad, and forming the memory micro-module.

3. The method of claim 2, wherein, The removing of the second adhesive on the second surface of the first memory chip to expose the second passivation layer and the second metal pad comprises: polishing and chemically cleaning the dummy chip and the second surface of the first memory chip to completely remove the second adhesive on the second surface of the first memory chip, while retaining part of the second adhesive on the surface of the dummy chip.

4. The method of claim 2, wherein, The side of the buffer chip facing the memory micro-module is provided with a third passivation layer and a third metal pad; The stacking of the plurality of memory micro-modules on the buffer chip in sequence through wafer-level hybrid bonding comprises: bonding the second passivation layer of a first layer of memory micro-modules with the third passivation layer on the buffer chip, and bonding the second metal pad of the first layer of memory micro-modules with the third metal pad on the buffer chip; sequentially stacking the remaining layers of memory micro-modules on the first layer of memory micro-modules through wafer-level hybrid bonding, wherein the first passivation layer and the second passivation layer in each adjacent two layers of memory micro-modules are bonded, and the first metal pad and the second metal pad in each adjacent two layers of memory micro-modules are bonded.

5. The method of claim 1, wherein, After the plurality of memory micro-modules are sequentially wafer-level mixedly bonded and stacked on the buffer chip, the method further comprises: forming a plurality of bumps on a surface of the buffer chip away from the memory micro-modules, the plurality of bumps corresponding to the plurality of first conductive vias.

6. A multi-tier stacked memory package structure, comprising: comprising a buffer chip and a plurality of memory micro-modules; the buffer chip is provided with a plurality of first conductive vias; the plurality of memory micro-modules are sequentially wafer-level mixedly bonded and stacked on the buffer chip, and the memory micro-modules are in the same size as the buffer chip in orthographic projection; each of the memory micro-modules comprises a dummy wafer and a first memory chip, the dummy wafer is provided with a groove, the groove is provided with the first memory chip, the dummy wafer is used to adjust two different sizes of the first memory chip and the buffer chip to the same size, and the first memory chip is provided with a plurality of second conductive vias corresponding to and electrically connected to the plurality of first conductive vias.

7. The package structure of claim 6, wherein, the first surface of the first memory chip away from the buffer chip is provided with a first passivation layer and a first metal pad, and the second surface of the first memory chip toward the buffer chip is provided with a second passivation layer and a second metal pad; the first passivation layer and the second passivation layer in each of the two adjacent layers of memory micro-modules are bonded and connected; and the first metal pad and the second metal pad in each of the two adjacent layers of memory micro-modules are bonded and connected.

8. The package structure of claim 7, wherein, the surface of the buffer chip toward the memory micro-modules is provided with a third passivation layer and a third metal pad; the third passivation layer is bonded and connected with the second passivation layer in the first layer of memory micro-modules, and the third metal pad is bonded and connected with the second metal pad in the first layer of memory micro-modules.

9. The package structure of any one of claims 6 to 8, wherein, adhesive is further provided between the two adjacent dummy wafers and between the groove sidewall and the first memory chip.

10. The package structure of any one of claims 6 to 8, wherein, the surface of the buffer chip away from the memory micro-modules is provided with a plurality of bumps, the plurality of bumps corresponding to the plurality of first conductive vias.

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