A method for interconnecting detachable bit-width DDR modules based on SiP stacking structure

Abstract

The present invention discloses a method for interconnecting a detachable bit-width DDR module based on a SiP stacking structure, comprising a SiP stacking module, wherein m chips inside the SiP stacking module are split into n groups of DDR subsystems, the bit width w1 of each group of DDR subsystems being w*m / n, where n is a positive integer greater than 1 and a divisor of m, and w is the bit width of the chip; within each group of DDR subsystems, the data lines of the m / n chips are directly connected to a substrate point-to-point, and each data signal is directly led out to a module package ball; within each group of DDR subsystems, the address signals, control signals, and clock signals of the m / n chips are interconnected with the substrate in a T-type or flyby topology and are led out to a package ball in groups; the n groups of DDR subsystems are interconnected at the application level with a controller on a system application board, and terminal matching resistors are placed at signal terminals depending on the bit-width interconnection situation, and the terminal matching resistors are placed on the system application board.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor memory chips, and in particular to a method for interconnecting detachable bit-width DDR modules based on a SiP stacking structure. Background Art

[0002] The rapid development of electronic equipment has placed higher demands on system-level packaging technology. Traditional tiled SiP chips are gradually being replaced by three-dimensional stacked SiP chips, enabling the development of chips with smaller size, higher reliability, and higher performance. As semiconductor memory chips are essential components of processors and FPGA peripherals, multi-memory chip packaging technology has emerged.

[0003] At present, taking high-speed DDR SDRAM as an example, 3D plus, Zhuhai Orbit, 771 Institute and other units have released 32-bit or 64-bit DDR3 module products, but the data bit width cannot be split and is mostly tiled, which is relatively large in size. The application number is 202110140717.6, and the invention name is: A patent application for a staggered stacked DDR module and a thermal analysis method thereof. It proposes a staggered stacking method and a corresponding heat dissipation analysis method, but does not describe the interconnection design method. Therefore, it is urgently necessary to adopt multi-chip three-dimensional stacking interconnection technology to design the DDR module into a flexible and variable bit width miniaturized storage component. Summary of the Invention

[0004] The present invention proposes a method for interconnecting DDR modules with a splittable bit width based on a SiP stacking structure, and the technical solution adopted is as follows:

[0005] A method for interconnecting a detachable bit-width DDR module based on a SiP stacking structure includes a SiP stacking module, wherein m chips within the SiP stacking module are split into n groups of DDR subsystems, the bit width w1 of each DDR subsystem being w*m / n, where n is a positive integer greater than 1 and a divisor of m, and w is the bit width of the chip; within each group of DDR subsystems, the data lines of the m / n chips are directly connected to a substrate point-to-point, and each data signal is directly led out to a module package ball; within each group of DDR subsystems, the address signals, control signals, and clock signals of the m / n chips are interconnected with the substrate in a T-type or flyby topology and led out to a package ball in groups; the n groups of DDR subsystems lead out n groups of address signals, n groups of control signals, and n groups of clock signals on the package ball; and the n groups of DDR subsystems lead out n groups of power supply signals on the package ball; the n groups of DDR subsystems achieve application-level interconnection with a controller on a system application board, and terminal matching resistors are placed at signal terminals depending on the bit-width interconnection situation, and the terminal matching resistors are placed on the system application board.

[0006] In the preferred embodiment of the technical solution of the present invention, when the DDR subsystem adopts the split bit width mode in the system application, n DDR subsystems need to place n groups of terminal matching resistors at the signal end.

[0007] In the preferred embodiment of the technical solution of the present invention, the DDR subsystem adopts a cascaded bit width mode in system application, and after n DDR subsystems are cascaded, a corresponding set of terminal matching resistors needs to be placed at the signal end.

[0008] Preferably, the SiP stack module includes m DDR bare cores, a DDR module substrate and a packaging cavity. The m DDR bare cores are stacked, and the stacked structure of the m DDR bare cores is configured on a DDR module substrate. The m DDR bare cores are interconnected with the DDR module substrate and packaged in a packaging cavity.

[0009] Preferably, the stacking structure of the m DDR bare cores is a vertical stacking structure, a left-right staggered stacking structure, or a cross stacking structure.

[0010] In a preferred embodiment of the technical solution of the present invention, the interconnection method between the m DDR bare cores and the DDR module substrate adopts but is not limited to WireBond bonding.

[0011] In a preferred embodiment of the technical solution of the present invention, m DDR bare cores use RDL preprocessing to lead PAD signals to one side or both sides of the bare core.

[0012] Preferably, the system application board is a system PCB board or substrate.

[0013] The beneficial effects of the present invention compared with the prior art are:

[0014] Compared with the existing DDR module that interconnects all DDR bare cores as a whole, the advantage of the design method of this invention is that one module is divided into several DDR subsystems for interconnection design. The stacking structure refers to but is not limited to an interleaved stacking or a TSV process stacking structure. On the one hand, this invention solves the problem of non-divisible bit width. While retaining the functions of the existing DDR module, the high-bit-width DDR module can be split into multiple small modules with low bit-width for use, thereby increasing user flexibility. On the other hand, the terminal matching resistor does not need to be placed inside the DDR module in an IPD array or discrete form, but is placed on the PCB board, thereby reducing the difficulty of substrate topology design caused by the stacking structure, reducing the substrate production cost, and improving the signal integrity performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 FIG. 1 is a schematic diagram of a stacking structure 1 of a 64-bit DDR module according to an embodiment.

[0016] Figure 2 FIG. 1 is a schematic diagram of a second stacking structure of a 64-bit DDR module according to an embodiment.

[0017] Figure 3 FIG. 4 is a schematic diagram of a stacking structure 3 of a 64-bit DDR module according to an embodiment.

[0018] Figure 4 FIG. 4 is a schematic diagram of a stacking structure of a 64-bit DDR module according to an embodiment.

[0019] Figure 5 Schematic diagram of the signal lead-out structure of the 64-bit DDR module interconnection structure of the embodiment.

[0020] Figure 6 Schematic diagram of the address line interconnection structure corresponding to splitting a 64-bit DDR module into two 32-bit systems when m=4 and n=2 in the embodiment.

[0021] Figure 7 Schematic diagram of the data line interconnection structure corresponding to splitting a 64-bit DDR module into two 32-bit systems when m=4 and n=2 in the embodiment.

[0022] Figure 8 Schematic diagram of the address line interconnection structure corresponding to a 64-bit DDR module cascaded to a 64-bit system when m=4 and n=2 in the embodiment.

[0023] Figure 9 Schematic diagram of the data line interconnection structure corresponding to a 64-bit DDR module cascaded to a 64-bit system when m=4 and n=2 in an embodiment. DETAILED DESCRIPTION

[0024] The technical solution of the present invention is described in detail below, but the protection scope of the present invention is not limited to the embodiments.

[0025] In order to make the content of the present invention more clear and easy to understand, the following Figures 1-9 The specific implementation methods are further described.

[0026] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0027] The specific implementation of this embodiment is a proposed method for interconnecting DDR modules with a detachable bit width based on a SiP stacking structure, including a SiP stacking module, wherein the m chips inside the SiP stacking module are split into n groups of DDR subsystems, and the bit width w1 of each group of DDR subsystems is w*m / n, where n is a positive integer greater than 1 and a divisor of m, and w is the bit width of the chip; within each group of DDR subsystems, the data lines of the m / n chips are directly connected to the substrate to achieve point-to-point connection, and each data signal is directly led out to the module package ball .... The address signals, control signals and clock signals of m / n chips are interconnected with the substrate in a T-type or flyby topology and are led out to the package ball in groups; n groups of DDR subsystems lead out n groups of address signals, n groups of control signals and n groups of clock signals on the package ball; and n groups of DDR subsystems lead out n groups of power supply signals on the package ball; n groups of DDR subsystems realize application-level interconnection with the controller on the system application board, and the terminal matching resistors are placed at the signal terminals depending on the bit width interconnection situation, and the terminal matching resistors are placed on the system application board.

[0028] like Figure 1 、 2 As shown in Figures 3 and 4, the SiP stack module includes m DDR bare cores, a DDR module substrate, and a packaging cavity. The m DDR bare cores are stacked, and the stacked structure of the m DDR bare cores is configured on a DDR module substrate. The m DDR bare cores are interconnected with the DDR module substrate and packaged in a packaging cavity. The interconnection method between the m DDR bare cores and the DDR module substrate adopts, but is not limited to, WireBond bonding. The m DDR bare cores use RDL pre-processing to lead the PAD signals to one or both sides of the bare core.

[0029] In this embodiment, in the SiP stack module, Figure 1 and 2 As shown, the DDR bare cores are stacked alternately on the left and right. After the RDL leads the pad of each DDR bare core to one side of the die, the signal is wired only from one side, without considering the wire outlet space of the spacer layer. The middle is bonded with fill glue. There are two cases: 1) Data, address, and control lines are wired point-to-point to the substrate and then the substrate interconnection design is performed, such as Figure 1 2) Data lines are all wired point-to-point to the substrate before interconnection design. The address / control lines of the higher "layer" on the same side are first wired to the bare core bump of the corresponding lower "layer" to form a flyby (daisy chain) topology and then wired to the substrate for interconnection design. Figure 2 shown.

[0030] In this embodiment, in the SiP stacking module, RDL leads the pad of each DDR bare core to both sides of the die, and the signal is wired from both sides. Figure 3As shown, the DDR bare cores are stacked vertically, with wires coming out from the left and right. The wire space between adjacent layers needs to be considered. The middle layer is bonded with gaskets, and all wires are connected to the substrate for interconnection. Figure 4 As shown, the DDR bare cores are stacked crosswise, with wires coming out from the left, right, front, and back of the DDR bare cores. In this structure, only the wire space of the spacer layer needs to be considered, and the middle is bonded with fill glue.

[0031] like Figure 1 、 2 , 3 and 4, in this embodiment, the three-dimensional stacking signal interconnection process is mainly divided into two types: WireBond wire bonding (gold wire bonding) and TSV silicon transfer substrate interconnection. At the same time, the stacking structure in the SiP stacking module can be but not limited to left and right staggered stacking ( Figure 1 and 2 ), direct vertical stacking ( Figure 3 ) and cross stacking ( Figure 4 It should be noted that the three-dimensional stacked signal interconnection process mentioned in this embodiment is known to those skilled in the art.

[0032] like Figure 5 As shown, in this embodiment, taking a 64-bit DDR module as an example, the design takes into account the application scenario of splitting into two 32-bit DDR modules, that is, the two modules are designed to have independent data, address, and control lines. Die1 and Die3 are a group, outputting A[14:0], D[31:0], etc., and Die2 and Die4 are a group, outputting A'[14:0], D'[31:0], etc.

[0033] In this embodiment, the system application board is a system PCB board or substrate. When the DDR subsystem adopts the split-width mode in the system application, n DDR subsystems need to place n sets of terminal matching resistors at the signal end.

[0034] like Figure 6 and 7 As shown, the DDR subsystem adopts the split bit width mode in system application. For example, a 64-bit DDR module with m=4 and n=2 is split into two 32-bit subsystems, which is further explained as follows: the system application board when split application.

[0035] like Figure 6 As shown in the figure, taking the address line application as an example, when the system uses two 32-bit controllers (controller 1 and controller 2), the address line A[14:0] of controller 1 is connected to the A[14:0] of the module on the system application board, and the terminal matching resistors are placed at each end of A[14:0]. The A[14:0] of controller 2 is connected to the A'[14:0] of the module, and the terminal matching resistors are placed at each end of A'[14:0].

[0036] like Figure 7As shown in the figure, taking the data line application as an example, when the system uses two 32-bit controllers (controller 1 and controller 2), the data line D[31:0] of controller 1 is connected to the D[31:0] of the module on the system application board, and the D[31:0] of controller 2 is connected to the D'[31:0] of the module.

[0037] In this embodiment, the system application board is a system PCB board or substrate. When the DDR subsystem adopts the cascaded bit width mode in the system application, a corresponding set of terminal matching resistors needs to be placed at the signal end after n DDR subsystems are cascaded.

[0038] like Figure 8 and 9 As shown, the DDR subsystem adopts the cascade bit width mode in system application. For example, a 64-bit DDR module with m=4 and n=2 is cascaded to form a 64-bit system. Further explanation: the system application board in cascade application.

[0039] like Figure 8 As shown in the figure, taking the address line application as an example, when the system uses a 64-bit controller, the controller's address lines A[14:0], module A[14:0], and A'[14:0] are interconnected on the system application board through a flyby topology, and the terminal matching resistor is placed at the end of A'[14:0].

[0040] like Figure 9 As shown, taking data line application as an example, when the system uses a 64-bit controller, the controller's data line D[31:0] is connected to the module's D[31:0] through a point-to-point topology on the system application board, and the controller's D[63:32] is connected to the module's D'[31:0].

[0041] The above embodiments are only for illustrating the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A method for interconnecting detachable bit-width DDR modules based on a SiP stacking structure, comprising a SiP stacking module, characterized in that: The m chips inside the SiP stack module are divided into n groups of DDR subsystems. The bit width w1 of each DDR subsystem is w*m / n, where n is a positive integer greater than 1 and a divisor of m, and w is the bit width of the chip. In each group of DDR subsystems, the data lines of the m / n chips are directly connected to the substrate point-to-point, and each data signal is directly led out to the module package ball. In each group of DDR subsystems, the address signals, control signals, and clock signals of the m / n chips are interconnected with the substrate in a T-type or flyby topology and are led out to the package ball in groups. n groups of DDR subsystems lead out n groups of Address signals, n groups of control signals and n groups of clock signals; and n groups of DDR subsystems lead out n groups of power supply signals on the package Ball; n groups of DDR subsystems realize application-level interconnection with the controller on the system application board, and the terminal matching resistors are placed at the signal terminals according to the bit width interconnection situation and the terminal matching resistors are placed on the system application board; when the DDR subsystem adopts the split bit width mode in the system application, then the n DDR subsystems need to place n groups of terminal matching resistors at the signal ends accordingly; when the DDR subsystem adopts the cascaded bit width mode in the system application, then after the n DDR subsystems are cascaded, one group of terminal matching resistors needs to be placed at the signal ends accordingly.

2. The method for interconnecting DDR modules with a splittable bit width based on a SiP stacking structure according to claim 1, wherein: The SiP stack module includes m DDR bare cores, a DDR module substrate and a packaging cavity. The m DDR bare cores are stacked, and the stacked structure of the m DDR bare cores is configured on a DDR module substrate. The m DDR bare cores are interconnected with the DDR module substrate and packaged in a packaging cavity.

3. The method for interconnecting DDR modules with a splittable bit width based on a SiP stacking structure according to claim 2, wherein: The stacking structure of the m DDR bare cores is a vertical stacking structure, a left-right staggered stacking structure, or a cross stacking structure.

4. The method for interconnecting DDR modules with a splittable bit width based on a SiP stacking structure according to claim 3, wherein: The interconnection method between the m DDR bare cores and the DDR module substrate adopts but is not limited to WireBond.

5. The method for interconnecting DDR modules with a splittable bit width based on a SiP stacking structure according to claim 3, wherein: The m DDR bare cores use RDL pre-processing to lead the PAD signals to one side or both sides of the bare core.

6. The method for interconnecting DDR modules with a splittable bit width based on a SiP stacking structure according to claim 1, wherein: The system application board is a system PCB board or substrate.

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