Semiconductor devices

Abstract

An embodiment provides a semiconductor device capable of suppressing poor connection between wirings. The semiconductor device of the present embodiment comprises a first chip and a second chip bonded to the first chip. The first chip comprises a substrate. A transistor is arranged on the substrate. A first wiring layer is arranged above the transistor and comprises a plurality of first wirings. A plurality of first solder pads are arranged above the first wirings. The second chip comprises a plurality of second solder pads bonded to the plurality of first solder pads. A second wiring layer is arranged above the second solder pad and comprises a plurality of second wirings. A memory cell array is arranged above the second wiring. The first wiring, the first solder pad, the second solder pad, and the second wiring constitute a first pattern connected in series.

Description

[0001] [Related applications]

[0002] This application claims priority based on Japanese Patent Application No. 2020-156722 (filing date: September 17, 2020), and the present application incorporates all the contents of the basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor device. Background Art

[0004] There is a wafer bonding technology for bonding a plurality of semiconductor wafers and joining the wirings of the plurality of semiconductor wafers to each other. In such a wafer bonding technology, if the wiring pads are recessed from the surface of the semiconductor wafer, there is a concern that poor connection between the wirings will occur. Summary of the invention

[0005] The embodiment provides a semiconductor device capable of suppressing poor connection between wirings.

[0006] The semiconductor device of this embodiment includes a first chip and a second chip bonded to the first chip. The first chip includes a substrate. A transistor is provided on the substrate. A first wiring layer is provided above the transistor and includes a plurality of first wirings. A plurality of first pads are provided above the first wirings. The second chip includes a plurality of second pads bonded to the plurality of first pads. The second wiring layer is provided above the second pads and includes a plurality of second wirings. A memory cell array is provided above the second wirings. The first wirings, the first pads, the second pads, and the second wirings constitute a first pattern connected in series.

[0007] Furthermore, it is preferable that the first pattern is a pattern in which the first wiring, the first pad, the second pad, and the second wiring are continuously connected in series in this order.

[0008] In addition, ideally, the semiconductor device of this embodiment has a third pad connected to the first wiring of the first pattern, and a fourth pad connected to the second wiring of the first pattern, the length of the first wiring from the third pad to the first or last first or second pad is less than 1 mm, and the length of the second wiring from the fourth pad to the first or last first or second pad is less than 1 mm.

[0009] Furthermore, it is preferable that the first pattern overlaps the memory cell array when viewed from a direction substantially perpendicular to the bonding surface of the first chip and the second chip.

[0010] Furthermore, it is preferable that the first pattern overlaps both the memory cell array and the step structure provided at the end of the memory cell array when viewed from a direction substantially perpendicular to the bonding surface of the first chip and the second chip.

[0011] In addition, it is ideal that when viewed from a direction approximately perpendicular to the bonding surface of the first chip and the second chip, the first pattern overlaps with the memory cell array, and with a stepped structure portion provided at the end of the memory cell array and a test pattern area surrounding the stepped structure portion.

[0012] According to the embodiment, a semiconductor device capable of suppressing poor connection between wirings can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a cross-sectional view showing the structure of the semiconductor device according to the present embodiment.

[0014] Figure 2 It is a cross-sectional view showing the structure of the columnar portion according to the present embodiment.

[0015] Figure 3 It is a schematic plan view showing the arrangement of the chain pattern according to the present embodiment.

[0016] Figure 4 It is a schematic plan view showing the structure of a chain pattern.

[0017] Figure 5 yes Figure 4 Schematic cross-sectional view of the chain pattern.

[0018] Figure 6 It is a schematic diagram showing an example of the configuration of a chain pattern and a metal pad.

[0019] Figure 7 It is a graph showing the relationship between the wiring length and the yield of the bonding portion.

[0020] Figure 8 This is a schematic cross-sectional view showing an example of poor bonding between metal pads.

[0021] Fig. 9 It is a figure which shows the state of the depression of the metal pad of a circuit chip.

[0022] Fig.10 It is a figure which shows the state of the depression of the metal pad of a circuit chip.

[0023] Fig.11 The diagram shows the positions of chips with poor bonding within the surface of the semiconductor wafer after bonding.

[0024] Fig.12The diagram shows the positions of chips with poor bonding within the surface of the semiconductor wafer after bonding. DETAILED DESCRIPTION

[0025] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. This embodiment does not limit the present invention. The accompanying drawings are schematic or conceptual diagrams, and the ratios of the various parts may not be the same as the actual objects. In the specification and the accompanying drawings, the same symbols are marked for the elements that are the same as those described in the above-mentioned drawings, and the detailed description is appropriately omitted.

[0026] Figure 1 It is a cross-sectional view showing the structure of the semiconductor device according to the present embodiment. Figure 1 The semiconductor device is a three-dimensional memory formed by bonding an array chip 1 and a circuit chip 2. The semiconductor device is, for example, a NAND (Not And) type flash memory. The circuit chip 2 is an example of a first chip, and the array chip 1 is an example of a second chip.

[0027] The array chip 1 includes a memory cell array 11 including a plurality of memory cells, an insulating film 12 on the memory cell array 11, and an interlayer insulating film 13 under the memory cell array 11. The insulating film 12 is, for example, a silicon oxide film or a silicon nitride film. The interlayer insulating film 13 is, for example, a silicon oxide film, or a laminated film including a silicon oxide film and other insulating films.

[0028] The circuit chip 2 is disposed under the array chip 1. Symbol S represents the bonding surface of the array chip 1 and the circuit chip 2. The circuit chip 2 includes an interlayer insulating film 14 and a substrate 15 under the interlayer insulating film 14. The interlayer insulating film 14 is, for example, a silicon oxide film or a laminated film including a silicon oxide film and other insulating films. The substrate 15 is, for example, a semiconductor substrate such as a silicon substrate.

[0029] Figure 1 The +Z direction represents the X direction and the Y direction which are parallel to the surface of the substrate 15 and perpendicular to each other, and the Z direction which is perpendicular to the surface of the substrate 15. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity.

[0030] The array chip 1 includes a plurality of word lines WL and source lines SL as electrode layers in the memory cell array 11 . Figure 1 The step structure portion 21 of the memory cell array 11 is shown. Each word line WL is electrically connected to the word line wiring layer 23 via a contact plug 22. Each columnar portion CL that passes through a plurality of word lines WL is electrically connected to a bit line BL via a via plug 24, and is electrically connected to a source line SL. The source line SL includes a first source layer SL1 as a semiconductor layer, and a second source layer SL2 as a metal layer. The memory cell array 11 is, for example, a three-dimensional memory cell array in which a plurality of memory cells are arranged three-dimensionally.

[0031] The circuit chip 2 includes a plurality of transistors 31. Each transistor 31 includes a gate electrode 32 disposed on a substrate 15 through a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) disposed in the substrate 15. The transistor 31 constitutes a logic circuit such as a CMOS (Complementary Metal Oxide Semiconductor) circuit, for example. The CMOS circuit controls the array chip 1. In addition, the circuit chip 2 includes a plurality of contact plugs 33 disposed on the gate electrodes 32, the source diffusion layer, or the drain diffusion layer of the transistors 31, a wiring layer 34 disposed on the contact plugs 33 and including a plurality of wirings, and a wiring layer 35 disposed on the wiring layer 34 and including a plurality of wirings.

[0032] The circuit chip 2 also includes a wiring layer 36 disposed on the wiring layer 35 and including a plurality of wirings, a plurality of through-hole plugs 37 disposed on the wiring layer 36, and a plurality of metal pads 38 disposed on these through-hole plugs 37. The wiring layer 36 as the first wiring is disposed above the logic circuit constituted by the transistor 31. The wiring layer 36 uses, for example, Cu (copper) or Al (aluminum). The metal pad 38 as the first pad is disposed above the wiring layer 36. In order to bond with the metal pad 41 of the array chip 1 on the bonding surface S, it is preferred that the metal pad 38 and the interlayer insulating film 14 are substantially in the same plane. The metal pad 38 also uses, for example, Cu (copper) or Al (aluminum). The metal pad 38 includes an effective pad and a dummy pad. The through-hole plug 37 as the first through-hole contact is disposed between the wiring layer 36 and the metal pad 38, and the wiring layer 36 and the metal pad 38 are electrically connected. As described above, the circuit chip 2 functions as a control circuit (logic circuit) for controlling the operation of the array chip 1. The control circuit is composed of transistors 31 and the like, and is electrically connected to the metal pads 38.

[0033] The array chip 1 includes a plurality of metal pads 41 disposed on the metal pads 38, and a plurality of through-hole plugs 42 disposed on the metal pads 41. In addition, the array chip 1 includes a wiring layer 43 disposed on these through-hole plugs 42 and including a plurality of wirings, and a wiring layer 44 disposed on the wiring layer 43 and including a plurality of wirings. In order to bond with the metal pads 38 of the circuit chip 2 on the bonding surface S, the metal pads 41 as the second pads are preferably substantially in the same plane as the interlayer insulating film 13. The metal pads 41 are made of, for example, Cu or Al. The metal pads 41 include effective pads and dummy pads. The wiring layer 43 as the second wiring is disposed above the metal pads 41. The wiring layer 43 is made of, for example, Cu or Al. The through-hole plug 42 as the second through-hole contact is disposed between the wiring layer 43 and the metal pad 41, and the wiring layer 43 and the metal pad 41 are electrically connected. Other wirings, via plugs, memory cell array 11, etc. are provided above wiring layer 43. Details of wiring layers 36, 43, via plugs 37, 42, and metal pads 38, 41 will be described below. In addition, via plugs 37, 42 are not necessarily provided. In this case, wiring layer 36 may be directly connected to metal pad 38 without via via plug 37. Wiring layer 43 may be directly connected to metal pad 41 without via via plug 42.

[0034] The array chip 1 further includes a plurality of via plugs 45 disposed on the wiring layer 44, a metal pad 46 disposed on the via plugs 45 or on the insulating film 12, and a passivation film 47 disposed on the metal pad 46 or on the insulating film 12. The metal pad 46 is made of, for example, Cu or Al. Figure 1 The passivation film 47 is an insulating film such as a silicon oxide film, and has an opening P that exposes the upper surface of the metal pad 46. The metal pad 46 can be connected to a mounting substrate or other devices through the opening P using a bonding wire, a solder ball, a metal bump, etc.

[0035] Figure 2 It is a cross-sectional view showing the structure of the columnar portion CL according to the present embodiment.

[0036] like Figure 2 As shown, the memory cell array 11 has an interlayer insulating film 13 ( Figure 1 ) are alternately stacked on a plurality of word lines WL and a plurality of insulating layers 51. The word lines WL are, for example, W (tungsten) layers. The insulating layers 51 are, for example, silicon oxide films.

[0037] The columnar portion CL includes a blocking insulating film 52, a charge storage layer 53, a tunnel insulating film 54, a channel semiconductor layer 55, and a core insulating film 56 in sequence. The charge storage layer 53 is, for example, a silicon nitride film, and the interlayer blocking insulating film 52 is formed on the side of the word line WL and the insulating layer 51. The charge storage layer 53 may also be a semiconductor layer such as a polysilicon layer. The channel semiconductor layer 55 is, for example, a polysilicon layer, and the interlayer tunnel insulating film 54 is formed on the side of the charge storage layer 53. The blocking insulating film 52, the tunnel insulating film 54, and the core insulating film 56 are, for example, a silicon oxide film or a metal insulating film.

[0038] Figure 3 It is a schematic plan view showing the arrangement of the chain pattern according to the present embodiment. Figure 3 The schematic plane of the array chip 1 viewed from a direction substantially perpendicular to the bonding surface S (Z direction) is shown.

[0039] The chain patterns 100a to 100c as the first pattern are TEG (Test Element Group) patterns for detecting a connection failure at a wiring junction between the array chip 1 and the circuit chip 2. The chain patterns 100a to 100c are as follows: Figure 5 The above-mentioned pattern is to continuously connect the metal pad 41, the through-hole plug 42, the wiring layer 43 of the array chip 1, and the wiring layer 36, the through-hole plug 37, and the metal pad 38 of the circuit chip 2. Figure 1 The metal pad 41 and the metal pad 38 are electrically connected to each other at the junction.

[0040] The memory cell array region R11 is a region where the memory cell array 11 is provided. The step region R21 is a region where the step structure portion 21 at the end of the memory cell array 11 is provided. The TEG region Rteg is provided outside the step region R21. In the TEG region Rteg, semiconductor elements such as the memory cell array 11 are not provided, but a test pattern is provided.

[0041] The chain pattern 100a is provided in the memory cell array region R11, and overlaps with the memory cell array 11 when viewed from above in the Z direction. The chain pattern 100a is a test pattern for detecting poor bonding between the metal pad 38 and the metal pad 41 below the memory cell array 11. In addition, the metal pad 41 of the chain pattern 100a is provided on the same layer as the metal pad for the memory cell array 11, but is not connected to the memory cell array 11, and is provided as a metal pad for a test pattern.

[0042] The chain pattern 100b overlaps both the memory cell array 11 and the step structure 21 provided at the end of the memory cell array 11 when viewed from the Z direction. That is, the chain pattern 100b is provided in a zigzag shape at the boundary between the memory cell array region R11 and the step region R21. At the end of the memory cell array 11, metal pads 38 and 41 for drain-side selection gates for connecting the bit line and the memory string are provided. The chain pattern 100b is a test pattern for detecting poor bonding between the metal pad 38 and the metal pad 41 for the drain-side selection gate.

[0043] The chain pattern 100c overlaps both the step structure 21 and the TEG region Rteg as a test region located around the step structure 21 when viewed from the top in the Z direction. That is, the chain pattern 100c is provided in a zigzag shape at the boundary between the step region R21 and the TEG region Rteg. The chain pattern 100c detects poor bonding between the metal pad 38 and the metal pad 41 located in the step structure 21 and the TEG region Rteg.

[0044] The structure of the array chip 1 changes at the boundary between the memory cell array region R11 and the step region R21, and at the boundary between the step region R21 and the TEG region Rteg. This structural change may cause poor connection of the metal pads 38 and 41. Therefore, in this embodiment, chain patterns 100a to 100c are configured not only in the memory cell array region R11, but also in the boundary between such a memory cell array region R11 and the step region R21, or at the boundary between the memory cell array region R11 and the TEG region Rteg. As a result, poor connection of the metal pads 38 and 41 can be easily detected.

[0045] A metal pad 46 is provided in the TEG region Rteg. The metal pad 46 as the third or fourth pad can be connected to external devices of the array chip 1 and the circuit chip 2. The metal pad 46 is connected to the end of the chain pattern 100a~100c, and is provided to input a test signal to the chain pattern 100a~100c from the outside. For example, a metal pad 46 is connected to both ends of each chain pattern 100a~100c. Electricity is applied between the metal pad 46 at one end of the chain pattern 100a~100c and the metal pad 46 at the other end, and the resistance value of each chain pattern 100a~100c is measured. When the resistance value is greater than a specific threshold value, it can be determined that a poor connection occurs between the metal pad 38 and the metal pad 41.

[0046] Figure 4 It is a schematic plan view showing the structure of a chain pattern. Figure 4 The schematic plan view of the chain pattern 100 a viewed from the Z direction is shown. Figure 5 yes Figure 4 Schematic cross-sectional view of the chain pattern.

[0047] like Figure 5 As shown, chain patterns 100a to 100c (hereinafter also collectively referred to as chain pattern 100) have a structure in which wiring layer 36, via plug 37, metal pad 38, metal pad 41, via plug 42, and wiring layer 43 are continuously connected in series in this order.

[0048] The chain pattern 100 has a unit chain structure U1 that connects the wiring layer 36, the via plug 37, the metal pad 38, the metal pad 41, the via plug 42, and the wiring layer 43 in series. The chain pattern 100 may have only one unit chain structure U1, or may be composed of a plurality of unit chain structures U1 connected in series. The unit chain structure U1 includes a junction between one metal pad 38 and a metal pad 41. Therefore, the chain pattern 100 includes the same number of junctions as the number of unit chain structures U1 connected in series. By testing such a chain pattern 100, it is possible to test the junctions of the unit chain structures U1 included in the chain pattern 100.

[0049] The number of unit chain structures U1 connected in series to one chain pattern 100 is not particularly limited. However, the number of chain patterns 100 connected in series is one or more, and there are 10×10 3 ~10×10 6 situation.

[0050] Figure 4 The joint B shown is the joint between the metal pad 38 and the metal pad 41. The through-hole plugs 37 and 42 overlap with the joint B. Figure 4 The wiring layer 36 and the wiring layer 43 are alternately connected between the adjacent plurality of joints B. In addition, the wiring layer 36 or 43 is Figure 3 The wiring position and wiring length of the chain pattern 100 are arbitrary and not particularly limited. However, although Figure 4 Although not shown in the figure, the chain patterns 100b and 100c preferably cross the boundary between the memory cell array region R11 and the step region R21 and the boundary between the step region R21 and the TEG region Rteg in the X direction. Thus, the chain patterns 100b and 100c can efficiently test the connection failure in these boundary portions.

[0051] Figure 6 It is a schematic diagram showing a configuration example of the chain pattern 100 and the metal pad 46 .

[0052] The wiring layer 43 includes wiring layers 43_1 and 43_2. The wiring layers 43_1 and 43_2 are wirings from the joints B at both ends of the chain pattern 100 to the metal pads 46, and are wirings at the ends of the chain pattern 100. The wiring layers 43_1 and 43_2 are wiring layers 43 from the metal pads 46 for connecting to the outside to the first (or last) joint B. Alternatively, the wiring layers 43_1 and 43_2 can also be said to be wiring layers 43 from the metal pads 46 to the first (or last) metal pads 38 or 41.

[0053] The wiring layer 36 includes wiring layers 36_1 and 36_2. The wiring layers 36_1 and 36_2 are wirings from the joints B at both ends of the chain pattern 100 to the metal pads 46, and are wirings at the ends of the chain pattern 100. The wiring layers 36_1 and 36_2 are wiring layers 36 from the metal pads 46 for connecting to the outside to the first (or last) joint B. Alternatively, the wiring layers 36_1 and 36_2 can also be said to be wiring layers 36 from the metal pads 46 to the first (or last) metal pads 38 or 41.

[0054] The lengths of the wiring layers 43_1 and 43_2 are L43_1 and L43_2, respectively. The lengths of the wiring layers 36_1 and 36_2 are L36_1 and L36_2, respectively. At this time, it can be seen that the relationship between the wiring lengths L43_1, L43_2, L36_1, L36_2 and the bonding defect rate is Figure 7 In addition, it can be seen that the relationship between the length of the wiring layer 36 between the bonding pad 38 and the bonding pad 41 and the wiring layer 36 between other bonding pads and the bonding defect rate also has the same relationship.

[0055] Figure 7 It is a graph showing the relationship between the wiring length L43_1, L43_2, L36_1, L36_2 and the yield of the joint B. According to the graph, if the wiring length L43_1, L43_2, L36_1, L36_2 is longer, the yield is reduced. This means that if the wiring length L43_1, L43_2, L36_1, L36_2 of the wiring layers 36 and 43 at the ends of each chain pattern 100 is longer, the poor bonding between the metal pad 41 and the metal pad 38 in the joint B increases. For example, if the wiring length L43_1, L43_2, L36_1, L36_2 of the wiring layers 36 and 43 exceeds 1 mm, the yield begins to decrease. Therefore, it is preferred that the wiring length L43_1, L43_2, L36_1, L36_2 of the wiring layers 36 and 43 is less than 1 mm. Furthermore, if the length of each of the wiring layer 36 between the bonding pad 38 and the bonding pad 41 and the wiring layer 36 between other bonding pads exceeds 1 mm, the yield will also begin to decrease.

[0056] That is, it is preferred that the length L36_1 and L36_2 of the wiring layer 36 from the metal pad 46 to the through-hole plug 37 are less than 1 mm. It is preferred that the length L43_1 and L43_2 of the wiring layer 43 from the metal pad 46 to the through-hole plug 42 are less than 1 mm. Furthermore, it is preferred that the lengths of the wiring layer 36 between the bonding pad 38 and the bonding pad 41 and the wiring layer 36 between other bonding pads are also less than 1 mm. As a result, the poor bonding between the metal pad 41 and the metal pad 38 can be reduced, and the yield can be improved. In addition, it can be seen that the poor bonding does not depend on the chain scale of the chain pattern 100 (the number of connections in the unit chain structure U1).

[0057] Next, the bonding failure between the metal pad 41 and the metal pad 38 will be described.

[0058] Figure 8 1 is a schematic cross-sectional view showing an example of poor bonding between metal pad 41 and metal pad 38 . Figure 8 The metal pad 38 and the metal pad 41 on the left side are normally bonded on the bonding surface S. Figure 8 The metal pad 38 and the metal pad 41 on the right side are separated on the bonding surface S, resulting in poor bonding. This is because the material of the metal pad 38 and / or 41 is eroded and removed in a step such as CMP (Chemical Mechanical Polishing).

[0059] Fig. 9 and Fig.10 2 is a diagram showing the depression of the metal pad 38 of the circuit chip 2. Fig. 9 and Fig.10 In the above description, the circuit chip 2 is described, but the depression of the metal pad 41 of the array chip 1 is also the same.

[0060] Before bonding the array chip 1 and the circuit chip 2, in the previous step, the metal pad 38 and the interlayer insulating film 14 are polished and flattened using the CMP method. In this CMP step, the metal pad 38 is not only physically polished by the polishing pad, but also chemically polished by contacting the slurry with the metal pad 38. For example, copper, which is the material of the metal pad 38, is polished by the slurry via Cu→Cu 2+ +2e －Chemical reaction removes. The chemical reaction between the slurry and the material (for example, copper) of the metal pad 38 varies depending on the configuration density of the metal pad 38 (the exposed area of ​​the metal pad 38 per unit area). That is, in an area where the configuration density of the metal pad 38 is high, the slurry is used to grind more metal pads 38, so the chemical potential of the slurry becomes lower. On the other hand, in an area where the configuration density of the metal pad 38 is low, the slurry is only used to grind fewer metal pads 38, so the chemical potential of the slurry is maintained at a high level. Therefore, in an area where the configuration density of the metal pad 38 is high, the metal pad 38 is not so removed and is not easily depressed. On the other hand, in an area where the configuration density of the metal pad 38 is low, the metal pad 38 is easily removed and is easily depressed. The same can be said about the metal pad 41 of the array chip 1.

[0061] So, for example Fig. 9 As shown in FIG. 1 , at the end E of the semiconductor chip or semiconductor wafer, the metal pads 38 and 41 are often recessed, which easily leads to poor bonding. Fig.10 As shown, in the region where the density of the metal pads 38 and 41 is low, the metal pads 38 and 41 are more likely to be recessed than in the region where the density of the metal pads 38 and 41 is high, and bonding failure is more likely to occur.

[0062] Fig.11 and Fig.12 This is a diagram showing the position of the chip with poor bonding within the surface of the semiconductor wafer after bonding. Fig.11 and Fig.12 , it can be seen that the semiconductor chip at the end of the semiconductor wafer has a poor bonding.

[0063] As described above, the depression of the metal pad 38 is suppressed by making the length L36_1 and L36_2 of the wiring layer 36 from the metal pad 46 to the via plug 37 less than 1 mm. This is because the exposure density of the metal pads 38 and 46 is reduced by making the length of the wiring layers 36 and 43 less than 1 mm. The lengths L43_1 and L43_2 of the wiring layer 43 from the metal pad 46 to the via plug 42, and the lengths of the wiring layer 36 between the bonding pad 38 and the bonding pad 41 and the wiring layer 36 between other bonding pads are also the same. As a result, the semiconductor device of the present embodiment can suppress poor bonding between wirings and improve the yield.

[0064] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments or their variations are included in the scope or subject matter of the invention, and are also included in the invention described in the claims and the scope equivalent thereto.

[0065] [Explanation of Symbols]

[0066] 1 Array Chip

[0067] 2 Circuit Chip

[0068] 11 Memory Cell Array

[0069] 12 Insulation film

[0070] 13, 14 interlayer insulation film

[0071] 15, 16 Substrate

[0072] 21 Step structure

[0073] 22, 33 Contact plug

[0074] 23 Word line wiring layer

[0075] 24, 37, 42, 45 through-hole plugs

[0076] 31 Transistor

[0077] 32. Gate electrode

[0078] 34, 35, 43, 44 wiring layer

[0079] 36 Wiring layer

[0080] 38, 41, 46 Metal pads

[0081] 47 Passivation film

[0082] 100a~100c Chain pattern.

Claims

1. A semiconductor device comprising: chip 1; and a second chip, bonded to the first chip; The first chip comprises: substrate; A transistor, disposed on the substrate; a first wiring layer, provided above the transistor and including a plurality of first wirings; and A plurality of first pads are arranged above the first wiring; The second chip comprises: A plurality of second bonding pads, connected to the plurality of first bonding pads; A second wiring layer is disposed above the second pad and includes a plurality of second wirings; and A memory cell array is arranged above the second wiring; The first wiring, the first pad, the second pad, and the second wiring constitute a first pattern connected in series; The semiconductor device further comprises: a third pad connected to the first wiring of the first pattern; and a fourth pad connected to the second wiring of the first pattern; The length of the first wiring from the third pad to the first or last first or second pad is less than 1 mm, The length of the second wiring from the fourth pad to the first or last first or second pad is 1 mm or less. 2 . The semiconductor device according to claim 1 , wherein the first pattern is a pattern in which the first wiring, the first pad, the second pad, and the second wiring are continuously connected in series in this order. 3 . The semiconductor device according to claim 1 , wherein the first pattern overlaps the memory cell array when viewed from a direction substantially perpendicular to a bonding surface of the first chip and the second chip.

4. A semiconductor device according to claim 1 or 2, wherein the first pattern overlaps both the memory cell array and a stepped structure portion provided at an end of the memory cell array when viewed from a direction substantially perpendicular to a bonding surface of the first chip and the second chip.

5. A semiconductor device according to claim 1 or 2, wherein the first pattern overlaps with both a stepped structure portion provided at the end of the memory cell array and a test pattern area located around the stepped structure portion when viewed from a direction approximately perpendicular to the bonding surface of the first chip and the second chip.

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