Memory cell structure for static random access memory and memory

Abstract

The application provides a memory cell structure of a static random access memory, a transistor cell comprising a first transfer transistor, a first common-gate complementary field effect transistor, a second common-gate complementary field effect transistor and a second transfer transistor arranged in sequence along a first direction, so that the memory cell structure of the static random access memory can use a continuous fin structure in manufacturing, without cutting off the fin structure process, thereby reducing process risk and cost, and the first bit line, the second bit line, the first interconnection line, the second interconnection line, the first power line and the second power line are parallel to the first direction, and the word line is perpendicular to the first direction, in combination with the field effect transistor, so that the occupied area is greatly reduced, the circuit integration is improved, and the cost is further reduced. The application further provides a memory.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a memory cell structure of a static random access memory and the memory. BACKGROUND

[0002] Static random access memory (SRAM) is a kind of random access memory. The memory cell of static random access memory is usually composed of a pull-up transistor (PU), a pull-down transistor (PD) and a pass-gate transistor (PG). In practical applications, the circuit area occupied by SRAM is large, and low integration will significantly increase the chip cost.

[0003] Therefore, it is necessary to provide a new memory cell structure of a static random access memory and the memory to solve the above problems existing in the prior art. SUMMARY

[0004] The purpose of the present application is to provide a memory cell structure of a static random access memory and the memory.

[0005] To achieve the above purpose, the memory cell structure of the static random access memory of the present application comprises a transistor unit and a connection unit connected to each other, wherein the transistor unit comprises a first pass-gate transistor, a first common-gate complementary field effect transistor, a second common-gate complementary field effect transistor and a second pass-gate transistor arranged in sequence along a first direction, the channel direction of the first pass-gate transistor, the channel direction of the first common-gate complementary field effect transistor, the channel direction of the second common-gate complementary field effect transistor and the channel direction of the second pass-gate transistor are all parallel to the first direction.

[0006] The connection unit comprises a word line, a first bit line, a second bit line, a first interconnection line, a second interconnection line, a first power supply line and a second power supply line, the word line is used to control the first pass-gate transistor and the second pass-gate transistor, the first bit line and the second bit line are used to realize signal transmission, the first interconnection line and the second interconnection line are used to realize the internal connection of the transistor unit, the first power supply line and the second power supply line are used to supply power or ground for the transistor unit, the first bit line, the second bit line, the first interconnection line, the second interconnection line, the first power supply line and the second power supply line are parallel to the first direction, and the word line is perpendicular to the first direction.

[0007] The storage unit structure of the static random access memory has the beneficial effects that: the transistor unit comprises a first transfer tube, a first common-gate complementary field effect transistor, a second common-gate complementary field effect transistor and a second transfer tube arranged in sequence along a first direction, the channel direction of the first transfer tube, the channel direction of the first common-gate complementary field effect transistor, the channel direction of the second common-gate complementary field effect transistor and the channel direction of the second transfer tube are all parallel to the first direction, so that the storage unit structure of the static random access memory can use a continuous fin structure in manufacturing without cutting off the fin structure process, thereby reducing the process risk and the cost, and the first bit line, the second bit line, the first interconnection line, the second interconnection line, the first power supply line and the second power supply line are parallel to the first direction, and the word line is perpendicular to the first direction, which greatly reduces the occupied area, improves the circuit integration and further reduces the cost in combination with the field effect transistor.

[0008] Optionally, the word line, the first interconnection line and the second interconnection line are device top interconnection lines. This has the beneficial effect that the wiring is facilitated and the process difficulty is reduced.

[0009] Optionally, the word line, the first interconnection line and the second interconnection line are located on the same or different metal interconnection layers on the device top. This has the beneficial effect that the wiring is reasonable and wiring conflicts are avoided.

[0010] Optionally, the first bit line and the second bit line are device top metal interconnection lines or metal buried lines in the substrate. This has the beneficial effect that the first bit line and the second bit line are device top metal interconnection lines, which facilitates the wiring, and the first bit line and the second bit line are metal buried lines in the substrate, which can reduce the wiring difficulty of the device top metal interconnection lines and avoid wiring conflicts.

[0011] Optionally, the first power supply line and the second power supply line are device top metal interconnection lines or metal buried lines in the substrate. This has the beneficial effect that the first power supply line and the second power supply line are device top metal interconnection lines, which facilitates the wiring, and the first power supply line and the second power supply line are metal buried lines in the substrate, which can reduce the wiring difficulty of the device top metal interconnection lines and avoid wiring conflicts.

[0012] Optionally, the first common-gate complementary field effect transistor comprises a first N-type field effect transistor and a first P-type field effect transistor arranged in stack, and the second common-gate complementary field effect transistor comprises a second N-type field effect transistor and a second P-type field effect transistor arranged in stack. This has the beneficial effect that the gates are shared, the process difficulty is reduced, the occupied area is reduced and the integration is greatly improved.

[0013] Optionally, the drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor are arranged on one side of the gate of the first common-gate complementary field effect transistor, and the source of the first N-type field effect transistor and the source of the first P-type field effect transistor are arranged on the other side of the gate of the first common-gate complementary field effect transistor. The beneficial effect is that the connection between the drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor is facilitated, the circuit integration is greatly improved, and the process difficulty is reduced.

[0014] Optionally, the drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor are arranged on one side of the gate of the first common-gate complementary field effect transistor, and the source of the first N-type field effect transistor and the source of the first P-type field effect transistor are arranged on the other side of the gate of the first common-gate complementary field effect transistor. The beneficial effect is that the connection between the drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor is facilitated, the circuit integration is greatly improved, and the process difficulty is reduced.

[0015] Optionally, the drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor are arranged on one side of the gate of the first common-gate complementary field effect transistor, and the source of the first N-type field effect transistor and the source of the first P-type field effect transistor are arranged on the other side of the gate of the first common-gate complementary field effect transistor. The beneficial effect is that the connection between the drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor is facilitated, the circuit integration is greatly improved, and the process difficulty is reduced.

[0016] Optionally, the drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor are arranged on one side of the gate of the first common-gate complementary field effect transistor, and the source of the first N-type field effect transistor and the source of the first P-type field effect transistor are arranged on the other side of the gate of the first common-gate complementary field effect transistor. The beneficial effect is that the connection between the drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor is facilitated, the circuit integration is greatly improved, and the process difficulty is reduced.

[0017] Optionally, the source of the first P-type field effect transistor is arranged opposite to the source of the second P-type field effect transistor, and the source of the first N-type field effect transistor is arranged opposite to the source of the second N-type field effect transistor. The beneficial effect is that the source of the first P-type field effect transistor and the source of the second P-type field effect transistor are connected with the second power supply line, and the source of the first N-type field effect transistor and the source of the second N-type field effect transistor are connected with the first power supply line, thereby greatly improving the circuit integration and reducing the process difficulty.

[0018] Optionally, the gate height of the first transmission tube, the gate height of the first common-gate complementary field effect transistor, the gate height of the second common-gate complementary field effect transistor and the gate height of the second transmission tube are the same, the channel, source and drain of the first P-type field effect transistor and the second P-type field effect transistor are at the same height, and the channel, source and drain of the first N-type field effect transistor and the second N-type field effect transistor are at the same height. The beneficial effect is that the same gate height facilitates the formation of the gates of all transistors at the same time, thereby greatly reducing the process difficulty.

[0019] Optionally, the channel, source and drain of the first transmission tube are at the same height as the channel, source and drain of at least one of the first P-type field effect transistor and the first N-type field effect transistor.

[0020] Optionally, the channel, source and drain of the second transmission tube are at the same height as the channel, source and drain of at least one of the second P-type field effect transistor and the second N-type field effect transistor.

[0021] Optionally, the number of channels of the first transmission tube, the second transmission tube, the first N-type field effect transistor, the second N-type field effect transistor, the first P-type field effect transistor and the second P-type field effect transistor is greater than or equal to 1. The beneficial effect is that low power consumption or high speed can be achieved.

[0022] Optionally, the first transmission tube and the second transmission tube are both field effect transistors.

[0023] Optionally, the first transmission tube and the second transmission tube are both N-type field effect transistors or P-type field effect transistors.

[0024] The application further provides a memory comprising at least one memory cell structure of the static random access memory.

[0025] The memory has the beneficial effects that the storage unit structure of the static random access memory is applied, a continuous fin structure can be used in manufacturing without cutting off the fin structure process, the process risk is reduced, the occupied area is greatly reduced in combination with the field effect transistor, the circuit integration is improved, and the cost is further reduced. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a sectional view of the storage unit structure of the static random access memory in some embodiments of the present application;

[0027] Figure 2 is a sectional view of the storage unit structure of the static random access memory in some embodiments of the present application; Figure 1 is a top view of the storage unit structure of the static random access memory shown in the figure;

[0028] Figure 3 is a top view of the memory in some embodiments of the present application;

[0029] Figure 4 is a circuit schematic diagram of the storage unit structure of the static random access memory in some embodiments of the present application;

[0030] Figure 5 is a structural schematic diagram of two-channel field effect transistors in some embodiments of the present application;

[0031] Figure 6 is a sectional view of the storage unit structure of the static random access memory in some other embodiments of the present application;

[0032] Figure 7 is a sectional view of the storage unit structure of the static random access memory in some other embodiments of the present application;

[0033] Figure 8 is a sectional view of the storage unit structure of the static random access memory in some other embodiments of the present application. DETAILED DESCRIPTION

[0034] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application. Unless otherwise defined, the technical terms or scientific terms used herein should be understood as the usual meanings understood by those of ordinary skill in the art to which the present application belongs. The words such as “comprise” and similar words used herein mean that the elements or objects before the words cover the elements or objects listed after the words and their equivalents, without excluding other elements or objects.

[0035] In view of the problems in the prior art, embodiments of the present application provide a memory, which comprises at least one memory cell structure of a static random access memory.

[0036] In some embodiments, the memory cell structure of the static random access memory comprises a transistor cell and a connection cell.

[0037] Figure 1 A sectional view of the memory cell structure of the static random access memory in some embodiments of the present application is shown in FIG. 1. Referring to FIG. 1, Figure 1 the transistor cell comprises a first transfer transistor 101, a first common-gate complementary field effect transistor 102, a second common-gate complementary field effect transistor 103 and a second transfer transistor 104 arranged in sequence along a first direction, and the channel direction of the first transfer transistor 101, the channel direction of the first common-gate complementary field effect transistor 102, the channel direction of the second common-gate complementary field effect transistor 103 and the channel direction of the second transfer transistor 104 are all parallel to the first direction.

[0038] In some embodiments, the first transfer transistor and the second transfer transistor are both field effect transistors. In other embodiments, the first transfer transistor and the second transfer transistor are both N-type field effect transistors or P-type field effect transistors.

[0039] Referring to FIG. 1, Figure 1 the connection cell comprises a word line 201, a first bit line 202, a second bit line (not shown in the figure), a first interconnection line 204, a second interconnection line (not shown in the figure), a first power supply line (not shown in the figure) and a second power supply line 205, the word line is used to control the first transfer transistor and the second transfer transistor, the first bit line 202 and the second bit line are used to realize signal transmission, the first interconnection line 204 and the second interconnection line are used to realize internal connection of the transistor cell, the first power supply line and the second power supply line 205 are used to supply power or ground for the transistor cell, the first bit line 202, the second bit line, the first interconnection line 204, the second interconnection line, the first power supply line and the second power supply line 205 are parallel to the first direction, and the word line 201 is perpendicular to the first direction. Among them, the first power supply line is grounded, and the second power supply line 205 is connected to a working voltage.

[0040] Referring to FIG. 1, Figure 1The first bit line 202 is connected with the first end of the first transmission tube 101, the second bit line is connected with the first end of the second transmission tube 104, the word line 201 is connected with the gate of the first transmission tube 101 and the gate of the second transmission tube 104 through a metal via, the first interconnection line 204 is connected with the second end of the first transmission tube 101, the two drain electrodes of the first common-gate complementary field effect transistor 102 and the gate of the second common-gate complementary field effect transistor 103 through a metal via, the second interconnection line is connected with the second end of the second transmission tube 104, the two drain electrodes of the second common-gate complementary field effect transistor 103 and the gate of the first common-gate complementary field effect transistor 102 through a metal via, the second power supply line 205 is connected with the source of the P-type field effect transistor of the first common-gate complementary field effect transistor 102 and the source of the P-type transistor of the second common-gate complementary field effect transistor 103 through a metal via, and the first power supply line is connected with the source of the N-type field effect transistor of the first common-gate complementary field effect transistor 102 and the source of the N-type transistor of the second common-gate complementary field effect transistor 103 through a metal via.

[0041] In some embodiments, the first transmission tube and the second transmission tube are both N-type field effect transistors. In other embodiments, the first transmission tube and the second transmission tube are both P-type field effect transistors.

[0042] In some embodiments, the first end of the first transmission tube is a drain electrode, and the second end of the first transmission tube is a source electrode.

[0043] In some embodiments, the first end of the first transmission tube is a source electrode, and the second end of the first transmission tube is a drain electrode.

[0044] In some embodiments, the first end of the second transmission tube is a drain electrode, and the second end of the second transmission tube is a source electrode.

[0045] In some embodiments, the first end of the second transmission tube is a source electrode, and the second end of the second transmission tube is a drain electrode.

[0046] In some embodiments, the word line, the first interconnection line and the second interconnection line are device top metal interconnection lines.

[0047] In some embodiments, the word line, the first interconnection line and the second interconnection line are located at the same or different interconnection layers of the device top.

[0048] In some embodiments, the first bit line and the second bit line are device top metal interconnection lines or metal buried lines in the substrate.

[0049] In some embodiments, the first power line and the second power line are top metal interconnect lines or buried metal lines in a substrate. When the first power line and the second power line are top metal interconnect lines, the first power line and the word line, the first interconnect line, and the second interconnect line are in the same or different top metal interconnect layers, and the second power line and the word line, the first interconnect line, and the second interconnect line are in the same or different top metal interconnect layers. Alternatively, when the first power line and the second power line are top metal interconnect lines, the first power line, the second power line, the word line, the first interconnect line, and the second interconnect line are in the same top metal interconnect layer.

[0050] Referring to Figure 1 , the word line 201, the first interconnect line 204, and the second interconnect line are in a first top metal interconnect layer, the first bit line 202 and the second bit line are in a second top metal interconnect layer, and the first power line and the second power line 205 are buried metal lines in a substrate.

[0051] In some embodiments, the first common-gate complementary field effect transistor includes a first N-type field effect transistor and a first P-type field effect transistor stacked, and the second common-gate complementary field effect transistor includes a second N-type field effect transistor and a second P-type field effect transistor stacked.

[0052] In some embodiments, the first N-type field effect transistor of the first common-gate complementary field effect transistor is stacked above the first P-type field effect transistor. In other embodiments, the first P-type field effect transistor of the first common-gate complementary field effect transistor is stacked above the first N-type field effect transistor.

[0053] In some embodiments, the second N-type field effect transistor of the second common-gate complementary field effect transistor is stacked above the second P-type field effect transistor. In other embodiments, the second P-type field effect transistor of the second common-gate complementary field effect transistor is stacked above the second N-type field effect transistor.

[0054] In some embodiments, the first pass transistor, the first common-gate complementary field effect transistor, the second common-gate complementary field effect transistor, and the second pass transistor share the same substrate, the gate height of the first pass transistor, the gate height of the first common-gate complementary field effect transistor, the gate height of the second common-gate complementary field effect transistor, and the gate height of the second pass transistor are the same, the channel, source, and drain of the first P-type field effect transistor and the second P-type field effect transistor are in the same height, and the channel, source, and drain of the first N-type field effect transistor and the second N-type field effect transistor are in the same height.

[0055] In some embodiments, the first transmission tube is located at the same height as at least one of the first P-type field effect transistor and the first N-type field effect transistor.

[0056] In some embodiments, the second transmission tube is located at the same height as at least one of the second P-type field effect transistor and the second N-type field effect transistor.

[0057] Referring to Figure 1 , the gate height of the first transmission tube 101, the gate height of the first common-gate complementary field effect transistor 102, the gate height of the second common-gate complementary field effect transistor 103, and the gate height of the second transmission tube 104 are the same.

[0058] Referring to Figure 1 , the first transmission tube 101, the first N-type field effect transistor 1021, the second N-type field effect transistor 1031, and the second transmission tube 104 are located at the same height, and the first P-type field effect transistor 1022 and the second P-type field effect transistor 1032 are located at the same height.

[0059] Referring to Figure 1 , the channels of all transistors are formed by the same fin structure.

[0060] In some embodiments, the drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor are both arranged on one side of the gate of the first common-gate complementary field effect transistor, and the source of the first N-type field effect transistor and the source of the first P-type field effect transistor are both arranged on the other side of the gate of the first common-gate complementary field effect transistor.

[0061] In some optional embodiments, the drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor are both arranged on the side of the gate of the first common-gate complementary field effect transistor facing the second common-gate complementary field effect transistor, and the source of the first N-type field effect transistor and the source of the first P-type field effect transistor are both arranged on the side of the gate of the first common-gate complementary field effect transistor facing the first transmission tube.

[0062] In some optional embodiments, the drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor are disposed on a side of the gate of the first common-gate complementary field effect transistor facing the first transmission tube, and the source of the first N-type field effect transistor and the source of the first P-type field effect transistor are disposed on a side of the gate of the first common-gate complementary field effect transistor facing the second common-gate complementary field effect transistor.

[0063] In some embodiments, the drain of the second N-type field effect transistor and the drain of the second P-type field effect transistor are disposed on a side of the gate of the second common-gate complementary field effect transistor, and the source of the second N-type field effect transistor and the source of the second P-type field effect transistor are disposed on another side of the gate of the second common-gate complementary field effect transistor.

[0064] In some optional embodiments, the drain of the second N-type field effect transistor and the drain of the second P-type field effect transistor are disposed on a side of the gate of the second common-gate complementary field effect transistor facing the first common-gate complementary field effect transistor, and the source of the second N-type field effect transistor and the source of the second P-type field effect transistor are disposed on a side of the gate of the second common-gate complementary field effect transistor facing the second transmission tube.

[0065] In some optional embodiments, the drain of the second N-type field effect transistor and the drain of the second P-type field effect transistor are disposed on a side of the gate of the second common-gate complementary field effect transistor facing the second transmission tube, and the source of the second N-type field effect transistor and the source of the second P-type field effect transistor are disposed on a side of the gate of the second common-gate complementary field effect transistor facing the first common-gate complementary field effect transistor.

[0066] In some optional embodiments, the source of the first P-type field effect transistor and the source of the second P-type field effect transistor are disposed opposite to each other, and the source of the first N-type field effect transistor and the source of the second N-type field effect transistor are disposed opposite to each other.

[0067] Reference is made to Figure 1The drain of the first N-type field-effect transistor 1021 faces the source of the first transmission transistor 101. The drain of the first P-type field-effect transistor 1022 and the drain of the first N-type field-effect transistor are located on the same side of the gate of the first common-gate complementary field-effect transistor 102. The drain of the second N-type field-effect transistor 1031 faces the source of the second transmission transistor 104. The drain of the second P-type field-effect transistor 1032 and the drain of the second N-type field-effect transistor 1031 are located on the same side of the gate of the second common-gate complementary field-effect transistor 103. The source of the first N-type field-effect transistor 1021 faces the source of the second N-type field-effect transistor 1031. The source of the first P-type field-effect transistor 1022 faces the source of the second P-type field-effect transistor 1032.

[0068] Reference Figure 1 A gate dielectric layer 105 is provided between the channel and gate of the first transmission transistor 101, the second transmission transistor 104, the first N-type field-effect transistor 1021, the first P-type field-effect transistor 1022, the second N-type field-effect transistor 1031, and the second P-type field-effect transistor 1032.

[0069] Figure 2 for Figure 1 The diagram shows a top view of the memory cell structure of a static random access memory (SRAM). (Refer to...) Figure 2 The extended portion of the word line 201 is located to the right of the first interconnect line 204 and the second interconnect line 206, and the first bit line 202 and the second bit line 203 are perpendicular to the word line 201.

[0070] Reference Figure 2 The gate of the first transmission transistor 101 and the gate of the second transmission transistor 104 both extend to the boundary of the transistor unit.

[0071] Figure 3 This is a top view of the memory in some embodiments of the present invention. (Refer to...) Figure 2 and Figure 3 The storage cell structure of a column of static random access memory shares a word line 201, and the storage cell structure of a row of static random access memory shares a first bit line 202 and a second bit line 203.

[0072] Reference Figure 2 and Figure 3 In the storage cell structure of the static random access memory, the gates of the first transmission transistor 101 of different transistor cells are interconnected, and the gates of the second transmission transistor 104 of different transistor cells are interconnected.

[0073] In some embodiments, the number of channels of the first transmission transistor, the second transmission transistor, the first N-type field-effect transistor, the second N-type field-effect transistor, the first P-type field-effect transistor, and the second P-type field-effect transistor is greater than or equal to 1.

[0074] Figure 4 This is a circuit schematic diagram of the storage cell structure of a static random access memory in some embodiments of the present invention. (Refer to...) Figure 4 Field-effect transistor PD1 is equivalent to the first N-type field-effect transistor, field-effect transistor PD2 is equivalent to the second N-type field-effect transistor, field-effect transistor PG1 is equivalent to the first transmission transistor, field-effect transistor PG2 is equivalent to the second transmission transistor, field-effect transistor PU1 is equivalent to the first P-type field-effect transistor, P-type field-effect transistor PU2 is equivalent to the second P-type field-effect transistor, bit line BL is equivalent to the first bit line, and bit line BLB is equivalent to the second bit line.

[0075] In some embodiments, the first transmission transistor, the second transmission transistor, the first N-type field-effect transistor, the second N-type field-effect transistor, the first P-type field-effect transistor, and the second P-type field-effect transistor can all be referred to as field-effect transistors. When the number of channels of a field-effect transistor is greater than or equal to 2, the sources of all channels are epitaxially grown together to form the source of the transistor, and the drains of all channels are epitaxially grown together to form the drain of the field-effect transistor.

[0076] In some other embodiments, when the number of channels of a field-effect transistor is greater than or equal to 2, the sub-sources of all channels are interconnected by metal to form the source of the transistor, and the sub-drains of all channels are interconnected by metal to form the drain of the field-effect transistor.

[0077] Figure 5 This is a schematic diagram of the structure of a two-channel field-effect transistor in some embodiments of the present invention. (Refer to...) Figure 5 The field-effect transistor includes two channels 301, a gate 302, a source 303, a drain 304, a gate dielectric layer 105, and a substrate (not shown in the figure). The sub-sources 3031 of the two channels are interconnected by a first metal 3032 to form the source 303 of the field-effect transistor, and the sub-drains 3041 of the two channels are interconnected by a second metal 3042 to form the drain 304 of the field-effect transistor. The gate dielectric layer 105 is disposed between the channel 301 and the gate.

[0078] In some embodiments, the shape of the metal via is not limited in any way, as long as it can enable the connection between the source, drain, gate, word line, first bit line, second bit line, first interconnect, second interconnect, first power line and second power line.

[0079] Figure 6 A cross-sectional view of a memory cell structure of a static random access memory in some embodiments of the present application. Figure 6 Compared with the prior art, Figure 1 The difference lies in that the first transfer tube 101, the first P-type field effect transistor 1022, the second P-type field effect transistor, and the second transfer tube 104 are located at the same height, the drain of the first P-type field effect transistor faces the source of the first transfer tube 101, the drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor are located at the same side of the first common gate complementary field effect transistor gate, the drain of the second P-type field effect transistor faces the source of the second transfer tube 104, and the drain of the second N-type field effect transistor and the drain of the second P-type field effect transistor are located at the same side of the second common gate complementary field effect transistor gate.

[0080] Figure 7 A cross-sectional view of a memory cell structure of a static random access memory in some embodiments of the present application. Figure 7 Compared with the prior art, Figure 1 The difference lies in that the second transfer tube 104, the first P-type field effect transistor 1022, and the second P-type field effect transistor 1032 are located at the same height, and the drain of the second P-type field effect transistor faces the source of the second transfer tube 104.

[0081] Figure 8 A cross-sectional view of a memory cell structure of a static random access memory in some embodiments of the present application. Figure 8 Compared with the prior art, Figure 1 The difference lies in that the first transfer tube 101 has two channels, and the channels are located at the same height as the channel of the first N-type field effect transistor 1021 and the channel of the first P-type field effect transistor 1022, respectively, and the sub-drains of the two channels of the first transfer tube 101 are connected in parallel through a third metal 1011 to form the drain of the first transfer tube 101, and the sub-sources of the two channels are connected in parallel through a fourth metal 1012 to form the source of the first transfer tube 101, the second transfer tube 104 has two channels, and the channels are located at the same height as the channel of the second N-type field effect transistor 1031 and the channel of the second P-type field effect transistor 1032, respectively, and the sub-drains of the two channels are connected in parallel through a fifth metal 1041 to form the drain of the second transfer tube 104, and the sub-sources of the two channels are connected in parallel through a sixth metal 1042 to form the source of the second transfer tube 104.

[0082] While the embodiments of the application have been illustrated and described in detail, it will be readily apparent to those skilled in the art that various modifications and changes can be made to the embodiments without departing from the scope and spirit of the application, as described in the claims. Moreover, the application described is not limited in its application to the details set forth in the description or illustrated in the drawings. The application is capable of other embodiments and of being practiced or carried out in various ways.

Claims

1. A memory cell structure for a static random access memory, characterized by, The transistor unit and the connection unit are connected to each other, wherein, The transistor unit comprises a first transfer transistor, a first complementary gate field effect transistor, a second complementary gate field effect transistor and a second transfer transistor arranged in sequence along a first direction, the channel direction of the first transfer transistor, the channel direction of the first complementary gate field effect transistor, the channel direction of the second complementary gate field effect transistor and the channel direction of the second transfer transistor are parallel to the first direction; the first transfer transistor and the second transfer transistor are field effect transistors; the first complementary gate field effect transistor comprises a first N-type field effect transistor and a first P-type field effect transistor arranged in stack, and the second complementary gate field effect transistor comprises a second N-type field effect transistor and a second P-type field effect transistor arranged in stack; the channels of all the transistors are formed by the same fin structure; The connection unit comprises a word line, a first bit line, a second bit line, a first interconnection line, a second interconnection line, a first power supply line and a second power supply line, the word line is used for controlling the first transfer transistor and the second transfer transistor, and the word line is connected with the gate of the first transfer transistor and the gate of the second transfer transistor; the first bit line and the second bit line are used for signal transmission, the first bit line is connected with the first end of the first transfer transistor, and the second bit line is connected with the first end of the second transfer transistor; the first interconnection line and the second interconnection line are used for internal connection of the transistor unit; the first power supply line and the second power supply line are used for power supply or grounding of the transistor unit; the first bit line, the second bit line, the first interconnection line, the second interconnection line, the first power supply line and the second power supply line are parallel to the first direction, and the word line is perpendicular to the first direction.

2. The memory cell structure of a static random access memory according to claim 1, wherein, The word line, the first interconnection line and the second interconnection line are device top metal interconnection lines.

3. The memory cell structure of a static random access memory according to claim 2, wherein, The word line, the first interconnection line and the second interconnection line are located at the same or different metal interconnection layers of the device top.

4. The memory cell structure of a static random access memory according to claim 1, wherein, The first bit line and the second bit line are device top metal interconnection lines or metal buried lines in the substrate.

5. The memory cell structure of a static random access memory according to claim 1, wherein, The first power supply line and the second power supply line are device top metal interconnection lines or metal buried lines in the substrate.

6. The memory cell structure of a static random access memory as claimed in claim 1, wherein, The drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor are arranged on one side of the gate of the first complementary gate field effect transistor, and the source of the first N-type field effect transistor and the source of the first P-type field effect transistor are arranged on the other side of the gate of the first complementary gate field effect transistor.

7. The memory cell structure of a static random access memory according to claim 6, wherein, The drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor are arranged on one side of the gate of the first complementary gate field effect transistor facing the first transfer transistor, and the source of the first N-type field effect transistor and the source of the first P-type field effect transistor are arranged on one side of the gate of the first complementary gate field effect transistor facing the second complementary gate field effect transistor.

8. The memory cell structure of a static random access memory as claimed in claim 1, wherein, The drain of the second N-type field effect transistor and the drain of the second P-type field effect transistor are arranged on one side of the gate of the second common-gate complementary field effect transistor, and the source of the second N-type field effect transistor and the source of the second P-type field effect transistor are arranged on the other side of the gate of the second common-gate complementary field effect transistor.

9. The memory cell structure of a static random access memory according to claim 8, wherein, The drain of the second N-type field effect transistor and the drain of the second P-type field effect transistor are arranged on one side of the gate of the second common-gate complementary field effect transistor facing the second transmission tube, and the source of the second N-type field effect transistor and the source of the second P-type field effect transistor are arranged on one side of the gate of the second common-gate complementary field effect transistor facing the first common-gate complementary field effect transistor.

10. The memory cell structure of a static random access memory as claimed in claim 1, wherein, The source of the first P-type field effect transistor is arranged opposite to the source of the second P-type field effect transistor, and the source of the first N-type field effect transistor is arranged opposite to the source of the second N-type field effect transistor.

11. The memory cell structure of a static random access memory as claimed in claim 1, wherein, The height of the gate of the first transmission tube, the height of the gate of the first common-gate complementary field effect transistor, the height of the gate of the second common-gate complementary field effect transistor and the height of the gate of the second transmission tube are the same, the height of the channel, the source and the drain of the first P-type field effect transistor and the second P-type field effect transistor are the same, and the height of the channel, the source and the drain of the first N-type field effect transistor and the second N-type field effect transistor are the same.

12. The memory cell structure of a static random access memory as claimed in claim 11, wherein, The height of the channel, the source and the drain of the first transmission tube is the same as the height of the channel, the source and the drain of at least one of the first P-type field effect transistor and the first N-type field effect transistor.

13. The memory cell structure of a static random access memory as claimed in claim 11, wherein, The height of the channel, the source and the drain of the second transmission tube is the same as the height of the channel, the source and the drain of at least one of the second P-type field effect transistor and the second N-type field effect transistor.

14. The memory cell structure of a static random access memory as claimed in claim 1, wherein, The number of the channels of the first transmission tube, the second transmission tube, the first N-type field effect transistor, the second N-type field effect transistor, the first P-type field effect transistor and the second P-type field effect transistor is greater than or equal to 1.

15. The memory cell structure of a static random access memory as claimed in claim 1, wherein, The first transmission tube and the second transmission tube are N-type field effect transistors or P-type field effect transistors.

16. A memory, comprising: A memory cell structure comprising at least one static random access memory as claimed in any one of claims 1 to 15.

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