Semiconductor device

Abstract

The semiconductor device of the embodiment includes: a first electrode; a second electrode; a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; a fourth semiconductor layer of the second conductivity type; a fifth semiconductor layer of the second conductivity type; and first and second control electrodes. The first semiconductor layer is disposed between the first electrode and the second electrode. The second semiconductor layer is disposed between the first semiconductor layer and the second electrode. The third semiconductor layer is selectively disposed between the second semiconductor layer and the second electrode. The fourth semiconductor layer is disposed between the first semiconductor layer and the first electrode. The fifth semiconductor layer between the first and second control electrodes arranged along the boundary between the first semiconductor layer and the second semiconductor layer includes: a first portion disposed in the first semiconductor layer; and a second portion disposed between the first semiconductor layer and the second semiconductor layer.

Description

[0001] Related Application

[0002] This application claims priority based on Japanese Patent Application No. 2020-157707 (filing date: September 18, 2020). This application incorporates the entire content of the base application by reference thereto. Technical Field

[0003] The embodiment relates to a semiconductor device. Background Art

[0004] In a semiconductor device used in a power converter such as an inverter, for example, a large breakdown tolerance against current concentration during turn-off is desired. Summary of the Invention

[0005] The embodiment provides a semiconductor device with improved breakdown tolerance.

[0006] The semiconductor device of the embodiment includes: a first electrode; a second electrode opposed to the first electrode; a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; the first semiconductor layer of the first conductivity type; the fourth semiconductor layer of the second conductivity type; the fifth semiconductor layer of the second conductivity type; a plurality of control electrodes; and a first insulating film. The first semiconductor layer is provided between the first electrode and the second electrode. The second semiconductor layer is provided between the first semiconductor layer and the second electrode and is electrically connected to the second electrode. The third semiconductor layer is selectively provided between the second semiconductor layer and the second electrode and is electrically connected to the second electrode. The fourth semiconductor layer is provided between the first semiconductor layer and the first electrode and is electrically connected to the first electrode. The plurality of control electrodes are respectively provided inside a trench having a depth from the surface of the third semiconductor layer to the first semiconductor layer and are arranged along the boundary between the first semiconductor layer and the second semiconductor layer. The first insulating film is provided between each of the plurality of control electrodes and the first semiconductor layer and between each of the plurality of control electrodes and the second semiconductor layer. The fifth semiconductor layer includes a first portion and a second portion between adjacent first and second control electrodes among the plurality of control electrodes. The first portion is provided in the first semiconductor layer. The second portion is provided between the first semiconductor layer and the second semiconductor layer and is electrically connected to the first portion and the second semiconductor layer. The first portion is located between the third semiconductor layer and the fourth semiconductor layer. Brief Description of the Drawings

[0007] Figure 1 It is a schematic cross-sectional view showing the semiconductor device of the first embodiment.

[0008] Figure 2 Figs. (a) and (b) are schematic cross-sectional views showing the operation of the semiconductor device of the first embodiment.

[0009] Figure 3 Figs. (a) and (b) are graphs showing the characteristics of the semiconductor device of the first embodiment.

[0010] Figure 4 is a graph showing other characteristics of the semiconductor device of the first embodiment.

[0011] Figure 5 Figs. (a) to (c) are schematic views showing the semiconductor device of the first modification of the first embodiment.

[0012] Figure 6 Figs. (a) to (c) are schematic views showing the semiconductor device of the second modification of the first embodiment.

[0013] Figure 7 Figs. (a) and (b) are schematic views showing the semiconductor device of the third modification of the first embodiment.

[0014] Figure 8 Figs. (a) to (c) are schematic views showing the semiconductor layer of the modification of the first embodiment.

[0015] Figure 9 Figs. (a) and (b) are schematic views showing the semiconductor device of the fourth modification of the first embodiment.

[0016] Figure 10 Figs. (a) and (b) are schematic views showing the semiconductor device of the fifth modification of the first embodiment.

[0017] Figure 11 Figs. (a) and (b) are schematic views showing the semiconductor device of the sixth modification of the first embodiment.

[0018] Figure 12 is a schematic cross-sectional view showing the semiconductor device of the second embodiment. Detailed Embodiment

[0019] Hereinafter, the embodiments will be described with reference to the drawings. The same parts in the drawings are denoted by the same reference numerals, and the detailed description thereof is appropriately omitted, and different parts will be described. In addition, the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as in reality. In addition, even when showing the same part, there are cases where the sizes and ratios thereof are shown differently according to the drawings.

[0020] Furthermore, the X-axis, Y-axis, and Z-axis shown in each figure are used to describe the configuration and structure of each part. The X-axis, Y-axis, and Z-axis are orthogonal to each other and represent the X-direction, Y-direction, and Z-direction, respectively. Additionally, sometimes the Z-direction is regarded as the upper side, and the opposite direction is regarded as the lower side for description.

[0021] (First Embodiment)

[0022] Figure 1 FIG. 7 is a schematic cross-sectional view showing a semiconductor device 1A according to the first embodiment. The semiconductor device 1A is, for example, an IGBT (Insulated Gate Bipolar Transistor).

[0023] As Figure 1 shown, the semiconductor device 1A includes a semiconductor portion 10, a first electrode 20, a second electrode 30, and a control electrode 40. The first electrode 20 is, for example, a collector electrode. The second electrode 30 is, for example, an emitter electrode. The control electrode 40 is, for example, a gate electrode.

[0024] The first electrode 20 and the second electrode 30 are disposed at opposing positions, and the semiconductor portion 10 is disposed between the first electrode 20 and the third electrode 30. The first electrode 20 is, for example, disposed on the back surface of the semiconductor portion 10. The second electrode 30 is disposed on the surface side of the semiconductor portion 10. The semiconductor portion 10 is, for example, silicon. The first electrode 20 and the second electrode 30 are, for example, metal layers containing aluminum.

[0025] The semiconductor portion 10, for example, includes a first semiconductor layer 11 of a first conductivity type, a second semiconductor layer 13 of a second conductivity type, a third semiconductor layer 15 of the first conductivity type, a fourth semiconductor layer 19 of the second conductivity type, and a fifth semiconductor layer 21 of the second conductivity type. Hereinafter, the first conductivity type is assumed to be n-type, and the second conductivity type is assumed to be p-type for description.

[0026] The first semiconductor layer 11 is, for example, an n-type base layer. The first semiconductor layer 11 extends between the first electrode 20 and the second electrode 30.

[0027] The second semiconductor layer 13 is, for example, a p-type base layer. The second semiconductor layer 13 is disposed between the first semiconductor layer 11 and the second electrode 30. The second semiconductor layer 13 is, for example, electrically connected to the second electrode 30 via a sixth semiconductor layer 17 of the second conductivity type. The sixth semiconductor layer 17 is, for example, a p-type emitter layer and contains a second conductivity type impurity having a concentration higher than the concentration of the second conductivity type impurity in the second semiconductor layer 13.

[0028] The third semiconductor layer 15 is, for example, an n-type emitter layer. The third semiconductor layer 15 is selectively disposed between the second semiconductor layer 13 and the second electrode 30. The third semiconductor layer 15 is electrically connected to the second electrode 30.

[0029] The fourth semiconductor layer 19 is, for example, a p-type collector layer. The fourth semiconductor layer 19 is provided between the first semiconductor layer 11 and the first electrode 20. The fourth semiconductor layer 19 is electrically connected to the first electrode 20.

[0030] The control electrode 40 is disposed inside a trench GT provided on the surface side of the semiconductor portion 10. The trench GT has a depth from the surface (upper surface) of the third semiconductor layer 17 to the first semiconductor layer 11.

[0031] The control electrode 40 is, for example, conductive polysilicon. The control electrode 40 is electrically insulated from the first semiconductor layer 11, the second semiconductor layer 13, the third semiconductor layer 15, and the sixth semiconductor layer 17 by a first insulating film 43. The first insulating film 43 is, for example, a gate insulating film. The first insulating film 43 is, for example, a silicon oxide film.

[0032] The control electrode 40 is provided between the semiconductor portion 10 and the second electrode 30. The control electrode 40 is electrically insulated from the second electrode 30 by a second insulating film 45. The second insulating film 45 is, for example, an interlayer insulating film. The second insulating film 45 is, for example, a silicon oxide film.

[0033] The control electrode 40 includes a portion located in the first semiconductor layer 11 and faces the first semiconductor layer 11 with the first insulating film 43 therebetween. In addition, the control electrode 40 faces the second semiconductor layer 13 with the first insulating film 43 therebetween. That is, the first insulating film 43 is provided between the first semiconductor layer 11 and the control electrode 40, and between the second semiconductor layer 13 and the control electrode 40. The third semiconductor layer 15 is in contact with the first insulating film 43.

[0034] A plurality of control electrodes 40 are provided and arranged, for example, in a direction (e.g., the X direction) along the boundary between the first semiconductor layer 11 and the second semiconductor layer 13. The plurality of control electrodes 40 include a first control electrode 40a and a second control electrode 40b.

[0035] For example, the third semiconductor layer 15 is provided between the first control electrode 40a and the second control electrode 40b. The fifth semiconductor layer 21 is also provided between the first control electrode 40a and the second control electrode 40b.

[0036] The fifth semiconductor layer 21 is located in the first semiconductor layer 11. The fifth semiconductor layer 21 contains, for example, a second conductive-type impurity having a concentration higher than the concentration of the second conductive-type impurity in the second semiconductor layer 13. The first semiconductor layer 11 includes a portion located between the second semiconductor layer 13 and the fifth semiconductor layer 21, and a portion located between the fifth semiconductor layer 21 and the first insulating film 43.

[0037] Figure 2Figures (a) and (b) show schematic cross-sectional views of the operation of the semiconductor device 1A according to the first embodiment. Figure 2 Figure (a) shows Figure 1 a schematic view of a part of the cross-section shown in Figure 2 Figure (b) shows Figure 2 a schematic view of the A-A cross-section shown in Figure (a) of

[0038] Figure 2 Figure (a) shows the flow of electrons and holes in the semiconductor device 1A in the on state. For example, if a gate voltage (on voltage) higher than the threshold voltage of the control electrode 40 is applied between the first electrode 30 and the control electrode 40, an inversion layer of the first conductivity type is induced at the interface between the second semiconductor layer 13 and the first insulating film 43. As a result, electrons are injected from the third semiconductor layer 15 into the first semiconductor layer 11 via the inversion layer. Correspondingly, holes are injected from the fourth semiconductor layer 19 into the first semiconductor layer 11.

[0039] As Figure 2 shown in Figure (b), the second semiconductor layer 13 extends, for example, in the Y direction between the first semiconductor layer 11 and the second electrode 30. The third semiconductor layer 15 and the sixth semiconductor layer 17 are alternately arranged, for example, in the extending direction of the second semiconductor layer 13.

[0040] The fifth semiconductor layer 21 includes a first portion 21a and a second portion 21b. The first portion 21a is disposed below the third semiconductor layer 15. In addition, the first portion 21a is disposed in the first semiconductor layer 11 between the third semiconductor layer 15 and the fourth semiconductor layer 19. The first semiconductor layer 11 includes a portion located between the second semiconductor layer and the first portion 21a.

[0041] On the other hand, the second portion 21b is disposed below the sixth semiconductor layer 17. The second portion 21b is disposed between the first semiconductor layer 11 and the sixth semiconductor layer 17. In addition, the second portion 21b is disposed between the first semiconductor layer 11 and the second semiconductor layer 13 and is electrically connected to the second semiconductor layer 13.

[0042] The first portion 21a is disposed in a manner connected to the second portion 21b. That is, the first portion 21a is electrically connected to the second semiconductor layer 13 via the second portion 21b.

[0043] Figure 2 Figure (b) shows the flow of electrons and holes when the semiconductor device 1A is turned off. For example, if the gate voltage applied between the first electrode 30 and the control electrode 40 is reduced to a turn-off voltage lower than the threshold voltage of the control electrode 40, the inversion layer induced at the interface between the second semiconductor layer 13 and the first insulating film 43 disappears.

[0044] When the electron injection from the third semiconductor layer 15 to the first semiconductor layer 11 via the inversion layer stops, the turn-off process of the semiconductor device 1A starts. As the electron injection to the first semiconductor layer 11 stops, the hole injection from the fourth semiconductor layer 19 to the first semiconductor layer 11 also stops. Therefore, the voltage between the first electrode 20 and the second electrode 30 rises, and the first semiconductor layer 11 is depleted. The electrons in the first semiconductor layer 11 are discharged to the first electrode 20 via the fourth semiconductor layer 19. The holes in the first semiconductor layer 11 are discharged to the second electrode 30 via the second semiconductor layer 13 and the sixth semiconductor layer 17.

[0045] In the semiconductor device 1A, since a fifth semiconductor layer 21 is provided between the first semiconductor layer 11 and the second semiconductor layer 13, the discharge of holes to the second electrode 30 is promoted.

[0046] As Figure 2 shown in (b) of [], the electrons in the first semiconductor layer 11 are discharged to the first electrode 20 via the fourth semiconductor layer 19. On the other hand, the holes in the first semiconductor layer 11 are discharged to the second electrode 30 via the second part 21b of the fifth semiconductor layer 21, the second semiconductor layer 13, and the sixth semiconductor layer 17. In addition, the holes in the first semiconductor layer 11 move from the first part 21a of the fifth semiconductor layer 21 to the second part 21b and are also discharged through the path via the second semiconductor layer 13 and the sixth semiconductor layer 17. Thereby, the electrons and holes in the first semiconductor layer 11 can be efficiently discharged to the first electrode 20 and the second electrode 30, and the first semiconductor layer 11 is depleted.

[0047] Furthermore, the hole injection to the part of the second semiconductor layer 13 between the first semiconductor layer 11 and the third semiconductor layer 15 can be suppressed from detouring to the sixth semiconductor layer 17 through the first part 21b of the fifth semiconductor layer 21 and then through the first part 21a of the fifth semiconductor layer 21. The impurity concentration of the first part 21a can be higher than the impurity concentration of the first semiconductor layer 11. Thereby, the influence of the conduction of the parasitic npn transistor composed of the first semiconductor layer 11, the second semiconductor layer 13, and the third semiconductor layer 15 can be reduced.

[0048] Figure 3 (a) and (b) of [] are characteristic curves showing the semiconductor device 1A of the first embodiment. Figure 3 (a) of [] shows the relationship between the voltage Vce and the current Ic between the first electrode 20 and the second electrode 30 in the on state. Figure 3(b) shows the time variations of the current Ic and the voltage Vce between the first electrode 20 and the second electrode 30 during the turn-off process. In each figure, the characteristics of the semiconductor device 1A and the semiconductor device CE of the comparative example are shown. The semiconductor device CE is different from the semiconductor device 1A in that it does not have the fifth semiconductor layer 21.

[0049] As Figure 3 shown in (a), the on-current of the semiconductor device 1A is smaller than that of the semiconductor device CE. This reflects that by providing the first portion 21a of the fifth semiconductor layer 21, the path of the electron current becomes narrower (see Figure 2 (a)), and the on-resistance becomes larger.

[0050] On the other hand, at time t1, when the gate voltage is set below the threshold voltage of the control electrode 40, as Figure 3 shown in (b), the voltage Vce of the semiconductor device 1A rises earlier than the Vce of the semiconductor device CE. In addition, the current Ic of the semiconductor device 1A decreases earlier than the Ic of the semiconductor device CE. Thus, by providing the fifth semiconductor layer 21, the turn-off time can be shortened and the switching loss can be reduced.

[0051] Figure 4 is a graph showing other characteristics of the semiconductor device of the first embodiment. In this figure, the characteristics of the semiconductor device 1A and the semiconductor device CE of the comparative example are shown.

[0052] For example, during the turn-off process, if the parasitic npn transistor is turned on, the current Ic increases, and a so-called snap back phenomenon in which the voltage Vce decreases occurs. As Figure 4 shown, the current Ic increases and the voltage Vce decreases, and then the voltage Vce turns to rise. The larger the decrease amount of the voltage Vce in this process, the easier it is to generate current concentration via the parasitic npn transistor, and the breakdown withstand voltage of the semiconductor device decreases.

[0053] In Figure 4 the example shown, compared with the semiconductor device CE, the decrease in the voltage Vce of the semiconductor device 1A is suppressed. This means that the current flowing when the parasitic npn transistor is turned on is reduced. That is, in the semiconductor device 1A, by providing the fifth semiconductor layer 21, the breakdown withstand voltage during turn-off can be improved.

[0054] Figure 5 (a) to (c) are schematic views showing the semiconductor device 1B of the first modification of the first embodiment.

[0055] Figure 5 (a) shows between the adjacent first control electrode 40a and the second control electrode 40b (seeFigure 1 ) Perspective view of the first semiconductor layer 11, the second semiconductor layer 13, the third semiconductor layer 15, and the sixth semiconductor layer 17.

[0056] Figure 5 (b) thereof is a perspective view showing the fifth semiconductor layer 21. Figure 5 (c) thereof is a cross-sectional view of the fifth semiconductor layer 21 along the Y-Z plane.

[0057] As Figure 5 shown in (a) to (c) of , the fifth semiconductor layer 21 includes a first portion 21a, a second portion 21b, and a third portion 21c. The third portion 21c is provided in a manner that connects the first portion 21a and the second portion 21b.

[0058] The first portion 21a is electrically connected to the second portion 21b via the third portion 21c. The first portion 21a is provided in a manner that extends from below the third semiconductor layer 15 to below the sixth semiconductor layer 17.

[0059] As Figure 5 shown in (a) of , the second portion 21b is provided to face the control electrode 40 with a first insulating film 43 (not shown) therebetween. That is, by increasing the width of the second portion 21b in the X direction, the resistance to the discharge of holes from the first semiconductor layer 11 to the second electrode 30 is reduced. On the other hand, the path of the electron current flowing from the third semiconductor layer 15 to the first semiconductor layer 11 is limited to the region where the second portion 21b is not provided.

[0060] Figure 6 (a) to (c) of are schematic views showing a semiconductor device 1C according to a second modification of the first embodiment.

[0061] Figure 6 (a) of is a perspective view of the first semiconductor layer 11, the second semiconductor layer 13, the third semiconductor layer 15, and the sixth semiconductor layer 17 between an adjacent first control electrode 40a and a second control electrode 40b (see Figure 1 ).

[0062] Figure 6 (b) thereof is a perspective view showing the fifth semiconductor layer 21. Figure 6 (c) thereof is a cross-sectional view of the fifth semiconductor layer 21 along the Y-Z plane.

[0063] As Figure 6 shown in (a) to (c) of , the fifth semiconductor layer 21 includes a first portion 21a, a second portion 21b, and a third portion 21c. The third portion 21c is provided in a manner that connects the first portion 21a and the second portion 21b.

[0064] The first part 21a is electrically connected to the second part 21b via the third part 21c. The first part 21a is arranged to extend from below the third semiconductor layer 15 to below the sixth semiconductor layer 17. In this example, the width WB of the second part 21b in the X direction is substantially the same as the width WA of the first part 21a in the X direction.

[0065] The first semiconductor layer 11 includes a portion located between the second part 21b of the fifth semiconductor layer 21 and the first insulating film 43 (not shown). Thereby, the path of the electron current flowing from the third semiconductor layer 15 to the first semiconductor layer 11 also extends to the region between the first semiconductor layer 11 and the sixth semiconductor layer 17. That is, in the semiconductor device 1C, the on-resistance can be reduced.

[0066] Figure 7 FIGS. (a) and (b) are schematic views showing a semiconductor device 1D according to a third modification of the first embodiment.

[0067] Figure 7 FIG. (a) shows a three-dimensional view of the first semiconductor layer 11, the second semiconductor layer 13, the third semiconductor layer 15, and the sixth semiconductor layer 17 between the adjacent first control electrode 40a and the second control electrode 40b (see Figure 1 ). Figure 7 FIG. (b) is a three-dimensional view showing the fifth semiconductor layer 21.

[0068] In this example, the fifth semiconductor layer 21 includes the second part 21b and two first parts 21a. The two first parts 21a are arranged in the X direction, for example. The first semiconductor layer 11 includes a portion located between the two first parts 21a and a portion located between the first part 21a and the first insulating film 43. Thereby, the path of the electron current flowing from the third semiconductor layer 15 to the first semiconductor layer 11 via the inversion layer can be expanded.

[0069] As Figure 7 shown in FIG. (a), the second part 21b is arranged to face the control electrode 40 via the first insulating film 43 (not shown). That is, by expanding the width of the second part 21b in the X direction, the resistance to the discharge of holes from the first semiconductor layer 11 to the second electrode 30 is reduced.

[0070] Figure 8 FIGS. (a) to (c) are schematic views illustrating the fifth semiconductor layer 21 according to a modification of the first embodiment. Figure 8 FIGS. (a) and (c) are three-dimensional views, Figure 8 and FIG. (b) is a Y-Z cross-sectional view. In any of the examples, the fifth semiconductor layer 21 includes the first part 21a and the second part 21b, and the first part 21a is electrically connected to the second part 21b.

[0071] In Figure 8 In the example shown in (a) of Figure 8 , the first part 21a is arranged to protrude from the side surface of the second part 21b in the -Y direction (the opposite direction of the Y direction).

[0072] In Figure 8 In the example shown in (b) of Figure 8 , the first part 21a is arranged to protrude obliquely downward from the side surface of the second part 21b. The first part 21a is arranged at a position separated from the second semiconductor layer 13 in the Z direction. Thus, holes can be efficiently discharged from the first semiconductor layer 11 via the first part 21a.

[0073] In Figure 8 In the example shown in (c) of Figure 8 , two first parts 21a are provided. The two first parts 21a are arranged, for example, in the X direction, and the interval between the two first parts 21a becomes narrower as they move away from the second part 21b. Thus, the path of the electron current flowing from the third semiconductor layer 15 to the first semiconductor layer 11 via the inversion layer can be widened, and holes can be efficiently discharged from the first semiconductor layer 11.

[0074] Figure 9 (a) and (b) of Figure 9 are schematic views showing the semiconductor device 2A of the fourth modification of the first embodiment.

[0075] Figure 9 (a) of Figure 9 is a perspective view showing the first semiconductor layer 11, the second semiconductor layer 13, the third semiconductor layer 15, and the sixth semiconductor layer 17 between the adjacent first control electrode 40a and the second control electrode 40b (see Figure 1 ). Figure 9 (b) of Figure 9 is a cross-sectional view of the fifth semiconductor layer 21 along the Y-Z plane.

[0076] As Figure 9 shown in (a) of Figure 9 , the fifth semiconductor layer 21 further includes a fourth part 21d. The fourth part 21d is provided below the first part 21a. The width WD in the X direction of the fourth part 21d is narrower than the width WA in the X direction of the first part 21a (see Figure 6 (b) of Figure 6 ). In addition, the second part 21b is arranged to face the control electrode 40 via a first insulating film 43 (not shown).

[0077] As Figure 9 shown in (b) of Figure 9 , the first part 21a is located between the second part 21b and the fourth part 21d. The fourth part 21d is electrically connected to the first part 21a via the third part 21c. In addition, the first part 21a is electrically connected to the second part 21b via the third part 21c.

[0078] The fourth portion 21d is disposed so as to extend from below the third semiconductor layer 13 to below the sixth semiconductor layer 17. In this example, by adding the fourth portion 21d, holes in the first semiconductor layer 11 can be discharged more efficiently.

[0079] Figure 10 (a) and (b) thereof are schematic views showing semiconductor devices 2B and 2C of a fifth modification of the first embodiment. Figure 10 (a) and (b) thereof are perspective views of the first semiconductor layer 11, the second semiconductor layer 13, the third semiconductor layer 15, and the sixth semiconductor layer 17 between an adjacent first control electrode 40a and second control electrode 40b (see Figure 1 ).

[0080] In Figure 10 the semiconductor device 2B shown in (a) thereof, the fifth semiconductor layer 21 includes two fourth portions 21d arranged in the Z direction. The two fourth portions 21d are electrically connected to each other via a third portion 21c (not shown) and are electrically connected to the first portion 21a (see Figure 9 (b) thereof).

[0081] In Figure 10 the semiconductor device 2C shown in (b) thereof, the fifth semiconductor layer 21 includes three fourth portions 21d arranged in the Z direction. The three fourth portions 21d are electrically connected to each other via a third portion 21c (not shown) and are electrically connected to the first portion 21a (see Figure 9 (b) thereof).

[0082] Thus, by arranging a plurality of fourth portions 21d in the Z direction, holes in the first semiconductor layer 11 can be discharged more effectively.

[0083] Figure 11 (a) and (b) thereof are schematic views showing semiconductor devices 3A and 3B of a sixth modification of the first embodiment. Figure 11 (a) and (b) thereof are perspective views of the first semiconductor layer 11, the second semiconductor layer 13, the third semiconductor layer 15, and the sixth semiconductor layer 17 between an adjacent first control electrode 40a and second control electrode 40b (see Figure 1 ).

[0084] In Figure 11 the semiconductor device 3A shown in (a) thereof, the first portion 21a of the fifth semiconductor layer 21 is disposed so as to extend in the Z direction below the third semiconductor layer 15. In addition, the first portion 21a also extends in the Y direction and is electrically connected to the second portion 21b below the sixth semiconductor layer 17. In addition, the second portion 21b is disposed so as to face the control electrode 40 via a first insulating film 43 (not shown).

[0085] In this example, a seventh semiconductor layer 23 of a first conductivity type is also provided between the first part 21a of the fifth semiconductor layer 21 and the first insulating film 43. The seventh semiconductor layer 23 is provided so as to extend along the first insulating film 43 in, for example, the Y direction and the Z direction. The seventh semiconductor layer 23 contains a first conductivity type impurity having a concentration higher than that of the first conductivity type impurity in the first semiconductor layer 11.

[0086] The first semiconductor layer 11 includes a portion located between the first part 21a of the fifth semiconductor layer 21 and the seventh semiconductor layer 23.

[0087] In this example, by extending the first part 21a of the fifth semiconductor layer 21 in the Z direction, holes in the first semiconductor layer 11 can be efficiently discharged. Further, by providing the seventh semiconductor layer 23, the resistance of the path of the electron current from the third semiconductor layer 15 to the first semiconductor layer 11 via the inversion layer can be reduced. Thereby, the on-resistance of the semiconductor device 3A can be reduced.

[0088] Figure 11 The semiconductor device 3B shown in (b) also includes the first part 21a of the fifth semiconductor layer 21 extending in the Z direction and the seventh semiconductor layer 23. Further, the width WB in the X direction of the second part 21b of the fifth semiconductor layer 21 is set to be substantially the same as the width WA in the X direction of the first part 21a (see Figure 6 (b)). Thereby, the first semiconductor layer 11 also includes a portion located between the second part 21b and the first insulating film 43. Therefore, the on-resistance of the semiconductor device 3B can be further reduced.

[0089] (Second Embodiment)

[0090] Figure 12 FIG. is a schematic cross-sectional view showing a semiconductor device 4 according to the second embodiment. The semiconductor device 4 includes, for example, a first semiconductor layer 111 of a first conductivity type, a second semiconductor layer 113 of a second conductivity type, a third semiconductor layer 115 of a first conductivity type, a fourth semiconductor layer 119 of a second conductivity type, a fifth semiconductor layer 121 of a second conductivity type, and a sixth semiconductor layer 117 of a second conductivity type. In addition, the semiconductor device 4 includes a first electrode 120, a second electrode 130, a control electrode 140, and a first insulating film 143.

[0091] As Figure 12 shown, the control electrode 140 is, for example, a gate electrode and is selectively provided on the first semiconductor layer 111. The first semiconductor layer 111 is, for example, an n-type base layer. The first insulating film 143 is provided between the first semiconductor layer 111 and the control electrode 140. The first insulating film 143 is, for example, a gate insulating film. That is, the semiconductor device 4 is an IGBT having a planar gate structure.

[0092] The second semiconductor layer 113 is, for example, a p-type base layer. The second semiconductor layer 113 is selectively provided on the first semiconductor layer 111. The second semiconductor layer 113 includes a portion located between the first semiconductor layer 111 and the first insulating film 143. That is, the second semiconductor layer 113 includes a portion facing the control electrode 140 with the first insulating film 143 interposed therebetween.

[0093] The third semiconductor layer 115 is, for example, an n-type emitter layer. The third semiconductor layer 115 is selectively provided on the second semiconductor layer 113. The third semiconductor layer 115 is arranged side by side with the portion of the second semiconductor layer 113 facing the control electrode 140.

[0094] The fourth semiconductor layer 119 is, for example, a p-type collector layer. The fourth semiconductor layer 119 is selectively provided above the first semiconductor layer 111. The fourth semiconductor layer 119 is provided at a position separated from the second semiconductor layer 113.

[0095] The fifth semiconductor layer 121 is provided in the second semiconductor layer 113. The fifth semiconductor layer 121 is provided between the first semiconductor layer 111 and the third semiconductor layer 115. The fifth semiconductor layer 121 contains second-conductive-type impurities having a concentration higher than the concentration of the second-conductive-type impurities in the second semiconductor layer 113.

[0096] The sixth semiconductor layer 117 is, for example, a p-type emitter layer. The sixth semiconductor layer 117 is selectively provided on the second semiconductor layer 113, and is arranged side by side with the portion of the second semiconductor layer 113 facing the control electrode 140 and the third semiconductor layer 115.

[0097] The fifth semiconductor layer 121 includes a first portion 121a provided between the first semiconductor layer 111 and the third semiconductor layer 115, and a second portion 121b electrically connected to the sixth semiconductor layer 117. The first portion 121a is electrically connected to the sixth semiconductor layer 117 via the second portion 121b.

[0098] The first electrode 120 is electrically connected to the fourth semiconductor layer 119. The second electrode 130 is electrically connected to the third semiconductor layer 115 and the sixth semiconductor layer 117.

[0099] During the turn-off process of the semiconductor device 4, electrons in the first semiconductor layer 111 are discharged to the first electrode 120 via the fourth semiconductor layer 119. Holes in the first semiconductor layer 111 are discharged to the second electrode 130 via the second semiconductor layer 113 and the sixth semiconductor layer 117.

[0100] In the semiconductor device 4, since the fifth semiconductor layer 121 is provided in the second semiconductor layer 113, holes can be efficiently discharged from the second semiconductor layer 113 to the sixth semiconductor layer 117. As a result, the influence of the turn-on of the parasitic npn transistor formed by the second semiconductor layer 113, the third semiconductor layer 115, and the sixth semiconductor layer 117 can be reduced, and the breakdown tolerance of the semiconductor device 4 can be improved.

[0101] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope or gist of the invention and are included in the invention described in the claims and its equivalents.

Claims

1. A semiconductor device comprising: A first electrode; A second electrode opposed to the first electrode; A first semiconductor layer of a first conductivity type provided between the first electrode and the second electrode; A second semiconductor layer of a second conductivity type provided between the first semiconductor layer and the second electrode and electrically connected to the second electrode; The third semiconductor layer of the first conductivity type selectively provided between the second semiconductor layer and the second electrode and electrically connected to the second electrode; The fourth semiconductor layer of the second conductivity type provided between the first semiconductor layer and the first electrode and electrically connected to the first electrode; A plurality of control electrodes respectively provided inside trenches extending from the third semiconductor layer to the first semiconductor layer in a first direction from the second electrode toward the first electrode and arranged in a second direction along the boundary between the first semiconductor layer and the second semiconductor layer; A first insulating film provided between each of the plurality of control electrodes and the first semiconductor layer and between each of the plurality of control electrodes and the second semiconductor layer; And The fifth semiconductor layer of the second conductivity type includes a first portion and a second portion between adjacent first control electrode and second control electrode among the plurality of control electrodes. The first portion is provided in the first semiconductor layer, the second portion is provided between the first semiconductor layer and the second semiconductor layer and is electrically connected to the first portion and the second semiconductor layer. The first portion is located between the third semiconductor layer and the fourth semiconductor layer. The fifth semiconductor layer includes a pair of the first portions. The pair of first portions are arranged in the second direction. One of the pair of first portions extends in a fourth direction which is along the boundary between the first semiconductor layer and the second semiconductor layer and intersects with the second direction. The other of the pair of first portions extends in a fifth direction which is along the boundary between the first semiconductor layer and the second semiconductor layer and intersects with the second direction and the fourth direction. The interval between the pair of first portions is narrower at the front end extending from the second portion than at the portion connected to the second portion.

2. The semiconductor device according to claim 1, wherein The first semiconductor layer includes a portion located between the first portion of the fifth semiconductor layer and the first insulating film.

3. The semiconductor device according to claim 2, wherein The first semiconductor layer includes a portion located between the second portion of the fifth semiconductor layer and the first insulating film.

4. The semiconductor device according to claim 1, wherein It further includes a sixth semiconductor layer of the second conductivity type. The sixth semiconductor layer is selectively provided between the second semiconductor layer and the second electrode and is arranged side by side with the third semiconductor layer along the second semiconductor layer. The sixth semiconductor layer is located between the second portion of the fifth semiconductor layer and the second electrode. The sixth semiconductor layer contains a second-conductivity-type impurity having a concentration higher than that of the second-conductivity-type impurity in the second semiconductor layer. The second semiconductor layer is electrically connected to the second electrode via the sixth semiconductor layer.

5. The semiconductor device according to claim 4, wherein the fifth semiconductor layer contains a second-conductivity-type impurity having a concentration higher than that of the second-conductivity-type impurity in the second semiconductor layer.

6. The semiconductor device according to claim 1, wherein the fifth semiconductor layer has the first portion extending in a third direction from the second portion, the third direction being a direction along the boundary between the first semiconductor layer and the second semiconductor layer and orthogonal to the second direction.

7. The semiconductor device according to claim 1, wherein the fifth semiconductor layer further includes a third portion disposed between the first portion and the second portion and electrically connecting the first portion and the second portion.

8. The semiconductor device according to claim 1, wherein the fifth semiconductor layer contains a plurality of the first portions, the plurality of first portions being arranged in the second direction.

9. The semiconductor device according to claim 1, wherein in a cross section including the first direction and the third direction, the fifth semiconductor layer includes the first portion extending in a direction intersecting the first direction and the third direction from the second portion toward the first electrode, the third direction being a direction along the boundary between the first semiconductor layer and the second semiconductor layer and orthogonal to the second direction.

10. The semiconductor device according to claim 7, wherein the fifth semiconductor layer further includes: at least one fourth portion arranged side by side with the second portion in the first direction; and another third portion electrically connecting the first portion and the fourth portion via the second portion and the third portion, the first portion and the second portion being located between the fourth portion and the second semiconductor layer.

11. The semiconductor device according to claim 1, wherein a seventh semiconductor layer is further provided, the seventh semiconductor layer being disposed between the fifth semiconductor layer and the first insulating film and containing a first-conductivity-type impurity having a concentration higher than that of the first-conductivity-type impurity in the first semiconductor layer.

12. A semiconductor device includes: a first semiconductor layer of a first conductivity type; a control electrode disposed on the first semiconductor layer; a first insulating film disposed between the first semiconductor layer and the control electrode; a second semiconductor layer of a second conductivity type selectively disposed on the first semiconductor layer and including a portion facing the control electrode with the first insulating film therebetween; the first-conductivity-type third semiconductor layer selectively disposed on the second semiconductor layer and arranged side by side with the portion of the second semiconductor layer facing the control electrode; the second-conductivity-type fourth semiconductor layer disposed at a position separated from the second semiconductor layer on the first semiconductor layer; The fifth semiconductor layer of the second conductivity type is disposed in the second semiconductor layer between the first semiconductor layer and the third semiconductor layer, and contains second conductivity type impurities having a concentration higher than that of the second conductivity type impurities in the second semiconductor layer; The sixth semiconductor layer of the second conductivity type is selectively disposed on the second semiconductor layer, is arranged side by side with the portion of the second semiconductor layer opposite to the control electrode and the third semiconductor layer, and is electrically connected to the fifth semiconductor layer; And A seventh semiconductor layer is disposed between the fifth semiconductor layer and the first insulating film, and contains first conductivity type impurities having a concentration higher than that of the first conductivity type impurities in the first semiconductor layer.

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