Semiconductor device

Abstract

An embodiment provides a semiconductor device with a high yield. The semiconductor device of the embodiment has a first electrode and a substrate. The substrate has a first surface contacted by the first electrode and a second surface opposed to the first surface. On the first surface, there is a first groove whose length in a second direction intersecting the first direction and parallel to the first surface is shorter than the length in the first direction parallel to the first surface. The substrate has: a first semiconductor layer of a first conductivity type, a second semiconductor layer provided between the first semiconductor layer and the second surface and having an impurity concentration of the first conductivity type higher than that of the first semiconductor layer, a first semiconductor region of a second conductivity type provided between the second semiconductor layer and the second surface, a second semiconductor region of the first conductivity type provided between the first semiconductor region and the second surface, and a second electrode provided to face the first semiconductor region with a first insulating film interposed therebetween in a first trench extending from the second surface to the second semiconductor layer and extending in the second direction.

Description

[0001] Related Application

[0002] This application claims priority based on Japanese Patent Application No. 2020-157832 (filing date: September 18, 2020). This application incorporates the entire contents of the base application by reference thereto. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices. Background Art

[0004] Semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used for applications such as power conversion. Regarding such semiconductor devices, semiconductor devices with high yield are desired. Summary of the Invention

[0005] Embodiments of the present invention provide semiconductor devices with high yield.

[0006] The semiconductor device of the embodiment has a first electrode and a substrate. The substrate has a first surface in contact with the first electrode and a second surface facing the first surface. The first surface of the substrate has a first groove whose length in a second direction is less than the length in a first direction. The first direction is parallel to the first surface, the second direction intersects the first direction and is parallel to the first surface. The substrate has: a first semiconductor layer of a first conductivity type, a second semiconductor layer provided between the first semiconductor layer and the second surface and having a higher impurity concentration of the first conductivity type than the first semiconductor layer, a first semiconductor region of a second conductivity type provided between the second semiconductor layer and the second surface, a second semiconductor region of the first conductivity type provided between the first semiconductor region and the second surface, and a second electrode provided in a first trench extending from the second surface to the second semiconductor layer and extending in the second direction and facing the first semiconductor region with a first insulating film therebetween. Description of the Drawings

[0007] Figure 1 is a schematic circuit diagram of the semiconductor device of the first embodiment.

[0008] Figure 2 is a schematic top view of the semiconductor device of the first embodiment.

[0009] Figure 3 is a schematic cross-sectional view of the semiconductor device of the first embodiment.

[0010] Figure 4 is a schematic cross-sectional view of the main part of the semiconductor device of the first embodiment.

[0011] Figure 5 It is another example of a schematic cross-sectional view of the main part of the semiconductor device according to the first embodiment.

[0012] Figure 6 It is a schematic cross-sectional view of the main part of the semiconductor device according to the first embodiment.

[0013] Figure 7 It is another example of a schematic cross-sectional view of the main part of the semiconductor device according to the first embodiment.

[0014] Figure 8 It is a schematic cross-sectional view of the main part of the semiconductor device according to the first embodiment.

[0015] Figure 9 It is a schematic cross-sectional view of the main part of the semiconductor device according to the first embodiment.

[0016] Figure 10 It is a schematic cross-sectional view of the semiconductor device that is a comparative mode of the first embodiment.

[0017] Figure 11 It is a schematic diagram of the main part of the semiconductor device according to the second embodiment.

[0018] Figure 12 It is a schematic cross-sectional view of the main part showing the manufacturing process of the semiconductor device according to the second embodiment.

[0019] Figure 13 It is a schematic diagram of the main part of the semiconductor device according to the third embodiment.

[0020] Figure 14 It is a schematic diagram of the main part of the semiconductor device according to the fourth embodiment.

[0021] Figure 15 It is a schematic diagram of the main part of the semiconductor device according to the fifth embodiment.

[0022] Figure 16 It is a schematic diagram of the main part of the semiconductor device according to the sixth embodiment. Detailed Embodiments

[0023] Hereinafter, embodiments of the present invention will be described while referring to the appended Figure 1 drawings. In addition, in the following description, the same reference numerals are given to the same components, etc., and the description of the components, etc., that have been described once is appropriately omitted.

[0024] In this specification, in order to represent the positional relationship of components, etc., the upper direction of the drawing is described as "upper", and the lower direction of the drawing is described as "lower". In this specification, the concepts of "upper" and "lower" are not necessarily terms indicating the relationship with the direction of gravity.

[0025] Hereinafter, an example in which the first conductivity type is n-type and the second conductivity type is p-type will be described.

[0026] In the following description, n + , n, n － and p + , p, p － marks indicate the relative levels of impurity concentrations in each conductivity type. That is, n + indicates that the impurity concentration of the n-type is relatively higher compared to n, and n － indicates that the impurity concentration of the n-type is relatively lower compared to n. Also, p + indicates that the impurity concentration of the p-type is relatively higher compared to p, and p － indicates that the impurity concentration of the p-type is relatively lower compared to p. In addition, there are cases where the n + type and n － type are only recorded as the n-type, and the p + type and p － type are only recorded as the p-type.

[0027] (First Embodiment)

[0028] The semiconductor device of this embodiment has a first electrode and a substrate. The substrate has a first surface in contact with the first electrode and a second surface opposite to the first surface. The first surface of the substrate has a first groove whose length in the second direction is smaller than the length in the first direction. The first direction is parallel to the first surface, and the second direction intersects the first direction and is parallel to the first surface. The substrate includes: a first semiconductor layer of the first conductivity type, a second semiconductor layer provided between the first semiconductor layer and the second surface and having a higher impurity concentration of the first conductivity type than the first semiconductor layer, a first semiconductor region of the second conductivity type provided between the second semiconductor layer and the second surface, a second semiconductor region of the first conductivity type provided between the first semiconductor region and the second surface, and a second electrode provided opposite to the first semiconductor region with a first insulating film interposed therebetween in a first trench extending from the second surface to the second semiconductor layer and extending in the second direction.

[0029] Furthermore, the substrate of the semiconductor device of this embodiment further includes a third semiconductor region of the second conductivity type provided between the second semiconductor layer and the second surface, a fourth semiconductor region of the first conductivity type provided between the third semiconductor region and the second surface, and a third electrode provided opposite to the third semiconductor region with a second insulating film interposed therebetween in a second trench extending from the second surface to the second semiconductor layer and extending in the second direction. The substrate has a first region and a second region. The first region includes the first semiconductor region, the second semiconductor region, and the second electrode. The second region is adjacent to the first region in the first direction and includes the third semiconductor region, the fourth semiconductor region, and the third electrode. The first groove straddles the first region and the second region.

[0030] Figure 1 is a schematic circuit diagram of the semiconductor device 100 of the present embodiment. The circuit of the semiconductor device 100 of the present embodiment is a circuit in which the drain of the first transistor Tr1 and the drain of the second transistor Tr2 are electrically connected. For example, the circuit of the semiconductor device 100 is a circuit for charging and discharging a secondary battery that can be charged and discharged. For example, Figure 1 the first current flowing from right to left in is the discharge current from the secondary battery. And, for example, Figure 1 the second current flowing from left to right in is the charging current to the secondary battery. Thus, the circuit of the semiconductor device 100 can flow the first current and the second current in opposite directions.

[0031] Here, consider the case where only the first transistor Tr1 is provided and the second transistor Tr2 is not provided. In this case, even if the first transistor Tr1 is to be turned off to stop the flow of the second current, the second current flows through the body diode BD1 of the first transistor Tr1.

[0032] And, consider the case where only the second transistor Tr2 is provided and the first transistor Tr1 is not provided. In this case, even if the second transistor Tr2 is to be turned off to stop the flow of the first current, the first current flows through the body diode BD2 of the second transistor Tr2.

[0033] Therefore, in the semiconductor device 100, the drain of the first transistor Tr1 and the drain of the second transistor Tr2 are electrically connected. By such a connection, the cathode of the body diode BD1 and the cathode of the body diode BD2 are electrically connected. Here, consider the case where the first transistor Tr1 and the second transistor Tr2 are turned off to stop the second current. In this case, even if the second current wants to flow through the body diode BD1 of the first transistor Tr1, since the cathode of the body diode BD2 and the cathode of the body diode BD1 are electrically connected, the second current does not flow. And, consider the case where the first transistor Tr1 and the second transistor Tr2 are turned off to stop the first current. In this case, even if the first current wants to flow through the body diode BD2 of the second transistor Tr2, since the cathode of the body diode BD1 and the cathode of the body diode BD2 are electrically connected, the first current does not flow. Thus, in the semiconductor device 100, the control of the first current and the second current can be performed.

[0034] Figure 2 is a schematic top view of the semiconductor device 100 of the present embodiment. Figure 3 is a schematic cross-sectional view of the semiconductor device 100 of the present embodiment. Figure 4 is a schematic cross-sectional view of the main part of the semiconductor device 100 of the present embodiment. Figure 5It is another example of a schematic cross-sectional view of the main part of the semiconductor device 100 of the present embodiment. Figure 6 It is a schematic cross-sectional view of the main part of the semiconductor device 100 of the present embodiment. Figure 7 It is another example of a schematic cross-sectional view of the main part of the semiconductor device 100 of the present embodiment.

[0035] Use Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 and Figure 7 to illustrate the semiconductor device 100 of the present embodiment.

[0036] The semiconductor device 100 includes a substrate 30. The substrate 30 has a first surface 32, a second surface 34, and a side surface 38. For example Figure 3 in (a) of Figure 3 and (b) of

[0037] a side surface 38a and a side surface 38b are provided as the side surface 38.

[0038] Here, an X direction (an example of the first direction), a Y direction (an example of the second direction) that intersects perpendicularly to the X direction, and a Z direction (an example of the third direction) that intersects perpendicularly to the X direction and the Y direction are defined. The first surface 32 and the second surface 34 are surfaces provided in parallel with respect to the XY plane parallel to the X direction and the Y direction.

[0038] Moreover, a first region 96 and a second region 98 ( Figure 2 ) are provided in the semiconductor device 100. The first region 96 and the second region 98 are respectively rectangular regions arranged side by side in the Y direction as shown in Figure 2 . In addition, for example, a first transistor Tr1 ( Figure 1 ) is provided in the first region 96, and a second transistor Tr2 ( Figure 1 ) is provided in the second region 98. The first transistor Tr1 and the second transistor Tr2 are respectively MOSFETs, for example, but are not limited thereto.

[0039] Figure 3 (a) of Figure 3 is a schematic cross-sectional view of a surface parallel to the XZ plane along the A - A' line of the first region 96. Figure 3 (b) of

[0040] is a schematic cross-sectional view of a surface parallel to the XZ plane along the B - B' line of the second region 98. Figure 3 (c) of

[0040] is a schematic cross-sectional view of a surface parallel to the YZ plane along the C - C' line straddling the first region 96 and the second region 98.

[0040] The drain electrode (an example of the first electrode) 60 is provided under the substrate 30 and contacts the first surface 32. In other words, the substrate 30 is provided above the drain electrode 60. The drain electrode 60 functions as a common drain electrode for the first transistor Tr1 and the second transistor Tr2.

[0041] The first surface 32 of the substrate 30 has a groove (an example of the first groove) 36 in which the length L2 in the Y direction is shorter than the length L1 in the X direction. Figure 3 In [it], grooves 36a, 36b, 36c, 36d, 36e, 36f, and 36g are illustrated as the groove 36. And, as shown in (a) of Figure 3 and Figure 3 (b) of [it], the grooves 36b and 36e do not penetrate the side surfaces 38 (side surfaces 38a and 38b) of the substrate 30. The other grooves 36a, 36c, 36d, 36f, and 36g also do not penetrate the side surfaces 38 of the substrate 30. In the case where a plurality of grooves 36 are provided, it is preferable that all the grooves 36 do not penetrate the side surfaces 38 of the substrate 30. And, the groove 36d straddles the first region 96 and the second region 98.

[0042] The volume ratio of the portion of the groove 36 with respect to the substrate 30 is preferably 5% or more and 20% or less.

[0043] The drain electrode 60 has a groove 66 (an example of the second groove) corresponding to the groove 36 by covering the groove 36 of the first surface 32. In other words, the bottom surface 62 of the drain electrode 60 has a groove (an example of the second groove) 66 in which the length L4 in the Y direction is shorter than the length L3 in the X direction under the groove 36. Figure 3 In [it], grooves 66a, 66b, 66c, 66d, 66e, 66f, and 66g are illustrated as the groove 66. Here, L3 < L1 and L4 < L2.

[0044] Figure 4 is a schematic cross-sectional view of the main part of the semiconductor device 100 in the first region 96.

[0045] A drain layer (an example of the first semiconductor layer) 10 is provided above the drain electrode 60. The drain layer 10 is, for example, an n + -type semiconductor material.

[0046] A drift layer (an example of the second semiconductor layer) 12 is provided above the drain layer 10. The drift layer 12 is a layer that functions as a drift layer of a MOSFET. The drift layer 12 is, for example, an n － -type semiconductor material.

[0047] The base region (an example of the first semiconductor region) 14 is provided above the drift layer 12. The base region 14 functions as the base of the MOSFET. The base region 14 is a region that can form a channel when a voltage is applied to the first gate electrode 28 described later and through which carriers flow between the drain layer 10 and the source region 16 described later. The base region 14 is, for example, a p-type semiconductor material.

[0048] The source region (an example of the second semiconductor region) 16 is provided above the base region 14. The source region 16 is a region that functions as the source of the MOSFET. When an appropriate voltage is applied to the first gate electrode 28 described later, carriers flow between the source region 16 and the drain layer 10. The source region 16 is, for example, an n + -type semiconductor material.

[0049] The contact region 18 is provided above the base region 14 and is electrically connected to the base region 14 and the source region 16. The contact region 18 is provided to improve the electrical contact between the base region 14 and the source region 16 and the source metal 70 described later. The contact region 18 is, for example, a p + -type semiconductor material.

[0050] The first trench 20 is provided so as to reach the drift layer 12 from above the base region 14 and the source region 16. The first trench 20 extends along the depth direction (Y direction) of the paper surface.

[0051] The third insulating film 22 is provided in the first trench 20. For example, the third insulating film 22 is provided so as to cover the first field plate electrode 24 described later. And, for example, the third insulating film 22 is provided between the first field plate electrode 24 and the first gate electrode 28. However, the manner of the third insulating film 22 is not limited to this. The third insulating film 22 contains SiO x (silicon oxide), but is not limited to this.

[0052] The first insulating film 21 is provided in the first trench 20 above the third insulating film 22, between the base region 14 and the first gate electrode 28, and between the interlayer insulating film 95 described later and the source region 16. The first insulating film 21 contains SiO x (silicon oxide) but is not limited to this.

[0053] The first field plate electrode 24 is provided in the first trench 20 opposite to the drift layer 12 with the third insulating film 22 interposed therebetween. For example, the first field plate electrode 24 is provided side by side with the drift layer 12. The first field plate electrode 24 is provided, for example, to promote the extension of the depletion layer from the base region 14 to the drift layer 12 and increase the breakdown voltage. In addition, the first field plate electrode 24 may not be provided.

[0054] The first gate electrode (an example of the second electrode) 28 is located above the first field plate electrode 24 and is disposed between a plurality of substrate regions 14 with the first insulating film 21 interposed therebetween. The first gate electrode 28 is an electrode that functions as the gate of the MOSFET.

[0055] An interlayer insulating film 95 is disposed above the source region 16, the first gate electrode 28, and the first insulating film 21. The interlayer insulating film 95 contains, for example, SiO x , but is not limited thereto.

[0056] Source metals 70 and source metal 74 ( Figure 3 in (a)) are disposed above the source region 16 and the contact region 18 and are electrically connected to the source region 16 and the contact region 18.

[0057] Figure 5 is another example of a schematic cross-sectional view of the main part of the semiconductor device 100 in the first region 96. The contact region 18 may not be provided.

[0058] Figure 6 is a schematic cross-sectional view of the main part of the semiconductor device 100 in the second region 98. For example, the drain electrode 60, the drain layer 10, and the drift layer 12 are provided in common with the first region 96.

[0059] On the other hand, in the second region 98, a substrate region (an example of the third semiconductor region) 54 is provided above the drift layer 12. A source region (an example of the fourth semiconductor region) 56 is provided above the substrate region 54. A contact region 58 is provided above the substrate region 54. In other words, with respect to the substrate region, the source region, and the contact region, they are independently provided in the first region 96 and the second region 98.

[0060] And, instead of the first trench 20, a second trench 40 extending in the depth direction (Y direction) of the paper surface is provided. Instead of the third insulating film 22, a fourth insulating film 42 is provided. Instead of the first insulating film 21, a second insulating film 41 is provided. Instead of the first field plate electrode 24, a second field plate electrode 44 is provided. Additionally, the second field plate electrode 44 may not be provided. Instead of the first gate electrode 28, a second gate electrode (an example of the third electrode) 48 is provided. Instead of the source metals 70 and source metal 74, source metals 82 and source metal 86 ( Figure 3 in (a)) are provided.

[0061] Figure 7 is another example of a schematic cross-sectional view of the main part of the semiconductor device 100 in the second region 98. The contact region 58 may not be provided.

[0062] In addition, the structures in the first region 96 and the second region 98 are not limited to the above relationship.

[0063] The gate metal 72 is disposed between the source metal 70 and the source metal 74 in the first region 96.

[0064] The gate metal 84 is disposed between the source metal 82 and the source metal 86 in the second region 98.

[0065] The gate metal 72 and the source metal 70 are separated by the interlayer insulating film 95b which is the interlayer insulating film 95. The gate metal 72 and the source metal 74 are separated by the interlayer insulating film 95c which is the interlayer insulating film 95. The gate metal 84 and the source metal 82 are separated by the interlayer insulating film 95f which is the interlayer insulating film 95. The gate metal 84 and the source metal 86 are separated by the interlayer insulating film 95g which is the interlayer insulating film 95.

[0066] The source metal 74 and the source metal 86 are separated by the interlayer insulating film 95j which is the interlayer insulating film 95. In addition, the source metal 70 and the source metal 82, and the gate metal 72 and the gate metal 84 are also separated by the interlayer insulating film 95.

[0067] Figure 8 It is a schematic cross-sectional view of the main part of the semiconductor device 100 of the first embodiment. Figure 8 It is a schematic cross-sectional view for showing an example of the connection method between the first field plate electrode 24 and the source metal 70 and an example of the connection method between the first gate electrode 28 and the gate metal 72. For example, Figures 4 to 7 The schematic cross-sectional view of Figure 8 corresponds to the schematic cross-sectional view in the D - D' cross-section of

[0068] The first field plate electrode 24 has a portion extending in the Z direction. In addition, using the portion extending in the Z direction, the first field plate electrode 24 is electrically connected to the source metal 70 via contact holes provided in the interlayer insulating film 95 and the third insulating film 22.

[0069] The first gate electrode 28 is electrically connected to the gate metal 72 via a contact hole provided in the interlayer insulating film 95. The source metal 70 and the first field plate electrode 24 are insulated from the first gate electrode 28 by the interlayer insulating film 95 and the third insulating film 22.

[0070] In addition, regarding the electrical connection between the source metal 74 and the first field plate electrode 24, the electrical connection between the source metal 82 and the second field plate electrode 44, the electrical connection between the gate metal 84 and the second gate electrode 48, and the electrical connection between the source metal 86 and the second field plate electrode 44, the same can be done.

[0071] The coating layers 88, 78, 80, 76, 90, and 92 are respectively disposed on the source metal 70, gate metal 72, source metal 74, source metal 82, gate metal 84, and source metal 86. In addition, the coating layers 88, 78, 80, 76, 90, and 92 are respectively electrically connected to the source metal 70, gate metal 72, source metal 74, source metal 82, gate metal 84, and source metal 86. The coating layers 88, 78, 80, 76, 90, and 92 are provided to improve the strength of the connection based on solder or the like with an external circuit (not shown).

[0072] The coating layer 88 and the coating layer 78 are separated by the insulating film 94b which is the insulating film 94. The coating layer 78 and the coating layer 80 are separated by the insulating film 94c which is the insulating film 94. The coating layer 76 and the coating layer 90 are separated by the insulating film 94f which is the insulating film 94. The coating layer 90 and the coating layer 92 are separated by the insulating film 94g which is the insulating film 94. The coating layer 80 and the coating layer 92 are separated by the insulating film 94j which is the insulating film 94. Additionally, the coating layer 88 and the coating layer 76, as well as the coating layer 78 and the coating layer 90, are also separated by the insulating film 94.

[0073] Figure 9 It is a schematic cross-sectional view of the main part of the semiconductor device of the first embodiment. Figure 9 It is a diagram showing an example of the cross-section of the groove 36. The groove 36 is preferably formed by plasma etching. Here, this plasma etching is performed by repeatedly executing isotropic etching using F (fluorine) - based radicals, formation of a protective film containing CF4 (carbon tetrafluoride) - based radicals, and anisotropic etching using F - based ions. Through such plasma etching, scallop - shaped portions 37 having a shell - like shape are formed on the side surface 35 of the groove 36. Specifically, scallop - shaped portions 37a, 37b, 37c, and 37d are formed. In addition, the illustration of the scallop - shaped portion 37 is omitted for the groove 36 in other drawings.

[0074] The substrate 30 is, for example, a silicon substrate. However, the substrate 30 can also be, for example, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate, etc.

[0075] When Si is used as the semiconductor material, for example, arsenic (As), phosphorus (P), or antimony (Sb) can be used as the n - type impurity, and for example, B (boron) can be used as the p - type impurity.

[0076] The first field plate electrode 24, the second field plate electrode 44, the first gate electrode 28, and the second gate electrode 48 include a conductive material such as polysilicon containing an impurity of a conductivity type.

[0077] The drain electrode 60, the source metal 70, the gate metal 72, the source metal 74, the source metal 82, the gate metal 84, and the source metal 86 include a metal material such as Al (aluminum), Ag (silver), Cu (copper), etc., and are formed, for example, by an electroplating method.

[0078] Next, the operation and effect of the semiconductor device of the present embodiment will be described.

[0079] Figure 10 It is a schematic cross-sectional view of a semiconductor device which is a comparative mode of the first embodiment.

[0080] In a semiconductor device including the first transistor Tr1 and the second transistor Tr2 as in the semiconductor device of the present embodiment, a reduction in the resistance of the drift layer 12 due to the thinning of the substrate 30 is particularly required. Here, if the substrate 30 is thinned, the substrate 30 warps, and there is a problem that handling etc. becomes impossible in the manufacturing process of the semiconductor device.

[0081] Especially in a semiconductor device having a trench gate structure which has an advantage in terms of miniaturization etc. of the semiconductor device, there is a problem that the warping of the substrate 30 becomes large. Here, as the form of the warping of the substrate 30, there are, for example, Figure 10 a case of warping upward in the central part in the XZ plane as shown in (a) of Figure 10 and a case of warping downward in the central part in the XZ plane as shown in (b) of

[0082] Therefore, the semiconductor device 100 of the present embodiment has a groove 36 on the first surface 32 of the substrate 30, and in this groove 36, the length in the Y direction crossing the X direction and parallel to the first surface 32 is shorter than the length in the X direction parallel to the first surface 32. And, in the substrate 30, the first trench 20 and the second trench 40 extend in the Y direction.

[0083] Thus, by providing the groove 36, warping of the substrate 30 that may occur in the XZ plane can be suppressed. Further, by forming the groove 36, a part of the substrate 30 can be thinned to reduce the resistance of the drift layer 12. Therefore, a semiconductor device with a high yield can be provided.

[0084] Moreover, if the groove 36 is formed by plasma etching, it is preferable because the depth and pattern of the formed groove 36 can be easily changed according to the shape of the warping of the substrate 30. In this case, the side surface 35 of the groove 36 has a scalloped portion 37.

[0085] Also, preferably, the groove 36 does not penetrate the side surface 38 of the substrate 30. This is because if the groove 36 penetrates the side surface 38 of the substrate 30, the strength of the penetrated portion of the substrate 30 becomes weak. For the same reason, when a plurality of grooves 36 are provided, preferably none of the grooves 36 penetrates the side surface 38 of the substrate 30.

[0086] When forming the drain electrode 60 on the first surface 32 of the substrate 30 in which the groove 36 is formed, a groove 66 having a length L4 in the Y direction shorter than the length L3 in the X direction is formed under the groove 36 on the bottom surface of the drain electrode 60. Here, for example, L3 < L1 and L4 < L2. This is formed by making the shape of the drain electrode 60 follow the shape of the groove 36 when forming the drain electrode 60.

[0087] According to the semiconductor device 100 of the present embodiment, a semiconductor device 100 with a high yield can be provided.

[0088] (Second Embodiment)

[0089] The difference between the semiconductor device of the present embodiment and the semiconductor device of the first embodiment is that a third groove is provided in the first groove, the length of the third groove is shorter than the length of the first groove, and the depth of the third groove is deeper than the depth of the first groove. Here, the description of the content overlapping with the first embodiment is omitted.

[0090] Figure 11 is a schematic diagram of the semiconductor device 110 of the present embodiment. Figure 11 (a) shows a schematic diagram of the first surface 32 of the substrate 30 and the groove 36 formed on the first surface 32. Figure 11 (b) is Figure 11 a schematic cross-sectional view of the substrate 30 and the groove 36 along the E - E' section of (a). Figure 11 In (a), the groove 36h1 (an example of the first groove), the grooves 36h2, 36h3, 36h4 (an example of the third groove), the grooves 36h5, 36h6, 36h7, 36h8, 36h9, and 36h10 are illustrated as the groove 36. The groove 36h4 is provided in the groove 36h1. AsFigure 11 As shown in (b) of Figure 11 the length L12 of the groove 36h4 is shorter than the length L11 of the groove 36h1. Also, as shown in (b) of

[0091] For example, in the groove 36d (an example of the first groove) shown in Figure 3 a groove (an example of the third groove) with a shorter length and a deeper depth than the groove 36d can be further provided.

[0092] Figure 12 FIG. is a schematic cross-sectional view showing the main part of the manufacturing process of the semiconductor device 110 according to the present embodiment. Figure 12 FIG. is a schematic cross-sectional view showing the main part of the manufacturing process of the groove 36 with respect to the first surface 32 of the substrate 30.

[0093] First, a photoresist Pa with a length L12 interval is formed on the first surface 32 of the substrate 30 ( Figure 12 in (a)).

[0094] Next, a part of the substrate 30 where the photoresist Pa is not provided is etched away by plasma etching to form the groove 36h4 and the groove 36h6 ( Figure 12 in (b)). Next, the photoresist Pa is removed ( Figure 12 in (c)).

[0095] Next, a photoresist Pb with an opening having a length L11 in the X direction is formed on the first surface 32 of the substrate 30 where the groove 36h4 and the groove 36h6 are not formed ( Figure 12 in (d)).

[0096] Next, a part of the substrate 30 where the photoresist Pa is not provided is etched away by plasma etching to form the groove 36h1 and the groove 36h7. Next, the photoresist Pa is removed ( Figure 12 in (e)). Through the above, the groove 36h1 and the groove 36h4 of the present embodiment can be formed.

[0097] In order to further suppress the warping of the substrate 30, by combining the manufacturing method of the present embodiment, grooves 36 of various shapes can be formed. For example, by setting the groove 36d shown in Figure 3 to be a groove with the same shape as the groove 36h1 and the groove 36h4 shown in Figure 11 it is possible to further suppress the warping of the substrate 30. Therefore, according to the semiconductor device 110 of the present embodiment, a semiconductor device with a higher yield can be provided.

[0098] (Third Embodiment)

[0099] The difference between the semiconductor device of the present embodiment and the semiconductor devices of the first and second embodiments is that the first surface has a fourth groove with a length in the second direction shorter than that of the first groove between the first groove and the end of the substrate. Here, the description of the content repeated with the first and second embodiments is omitted.

[0100] Figure 13 It is a schematic diagram of the semiconductor device 120 of the present embodiment. Figure 13 It is a schematic diagram showing the first surface 32 of the substrate 30 and the groove 36 formed in the first surface 32. Figure 13 In it, the groove 36i1 (an example of the fourth groove), the groove 36i2 (an example of the fourth groove), the groove 36i3 (an example of the fourth groove), the groove 36i4 (an example of the first groove), the groove 36i5 (an example of the fourth groove), the groove 36i6 (an example of the fourth groove), and the groove 36i7 (an example of the fourth groove) are illustrated as the groove 36. The lengths of the grooves 36i1, 36i2, 36i3, 36i5, 36i6, and 36i7 in the Y direction are d2, which is shorter than the length d1 of the groove 36i4 in the Y direction.

[0101] For example, it is possible to make Figure 3 the lengths in the Y direction of the illustrated grooves 36a (an example of the fourth groove), 36b (an example of the fourth groove), 36c (an example of the fourth groove), 36e (an example of the fourth groove), 36f (an example of the fourth groove), and 36g (an example of the fourth groove) shorter than the length in the Y direction of the groove 36d (an example of the first groove).

[0102] By making the length in the Y direction of the groove 36i4 in the central portion of the first surface 32 longer than that of the other grooves, it is possible to suppress the warping in the case where the warping in the central portion of the substrate 30 is stronger.

[0103] According to the semiconductor device 120 of the present embodiment, a semiconductor device 120 with a high yield can be provided.

[0104] (Fourth Embodiment)

[0105] The difference between the semiconductor device of the present embodiment and the semiconductor devices of the first to third embodiments is that the first surface has a fifth groove with a length in the second direction longer than that of the first groove between the first groove and the end of the substrate. Here, the description of the content repeated with the first to third embodiments is omitted.

[0106] Figure 14 It is a schematic diagram of the semiconductor device 130 of the present embodiment. Figure 14 It is a schematic diagram showing the first surface 32 of the substrate 30 and the groove 36 formed in the first surface 32. Figure 14The figure shows groove 36j1 (an example of the fifth groove), groove 36j2 (an example of the first groove), groove 36j3 (an example of the first groove), groove 36j4 (an example of the first groove), and groove 36j5 (an example of the fifth groove) as groove 36. The lengths of groove 36j1 and groove 36j5 in the Y direction are d3, which is longer than the lengths d4 of groove 36j2, groove 36j3, and groove 36j4 in the Y direction.

[0107] For example, it is possible to make Figure 3 The lengths in the Y direction of groove 36a (an example of the fifth groove), groove 36b (an example of the fifth groove), groove 36c (an example of the fifth groove), groove 36e (an example of the fifth groove), groove 36f (an example of the fifth groove), and groove 36g (an example of the fifth groove) shown are longer than the length in the Y direction of groove 36d (an example of the first groove).

[0108] By making the lengths in the Y direction of groove 36j1 and groove 36j5 at the end portion of the first surface 32 longer than the lengths in the Y direction of groove 36j2, groove 36j3, and groove 36j4, it is possible to suppress warping in the case where the warping at the end of the substrate 30 is stronger.

[0109] According to the semiconductor device 130 of the present embodiment, a semiconductor device 130 with a high yield can be provided.

[0110] (Fifth Embodiment)

[0111] The difference between the semiconductor device of the present embodiment and the semiconductor devices of the first to fourth embodiments is that the first surface has: a plurality of sixth grooves arranged side by side with the first groove in the first direction, and a plurality of seventh grooves arranged side by side with the first groove and the plurality of sixth grooves respectively in the second direction. The description of the content repeated with the first to fourth embodiments is omitted here.

[0112] Figure 15 It is a schematic diagram of the semiconductor device 140 of the present embodiment. Figure 15 It is a schematic diagram showing the first surface 32 of the substrate 30 and the groove 36 formed on the first surface 32. Figure 15 The figure shows, as groove 36, groove 36o1, groove 36o2, groove 36o3, groove 36o4, groove 36o5, groove 36o6, groove 36o7, groove 36n1, groove 36n2, groove 36n3, groove 36n4, groove 36n5, groove 36n6, groove 36n7, groove 36m1, groove 36m2, groove 36m3, groove 36m4, groove 36m5, groove 36m6, groove 36m7, groove 36l1, groove 36l2, groove 36l3, groove 36l4, groove 36l5, groove 36l6, groove 36l7, groove 36k1, groove 36k2, groove 36k3, groove 36k4, groove 36k5, groove 36k6, groove 36k7.

[0113] The groove 36o1, the groove 36n1, the groove 36l1, and the groove 36k1 (an example of a plurality of sixth grooves) are arranged side by side in the X direction with the groove 36m1 (an example of a first groove). The groove 36o3, the groove 36o4, the groove 36o5, the groove 36o6, and the groove 36o7 (an example of a plurality of seventh grooves) are arranged side by side in the Y direction with the groove 36o1. The groove 36n2, the groove 36n3, the groove 36n4, the groove 36n5, the groove 36n6, and the groove 36n7 (an example of a plurality of seventh grooves) are arranged side by side in the Y direction with the groove 36n1. The groove 36l2, the groove 36l3, the groove 36l4, the groove 36l5, the groove 36l6, and the groove 36l7 (an example of a plurality of seventh grooves) are arranged side by side in the Y direction with the groove 36l1. The groove 36k2, the groove 36k3, the groove 36k4, the groove 36k5, the groove 36k6, and the groove 36k7 (an example of a plurality of seventh grooves) are arranged side by side in the Y direction with the groove 36k1.

[0114] The width of the groove 36m4 in the Y direction is d7. The widths of the grooves 36m3 and 36m5 in the Y direction are d6, and d6 < d7. The widths of the grooves 36m1, 36m2, 36m6, and 36m7 in the Y direction are d5, and d5 < d6. On the other hand, the widths of the grooves 36m1, 36m2, 36m3, 36m4, 36m5, 36m6, and 36m7 in the X direction are d8, and they are all equal. The grooves 36 in the present embodiment are arranged with such grooves 36m1, 36m2, 36m3, 36m4, 36m5, 36m6, and 36m7 in the X direction.

[0115] For example, by dividing the grooves 36a, 36b, 36c, 36d, 36e, 36f, and 36g shown in Figure 3 into five parts in the X direction and changing the widths in the Y direction, the grooves 36 shown in Figure 15 can be obtained.

[0116] Such an arrangement of the grooves 36 in the semiconductor device 140 of the present embodiment can suppress such distortion when the substrate 30 is distorted as a whole.

[0117] According to the semiconductor device 140 of the present embodiment, a semiconductor device 140 with a high yield can be provided.

[0118] (Sixth Embodiment)

[0119] The difference between the semiconductor device of the present embodiment and the semiconductor devices of the first to fifth embodiments is that grooves with different shapes are arranged under the plating layer 76, under the plating layer 80, under the plating layer 88, and under the plating layer 92. Here, the description of the content repeated with the first to fifth embodiments is omitted.

[0120] Figure 16It is a schematic diagram of the semiconductor device 150 of the present embodiment. Figure 16 It is a schematic diagram showing the first surface 32 of the substrate 30 and the groove 36 formed on the first surface 32. The semiconductor device 150 of the present embodiment further includes: a plating layer 76 (an example of a fourth electrode) provided on the second surface 34 above the first region 96 and electrically connected to the source region 16 (an example of a second semiconductor region), a plating layer 80 (an example of a fifth electrode) provided on the second surface 34 above the first region 96 and electrically connected to the source region 16 (an example of a second semiconductor region), a plating layer 78 (an example of a sixth electrode) provided on the second surface 34 between the plating layer 76 (an example of a fourth electrode) and the plating layer 80 (an example of a fifth electrode) and electrically connected to the first gate electrode 28 (an example of a second electrode), a plating layer 88 (an example of a seventh electrode) provided on the second surface 34 above the second region 98 and electrically connected to the source region 56 (an example of a fourth semiconductor region), a plating layer 92 (an example of an eighth electrode) provided on the second surface 34 above the second region 98 and electrically connected to the source region 56 (an example of a fourth semiconductor region), a plating layer 90 (an example of a ninth electrode) provided on the second surface 34 between the plating layer 88 (an example of a seventh electrode) and the plating layer 92 (an example of an eighth electrode) and electrically connected to the second gate electrode 48 (an example of a third electrode). The first surface 32 further includes: a groove 36p1 (an example of an eighth groove) provided under the plating layer 76 (an example of a fourth electrode), a groove 36p2 (an example of a ninth groove) provided under the plating layer 80 (an example of a fifth electrode), a groove 36p3 (an example of a tenth groove) provided under the plating layer 88 (an example of a seventh electrode), and a groove 36p4 (an example of an eleventh groove) provided under the plating layer 92 (an example of an eighth electrode).

[0121] The shapes of the grooves 36p1, 36p2, 36p3, and 36p4 are different from each other. Specifically, the lengths d11, d12, d13, and d14 in the X direction of the grooves 36p1, 36p2, 36p3, and 36p4 are different from each other. And the lengths d21, d22, d23, and d24 in the Y direction of the grooves 36p1, 36p2, 36p3, and 36p4 are different from each other. In addition, the manner in which the shapes of the grooves 36p1, 36p2, 36p3, and 36p4 are different is not limited to the above manner, of course.

[0122] In the case where the substrate 30 has complex warping, by changing the shape of the groove 36 as described above, warping can be suppressed.

[0123] According to the semiconductor device 150 of the present embodiment, a semiconductor device 150 with a high yield can be provided.

[0124] Several embodiments and examples of the present invention are illustrated, but these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalents.

Claims

1. A semiconductor device, comprising: a first electrode; and a substrate having a first surface contacted by the first electrode and a second surface opposed to the first surface, the substrate having a first groove on the first surface with a length in a second direction shorter than a length in a first direction, the first direction being parallel to the first surface, the second direction intersecting the first direction and being parallel to the first surface, the substrate comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer provided between the first semiconductor layer and the second surface, and an impurity concentration of the first conductivity type in the second semiconductor layer being lower than an impurity concentration of the first conductivity type in the first semiconductor layer; a first semiconductor region of a second conductivity type provided between the second semiconductor layer and the second surface; a second semiconductor region of the first conductivity type provided between the first semiconductor region and the second surface; and a second electrode disposed opposite to the first semiconductor region with a first insulating film therebetween in a first trench extending from the second surface to the second semiconductor layer and extending in the second direction, a third groove is provided in the first groove, a length of the third groove in the first direction being shorter than a length of the first groove in the first direction, and a depth of the third groove being deeper than a depth of the first groove in a third direction intersecting the first direction and the second direction.

2. The semiconductor device according to claim 1, the first groove not penetrating a side surface of the substrate.

3. The semiconductor device according to claim 1 or 2, the first electrode having a second groove corresponding to the first groove by covering the first groove on the first surface.

4. The semiconductor device according to claim 1 or 2, the first surface having a fourth groove with a shorter length in the second direction than the first groove between the first groove and an end of the substrate in the second direction.

5. The semiconductor device according to claim 1 or 2, the first surface having a fifth groove with a longer length in the second direction than the first groove between the first groove and an end of the substrate in the second direction.

6. The semiconductor device according to claim 1 or 2, the first surface having a plurality of sixth grooves and a plurality of seventh grooves, the plurality of sixth grooves being arranged side by side with the first groove in the first direction, and the plurality of seventh grooves being arranged side by side with the first groove and the plurality of sixth grooves respectively in the second direction.

7. The semiconductor device according to claim 1 or 2, the substrate further comprising: a third semiconductor region of the second conductivity type provided between the second semiconductor layer and the second surface; a fourth semiconductor region of the first conductivity type provided between the third semiconductor region and the second surface; and a third electrode disposed opposite to the third semiconductor region with a second insulating film therebetween in a second trench extending from the second surface to the second semiconductor layer and extending in the second direction, The above-mentioned substrate has a first region and a second region. The above-mentioned first region has the above-mentioned first semiconductor region, the above-mentioned second semiconductor region, and the above-mentioned second electrode. The above-mentioned second region is adjacent to the above-mentioned first region in the above-mentioned first direction, and the above-mentioned second region has the above-mentioned third semiconductor region, the above-mentioned fourth semiconductor region, and the above-mentioned third electrode. The above-mentioned first groove straddles the above-mentioned first region and the above-mentioned second region.

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