Mixer circuit with noise cancellation

Abstract

The present disclosure relates to a mixer circuit with noise cancellation. This disclosure provides an electronic device that may include wireless circuitry having a baseband processor, a transceiver, a front-end module, and an antenna. The transceiver may include a mixer circuit. The mixer circuit may include a switch controlled by an oscillator signal. The mixer circuit may also include an oscillator phase noise cancellation capacitor controlled by an inverted oscillator signal. Operating in this manner, the mixer circuit exhibits improved noise figure performance.

Description

[0001] This application claims priority to U.S. patent application No. 17 / 026,056, filed on September 18, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0002] The present disclosure relates generally to electronic devices and, more particularly, to electronic devices having wireless communication circuitry. Background Art

[0003] Electronic devices often have wireless communication capabilities. These devices contain wireless communication circuitry with one or more antennas. The wireless receiver circuitry in the wireless communication circuitry uses the antennas to receive radio frequency signals.

[0004] The signal received by the antenna is fed through a transceiver, which typically includes a mixer for demodulating the radio frequency signal. Designing a satisfactory mixer for use in electronic equipment can be challenging. Summary of the Invention

[0005] An electronic device may include wireless communication circuitry. The wireless communication circuitry may include: an antenna; a transceiver configured to receive a radio frequency signal from the antenna and generate a corresponding baseband signal; and a baseband processor configured to receive the baseband signal from the transceiver.

[0006] One aspect of the present disclosure provides a mixer circuit. The mixer circuit may include an input port configured to receive a radio frequency signal from an antenna; an output port generating a baseband signal at the output port based on the radio frequency signal; an oscillator configured to generate a first oscillator signal, a second oscillator signal different from the first oscillator signal, and a third oscillator signal inverted relative to the second oscillator signal; a first switch having an input terminal coupled to the input port, an output terminal coupled to the output port, and a control terminal configured to receive the first oscillator signal; a second switch having an input terminal coupled to the output terminal of the first switch, an output terminal coupled to the output port, and a control terminal configured to receive the second oscillator signal; and an oscillator phase noise cancellation capacitor having a first terminal coupled to the input terminal of the second switch and a second terminal configured to receive the third oscillator signal. The oscillator phase noise cancellation capacitor may be a metal-oxide-semiconductor capacitor, a metal-insulator-metal capacitor, or a metal-oxide-metal capacitor.

[0007] One aspect of the present disclosure provides a method for operating a mixer. The method may include using an input port to receive a radio frequency signal; using an oscillator to generate a first oscillator signal, a second oscillator signal different from the first oscillator signal, and a third oscillator signal that is inverted relative to the second oscillator signal; using a first switch to receive the radio frequency signal from the input port and receive the first oscillator signal; using a second switch to receive a signal from the first switch, receive the second oscillator signal, and generate a corresponding baseband signal based on the radio frequency signal; and using an oscillator phase noise canceller to receive the third oscillator signal and reduce the phase noise associated with the second oscillator signal. The method may also include using a flip-flop to generate a first output signal and a second output signal, using a first series buffer to receive the first output signal and generate the first oscillator signal, and using a second series buffer to receive the second output signal and generate the second oscillator signal.

[0008] One aspect of the present disclosure provides an electronic device, the electronic device including an antenna configured to receive a radio frequency signal; a baseband processor configured to receive a baseband signal generated based on the radio frequency signal; an oscillator configured to generate an oscillator signal and an inverted oscillator signal that is inverted relative to the oscillator signal; and a mixer configured to receive the radio frequency signal from the antenna and generate the baseband signal. The mixer may include a transistor having a gate terminal configured to receive the oscillator signal; and a capacitor having a first terminal directly connected to the transistor and a second terminal configured to receive the inverted oscillator signal. The oscillator may include a flip-flop having a first output terminal and a second output terminal; a first plurality of buffers coupled to the first output terminal and configured to generate a first oscillator signal among the oscillator signals; and a second plurality of buffers coupled to the second output terminal and configured to generate a second oscillator signal among the oscillator signals. The oscillator may further include a first inverter coupled to a last buffer in the first plurality of buffers, and a second inverter coupled to a last buffer in the second plurality of buffers. The first inverter may be configured to generate a first inverted oscillator signal among the inverted oscillator signals. The second inverter may be configured to generate a second inverted oscillator signal among the inverted oscillator signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagram of an illustrative electronic device with wireless communications circuitry in accordance with some embodiments.

[0010] Figure 2 is a diagram of an illustrative wireless communications circuit having transceiver circuitry, according to some implementations.

[0011] Figure 3 is a diagram of an illustrative mixer circuit, according to some implementations.

[0012] Figure 4 is a diagram of an exemplary local oscillator according to some implementations.

[0013] Figure 5 is a diagram of an illustrative mixer switch coupled to an oscillator phase noise cancellation capacitor, according to some implementations.

[0014] Figure 6 is a circuit diagram of a portion of a mixer circuit configured to generate an in-phase output signal, according to some embodiments.

[0015] Figure 7 is a circuit diagram of a portion of a mixer circuit configured to generate a quadrature-phase output signal, according to some embodiments.

[0016] Figure 8 is a circuit diagram of an illustrative local oscillator configured to generate an oscillator signal for controlling a mixer circuit, according to some embodiments.

[0017] Figure 9 is a diagram illustrating exemplary oscillator signal waveforms according to some embodiments.

[0018] Figure 10 is a diagram illustrating how performing oscillator phase noise cancellation can reduce noise figure according to some embodiments.

[0019] Figure 11 According to some embodiments, the Figures 2 to 8 Flowchart of illustrative steps involved in a mixer circuit of the type shown. DETAILED DESCRIPTION

[0020] Electronic devices such as Figure 1 The electronic device 10 may include wireless circuitry. The wireless circuitry may include a passive mixer circuit for downconverting a radio frequency signal to baseband. The passive mixer circuit includes a mixer and a local oscillator. The local oscillator generates an oscillator output signal to control one or more switches in the mixer. The passive mixer circuit may be provided with an oscillator phase noise cancellation component configured to cancel phase noise that may be parasitically coupled to the mixer input. The oscillator phase noise cancellation component may be a capacitor structure configured to receive an anti-phase oscillator output signal. Arranged and operated in this manner, the passive mixer circuit can generate a baseband signal with improved noise figure performance.

[0021] Figure 1The electronic device 10 may be: a computing device, such as a laptop computer, a desktop computer, a computer monitor containing an embedded computer, a tablet computer, a cellular phone, a media player, or other handheld or portable electronic device; a smaller device, such as a wristwatch device, a pendant device, a headset or earpiece device, a device embedded in glasses; or other equipment worn on the user's head; or other wearable or miniature devices, a television, a computer display that does not contain an embedded computer, a gaming device, a navigation device, an embedded system (such as a system in which electronic equipment with a display is installed in an information kiosk or a car), a voice-controlled speaker connected to wireless Internet, a home entertainment device, a remote control device, a game controller, a peripheral user input device, a wireless base station or access point, equipment that implements the functions of two or more of these devices; or other electronic equipment.

[0022] like Figure 1 As shown in the schematic diagram in FIG, device 10 may include components located on or within an electronic device housing, such as housing 12. Housing 12 (sometimes referred to as a casing) may be formed from plastic, glass, ceramic, fiber composite materials, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or combinations of these materials. In some cases, part or all of housing 12 may be formed from a dielectric or other low-conductivity material (e.g., glass, ceramic, plastic, sapphire, etc.). In other cases, housing 12 or at least some of the structures comprising housing 12 may be formed from metal elements.

[0023] Device 10 may include control circuitry 14. Control circuitry 14 may include storage, such as storage circuitry 16. Storage circuitry 16 may include hard drive storage, non-volatile memory (e.g., flash memory or other electrically programmable read-only memory configured to form a solid-state drive), volatile memory (e.g., static random access memory or dynamic random access memory), etc. Storage circuitry 16 may include storage integrated within device 10 and / or removable storage media.

[0024] Control circuitry 14 may include processing circuitry, such as processing circuitry 18. Processing circuitry 18 may be used to control the operation of device 10. Processing circuitry 18 may include one or more microprocessors, microcontrollers, digital signal processors, host processors, baseband processor integrated circuits, application-specific integrated circuits, central processing units (CPUs), and the like. Control circuitry 14 may be configured to perform operations in device 10 using hardware (e.g., dedicated hardware or circuitry), firmware, and / or software. Software code for performing operations in device 10 may be stored on storage circuitry 16 (e.g., storage circuitry 16 may include a non-transitory (tangible) computer-readable storage medium storing software code). This software code may sometimes be referred to as program instructions, software, data, instructions, or code. The software code stored on storage circuitry 16 may be executed by processing circuitry 18.

[0025] Control circuitry 14 may be used to run software on device 10, such as satellite navigation applications, internet browsing applications, voice over internet protocol (VOIP) phone call applications, email applications, media playback applications, operating system functions, and the like. To support interaction with external equipment, control circuitry 14 may be used to implement communication protocols. Communication protocols that may be implemented using control circuitry 14 include: Internet Protocol, wireless local area network (WLAN) protocols (e.g., IEEE 802.11 protocols—sometimes referred to as ), protocols for other short-range wireless communication links such as The present invention relates to a wireless personal area network (WPAN) protocol or other wireless personal area network (WPAN) protocol, an IEEE 802.11ad protocol (e.g., an ultra-wideband protocol), a cellular telephone protocol (e.g., a 3G protocol, a 4G (LTE) protocol, a 5G New Radio (NR) protocol, etc.), a MIMO protocol, an antenna diversity protocol, a satellite navigation system protocol (e.g., a Global Positioning System (GPS) protocol, a Global Navigation Satellite System (GLONASS) protocol, etc.), an antenna-based spatial ranging protocol (e.g., a Radio Detection and Ranging (RADAR) protocol for signals transmitted at millimeter wave frequencies and centimeter wave frequencies, or other desired distance detection protocols), or any other desired communication protocol. Each communication protocol may be associated with a corresponding radio access technology (RAT), which specifies a physical connection method for implementing the protocol.

[0026] Device 10 may include input-output circuitry 20. Input-output circuitry 20 may include input-output devices 22. Input-output devices 22 may be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to external devices. Input-output devices 22 may include user interface devices, data port devices, and other input-output components. For example, input-output devices 22 may include a touch sensor, a display, a light-emitting component such as a display without touch sensor capabilities, buttons (mechanical, capacitive, optical, etc.), a scroll wheel, a touchpad, a keypad, a keyboard, a microphone, a camera, buttons, a speaker, a status indicator, an audio jack and other audio port components, a digital data port device, a motion sensor (accelerometer, gyroscope, and / or compass to detect motion), a capacitive sensor, a proximity sensor, a magnetic sensor, a force sensor (e.g., a force sensor coupled to a display to detect pressure applied to the display), and the like. In some configurations, a keyboard, headset, display, pointing device such as a trackpad, mouse, electronic pencil (e.g., stylus) and joystick, and other input-output devices may be coupled to device 10 using wired or wireless connections (e.g., some of input-output devices 22 may be peripheral devices coupled to a main processing unit or other portion of device 10 via a wired or wireless link).

[0027] Input-output circuitry 24 may include wireless communication circuitry, such as wireless communication circuitry 34 (sometimes referred to herein as wireless circuitry 24), for wirelessly transmitting radio frequency signals. Although control circuitry 14 is shown as separate from wireless communication circuitry 24 for clarity, wireless communication circuitry 24 may include processing circuitry that forms part of processing circuitry 18 and / or memory circuitry that forms part of memory circuitry 16 of control circuitry 14 (e.g., portions of control circuitry 14 may be implemented on wireless communication circuitry 24). For example, control circuitry 14 (e.g., processing circuitry 18) may include baseband processor circuitry or other control components that form part of wireless communication circuitry 24.

[0028] Wireless communication circuitry 24 may include radio frequency (RF) transceiver circuitry formed from one or more integrated circuits, a power amplifier circuit configured to amplify uplink RF signals (e.g., RF signals transmitted by device 10 to an external device), a low-noise amplifier configured to amplify downlink RF signals (e.g., RF signals received by device 10 from an external device), passive RF components, one or more antennas, transmission lines, and other circuitry for processing RF wireless signals. Wireless signals may also be transmitted using light (e.g., using infrared communication).

[0029] The wireless circuitry 24 may include RF transceiver circuitry for handling transmission and / or reception of RF signals in various RF communication bands. For example, the RF transceiver circuitry may handle: wireless local area network (WLAN) communication bands, such as 2.4 GHz and 5 GHz. (IEEE 802.11) frequency band; Wireless Personal Area Network (WPAN) communication band, such as 2.4 GHz Communications bands; cellular telephone communications bands, such as cellular low band (LB) (e.g., 600 MHz to 960 MHz), cellular low-mid band (LMB) (e.g., 1400 MHz to 1550 MHz), cellular mid band (MB) (e.g., from 1700 MHz to 2200 MHz), cellular high band (HB) (e.g., from 2300 MHz to 2700 MHz), cellular ultra-high band (UHB) (e.g., from 3300 MHz to 5000 MHz), or other cellular communications bands between about 600 MHz and about 5000 MHz (e.g., 3G bands, 4G LTE bands, 5G new radio frequency range 1 (FR1) bands below 10 GHz, 5G new radio frequency range 2 (FR2) bands at millimeter and centimeter wavelengths between 20 GHz and 60 GHz, etc.); near field communication (NFC) bands (e.g., at 13.56 MHz); satellite navigation bands (e.g., L1 Global Positioning System (GPS) band at 1575 MHz, L5 GPS band at 1176 MHz, Global Navigation Satellite System (GLONASS) band, BeiDou Navigation Satellite System (BDS) band, etc.); ultra-wideband (UWB) communication bands supported by IEEE 802.15.4 protocol and / or other UWB communication protocols (e.g., a first UWB communication band at 6.5 GHz and / or a second UWB communication band at 8.0 GHz); and / or any other desired communication bands. The communication bands handled by such radio frequency transceiver circuitry may sometimes be referred to herein as frequency bands or simply “bands” and may span corresponding frequency ranges. Generally speaking, the radio frequency transceiver circuitry within wireless circuitry 24 may cover (process) any desired frequency band of interest.

[0030] Figure 2 is a diagram showing illustrative components within wireless circuitry 24. Figure 2 As shown, wireless circuitry 24 may include a baseband processor such as baseband processor 26, radio frequency (RF) transceiver circuitry such as RF transceiver 28, RF front-end circuitry such as RF front-end module (FEM) 40, and antenna 42. Baseband processor 26 may be coupled to transceiver 28 via a baseband path 34. Transceiver 28 may be coupled to antenna 42 via an RF transmission line path 36. RF front-end module 40 may be interposed on RF transmission line path 36 between transceiver 28 and antenna 42.

[0031] exist Figure 2 In the example shown, for clarity, wireless circuitry 24 is shown as including only a single baseband processor 26, a single transceiver 28, a single front-end module 40, and a single antenna 42. Generally speaking, wireless circuitry 24 may include any desired number of baseband processors 26, any desired number of transceivers 36, any desired number of front-end modules 40, and any desired number of antennas 42. Each baseband processor 26 may be coupled to one or more transceivers 28 via a corresponding baseband path 34. Each transceiver 28 may include transmitter circuitry 30 configured to output uplink signals to antenna 42, may include receiver circuitry 32 configured to receive downlink signals from antenna 42, and may be coupled to one or more antennas 42 via a corresponding RF transmission line path 36. Each RF transmission line path 36 may have a corresponding front-end module 40 interposed thereon. If desired, two or more front-end modules 40 may be interposed on the same RF transmission line path 36. If desired, one or more of the RF transmission line paths 36 in wireless circuitry 24 may be implemented without any front-end modules interposed thereon.

[0032] RF transmission line path 36 may be coupled to an antenna feed on antenna 42. The antenna feed may, for example, include a positive antenna feed terminal and a ground antenna feed terminal. RF transmission line path 36 may have a positive transmission line signal path coupled to the positive antenna feed terminal on antenna 42. RF transmission line path 36 may have a ground transmission line signal path coupled to the ground antenna feed terminal on antenna 42. This example is merely illustrative, and in general, antenna 42 may be fed using any desired antenna feeding scheme. If desired, antenna 42 may have multiple antenna feeds coupled to one or more RF transmission line paths 36.

[0033] The RF transmission line path 36 may include a path for routing the device 10 ( Figure 1) within the device 10. The transmission lines in the device 10 may include coaxial cables, microstrip transmission lines, stripline transmission lines, edge-coupled microstrip transmission lines, edge-coupled stripline transmission lines, transmission lines formed from combinations of these types of transmission lines, and the like. The transmission lines in the device 10 (such as the transmission lines in the RF transmission line path 36) may be integrated into a rigid and / or flexible printed circuit board. In one suitable arrangement, the RF transmission line paths (such as the RF transmission line path 36) may also include transmission line conductors that are integrated within a multilayer laminate structure (e.g., layers of conductive material (such as copper) and dielectric material (such as resin) laminated together without an intervening adhesive). If desired, the multilayer laminate structure may be folded or bent in multiple dimensions (e.g., two or three dimensions) and may retain the bent or folded shape after bending (e.g., the multilayer laminate structure may be folded into a specific three-dimensional structural shape to route around other device components and may be sufficiently rigid to retain its shape after folding without reinforcements or other structures to hold it in place). All of the multiple layers of the laminate structure can be batch laminated together (eg, in a single pressing process) without an adhesive (eg, as opposed to performing multiple pressing processes to laminate the multiple layers together with an adhesive).

[0034] When performing wireless transmissions, the baseband processor 26 may provide a baseband signal to the transceiver 28 via the baseband path 34. The transceiver 28 may also include circuitry for converting the baseband signal received from the baseband processor 26 into a corresponding radio frequency signal. For example, the transceiver circuitry 28 may include a mixer circuit 50 for up-converting (or modulating) the baseband signal to radio frequency prior to transmission via the antenna 42. The transceiver circuitry 28 may also include a digital-to-analog converter (DAC) circuit and / or an analog-to-digital converter (ADC) circuit for converting signals between the digital domain and the analog domain. The transceiver 28 may include a transmitter component to transmit the radio frequency signal via the radio frequency transmission line path 36 and the front-end module 40 through the antenna 42. The antenna 42 may transmit the radio frequency signal to external wireless equipment by radiating the radio frequency signal into free space.

[0035] When performing wireless reception, antenna 42 can receive radio frequency signals from external wireless equipment. The received radio frequency signals can be transmitted to transceiver 28 via radio frequency transmission line path 36 and front-end module 40. Transceiver 28 may include circuitry for converting the received radio frequency signals into corresponding baseband signals. For example, transceiver 28 may use mixer circuitry 50 to downconvert (or demodulate) the received radio frequency signals to baseband frequencies before transmitting the received signals to baseband processor 26 via baseband path 34. Mixer circuitry 50 may include oscillator circuitry, such as local oscillator 52. Local oscillator 52 can generate an oscillator signal that mixer circuitry 50 can use to modulate a transmit signal from a baseband frequency to a radio frequency and / or to demodulate a received signal from a radio frequency to a baseband frequency.

[0036] The front-end module (FEM) 40 may include RF front-end circuitry that operates on RF signals transmitted (transmitted and / or received) via the RF transmission line path 36. The front-end module may include, for example, front-end module (FEM) components such as RF filter circuitry 44 (e.g., a low-pass filter, a high-pass filter, a notch filter, a band-pass filter, a multiplexing circuit, a duplexer circuit, a diplexer circuit, a triplexer circuit, etc.), switching circuitry 46 (e.g., one or more RF switches), RF amplifier circuitry 48 (e.g., one or more power amplifiers and one or more low-noise amplifiers), impedance matching circuitry (e.g., circuitry that helps match the impedance of the antenna 42 to the impedance of the RF transmission line 36), antenna tuning circuitry (e.g., a network of capacitors, resistors, inductors, and / or switches that adjusts the frequency response of the antenna 42), RF coupler circuitry, charge pump circuitry, power management circuitry, digital control and interface circuitry, and / or any other desired circuitry that operates on RF signals transmitted and / or received by the antenna 42. Each of the front-end module components may be mounted to a common (shared) substrate, such as a rigid printed circuit board substrate or a flexible printed circuit substrate. If desired, the various front-end module components can also be integrated into a single integrated circuit chip.

[0037] Filter circuitry 44, switching circuitry 46, amplifier circuitry 48, and other circuitry may be interposed within RF transmission line path 36, may be incorporated into FEM 40, and / or may be incorporated into antenna 42 (e.g., to support antenna tuning, to support operation in a desired frequency band, etc.). These components (sometimes referred to herein as antenna tuning components) may be adjusted (e.g., using control circuitry 14) to adjust the frequency response and wireless performance of antenna 42 over time.

[0038] The transceiver 28 may be separate from the front-end module 40. For example, the transceiver 28 may be formed on another substrate such as the main logic board of the device 10, a rigid printed circuit board, or a flexible printed circuit that is not part of the front-end module 40. Although for clarity, the transceiver 28 is shown in FIG. Figure 1 In the example shown, control circuitry 14 is shown as being separate from radio circuitry 24, but radio circuitry 24 may include processing circuitry that forms part of processing circuitry 18 and memory circuitry that forms part of memory circuitry 16 of control circuitry 14 (e.g., portions of control circuitry 14 may be implemented on radio circuitry 24). For example, baseband processor 26 and / or portions of transceiver 28 (e.g., a host processor on transceiver 28) may form part of control circuitry 14. Control circuitry 14 (e.g., portions of control circuitry 14 formed on baseband processor 26, portions of control circuitry 14 formed on transceiver 28, and / or portions of control circuitry 14 that are separate from radio circuitry 24) may provide control signals (e.g., via one or more control paths in device 10) that control the operation of front-end module 40.

[0039] Transceiver circuitry 28 may include processors that handle WLAN communication bands (e.g., (IEEE 802.11) or other WLAN communication bands) such as the 2.4 GHz WLAN band (e.g., from 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., from 5180 MHz to 5825 MHz), 6E band (e.g., from 5925 MHz to 7125 MHz) and / or other Wireless LAN transceiver circuits for frequency bands (e.g., from 1875 MHz to 5160 MHz); handles 2.4 GHz wireless personal area network transceiver circuitry for a wireless personal area network (WLAN) frequency band or other WPAN communication band; a cellular telephone transceiver circuitry for processing cellular telephone frequency bands (e.g., frequency bands from about 600 MHz to about 5 GHz, 3G frequency bands, 4G LTE frequency bands, 5G new radio frequency range 1 (FR1) bands below 10 GHz, 5G new radio frequency range 2 (FR2) bands between 20 GHz and 60 GHz, etc.); a near field communication (NFC) transceiver circuitry for processing near field communication frequency bands (e.g., at 13.56 MHz); a satellite navigation receiver circuitry for processing satellite navigation frequency bands (e.g., GPS frequency bands from 1565 MHz to 1610 MHz, Global Navigation Satellite System (GLONASS) frequency bands, BeiDou Navigation Satellite System (BDS) frequency bands, etc.); an ultra-wideband (UWB) transceiver circuitry for processing communications using the IEEE 802.15.4 protocol and / or other ultra-wideband communication protocols; and / or any other desired radio frequency transceiver circuitry for covering any other desired communication frequency bands of interest.

[0040] Wireless circuitry 24 may include one or more antennas, such as antenna 42. Antenna 42 may be formed using any desired antenna structure. For example, antenna 42 may be an antenna having a resonant element formed from a loop antenna structure, a patch antenna structure, an inverted-F antenna structure, a slot antenna structure, a planar inverted-F antenna structure, a helical antenna structure, a monopole antenna, a dipole, a hybrid of these designs, or the like. Two or more antennas 42 may be arranged into one or more phased antenna arrays (e.g., for transmitting radio frequency signals at millimeter wave frequencies). Parasitic elements may be included in antenna 42 to adjust antenna performance. Antenna 42 may be provided with a conductive cavity that supports the antenna resonant element of antenna 42 (e.g., antenna 42 may be a cavity-backed antenna, such as a cavity-backed slot antenna).

[0041] As described above, mixer circuit 50 may be used to downconvert a radio frequency signal to a baseband frequency for demodulation. Figure 3 is a diagram of an exemplary mixer circuit 50. Figure 3 As shown, the mixer circuit 50 may include an input port RFIN, a first mixer section 50-I, a second mixer section 50-Q, and an associated local oscillator (LO) 52. The input port RFIN is configured to receive a radio frequency signal from the front-end module 40. For example, the input port RFIN may be configured to receive a radio frequency from a low-noise amplifier within the front-end module 40. For another example, the input port RFIN may be configured to receive a radio frequency signal from a balun. For another example, the input port RFIN may be configured to receive a radio frequency signal from other front-end module components or directly from the antenna 42.

[0042] The oscillator 52 can be configured to generate a first oscillator output signal and a second oscillator output signal that is phase-shifted 90° relative to the first oscillator output signal. The first oscillator output signal is fed to a first mixer section 50-I. The first mixer section 50-I can mix the RF input signal received at the input port RFIN with the first oscillator output signal to generate a corresponding in-phase signal I(n). The second mixer section 50-Q can mix the RF input signal received at the RFIN port with the second oscillator output signal to generate a corresponding quadrature-phase signal Q(n). The in-phase signal I(n) and the quadrature-phase signal Q(n) can be generated at the output of the mixer, which can be collectively referred to as baseband signals, and then fed to the baseband processor 26.

[0043] Figure 4 is a block diagram of the local oscillator 52. Figure 4As shown, oscillator 52 may include a voltage controlled oscillator such as voltage controlled oscillator (VCO) 60, one or more digital flip-flops such as digital flip-flop 62, and associated buffer circuits such as buffer 64. Voltage controlled oscillator 60 may output a periodic signal to control digital flip-flop 62. Flip-flop 62 may be any latch-based digital circuit for generating a clock signal based on the periodic signal provided by voltage controlled oscillator 60. The clock signal generated by flip-flop 62 may be fed through a corresponding chain of buffer circuits 64 to generate one or more oscillator output signals 66.

[0044] like Figure 3 As shown in the example of FIG, oscillator 52 can generate at least two different oscillator output signals having different phases (e.g., a 0° LO phase signal and a 90° LO phase signal). As another example, oscillator 52 can generate at least four different oscillator output signals (e.g., a 0° LO phase signal, a 90° LO phase signal, a 180° LO phase signal, and a 270° LO phase signal). In general, oscillator 52 can generate any suitable number of LO phases (e.g., two or more LO phases, three or more LO phases, more than four LO phases, four to ten LO phases, more than ten LO phases, etc.). In practice, digital flip-flop 62 and buffer circuit 64 are susceptible to rise and fall time variations, random phase shifts, and signal jitter, all of which result in random phase noise that can be introduced by the local oscillator to degrade the noise figure performance of the overall mixer circuit.

[0045] The mixer circuit 50 can be an active mixer or a passive mixer. Active mixers consume power but can be used to provide gain. Passive mixers can also provide gain, but can achieve improved linearity and consume less power than active mixers. Conventional passive mixers can suffer from noise figure degradation due to phase noise associated with the local oscillator (e.g., due to noise associated with the digital flip-flop and buffer circuits when generating various LO phases). If care is not taken, different oscillator signals generated by the local oscillator can parasitically couple to the input port of the passive mixer, which can then self-mix with the local oscillator frequency. This undesirable coupling of local oscillator signals (sometimes referred to herein as local oscillator phase noise, oscillator phase noise, or LO phase noise) can lead to noise degradation at the baseband. This noise degradation is exacerbated in advanced complementary metal-oxide-semiconductor (CMOS) processes, which are more susceptible to flicker noise.

[0046] Figure 5 is a diagram of an exemplary passive mixer circuit 50 provided with an oscillator phase noise cancellation component to cancel (compensate for) the LO phase that may be inadvertently coupled to the input port of the passive mixer. Figure 5As shown, mixer circuit 50 may include at least one passive mixer switch, such as switch 51. Switch 51 may be implemented, for example, as a transistor, such as an n-channel metal-oxide-semiconductor (NMOS) transistor. This is merely illustrative. As another example, switch 51 may be implemented as a p-channel metal-oxide-semiconductor (PMOS) transistor. Generally speaking, any suitable type of semiconductor switch component may be used. Configurations in which switch 51 is implemented as an NMOS transistor may sometimes be described herein as an example.

[0047] The switch 51 may have an input terminal (e.g., a transistor source terminal) coupled to the mixer input port RFIN. The switch 51 may have an output terminal (e.g., a transistor drain terminal) coupled to the mixer output port BBout. The baseband signal may be provided at the mixer output port BBout. The switch 51 may also include a control terminal (e.g., a transistor gate terminal) configured to receive an oscillator signal 66 generated by the oscillator 52. The terms "source" and "drain" terminals used to refer to current carrying terminals in a transistor are used interchangeably and are sometimes referred to as "source-drain" terminals. Therefore, Figure 5 The arrangement may also be described as a transistor 51 having a first source-drain terminal coupled to the RFIN port and a second source-drain terminal coupled to the BBout port.

[0048] like Figure 5 As shown, parasitic components, such as parasitic capacitance Cpar, may be present between the control (G) terminal and the input (S) terminal of switch 51. Parasitic capacitance Cpar may couple random noise sources associated with LO signal 66 to input port RFIN, which may then self-mix with the LO frequency and may directly degrade the noise figure of the baseband signal generated at output port BBout.

[0049] To help compensate (mitigate) this undesirable parasitic coupling effect, mixer circuit 50 is provided with an oscillator phase noise cancellation capacitor Ccancel. Phase noise cancellation capacitor Ccancel has a first terminal coupled to mixer input port RFIN and a second terminal configured to receive an inverted oscillator signal 68. Signal 68 may be inverted relative to signal 66 (e.g., signal 68 may be an inverted version of signal 66). Configured and operated in this manner, any phase noise injected into the RFIN node from the control (G) terminal of switch 51 via parasitic capacitance Cpar can be offset or canceled by a corresponding compensating coupling signal, which is simultaneously injected into the RFIN node as a result of controlling capacitor Ccancel using the inverted (opposite) oscillator signal 68. Consequently, phase noise coupled through Cpar associated with switch 51 will not be transferred to baseband output port BBout. Consequently, capacitor Ccancel is sometimes referred to as an oscillator phase noise cancellation component, an oscillator phase noise canceller, an oscillator phase noise cancellation circuit, an oscillator phase noise reduction circuit, an oscillator phase noise compensation circuit, or an oscillator phase noise mitigation circuit.

[0050] In some embodiments, the oscillator phase noise cancellation capacitor Ccancel has a fixed capacitance value. As another example, the capacitor Ccancel may exhibit a variable capacitance that can be adjusted to tune the cancellation gain associated with the capacitor Ccancel (e.g., to adjust the amount of LO phase noise cancellation provided by Ccancel). The capacitor Ccancel may be implemented as a capacitor bank (e.g., an array of capacitors, at least some of which can be switched into use depending on the desired capacitance value).

[0051] Figure 6 FIG. 5 is a circuit diagram of a first mixer section 50-I formed as a passive differential mixer. Figure 6 As shown, the first mixer section 50-I may have a differential input port having a positive input port rfp and a negative input port rfn. The differential input ports rfp and rfn may be collectively represented as Figure 3 and Figure 5 The mixer input port RFIN is shown. The mixer section 50-I may have a differential output port having a positive output port iop and a negative output port ion. An in-phase signal I(n) may be generated across the differential output ports iop and ion.

[0052] The mixer section 50-I may also include switches M1-M12 and capacitors C1-C8. Figure 6In the example shown, switches M1-M12 are implemented as n-channel transistors (e.g., NMOS transistors). This is illustrative only. In other embodiments, at least some or all of the switches in mixer section 50-1 may be implemented as p-channel transistors (e.g., PMOS transistors).

[0053] Transistors M1, M2, and M3 may be coupled in series between the positive input port rfp and the positive output port iop. Transistor M1 has a gate (control) terminal configured to receive an oscillator signal IN. Transistor M2 has a gate (control) terminal configured to receive an oscillator signal IP. Transistor M3 has a gate (control) terminal configured to receive an oscillator signal IN. Signals IP and IN are generated by a local oscillator 52 and are combined below. Figure 8 and Figure 9 Detailed description. Capacitor C1 has a first terminal coupled to the positive input port rfp and a second terminal coupled to a node interposed between the source-drain terminals of transistors M4 and M5. Capacitor C3 has a first terminal coupled to the positive input port rfp and a second terminal coupled to a node A interposed between the source-drain terminals of transistors M2 and M3.

[0054] Transistors M4, M5, and M6 may be coupled in series between the negative input port rfn and the positive output port iop. Transistor M4 has a gate (control) terminal configured to receive an oscillator signal IP. Transistor M5 has a gate (control) terminal configured to receive an oscillator signal IN. Transistor M6 has a gate (control) terminal configured to receive an oscillator signal IP. Capacitor C2 has a first terminal coupled to the negative input port rfn and a second terminal coupled to a node interposed between the source-drain terminals of transistors M1 and M2. Capacitor C4 has a first terminal coupled to the negative input port rfn and a second terminal coupled to a node B interposed between the source-drain terminals of transistors M5 and M6.

[0055] Phase noise associated with the oscillator signal IP may be coupled to node A via the parasitic capacitance of transistor M2. Similarly, phase noise associated with the oscillator signal IN may also be coupled to node A via the parasitic capacitance of transistor M3. The phase noise coupled to node A may then be mixed with the oscillator signal IN through transistor M3, which results in noise degradation in the baseband output signal. In order to cancel the LO phase noise associated with the signals IP and IN, the mixer section 50-I is provided with capacitors n1 and n2 coupled to node A. Figure 6In the example shown, capacitors n1 and n2 are implemented as metal-oxide-semiconductor capacitors (MOSCAPs). This is merely illustrative. In another example, capacitors n1 and n2 may be implemented as metal-insulator-metal (MIM) capacitors. In another example, capacitors n1 and n2 may be implemented as metal-oxide-metal (MOM) capacitors. Generally speaking, capacitors n1 and n2 may be implemented using any suitable semiconductor capacitor structure.

[0056] Capacitor n1 has a first (body) terminal coupled to node A and a second (gate) terminal configured to receive oscillator signal IPb (e.g., a signal inverted relative to signal IP). Capacitor n2 has a first (body) terminal coupled to node A and a second (gate) terminal configured to receive oscillator signal INb (e.g., a signal inverted relative to signal IN). By connecting capacitor n1 to the source-drain (output) terminals of transistor M2 and modulating capacitor n1 with the opposite (inverted) LO phase IPb, any phase noise coupled to node A via the parasitic capacitance of transistor M2 is canceled by the equal and opposite coupling effect from capacitor n1. The other source-drain (input) terminal of transistor M2 is directly connected to transistor M1. Similarly, by connecting capacitor n2 to the source-drain (input) terminals of transistor M3 and modulating capacitor n2 with the opposite (inverted) LO phase INb, any phase noise coupled to node A via the parasitic capacitance of transistor M3 is canceled by the equal and opposite coupling effect from capacitor n2. The other source-drain (output) terminal of the transistor M3 is connected to the positive output port iop.

[0057] The mixer section 50-I may also be provided with capacitors n3 and n4 coupled to the node B. Figure 6 In the example shown, capacitors n3 and n4 are implemented as metal-oxide-semiconductor capacitors (MOSCAPs), which is merely illustrative. If desired, capacitors n3 and n4 can be implemented as metal-insulator-metal (MIM) capacitors, metal-oxide-metal (MOM) capacitors, or any suitable semiconductor capacitor structure.

[0058] Capacitor n3 has a first (body) terminal coupled to node B and a second (gate) terminal configured to receive oscillator signal IPb (e.g., a signal inverted relative to signal IP). Capacitor n4 has a first (body) terminal coupled to node B and a second (gate) terminal configured to receive oscillator signal INb (e.g., a signal inverted relative to signal IN). By connecting capacitor n4 to the source-drain (output) terminals of transistor M5 and modulating capacitor n4 with an opposite (inverted) LO phase INb, any phase noise coupled to node B via the parasitic capacitance of transistor M5 can be canceled by the equal and opposite coupling effect from capacitor n4. Similarly, by connecting capacitor n3 to the source-drain (input) terminals of transistor M6 and modulating capacitor n3 with an opposite (inverted) LO phase IPb, any phase noise coupled to node B via the parasitic capacitance of transistor M6 can be canceled by the equal and opposite coupling effect from capacitor n3.

[0059] Capacitors n1, n2, n3, and n4 used to cancel LO phase noise may be collectively referred to as an oscillator phase noise cancellation circuit 70. Each of capacitors n1-n4 may be referred to as an oscillator phase noise cancellation capacitor, an oscillator phase noise compensation capacitor, an oscillator phase noise cancellation component, or an oscillator phase noise cancellation circuit.

[0060] In a single-ended approach, the passive in-phase mixer section 50-I may include only the components M1-M6, C1-C4, and n1-n4 connected in the manner described above. In a differential signaling scheme, the mixer section 50-I may include another half circuit (see, for example, transistors M7-M12, C5-C8, and n5-n8) for generating a signal at the negative output port ion.

[0061] Transistors M7, M8, and M9 may be coupled in series between the positive input port rfp and the negative output port ion. Transistor M7 has a gate (control) terminal configured to receive an oscillator signal IP. Transistor M8 has a gate (control) terminal configured to receive an oscillator signal IN. Transistor M9 has a gate (control) terminal configured to receive an oscillator signal IP. Capacitor C5 has a first terminal coupled to the positive input port rfp and a second terminal coupled to a node interposed between the source-drain terminals of transistors M10 and M11. Capacitor C7 has a first terminal coupled to the positive input port rfp and a second terminal coupled to a node C interposed between the source-drain terminals of transistors M8 and M9.

[0062] Transistors M10, M11, and M12 may be coupled in series between the negative input port rfn and the negative output port ion. Transistor M10 has a gate (control) terminal configured to receive an oscillator signal IN. Transistor M11 has a gate (control) terminal configured to receive an oscillator signal IP. Transistor M12 has a gate (control) terminal configured to receive an oscillator signal IN. Capacitor C6 has a first terminal coupled to the negative input port rfn and a second terminal coupled to a node interposed between the source-drain terminals of transistors M7 and M8. Capacitor C8 has a first terminal coupled to the negative input port rfn and a second terminal coupled to a node D interposed between the source-drain terminals of transistors M11 and M12.

[0063] Phase noise associated with the oscillator signal IN may be coupled to node C via parasitic capacitance associated with transistor M8. Similarly, phase noise associated with the oscillator signal IP may also be coupled to node C via parasitic capacitance associated with transistor M9. The phase noise coupled to node C may then be mixed with the oscillator signal IP through transistor M9, which results in noise degradation in the baseband output signal at output port ion.

[0064] Oscillator phase noise cancellation capacitors n5-n8 can be used to cancel the LO phase noise associated with signals IP and IN. Figure 6 In the example of FIG, capacitors n5-n8 are implemented as metal oxide semiconductor capacitors (MOSCAP), which is merely illustrative. As other examples, capacitors n5-n8 may be implemented as MIM capacitors, MOM capacitors, or other suitable semiconductor capacitor structures.

[0065] Capacitor n5 has a first (body) terminal coupled to node C and a second (gate) terminal configured to receive oscillator signal INb. Capacitor n6 has a first (body) terminal coupled to node C and a second (gate) terminal configured to receive oscillator signal IPb. By connecting capacitor n5 to the source-drain (output) terminal of transistor M8 and modulating capacitor n5 with the opposite (inverted) LO phase INb, any phase noise coupled to node C via the parasitic capacitance of transistor M8 is canceled by the equal and opposite coupling effect from capacitor n5. The other source-drain (input) terminal of transistor M8 is directly connected to transistor M7. Similarly, by connecting capacitor n6 to the source-drain (input) terminal of transistor M9 and modulating capacitor n6 with the opposite (inverted) LO phase IPb, any phase noise coupled to node C via the parasitic capacitance of transistor M9 is canceled by the equal and opposite coupling effect from capacitor n6. The other source-drain (output) terminal of transistor M9 is connected to the negative output port ion.

[0066] Capacitor n7 has a first (body) terminal coupled to node D and a second (gate) terminal configured to receive oscillator signal INb. Capacitor n8 has a first (body) terminal coupled to node D and a second (gate) terminal configured to receive oscillator signal IPb. By connecting capacitor n8 to the source-drain (output) terminals of transistor M11 and modulating capacitor n8 with the opposite (inverted) LO phase IPb, any phase noise coupled to node D through the parasitic capacitance of transistor M11 can be canceled by the equal and opposite coupling effect from capacitor n8. Similarly, by connecting capacitor n7 to the source-drain (input) terminals of transistor M12 and modulating capacitor n7 with the opposite (inverted) LO phase INb, any phase noise coupled to node D through the parasitic capacitance of transistor M12 can be canceled by the equal and opposite coupling effect from capacitor n7.

[0067] Capacitors n5, n6, n7, and n8 used to cancel LO phase noise may also be considered part of oscillator phase noise cancellation circuit 70. Each of capacitors n5-n8 may be referred to as an oscillator phase noise cancellation capacitor, an oscillator phase noise compensation capacitor, an oscillator phase noise cancellation component, or an oscillator phase noise cancellation circuit.

[0068] The size of each oscillator phase noise cancellation capacitor n1-n8 can be carefully selected. Since capacitor n1 is configured to offset the coupling effect associated with the gate-source parasitic capacitance Cgs of transistor M2 (which represents only half of the parasitic capacitance at the gate terminal of M2), MOS capacitor n1 can be at least half the size of transistor M2 or otherwise appropriately sized to match Cgs of transistor M2. Similarly, since capacitor n2 is configured to offset the coupling effect associated with the gate-drain parasitic capacitance Cgd of transistor M3 (which represents only half of the parasitic capacitance at the gate terminal of M3), MOS capacitor n2 can be at least half the size of transistor M3 or otherwise appropriately sized to match Cgd of transistor M3. Similarly, capacitors n3, n4, n5, n6, n7, and n8 can be half the size of transistors M5, M6, M8, M9, M11, and M12, respectively.

[0069] The oscillator signals that control some of the other switches may also be coupled to internal nodes A, B, C, and D. For example, oscillator signal IN controlling the gate of transistor M1 may also be coupled to node A via capacitor C3. As another example, oscillator signal IN controlling the gate of transistor M5 may be coupled to node A via capacitors C1 and C3. As another example, oscillator signal IP controlling the gate of transistor M4 may be coupled to node A via capacitors C1 and C3. As another example, oscillator signal IP controlling the gate of transistor M7 may be coupled to node A via capacitor C3. As another example, oscillator signal IN controlling the gate of transistor M10 may be coupled to node A via capacitors C5 and C3. As another example, oscillator signal IP controlling the gate of transistor M11 may also be coupled to node A via capacitors C5 and C3. The size of LO phase noise cancellation capacitors n1 and n2 can be optimized to cancel LO noise from all of these coupling paths. Capacitor n1 may be larger than half the size of M2 to help compensate for the additional parasitic coupling paths. Similarly, the size of capacitor n2 may be greater than half the size of M3 to help compensate for the additional parasitic coupling path.

[0070] Figure 6 The example in which mixer section 50-I includes 12 switches, 8 capacitors, and 8 LO phase noise cancellation capacitors is merely illustrative. In general, mixer section 50-I can be any passive mixer circuit configured to provide voltage gain and including any suitable number of components. For example, mixer section 50-I can include fewer than 12 switches, 1-11 switches, 2-10 switches, 3-9 switches, more than 12 switches, 12-20 switches, 13-19 switches, 14-18 switches, or more than 20 switches. For another example, mixer section 50-I can include fewer than 8 capacitors, 1-7 capacitors, 2-6 capacitors, more than 8 capacitors, 8-16 capacitors, more than 10 capacitors, 10-20 capacitors, more than 20 capacitors, or no capacitors. As another example, the mixer portion 50-I may include fewer than 8 phase noise cancellation capacitors, at least one phase noise cancellation capacitor, at least two phase noise cancellation capacitors, four or more phase noise cancellation capacitors, 1-7 phase noise cancellation capacitors, 2-6 phase noise cancellation capacitors, more than 8 phase noise cancellation capacitors, 8-16 phase noise cancellation capacitors, or more than 16 phase noise cancellation capacitors.

[0071] Figure 6 The first mixer section 50-I is used to generate an in-phase signal I(n). Figure 7 FIG. 5 is a circuit diagram of a second mixer section 50-Q for generating a quadrature phase signal Q(n). Figure 7As shown, the second mixer section 50-Q may have a differential input port having a positive input port rfp and a negative input port rfn. The differential input ports rfp and rfn may be collectively represented as Figure 3 and Figure 5 The mixer input port RFIN is shown. The mixer section 50-Q may have a differential output port having a positive output port qop and a negative output port qon. A quadrature phase signal Q(n) may be generated across the differential output ports qop and qon.

[0072] Mixer section 50-Q may include switches, capacitors, and LO phase noise cancellation circuitry 70. The structure and connections of the switches, capacitors, and circuitry 70 in mixer section 50-Q may be similar to those of mixer section 50-I and need not be repeated in detail to avoid obscuring the disclosed embodiments. The mixer switches may be controlled by oscillator signals QN and QP. To help mitigate LO phase noise associated with signals QN and QP coupled to internal nodes E, F, G, and H within mixer section 50-Q, oscillator phase noise cancellation capacitors 70 are directly connected to internal nodes E, F, G, and H and modulated by anti-phase oscillator signals QPb and QNb to provide equal and opposite coupling effects.

[0073] Figure 8 is a circuit diagram of a local oscillator 52 configured to generate oscillator signals IP, IPb, IN, INb for controlling the in-phase mixer section 50-I, and signals QP, QPb, QN, QNb for controlling the non-phase mixer section 50-Q. Figure 8 As shown, the oscillator 52 uses a voltage-controlled oscillator 60 to generate a periodic signal (e.g., a clock signal, a square wave, or a sinusoidal signal). The periodic signal generated by the voltage-controlled oscillator 60 is fed to the clock inputs of digital flip-flops 62-I and 62-Q. The flip-flop 62-I has a first output terminal and a second output terminal, where a first oscillator signal is generated at the first output terminal and a second oscillator signal is generated at the second output terminal. The second oscillator signal may be phase-shifted 180° relative to the first oscillator signal. The first oscillator signal may be fed through a first chain of buffers 64 to generate a corresponding oscillator output signal IP. The second oscillator signal may be fed through a second chain of buffers 64 to generate a corresponding oscillator output signal IN.

[0074] Oscillator 52 may also include an inverting buffer, such as inverter 80-1, coupled to the input of the last buffer stage 64' in the first buffer chain. In other words, inverter 80-1 receives a signal from the second-to-last buffer in the first buffer chain. Inverter 80-1 is used to generate an oscillator output signal IPb that is inverted relative to signal IP. By coupling inverter 80-1 only to the final buffer stage 64', any potential noise contribution caused by unshared inverter paths is minimized.

[0075] Oscillator 52 may also include an inverting buffer, such as inverter 80-2, coupled to the input of the last buffer stage 64' in the second buffer chain. In other words, inverter 80-2 receives a signal from the second-to-last buffer in the second buffer chain (i.e., the buffer immediately preceding the last buffer stage 64'). Inverter 80-2 is used to generate an oscillator output signal INb that is inverted relative to signal IN. By coupling inverter 80-2 only to the final buffer stage 64', any potential noise contribution caused by unshared inverter paths is minimized.

[0076] Flip-flop 62-Q has a first output terminal, at which a third oscillator signal is generated, and a second output terminal, at which a fourth oscillator signal is generated. The third oscillator signal may be phase-shifted 90° relative to the first oscillator signal. The third oscillator signal may be fed through a third chain of buffers 64 to generate a corresponding oscillator output signal QP. The fourth oscillator signal may be fed through a fourth chain of buffers 64 to generate a corresponding oscillator output signal QN.

[0077] Oscillator 52 may also include an inverting buffer, such as inverter 80-3, coupled to the input of the last buffer stage 64' in the third buffer chain. In other words, inverter 80-3 receives a signal from the second-to-last buffer in the third buffer chain. Inverter 80-3 is used to generate an oscillator output signal QPb that is inverted relative to signal QP. By coupling inverter 80-3 only to the final buffer stage 64', any potential noise contribution caused by unshared inverter paths is minimized.

[0078] Oscillator 52 may also include an inverting buffer, such as inverter 80-4, coupled to the input of the last buffer stage 64' in the fourth buffer chain. In other words, inverter 80-4 receives a signal from the second-to-last buffer in the fourth buffer chain. Inverter 80-4 is used to generate an oscillator output signal QNb that is inverted relative to signal QN. By coupling inverter 80-4 only to the final buffer stage 64', any potential noise contribution caused by unshared inverter paths is minimized.

[0079] In some embodiments, inverters 80-1, 80-2, 80-3, and 80-4 may be programmable inverters with adjustable delays. The delays of these inverters may be adjusted statically during calibration operations or dynamically during normal wireless operation to compensate for potential process, voltage, and temperature (PVT) variations.

[0080] Figure 9 is a diagram showing exemplary signal waveforms related to the operation of the local oscillator 52. Figure 9 As shown, the VCO output can be used as a base clock signal. Although the VCO waveform is shown as a digital square wave, the VCO waveform can be an analog oscillating signal, a sinusoidal signal, or other periodic waveform. The oscillator signal IP can be aligned with the rising edge of the VCO (e.g., with a 0° phase offset). The signal IP can be fed, for example, to Figure 6 The control / gate terminals of the mixer switches M2, M4, M6, M7, M9, and M11 are connected to the oscillator signal IPb. The oscillator signal IPb may be inverted relative to the signal IP and may therefore sometimes be referred to as the inverted oscillator signal IPb. The inverted signal IPb may, for example, be fed to the Figure 6 The oscillator phase noise elimination circuits n1, n3, n6 and n8 in FIG.

[0081] The oscillator signal IN may be phase-shifted by 180° relative to the signal IP, as indicated by arrow 104. The signal IN may, for example, be fed to Figure 6 The control / gate terminals of the mixer switches M1, M3, M5, M8, M10, and M12 are connected to the control / gate terminals of the mixer switches M1, M3, M5, M8, M10, and M12. The oscillator signal INb may be inverted relative to the signal IN and may therefore sometimes be referred to as the inverted oscillator signal INb. The inverted signal INb may, for example, be fed to Figure 6 The oscillator phase noise elimination circuits n2, n4, n5 and n7 in FIG.

[0082] The oscillator signal QP may be phase-shifted by 90° relative to the signal IP, as indicated by arrow 100. The signal QP may, for example, be fed to Figure 7 The oscillator signal QPb may be inverted relative to the signal QP and may therefore sometimes be referred to as the inverted oscillator signal QPb. The inverted signal QPb may, for example, be fed to the control / gate terminal of the corresponding mixer switch in FIG. Figure 7 The corresponding oscillator phase noise in MOSCAP is eliminated. The oscillator signal QN may be phase-shifted by 180° relative to the signal IN, as indicated by arrow 106. The signal QN may, for example, be fed to Figure 7 The oscillator signal QNb may be inverted relative to the signal QN and may therefore sometimes be referred to as the inverted oscillator signal QNb. The inverted signal QNb may, for example, be fed to the control / gate terminal of the corresponding mixer switch in FIG. Figure 7The corresponding oscillator phase noise cancellation capacitor in.

[0083] Figure 9 The example in which oscillator signals IP, IPb, QP, QPb, IN, INb, QN, and QNb have a 25% duty cycle is merely illustrative. For another example, the oscillator signal may have a 50% duty cycle. For another example, the oscillator signal may have a 10% duty cycle. For another example, the oscillator signal may have a 20% duty cycle. For another example, the oscillator signal may have a 30% duty cycle. For another example, the oscillator signal may have a 40% duty cycle. For another example, the oscillator signal may have a duty cycle between 10% and 50%. For another example, the oscillator signal may have a duty cycle greater than 50%. For another example, the oscillator signal may have a 60% duty cycle. For another example, the oscillator signal may have a duty cycle between 50% and 90%. The duty cycle of the oscillator signal may be adjustable, if desired.

[0084] Figure 10 1 is a graphical representation of how performing oscillator phase noise cancellation can reduce the noise figure of a baseband signal. Curve 110 plots the noise figure of a signal output by a passive mixer circuit as a function of frequency (on a logarithmic scale) without the oscillator phase noise cancellation circuit. Curve 112 plots the noise figure of a signal output from a passive mixer circuit as a function of frequency when the oscillator phase noise cancellation circuit is enabled. Figure 10 As shown, using an oscillator phase noise cancellation circuit can help reduce the noise figure over a wide range of operating frequencies.

[0085] Figure 11 Is the operation at least Figures 2 to 8 Flowchart of illustrative steps involved in a mixer circuit of the type shown. At step 120, a local oscillator (e.g., oscillator 52) generates an oscillator signal and an inverted oscillator signal. The oscillator signal may include signals IP, QP, IN, and QN, while the inverted oscillator signal may include signals IPb, QPb, INb, and QNb. Signals IP, QP, IN, QN, IPb, QPb, INb, and QNb may all be generated at different oscillator output terminals.

[0086] At step 122, the mixer circuit may receive a radio frequency signal from an antenna or other circuit within the front-end module (see Figure 2 ).

[0087] At step 124, the mixer circuit may be configured to operate by controlling the mixer switches with the oscillator signal while controlling the phase noise cancellation circuit with the inverse oscillator signal (see, e.g., Figure 5 The capacitor Ccancel and Figures 6 and 7The RF signal is down-converted using circuit 70 in FIG. Using an inverted LO signal to modulate the LO phase noise cancellation circuit can help cancel or compensate for parasitic coupling of the non-inverted LO signal to internal nodes in the mixer circuit. This can help improve the noise figure performance of the mixer circuit.

[0088] At step 126 , the mixer circuit may then output the corresponding baseband signal to one or more baseband processors.

[0089] These steps are illustrative only. At least some of the steps described may be modified or omitted; some of the steps described may be performed in parallel; additional steps may be added or inserted between the steps described; the order of some steps may be reversed or changed; the timing of the steps described may be adjusted so that they occur at slightly different times, or the steps described may be distributed throughout the system.

[0090] Combination of the above Figures 1 to 11 The described methods and operations may be performed by the components of device 10 using software, firmware, and / or hardware (e.g., dedicated circuitry or hardware). The software code for performing these operations may be stored on a non-transitory computer-readable storage medium (e.g., a tangible computer-readable storage medium) stored on one or more of the components of device 10 (e.g., a computer-readable storage medium). Figure 1 The software code may sometimes be referred to as software, data, instructions, program instructions, or code. Non-transitory computer-readable storage media may include a drive, non-volatile memory such as non-volatile random access memory (NVRAM), a removable flash drive or other removable media, other types of random access memory, etc. The software stored on the non-transitory computer-readable storage media may be executed by processing circuitry on one or more of the components of device 10 (e.g., processing circuitry in wireless circuitry 24, Figure 1 The processing circuit may include a microprocessor, an application processor, a digital signal processor, a central processing unit (CPU), an application-specific integrated circuit having a processing circuit, or other processing circuit.

[0091] According to one embodiment, a mixer circuit is provided, the mixer circuit including an input port configured to receive a radio frequency signal; an output port at which a baseband signal is generated based on the radio frequency signal; an oscillator having a first oscillator output terminal at which a first oscillator signal is generated, a second oscillator output terminal at which a second oscillator signal different from the first oscillator signal is generated, and a third oscillator output terminal at which a third oscillator signal that is inverted relative to the second oscillator signal is generated; a first switch having an input terminal coupled to the input port, an output terminal coupled to the output port, and a control terminal coupled to the first oscillator output terminal; a second switch having an input terminal coupled to the output terminal of the first switch, an output terminal coupled to the output port, and a control terminal coupled to the second oscillator output terminal; and an oscillator phase noise cancellation capacitor having a first terminal coupled to the input terminal of the second switch and a second terminal coupled to the third oscillator output terminal.

[0092] According to another embodiment, the oscillator has a fourth oscillator output terminal at which a fourth oscillator signal that is inverted relative to the first oscillator signal is generated, and the mixer circuit includes an additional oscillator phase noise cancellation capacitor having a first terminal coupled to the input terminal of the second switch and a second terminal coupled to the fourth oscillator output terminal.

[0093] According to another embodiment, the oscillator phase noise cancellation capacitor includes a metal oxide semiconductor capacitor having a body terminal coupled to the input terminal of the second switch and a gate terminal coupled to the third oscillator output terminal.

[0094] According to another embodiment, the oscillator phase noise cancellation capacitor comprises a metal-insulator-metal capacitor or a metal-oxide-metal capacitor.

[0095] According to another embodiment, the mixer circuit includes a third switch having an input terminal coupled to the input port, an output terminal coupled to the input terminal of the first switch, and a control terminal coupled to the second oscillator output terminal.

[0096] According to another embodiment, an oscillator includes a flip-flop having a first output terminal and a second output terminal; a first buffer chain having an input terminal coupled to the first output terminal and an output terminal at which a first oscillator signal is generated; and a second buffer chain having an input terminal coupled to the second output terminal and an output terminal at which a second oscillator signal is generated.

[0097] According to another embodiment, the oscillator includes a first inverter having an input terminal coupled to a last buffer in a first buffer chain and an output terminal at which a fourth oscillator signal is generated, and a second inverter having an input terminal coupled to a last buffer in a second buffer chain and an output terminal at which a third oscillator signal is generated.

[0098] According to another embodiment, the first inverter and the second inverter have adjustable delays to compensate for process, voltage, and temperature variations.

[0099] According to another embodiment, the metal-oxide-semiconductor capacitor is at least half the size of the second switch.

[0100] According to another embodiment, the metal-oxide-semiconductor capacitor is larger than half the size of the second switch.

[0101] According to one embodiment, a method of operating a mixer is provided, the method comprising receiving a radio frequency signal using an input port; generating a first oscillator signal, a second oscillator signal different from the first oscillator signal, and a third oscillator signal that is inverted relative to the second oscillator signal using an oscillator; receiving the radio frequency signal from the input port and receiving the first oscillator signal using a first switch; receiving a signal from the first switch, receiving the second oscillator signal, and generating a corresponding baseband signal based on the radio frequency signal using a second switch; and receiving the third oscillator signal and reducing phase noise associated with the second oscillator signal using an oscillator phase noise canceller.

[0102] According to another embodiment, the method includes generating, with an oscillator, a fourth oscillator signal that is inverted relative to the first oscillator signal, and receiving the fourth oscillator signal and reducing phase noise associated with the first oscillator signal with an additional phase noise canceller.

[0103] According to another embodiment, generating the first oscillator signal, the second oscillator signal, the third oscillator signal, and the fourth oscillator signal includes utilizing a flip-flop to generate the first output signal and the second output signal, utilizing a first series of buffers to receive the first output signal and generate the first oscillator signal, and utilizing a second series of buffers to receive the second output signal and generate the second oscillator signal.

[0104] According to another embodiment, generating the first oscillator signal, the second oscillator signal, the third oscillator signal, and the fourth oscillator signal includes receiving a signal from a second-to-last buffer in a first series of buffers using a first inverter and generating the fourth oscillator signal, and receiving a signal from a second-to-last buffer in a second series of buffers using a second inverter and generating the third oscillator signal.

[0105] According to another embodiment, the method includes tuning the oscillator phase noise canceller to adjust an amount of cancellation gain provided by the oscillator phase noise canceller and adjusting a delay of the first inverter or the second inverter to compensate for process, voltage, and temperature variations.

[0106] According to one embodiment, an electronic device is provided, comprising an antenna configured to receive a radio frequency signal; a baseband processor configured to receive a baseband signal generated based on the radio frequency signal; an oscillator having a first oscillator output terminal at which an oscillator signal is generated, and a second oscillator output terminal at which an inverted oscillator signal that is inverted relative to the oscillator signal is generated; and a mixer configured to receive the radio frequency signal from the antenna and to generate the baseband signal, the mixer having a transistor and a capacitor, the transistor having a gate terminal coupled to the first oscillator output terminal, the capacitor having a first terminal coupled to the transistor and a second terminal coupled to the second oscillator output terminal.

[0107] According to another embodiment, a mixer has an input port and an output port, and the transistors include a first transistor having a first source-drain terminal coupled to the input port, a second source-drain terminal coupled to the output port, and a gate terminal configured to receive a first oscillator signal among the oscillator signals, and a second transistor having a first source-drain terminal coupled to the second source-drain terminal of the first transistor, a second source-drain terminal coupled to the output port, and a gate terminal configured to receive a second oscillator signal among the oscillator signals.

[0108] According to another embodiment, the capacitor includes a first capacitor having a first terminal directly connected to the first transistor and a second terminal configured to receive a first of the inverted oscillator signals, and a second capacitor having a first terminal directly connected to the second transistor and a second terminal configured to receive a second of the inverted oscillator signals.

[0109] According to another embodiment, an oscillator includes a flip-flop having a first output terminal and a second output terminal; a first plurality of buffers coupled to the first output terminal and configured to generate a first oscillator signal among the oscillator signals; and a second plurality of buffers coupled to the second output terminal and configured to generate a second oscillator signal among the oscillator signals.

[0110] According to another embodiment, an oscillator includes a first inverter coupled to a last buffer in a first plurality of buffers, the first inverter configured to generate a first inverted oscillator signal in the inverted oscillator signals and having an adjustable delay, and a second inverter coupled to a last buffer in a second plurality of buffers, the second inverter configured to generate a second inverted oscillator signal in the inverted oscillator signals and having an adjustable delay.

[0111] The foregoing is merely exemplary and various modifications may be made to the embodiments described. The foregoing embodiments may be implemented independently or in any combination.

Claims

1. Mixer circuit, including: an input port configured to receive a radio frequency signal; an output port, generating a baseband signal on the output port based on the radio frequency signal; an oscillator having a first oscillator output terminal, a second oscillator output terminal, and a third oscillator output terminal, wherein a first oscillator signal is generated at the first oscillator output terminal, a second oscillator signal different from the first oscillator signal is generated at the second oscillator output terminal, and a third oscillator signal inverted relative to the second oscillator signal is generated at the third oscillator output terminal; a first switch having an input terminal coupled to the input port, an output terminal coupled to the output port, and a control terminal coupled to the first oscillator output terminal; a second switch having an input terminal coupled to the output terminal of the first switch, an output terminal coupled to the output port, and a control terminal coupled to the second oscillator output terminal; as well as An oscillator phase noise cancellation capacitor has a first terminal coupled to the input terminal of the second switch and a second terminal coupled to the third oscillator output terminal.

2. The mixer circuit according to claim 1 , wherein the oscillator has a fourth oscillator output terminal, and a fourth oscillator signal inverted relative to the first oscillator signal is generated at the fourth oscillator output terminal, the mixer circuit further comprising: An additional oscillator phase noise cancellation capacitor has a first terminal coupled to the input terminal of the second switch and a second terminal coupled to the fourth oscillator output terminal.

3. The mixer circuit of claim 2 , wherein the oscillator phase noise cancellation capacitor comprises a metal-oxide-semiconductor capacitor having a body terminal coupled to the input terminal of the second switch and a gate terminal coupled to the third oscillator output terminal. 4 . The mixer circuit of claim 2 , wherein the oscillator phase noise cancellation capacitor comprises a metal-insulator-metal capacitor or a metal-oxide-metal capacitor.

5. The mixer circuit according to claim 2, further comprising: A third switch has an input terminal coupled to the input port, an output terminal coupled to the input terminal of the first switch, and a control terminal coupled to the second oscillator output terminal.

6. The mixer circuit of claim 2 , wherein the oscillator comprises: a flip-flop having a first output terminal and a second output terminal; a first buffer chain having an input terminal coupled to the first output terminal and an output terminal at which the first oscillator signal is generated; as well as A second buffer chain has an input terminal coupled to the second output terminal and an output terminal at which the second oscillator signal is generated.

7. The mixer circuit of claim 6 , wherein the oscillator comprises: a first inverter having an input terminal coupled to a last buffer in the first buffer chain and an output terminal at which the fourth oscillator signal is generated; as well as A second inverter has an input terminal coupled to a last buffer in the second buffer chain and an output terminal at which the third oscillator signal is generated.

8. The mixer circuit of claim 7, wherein the first inverter and the second inverter have adjustable delays to compensate for process, voltage, and temperature variations.

9. The mixer circuit of claim 3, wherein the metal-oxide-semiconductor capacitor is at least half the size of the second switch. 10 . The mixer circuit of claim 9 , wherein the metal-oxide-semiconductor capacitor is larger than half the size of the second switch.

11. A method of operating a mixer, comprising: Using the input port to receive the radio frequency signal; generating, by an oscillator, a first oscillator signal, a second oscillator signal different from the first oscillator signal, and a third oscillator signal inverted relative to the second oscillator signal; receiving the radio frequency signal from the input port and receiving the first oscillator signal using a first switch; receiving a signal from the first switch using a second switch, receiving the second oscillator signal, and generating a corresponding baseband signal based on the radio frequency signal; as well as An oscillator phase noise canceller is utilized to receive the third oscillator signal and reduce phase noise associated with the second oscillator signal.

12. The method according to claim 11, further comprising: generating, using the oscillator, a fourth oscillator signal that is inverted relative to the first oscillator signal; as well as An additional phase noise canceller is utilized to receive the fourth oscillator signal and reduce phase noise associated with the first oscillator signal.

13. The method of claim 12, wherein generating the first oscillator signal, the second oscillator signal, the third oscillator signal, and the fourth oscillator signal comprises: generating a first output signal and a second output signal using a flip-flop; utilizing a first series of buffers to receive the first output signal and generate the first oscillator signal; as well as A second series of buffers is utilized to receive the second output signal and generate the second oscillator signal.

14. The method of claim 13, wherein generating the first oscillator signal, the second oscillator signal, the third oscillator signal, and the fourth oscillator signal further comprises: receiving a signal from a second to last buffer in the first series of buffers using a first inverter and generating the fourth oscillator signal; as well as The third oscillator signal is generated using a second inverter to receive a signal from a second to last buffer in the second series of buffers.

15. The method according to claim 14, further comprising: tuning the oscillator phase noise canceller to adjust an amount of cancellation gain provided by the oscillator phase noise canceller; as well as The delay of the first inverter or the second inverter is adjusted to compensate for process, voltage, and temperature variations.

16. An electronic device, comprising: an antenna configured to receive a radio frequency signal; a baseband processor configured to receive a baseband signal generated based on the radio frequency signal; an oscillator having a first oscillator output terminal and a second oscillator output terminal, generating an oscillator signal at the first oscillator output terminal and generating an inverted oscillator signal inversely phased with respect to the oscillator signal at the second oscillator output terminal; as well as A mixer configured to receive the radio frequency signal from the antenna and to generate the baseband signal, the mixer having a transistor having a gate terminal coupled to the first oscillator output terminal, and A capacitor has a first terminal coupled to the transistor and a second terminal coupled to the second oscillator output terminal.

17. The electronic device according to claim 16, wherein the mixer has an input port and an output port, and the transistor comprises: a first transistor having a first source-drain terminal coupled to the input port, a second source-drain terminal coupled to the output port, and a gate terminal configured to receive a first of the oscillator signals; as well as a second transistor having a first source-drain terminal coupled to the second source-drain terminal of the first transistor, a second source-drain terminal coupled to the output port, and a gate terminal configured to receive a second one of the oscillator signals.

18. The electronic device of claim 17, wherein the capacitor comprises: a first capacitor having a first terminal directly connected to the first transistor and a second terminal configured to receive a first of the inverted oscillator signals; as well as A second capacitor has a first terminal directly connected to the second transistor and a second terminal configured to receive a second one of the inverted oscillator signals.

19. The electronic device of claim 16, wherein the oscillator comprises: a trigger having a first output terminal and a second output terminal; a first plurality of buffers coupled to the first output and configured to generate a first one of the oscillator signals; as well as A second plurality of buffers is coupled to the second output and configured to generate a second one of the oscillator signals.

20. The electronic device of claim 19, wherein the oscillator comprises: a first inverter coupled to a last buffer of the first plurality of buffers, the first inverter configured to generate a first of the inverted oscillator signals and having an adjustable delay; as well as A second inverter is coupled to a last buffer of the second plurality of buffers, the second inverter being configured to generate a second one of the inverted oscillator signals and having an adjustable delay.

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