FinFET semiconductor devices

Abstract

A semiconductor device is disclosed, including a plurality of fins on a substrate. A long channel gate is disposed above a first portion of the plurality of fins. A gate contact is provided, having an extension portion extending from a gate contact base outside an active region into the active region.

Description

[0001] Priority claim

[0002] This patent application claims priority to application No. 16 / 526,756, filed on July 30, 2019, entitled “FinFET Semiconductor Device,” which is assigned to the assignee of the present application and is expressly incorporated herein by reference. Technical Field

[0003] The disclosed subject matter relates to semiconductor devices. In some aspects, the disclosed subject matter relates to metal oxide semiconductor field effect transistor (MOSFET) semiconductor devices, including fin field effect transistor (FinFET) devices having long channel transistors and short channel transistors. Background Art

[0004] The size of traditional semiconductor devices such as MOSFET devices is being reduced to increase processing speed, reduce power consumption, reduce device size and / or reduce manufacturing costs. The demand for improved performance and reduced size of semiconductor devices has led to the use of multi-gate devices. These multi-gate devices include multi-gate fin-type field effect transistors (FinFETs). In a FinFET, a channel is formed on a "fin" extending from a substrate. FinFET devices allow the gate width of the device to be reduced by providing gates on the sides and top of the fins including the channel region.

[0005] However, the size reduction may lead to negative impacts on semiconductor devices including MOSFET devices and FinFETs discussed in this article. Conventional semiconductor devices using FinFETs with long channel transistors and short channel transistors may not achieve their desired threshold voltage (Vt) for each transistor type (long channel or short channel).

[0006] Thus, it may be advantageous to have a FinFET design that can allow both short channel transistors and long channel transistors to achieve their required Vt. Summary of the invention

[0007] This Summary identifies features of some example aspects and is not an exclusive or exhaustive description of the disclosed subject matter. Whether a feature or aspect is included or omitted from this Summary is not intended to indicate the relative importance of those features. Additional features and aspects are described and will become apparent to those skilled in the art upon reading the following Detailed Description and reviewing the accompanying drawings, which form a part thereof.

[0008] One aspect of the present disclosure includes a semiconductor device including a plurality of fins on a substrate, a long channel gate disposed above a first portion of the plurality of fins, and a gate contact having a gate contact base and an extension extending from the gate contact base outside the active region into the active region.

[0009] Another aspect of the present disclosure includes a method for manufacturing a semiconductor device. The method includes: forming a plurality of fins on a substrate. A long channel gate is disposed above a first portion of the plurality of fins. A gate contact is formed to have a gate contact base and an extension extending from the gate contact base outside the active region into the active region.

[0010] Other objects and advantages associated with the various aspects disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The figures are provided to help describe examples of one or more aspects of the disclosed subject matter and are provided solely for purposes of illustration and not limitation thereof.

[0012] Figure 1 is a graph illustrating the difference between conventional short channel and long channel Vt and target values.

[0013] Figure 2 is a graph illustrating the difference in short channel and long channel Vt from target values ​​according to one or more aspects of the present disclosure.

[0014] Figure 3 is a diagram of a traditional FinFET.

[0015] Figure 4 is an illustration of a FinFET according to one or more aspects of the present disclosure.

[0016] Figure 5 is an illustration of a portion of a process of forming a FinFET according to one or more aspects of the present disclosure.

[0017] Figure 6 is an illustration of a portion of a process of forming a FinFET according to one or more aspects of the present disclosure.

[0018] Figure 7 is an illustration of a portion of a process of forming a FinFET according to one or more aspects of the present disclosure.

[0019] Figure 8 is an illustration of a portion of a process of forming a FinFET according to one or more aspects of the present disclosure.

[0020] Fig. 9is an illustration of a portion of a process of forming a FinFET according to one or more aspects of the present disclosure.

[0021] Fig.10 is an illustration of a portion of a process of forming a FinFET according to one or more aspects of the present disclosure.

[0022] Fig.11 is an illustration of a portion of a process of forming a FinFET according to one or more aspects of the present disclosure.

[0023] Fig.12 is an illustration of a portion of a process of forming a FinFET according to one or more aspects of the present disclosure.

[0024] Fig.13 is an illustration of a portion of a process of forming a FinFET according to one or more aspects of the present disclosure.

[0025] Fig.14 is an illustration of a portion of a process of forming a FinFET according to one or more aspects of the present disclosure.

[0026] Fig.15 is an illustration of a portion of a process of forming a FinFET according to one or more aspects of the present disclosure.

[0027] Fig.16 A flow chart illustrating an example method of fabricating a semiconductor device according to one or more aspects of the present disclosure is illustrated.

[0028] Fig.17 An example device is illustrated in which aspects of the present disclosure are integrated.

[0029] Fig.18 Additional examples of devices in which aspects of the disclosure are integrated are illustrated. DETAILED DESCRIPTION

[0030] Various aspects of the subject matter are provided in the following description and related drawings of specific examples of the disclosed subject matter. Alternative solutions can be designed without departing from the scope of the disclosed subject matter. Additionally, well-known elements will not be described in detail or omitted to avoid confusing the relevant details.

[0031] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects. Likewise, the term "aspects" does not require that all aspects include the discussed feature, advantage, or mode of operation.

[0032] The terms used herein describe only specific aspects and should not be construed as limiting any aspect disclosed herein. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to also include plural forms. It will be further understood by those skilled in the art that the terms "comprises", "comprising", "includes" and / or "including" as used herein specify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups thereof.

[0033] Further, various aspects can be described according to the sequence of actions to be performed by, for example, an element of a computing device. Those skilled in the art will recognize that the various actions described herein can be performed by a specific circuit (e.g., an application specific integrated circuit (ASIC)), by a program instruction executed by one or more processors, or by a combination of the two. Additionally, the sequences of actions described herein can be considered to be fully embodied in any form of non-transient computer-readable medium, on which a corresponding computer instruction set is stored, which may cause the associated processor to perform the functions described herein when executed. Therefore, the various aspects described herein can be embodied in several different forms, all of which are considered to be within the scope of the claimed subject matter. In addition, for each of the aspects described herein, the corresponding form of any such aspect can be described herein as, for example, "logic configured as..." and / or other structural components configured to perform the described actions.

[0034] Further, it should be noted that the terms "connected", "coupled" or any variations thereof represent any direct or indirect connection or coupling between elements, and may include the presence of intermediate elements between two elements that are "connected" or "coupled" together via intermediate elements. It should also be understood that, unless otherwise specified, "coupled" or "connected" as used herein means electrical coupling or electrical connection.

[0035] As indicated above, disadvantages of conventional circuit designs include the inability to adjust the desired Vt for both short channel transistors and long channel transistors. Figure 1 The difference between conventional short channel and long channel Vt and target values ​​is illustrated. It should be appreciated that conventional FinFET manufacturing technology cannot meet the target Vt for short channel transistors (which can be used in logic circuits) and long channel transistors (which can be used in analog / radio frequency (RF) circuits) using conventional Vt tuning techniques (e.g., adjusting Well, Halo and / or work function (WF)). Figure 1This result is illustrated for a 7 nanometer node technology with short channels and long channels. The X-axis is devices with different Vt types and gate lengths. For example, RVT_L8 indicates that the Vt type is regular voltage threshold (RVT), gate length = 8nm; LVT_L200 indicates that the Vt type is LVT low voltage threshold (LVT), gate length = 200nm; SLVT_L8 indicates that the Vt type is ultra-low voltage threshold (SVLT), gate length = 8nm. As illustrated in the example, in 7 nanometer technology (7nm), the Vt at opposite sides of the pMOS design produces a short channel (SC) with a Vt of about 30mV to 50mV below the target and a long channel (LC) with a Vt of about 20mV to 50mV above the target. Conventional Vt tuning techniques move the Vt in the same direction, so achieving an SC device by increasing the Vt may result in an LC device further away from the target Vt. Thus, conventional Vt tuning techniques do not provide a solution to meet the Vt of analog circuits using long channel transistors.

[0036] Figure 2 The difference between the target Vt of short channel and long channel in accordance with one or more aspects of the present disclosure is illustrated. Again, the difference between the target Vt of short channel and long channel in 7nm technology is shown. Figure 1 The deviation shown is opposite, Figure 2 In the embodiment, the Vt of the pMOS design produces a short channel (SC) design with a Vt about 10mV to 20mV below the target and a long channel (LC) design with a Vt about 10mV to 20mV above the target, which is a significant improvement over the conventional design and is within the expected range of Vt variation (e.g., -20mV to +20mV). After briefly introducing the conventional design, the details of the FinFET design according to various aspects of the present disclosure will be described in the following paragraphs.

[0037] Figure 3 is a diagram of a conventional FinFET semiconductor device 300. Conventional FET devices are typically planar devices, where the entire channel region of the device is formed parallel to and slightly below the upper planar surface of a semiconductor substrate. In contrast, FinFETs are considered to be 3D devices formed above a semiconductor substrate. Figure 3As shown, according to a plan view, in a short channel (SC) device 310, a short channel gate 314 (SC gate) overlaps a fin 312, which can be made of a material similar to the substrate (e.g., silicon, not shown). The fins 312 can protrude from the substrate and be separated by a plurality of fin-forming trenches between the fins 312. The gate width of the SC device 310 is orthogonal to the gate length direction as illustrated by the short channel gate 314. The portions of the fins 312 covered by the short channel gate 314 are the channel regions of the SC device 310. The portions of the fins 312 located outside the short channel gate 314 are the source / drain regions and are generally considered to be the active region 318 of the SC device 310. A gate contact 316 is provided at one end of the short channel gate 314 located outside the active region 318.

[0038] Likewise, Figure 3 As shown, a long channel (LC) device 320 includes a long channel gate 324 (LC gate) overlapping a fin 322, which may be made of a material similar to the substrate (e.g., silicon, not shown). The fins 322 may protrude from the substrate and be separated by a plurality of fin-forming trenches between the fins 322. The gate width of the LC device 320 is orthogonal to the gate length direction as illustrated by the long channel gate 324. The portions of the fins 322 covered by the long channel gate 324 are the channel regions of the LC device 320. The portions of the fins 322 located outside the long channel gate 324 are the source / drain regions of the LC device 320 and are generally considered to be the active region 328 of the LC device 320. A gate contact 326 is provided at one end of the long channel gate 324 located outside the active region 328.

[0039] As noted above, FinFET devices can be formed with different channel lengths (critical dimensions) and different threshold voltages (Vt), causing the FinFET devices to exhibit different characteristics that allow integrated circuits to have transistors that behave with different characteristics. For example, in some applications, an integrated circuit is designed with multiple short channel devices and multiple long channel devices, such as Figure 3 and Figure 4As shown. The critical dimension or channel length of a long channel device is generally greater than the channel length or critical dimension of a short channel device, and the threshold voltage (Vt) of a short channel device is generally less than the threshold voltage of a long channel device. In contrast, the off-state leakage current of a short channel device is generally greater than the off-state leakage current of a long channel device. In general, short channel devices exhibit faster switching speeds and higher off-state leakage currents relative to long channel devices. Short channel devices are often used in the logic portion of an integrated circuit where fast switching speeds of transistors are desired. In contrast, long channel devices can be used in circuits where the switching speed of a transistor is not as important as its ability to exhibit low off-state leakage currents. For example, long channel devices can be used in analog portions, RF portions, and / or for input / output circuits.

[0040] Figure 4 is an illustration of a FinFET according to one or more aspects of the present disclosure. As illustrated, according to a plan view, the semiconductor device 400 may include one or more short channel (SC) FinFET devices 410 and / or one or more long channel (LC) FinFET devices 420. In the short channel (SC) FinFET device 410, the short channel gate 414 (SC gate) overlaps with the fin 412, which may be made of a material similar to a substrate (not shown). In some aspects, the substrate may be a bulk semiconductor substrate or a silicon on insulator (SOI) substrate, and may be formed of at least one of the following: silicon, germanium, silicon-germanium alloy, carbon-doped silicon, carbon-doped silicon-germanium alloy, gallium arsenide, indium phosphide, or any other conventional semiconductor substrate. The fins 412 may protrude from the substrate and be separated by a plurality of fin-forming grooves between the fins 412. Three fins 412 are provided for illustration only, and more or fewer fins may be provided. Again, two SC gates 414 are provided for illustration only, and the number of gates may be greater or less. The gate width of the SC FinFET device 410 is orthogonal to the gate length direction “L” illustrated by the short channel gate 414. The portion of the fin 412 covered by the short channel gate 414 is the channel region of the SC FinFET device 410. The portion of the fin 412 outside the short channel gate 414 is the source / drain region and is generally considered to be the active region 418 of the SC FinFET device 410. The gate contact 416 is disposed at one end of the short channel gate 414 outside the active region 418. It should be appreciated that the SC FinFET device 410 is similar to the SC device 310.

[0041] Likewise, Figure 4As shown, the semiconductor device 400 may include a long channel (LC) FinFET device 420, including a long channel gate 424 (LC gate) overlapping a fin 422, which may be made of a material similar to the substrate (e.g., silicon, not shown). The fins 422 may protrude from the substrate and be separated by a plurality of fin-forming grooves between the fins 422. Three fins 422 are provided for illustration only, and more or fewer fins may be provided. Similarly, two LC gates 424 are provided for illustration only, and the number of gates may be more or less. The gate width of the LC FinFET device 420 is orthogonal to the gate length direction illustrated by the long channel gate 424. The portion of the fin 422 covered by the long channel gate 424 is the channel region of the LC device 420. The portion of the fin 422 located outside the short channel gate 424 is the source / drain region of the LC FinFET device 420, and is generally considered to be the active region 428 of the LC FinFET device 420. The gate contact 425 includes a gate contact base 426 disposed at one end of the long channel gate 424 outside the active area 428 and also includes an extension portion 427 extending into the active area 428 (e.g., area with fins, source / drain) of the FinFET device 420.

[0042] In some aspects, the extension portion 427 extends beyond the fin 422. It should be appreciated that since the extension portion 427 must be maintained separate from the active area 428 to avoid potential short circuits or excessive leakage to the active area 428, the extension portion 427 may have a different size than the gate contact base 426. In some aspects, the length (L) of the gate contact base 426 is in the range of 30nm to 300nm and the thickness / height is in the range of 10nm to 50nm. In some aspects, the length of the extension portion 427 may be less than the length of the gate contact base 426 (in the "L" direction). For example, the length (L) of the extension portion 427 may be narrower than the gate contact base 426 by about 10nm. Thus, in some aspects, the length of the extension portion may be in the range of 20nm to 290nm. In some aspects, the extension portion is formed on a common center line with the gate contact base (centered in the L direction), for example, each side is narrow by 5nm to provide additional margin to prevent short circuits, leakage, etc. However, in some aspects, the extension portion 427 can have the same length or a greater length (in the "L" direction) relative to the gate contact base 426. The gate contact base 426 and the extension portion 427 can be formed of the same material (e.g., titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), aluminum, tungsten, copper, or any suitable conductive material). The extension portion 427 allows the designer to adjust the additional tuning parameters of the Vt of the long channel device, which also allows for greater adjustment of the traditional tuning parameters (discussed above) so that both the long channel target threshold voltage and the short channel target threshold voltage can be met, such as Figure 2 It should be appreciated that the foregoing dimensions and materials, as well as the illustrated configurations, are provided as examples only and should not be construed as limiting the various aspects disclosed herein.

[0043] Thus, at least one aspect of the present disclosure includes a semiconductor device (e.g., 400) having a plurality of fins (e.g., 422) of a substrate. A long channel gate (e.g., 424) is disposed above a first portion of the plurality of fins (e.g., 422). The semiconductor device (e.g., 400) also has a gate contact (e.g., 425) having a gate contact (e.g., 426) and an extension (e.g., 427) extending from a gate contact base (e.g., 426) outside the active region into the active region (e.g., 418).

[0044] Further, it should be appreciated that the aspects disclosed herein can be manufactured without additional cost, impact on yield, and without additional masks or process steps, as discussed in more detail in the following paragraphs. In the following process descriptions, like parts are numbered the same. However, not all parts will be numbered and / or discussed in successive figures to avoid excessive redundancy and focus on the parts of the device associated with each part of the illustrated manufacturing process.

[0045] Figure 5 is a diagram of a portion of a process for forming a FinFET according to one or more aspects of the present disclosure. As illustrated, a silicon (Si) substrate is effectively divided into three separate regions using a conventional shallow trench isolation (STI) process. For example, by using photolithography techniques, optionally in combination with one or more photolithography masks, a designer can define the lateral dimensions, positions, and shapes of substrate portions (e.g., Si substrates 510, 520, and 530). Optionally, the substrate portions can be formed in a separate patterning sequence. Separate substrate portions can be used for different applications. For example, Si substrate 510 can be used for SC logic devices and separated from other portions of the silicon substrate by STI portions 512. Si substrate 520 can be used for LC logic devices and separated from other portions of the silicon substrate by STI portions 512 and STI portions 522. Si substrate 520 can be used for LC input / output (I / O) devices and separated from other portions of the silicon substrate by STI portions 522. However, it should be appreciated that the illustrated substrate and intended use are for illustration only, and that more or less substrate portions may be formed and intended use may differ from the illustrated examples.

[0046] Figure 6 is an illustration of a portion of a process for forming a FinFET according to one or more aspects of the present disclosure. As illustrated, dummy gates are patterned and formed on various Si substrate portions using conventional processes. For example, SC dummy gate 610 is formed over Si substrate 510, LC dummy gate 620 is formed over Si substrate 520, and LC dummy gate 630 is formed over Si substrate 530.

[0047] Figure 7is an illustration of a portion of a process for forming a FinFET according to one or more aspects of the present disclosure. As illustrated, an insulating spacer can be applied to the gate using a conventional process. For example, an insulating spacer 710 is formed on a SC dummy gate 610 formed on a Si substrate 510, an insulating spacer 720 is formed on a LC dummy gate 620 formed above the Si substrate 520, and an insulating spacer 730 is formed on a LC dummy gate 630 formed above the Si substrate 530. Portions 712, 714 are source / drain regions in the Si substrate 510, portions 722, 724 are source / drain regions in the Si substrate 520, and portions 732, 734 are source / drain regions in the Si substrate 530 and are formed using a conventional process.

[0048] Figure 8 is an illustration of a portion of a process for forming a FinFET according to one or more aspects of the present disclosure. Conventional epitaxially grown materials may be used to form source / drain regions of a FinFET device. As illustrated, source / drain epitaxial layers are grown, source / drain regions 812 and 814 are formed adjacent to the SC dummy gate 610 and are formed above the Si substrate 510, source / drain regions 822 and 824 are formed adjacent to the LC dummy gate 620 and are formed above the Si substrate 520, and source / drain regions 832 and 834 are formed adjacent to the LC dummy gate 630 and are formed above the Si substrate 530.

[0049] Fig. 9 is an illustration of a portion of a process for forming a FinFET according to one or more aspects of the present disclosure. A first dielectric layer 900 may be formed over source / drain regions 812, 814, 822, 824, 832, and 834, SC dummy gate 610, insulating spacer 710, Si substrate 510, LC dummy gate 620, insulating spacer 720, Si substrate 520, LC dummy gate 630, insulating spacer 730, and Si substrate 530. The first dielectric layer 900 may be planarized until the SC dummy gate 610, insulating spacer 710, LC dummy gate 620, insulating spacer 720, LC dummy gate 630, and insulating spacer 730 are exposed through the first dielectric layer 900. Chemical mechanical polishing (CMP) may be performed until the first dielectric layer 900 is substantially coplanar or substantially flush with the top portion as illustrated. The first dielectric layer 900 may remain over the substrate portion and the source / drain regions to protect these regions during subsequent processing.

[0050] Fig.10900 is an illustration of a portion of a process for forming a FinFET according to one or more aspects of the present disclosure. As illustrated, the SC dummy gate 610, the LC dummy gate 620, and the LC dummy gate 630 are removed using conventional techniques such as a vertical etching process such as reactive ion etching (RIE). This leaves a void within the insulating spacers 710, 720, and 730 surrounded by the first dielectric layer 900.

[0051] Fig.11 is an illustration of a portion of a process for forming a FinFET according to one or more aspects of the present disclosure. As illustrated, the gaps left within the insulating spacers 710, 720, and 730 are filled with high-K (HK or HiK) (e.g., 1112) / metal gate (MG) (e.g., 1114) deposits to form SC gate 1110, LC gate 1120, and LC gate 1130. The term high-K refers to a material with a high dielectric constant κ relative to silicon dioxide. After deposition, the gate material is planarized using CMP. As illustrated, after the CMP process, the first dielectric layer 900 is substantially coplanar or substantially flush with the top portions of the SC gate 1110, insulating spacer 710, LC gate 1120, insulating spacer 720, LC gate 1130, and insulating spacer 730.

[0052] Fig.12 1 is an illustration of a portion of a process for forming a FinFET according to one or more aspects of the present disclosure. As illustrated, a second dielectric layer 1200 may be formed over the first dielectric layer 900 and the top portions of the SC gate 1110, the insulating spacer 710, the LC gate 1120, the insulating spacer 720, the LC gate 1130, and the insulating spacer 730.

[0053] Fig.13 is an illustration of a portion of a process for forming a FinFET according to one or more aspects of the present disclosure. As illustrated, source / drain contacts are formed through the first dielectric layer 900 and the second dielectric layer 1200. Specifically, source / drain contacts 1312, 1314, 1322, 1324, 1332, and 1334 are coupled to source / drain regions 812, 814, 822, 824, 832, and 834, respectively.

[0054] Fig.141 is an illustration of a portion of a process for forming a FinFET according to one or more aspects of the present disclosure. As illustrated, gate contacts 1410, 1420, and 1430 are formed through the second dielectric layer 1200. Specifically, the gate contact 1410 is coupled to the SC gate 1110 using a conventional process. However, the LC gate contact 1420 coupled to the LC gate 1120 has an extension portion extending over the top of the LC gate 1120. Likewise, the LC gate contact 1430 coupled to the LC gate 1130 has an extension portion extending over the top of the LC gate 1130.

[0055] Fig.15 1 is an illustration of a two-dimensional (2D) plan view FinFET according to one or more aspects of the present disclosure. As illustrated, an extension portion 1527 extends from a gate contact base 1526 of a gate contact 1420. It should be appreciated that the extension portion 1527 and the gate contact base 1526 of the LC gate contact 1420 are both formed as one structure, such as Fig.14 As shown. Extension portion 1527 extends over the active area and at least one of fins 1522. In some aspects, extension portion 1527 extends over all of fins 1522. Thus, no additional process steps are required to form an extended gate configuration. Similarly, extension portion 1537 extends from gate contact base 1536 of gate contact 1430. Extension portion 1537 extends over the active area and at least one of fins 1532. In some aspects, extension portion 1537 extends over all of fins 1532. It should be appreciated that extension portion 1537 and gate contact base 1536 of LC gate contact 1430 are also formed as one structure, as shown. Fig.14 As shown. Compared to the extended portion of the gate contact previously discussed, the SC gate contact 1410 is formed in a conventional manner and does not extend over the fin 1512. Thus, the various aspects of the present disclosure allow for the improvement of long channel FinFET devices without affecting short channel devices. Additionally, the various aspects disclosed do not require additional process steps and therefore do not negatively impact production complexity or cost.

[0056] It should be appreciated that additional metal processing such as separating source / drain contacts 1312, 1314, 1322, 1324, 1332, and 1334 and coupling gate contacts, source contacts, and drain contacts to additional transistors and / or other elements can be performed using conventional techniques known in the art. Further, it should be appreciated that in the foregoing description, no exhaustive details of conventional process methods for forming FinFETs are provided. Further, the various aspects described herein are not limited to the details provided in the foregoing manufacturing process descriptions, and skilled designers can use a variety of known processes to form semiconductor devices according to the disclosed aspects.

[0057] Thus, it should be appreciated that various aspects disclosed herein include methods for fabricating semiconductor devices. Fig.16 FIG. 1 is a flowchart illustrating an exemplary method of manufacturing a semiconductor device according to some examples of the present disclosure. Fig.16 As shown, method 1600 begins at block 1602: forming a plurality of fins on a substrate. Method 1600 continues at block 1604: forming a long channel gate disposed over a first portion of the plurality of fins. Method 1600 continues at block 1606: forming a gate contact having a gate contact base and an extension extending from the gate contact base outside the active region into the active region.

[0058] Fig.17 An exemplary mobile device according to some examples of the present disclosure is illustrated. Now, with reference to Fig.17 , depicts a block diagram of a mobile device configured according to exemplary aspects and generally designated 1700. In some aspects, the mobile device 1700 can be configured as a wireless communication device that can include one or more FinFET semiconductor devices (e.g., logic, memory, RF, I / O, etc.) as disclosed herein, which can be integrated into various active devices discussed below. As shown, the mobile device 1700 includes a processor 1701. The processor 1701 is shown to include an instruction pipeline 1712, a buffer processing unit (BPU) 1708, a branch instruction queue (BIQ) 1711, and a throttle 1710, as is known in the art. For clarity, other well-known details of these blocks (e.g., counters, entries, trust regions, weighted sums, comparators, etc.) are omitted from this view of the processor 1701.

[0059] The processor 1701 may be communicatively coupled to the memory 1732 via a link. The mobile device 1700 also includes a display 1728 and a display controller 1726, wherein the display controller 1726 is coupled to the processor 1701 and the display 1728.

[0060] In some aspects, Fig.17 It may include a coder / decoder (CODEC) 1734 (e.g., an audio and / or voice CODEC) coupled to the processor 1701; a speaker 1736 and a microphone 1738 coupled to the CODEC 1734; and a wireless controller 1740 (which may include a modem) coupled to a wireless antenna 1742 and the processor 1701.

[0061] In certain aspects where one or more of the above-mentioned blocks are present, the processor 1701, the display controller 1726, the memory 1732, the CODEC 1734, and the wireless controller 1740 may be included in a system-in-package device or a system-on-chip device 1722. An input device 1730 (e.g., a physical or virtual keyboard), a power source 1744 (e.g., a battery), the display 1728, the input device 1730, the speaker 1736, the microphone 1738, the wireless antenna 1742, and the power source 1744 may be located external to the system-on-chip device 1722 and may be coupled to components of the system-on-chip device 1722, such as an interface or controller.

[0062] It should be noted that although Fig.17 A mobile device is depicted, and the processor 1701 and memory 1732, as well as other components that may include one or more semiconductor devices as disclosed herein, may also be integrated into a set-top box, a music player, a video player, an entertainment unit, a navigation device, a personal digital assistant (PDA), a fixed location data unit, a computer, a laptop, a tablet computer, a communication device, a mobile phone, or other similar device.

[0063] Fig.18 Various electronic devices that may be integrated with any of the above-described integrated devices, semiconductor devices, integrated circuits, dies, interposers, packages, or packages-on-package (PoP) according to some examples of the present disclosure are illustrated. For example, a mobile phone device 1802, a laptop device 1804, and a fixed location terminal device 1806 may include one or more semiconductor devices 1800 as described herein and disclosed herein. The integrated device 1800 may be, for example, an integrated circuit, a die, an integrated device, an integrated device package, an integrated circuit device, a device package, an integrated circuit (IC) package, a package-on-package device as described herein. Fig.18 The devices 1802, 1804, 1806 illustrated in the figure are exemplary only. Other electronic devices may also feature the integrated device 1800, including but not limited to a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants, devices supporting global positioning systems (GPS), navigation devices, set-top boxes, music players, video players, entertainment devices), fixed location data units (such as meter reading devices, communication devices, smart phones, tablet computers, computers, wearable devices, servers, routers), electronic devices implemented in motor vehicles, drones, autonomous vehicles, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0064] Based on the foregoing disclosure, it should be appreciated that additional processes for making the various aspects disclosed herein will be apparent to those skilled in the art and that literal reproduction of all variations of the processes discussed above and illustrated in the accompanying figures is not necessary.

[0065] The aforementioned disclosed devices and functions (e.g., as referenced in Figures 4 to 18 Any one or more of the above) can be designed and configured as a computer file (e.g., RTL, GDSII, GERBER, etc.) stored on a computer readable medium. Some or all of such files can be provided to a manufacturing process person who manufactures a device based on such files. The resulting products may include semiconductor wafers, which are then cut into semiconductor dies and packaged into semiconductor chips. These chips can then be employed in devices as described above.

[0066] The methods, sequences and / or algorithms described in conjunction with the embodiments disclosed herein may be directly embodied in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be integrated into the processor.

[0067] Thus, the embodiments disclosed herein may include a non-transitory computer-readable medium embodying a method of manufacturing one or more semiconductor devices as disclosed herein. Thus, since any means for performing the manufacturing process described herein are contemplated by the present disclosure, the present disclosure is not limited to the illustrated examples.

[0068] Although the foregoing disclosure shows various illustrative embodiments, it should be noted that various changes and modifications may be made herein without departing from the teaching scope of the present disclosure as defined in the appended claims. The various materials identified and illustrated by way of example may be replaced by known equivalent or alternative materials. The example manufacturing process discussed above may combine or split various process operations into additional process operations. Additionally, unless specifically described as requiring a specific order or if necessary such as depending on a previous process, the processes, functions, steps and / or actions described in the method claims of the embodiments of the present disclosure described herein do not need to be performed in any particular order. Furthermore, although the elements of the present disclosure may be described or claimed in the singular, the plural is contemplated unless it is explicitly stated to be limited to the singular.

Claims

1. A semiconductor device comprising: A plurality of fins are located on the substrate; a long channel device having a long channel gate disposed over a first portion of the plurality of fins; as well as a gate contact having a gate contact base and an extension extending from the gate contact base outside the active region into the active region; a short channel device having a short channel gate disposed over a second portion of the plurality of fins on a second portion of the substrate; as well as a second gate contact located outside a second active region of the second portion of the plurality of fins, wherein the short channel gate is active, The extension portion allows additional tuning parameters to adjust the threshold voltage of the long channel device, so that the threshold voltage of the long channel device is adjusted to be higher than a target threshold voltage within about 10mV to 20mV, while the threshold voltage of the short channel device is lower than the target threshold voltage within about 10mV to 20mV. 2 . The semiconductor device of claim 1 , wherein the extension portion has a length that is smaller than a length of the gate contact base. 3 . The semiconductor device of claim 1 , wherein the extension portion has a length that is substantially the same as a length of the gate contact base. The semiconductor device of claim 1 , wherein the extension portion extends over at least one fin of the plurality of fins. The semiconductor device of claim 1 , wherein the extending portion extends over the plurality of fins.

6. The semiconductor device according to claim 1, further comprising: a second long channel gate disposed over a third portion of the plurality of fins on a third portion of the substrate; as well as A third gate contact has an extension portion extending from a gate contact base outside the active region into the active region of the third portion of the plurality of fins. 7 . The semiconductor device of claim 6 , wherein the first portion of the substrate, the second portion of the substrate, and the third portion of the substrate are isolated from each other by one or more shallow trench isolation (STI) regions. 8 . The semiconductor device of claim 7 , wherein the first and third portions of the substrate are configured for analog circuits and / or radio frequency circuits, and the second portion of the substrate is configured for logic circuits.

9. The semiconductor device of claim 1, wherein the substrate is a bulk semiconductor substrate.

10. The semiconductor device of claim 1, wherein the substrate is a silicon-on-insulator substrate.

11. The semiconductor device of claim 1, wherein the substrate is at least one of silicon, germanium, a silicon-germanium alloy, carbon-doped silicon, a carbon-doped silicon-germanium alloy, gallium arsenide, or indium phosphide. 12 . The semiconductor device according to claim 1 , wherein the gate contact including the extension portion and the gate contact base are made of the same material.

13. The semiconductor device of claim 12, wherein the gate contact is at least one of the following: titanium nitride, titanium aluminum nitride, titanium aluminum, aluminum, copper, or tungsten. 14 . The semiconductor device of claim 1 , wherein the gate contact base has a length in a range of 30 nm to 300 nm. 15 . The semiconductor device of claim 14 , wherein the gate contact base has a height in the range of 10 nm to 50 nm. 16 . The semiconductor device of claim 14 , wherein the extension portion has a length that is approximately 10 nm narrower than a length of the gate contact base. 17 . The semiconductor device of claim 16 , wherein the extension portion has a common centerline with the gate contact base. 18 . The semiconductor device of claim 1 , wherein the extension portion has a length in a range of 20 nm to 290 nm.

19. The semiconductor device of claim 1, wherein the semiconductor device is incorporated into a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a component in a motor vehicle.

20. A method for manufacturing a semiconductor device, the method comprising: forming a plurality of fins on a substrate; forming a long channel device having a long channel gate disposed over a first portion of the plurality of fins; forming a gate contact having a gate contact base and an extension portion extending from the gate contact base outside the active region into the active region; forming a short channel device having a short channel gate disposed over a second portion of the plurality of fins on a second portion of the substrate; as well as forming a second gate contact located outside a second active area of ​​the second portion of the plurality of fins, wherein the short channel gate is active, The extension portion allows additional tuning parameters to adjust the threshold voltage of the long channel device, so that the threshold voltage of the long channel device is adjusted to be higher than a target threshold voltage within about 10mV to 20mV, while the threshold voltage of the short channel device is lower than the target threshold voltage within about 10mV to 20mV.

21. The method of claim 20, wherein the extension portion has a length that is less than a length of the gate contact base.

22. The method of claim 20, wherein the extension portion has a length that is substantially the same as a length of the gate contact base.

23. The method of claim 20, wherein the extension portion extends over at least one fin of the plurality of fins.

24. The method of claim 20, wherein the extension portion extends over the plurality of fins.

25. The method of claim 20, further comprising: forming a second long channel gate disposed above a third portion of the plurality of fins on a third portion of the substrate; as well as A third gate contact is formed having an extension portion extending from a gate contact base outside the active region into the active region of the third portion of the plurality of fins.

26. The method according to claim 25, further comprising: One or more shallow trench isolation (STI) processes are performed to isolate the first portion of the substrate, the second portion of the substrate, and the third portion of the substrate from one another.

27. The method of claim 20, wherein the substrate is a bulk semiconductor substrate and is at least one of silicon, germanium, a silicon-germanium alloy, carbon-doped silicon, a carbon-doped silicon-germanium alloy, gallium arsenide, or indium phosphide.

28. The method of claim 20, wherein the gate contact including the extension portion and the gate contact substrate are made of the same material and formed in the same process.

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