Chemical etching of non-volatile material for MRAM patterning

Abstract

A method is provided. A substrate disposed in a chamber is exposed to a halogen-containing gas and a plasma is ignited to modify a surface of the substrate to form a modified surface, wherein the halogen-containing gas includes an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin. The substrate is exposed to an activated activation gas to etch at least a portion of the modified surface.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Application No. 62 / 881,131, filed July 31, 2019, which is incorporated herein by reference for all purposes. Background Technology

[0003] The background description provided herein is intended to generally present the context of this disclosure. Nothing described in this background section, nor any potential aspect of the written description, is expressly or impliedly acknowledged as prior art to this application.

[0004] Semiconductor processing involves etching of various materials, including metals and metal alloys. However, as devices shrink and the processing of various structural types becomes more complex, some etching byproducts may redeposit on other exposed areas of the substrate, potentially causing defects and ultimately device malfunction. Therefore, alternative etching techniques are gaining attention.

[0005] In the etching of memory stacks, different metal-containing layers are etched. Dielectric layers may lie between different metal-containing layers. The different metal layers should be etched with minimal redeposition. Summary of the Invention

[0006] To achieve the foregoing and in accordance with the purposes of this disclosure, a method is provided. A substrate placed indoors is exposed to a halogen-containing gas, wherein the halogen-containing gas comprises an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin. In the scope of this specification and claims, the halogen-containing gas comprising an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin means that the gas has molecules, wherein the molecules have at least one halogen atom and at least one atom of at least one of the group consisting of silicon, germanium, carbon, titanium, and tin. A plasma is ignited to modify the surface of the substrate and form a modified surface. The substrate is exposed to an activated gas to etch at least a portion of the modified surface.

[0007] In another form, an apparatus for etching features in a stack is provided. A plasma chamber is provided. A substrate support is located within the plasma chamber. A delivery system delivers gas into the plasma chamber. A gas source provides gas to the delivery system, wherein the gas source includes a halogen-containing gas source and an activating gas source. An electrode provides radio frequency (RF) power to the plasma chamber. At least one RF generator is connected to the electrode. A controller is controllably connected to the gas source and the at least one RF generator. The controller includes at least one processor and a computer readable medium including computer readable code for etching at least a portion of a stack. The computer readable code includes computer readable code for flowing a halogen-containing gas from a halogen-containing gas source into the plasma chamber, wherein the halogen-containing gas includes an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin; computer readable code for igniting a plasma from the halogen-containing gas to modify a surface of a substrate and form a modified surface; computer readable code for flowing an activating gas from an activating gas source; and computer readable code for activating the activating gas to form an activated activating gas in the plasma chamber to etch at least a portion of the modified surface.

[0008] These and other features of the present disclosure will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a schematic diagram of an exemplary substrate.

[0010] Figure 2 is a process flow diagram depicting operations of a method performed in accordance with disclosed embodiments.

[0011] Figures 3A-3G is a schematic diagram of an exemplary substrate operating in accordance with disclosed embodiments.

[0012] Figures 4A-4K is a schematic diagram of an exemplary mechanism for etching a substrate in accordance with certain disclosed embodiments.

[0013] Figure 4L is a schematic diagram of a metal silo composite.

[0014] Figure 5 is a schematic diagram of an exemplary processing chamber for performing disclosed embodiments.

[0015] Figure 6 is a schematic diagram of an exemplary processing apparatus for performing disclosed embodiments.

[0016] Figure 7 is a graph showing the etch rate of CoPt material sputtered exposed to SiCl4with He and He only from experiments performed according to certain disclosed embodiments.

[0017] Figure 8 is a schematic design of another plasma processing chamber used in another embodiment.

[0018] Figure 9 is a schematic diagram of a computer system that can be used to implement embodiments. DETAILED DESCRIPTION

[0019] In the following description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments can be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail, so as not to unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with particular embodiments, it should be understood that this is not intended to limit the disclosed embodiments.

[0020] During processing of semiconductor wafers, features can be etched through metal-containing layers. In the formation of magnetic random access memory (MRAM), multiple thin metal layers, or films, can be etched in sequence to form a magnetic tunnel junction stack.

[0021] A magnetic tunnel junction (MTJ) is composed of a thin dielectric barrier between two magnetic materials. Electrons pass through the barrier by a process of quantum tunneling. This can serve as the basis for magnetic memory-based.

[0022] Spin transfer torque is an effect in which a spin-polarized current can be used to change the orientation of a magnetic layer in an MTJ. Charge carriers (e.g., electrons) have a property called spin, which is a tiny amount of angular momentum inherent to the carrier. Current is usually non-polarized (50% up and 50% down electrons). By passing current through a thick magnetic layer (usually called the "fixed layer"), a spin-polarized current with more electrons of either spin can be created. If this spin-polarized current is directed into a second, thinner magnetic layer ("free layer"), angular momentum can be transferred to the layer, changing its orientation. This effect can be used to excite oscillations, or even flip the orientation of a magnet.

[0023] Spin-transfer torques can be used to flip active components in magnetic random access memory (MRAM). Compared to conventional magnetoresistive random access memory (MRAM) that uses a magnetic field to flip active components, spin-transfer torque magnetic random access memory (STT-RAM or STT-MRAM) offers advantages in terms of lower power consumption and better miniaturization. Spin-transfer torque technology has the potential to enable MRAM devices that combine low current requirements with reduced costs. Ralph, DC; Stiles, MD (April 2008). "Spintransfer torques". Journal of Magnetism and Magnetic Materials 320(7):1190–1216.

[0024] Figure 1 An exemplary MTJ stack is provided. Figure 1 The stack 100 is shown, comprising a silicon oxide etch stop layer 101, a tantalum nitride barrier layer 103, a ruthenium metal layer 105, a fixing layer 107, a dielectric layer 109, a free layer 111, a tantalum layer 113, and another ruthenium metal layer 115. As shown, the MTJ stack 120 is composed of the free layer 111, the dielectric layer 109, and the fixing layer 107. It should be noted that although... Figure 1 Specific chemicals are shown, but other suitable chemicals may be present in such a stack. The free layer and the fixed layer may comprise metals and / or metal alloys, such as cobalt iron or cobalt platinum. Dielectric layer 109 is adjacent to fixed layer 107 and free layer 111.

[0025] One of the key challenges remaining to be overcome in the high-density scaling of spin-transfer torque magnetoresistive random access memory (STT MRAM) is the patterning of MRAM stacks. MRAM stacks contain non-volatile and ferromagnetic materials such as cobalt (Co), iron (Fe), manganese (Mn), nickel (Ni), platinum (Pt), palladium (Pd), and ruthenium (Ru), which are extremely difficult to pattern without the use of complex methods such as ion beam etching (IBE), reactive ion etching (RIE), and wet chemicals. Despite years of development, current patterning techniques still suffer from several drawbacks, such as sidewall redeposition causing tapered profiles and short circuits from the MTJ to the anchor layer, and corrosion that damages the MTJ layer. In some conventional techniques, chlorine-containing chemicals are used to etch the metal, but the etched byproducts include non-volatile compounds that can subsequently redeposit on the sidewalls of the features.

[0026] As described in this article, in MRAM applications, the materials used for the free and fixed layers of MRAM are primarily composed of cobalt-iron-boron (CoFeB), cobalt-platinum alloy (CoPt), and other non-volatile metals. The magnesium oxide (MgO) layer is a critical layer between the free and fixed layers, but it is highly sensitive to electrical and magnetic properties and susceptible to damage from halogen plasma treatment. Therefore, etching processes using physical sputtering with ion beam etching can negatively impact the layers of the MRAM stack. Sputtering-based processes present challenges. For example, in some cases, redeposition of metal material may occur, affecting yield. In some cases, metal material may redeposit along the sidewalls during etching, potentially creating short-circuit paths in the MTJ. Similarly, redeposition at the etch front can create shunt passes connecting pillars. In some cases, when scaling down to smaller devices, aspect ratios may be limited, and this process may not be applicable. For example, because angularly angled ions have difficulty reaching the etch front or the foot of the pillars, thus affecting the etch profile, ion blocking from adjacent pillars can make pattern transfer using IBE difficult when the pitch decreases. In some cases, iso-dense loading may occur because iso-dense regions exhibit more efficient sputtering in the absence of reactant and byproduct transport limitations. Iso-dense indicates that the region has a uniform density.

[0027] Etching non-volatile metals (e.g., Co, CoFe, CoPt) is challenging because common byproducts of metal halides are non-volatile. This paper addresses current issues related to IBE technology by chemically etching these materials used in equipment to form volatile byproducts.

[0028] This document describes a chemical etching method for etching MRAM stacks using atomic layer etching (ALE) processes, wherein the chemical etching method uses a gas containing one or more of silicon, germanium, titanium, carbon, and tin, as well as molecules containing halogens. For example, the ALE chemical process used in some disclosed embodiments may include two operations: (i) silicon- and chloride-containing plasma (e.g., silicon tetrachloride, SiCl4) to modify the surface; and (ii) removing the modified surface by using directional ions to form volatile byproducts. While silicon- and chloride-containing plasmas for modification are described herein, it should be understood that germanium- and halogen-containing plasmas, as well as tin- and halogen-containing plasmas, may also be used in various embodiments. SiCl4-assisted ALE processes fundamentally overcome various challenges, such as those mentioned above, in handling non-volatile metals during the patterning of MRAM.

[0029] ALE is a technique that uses sequential self-limiting reactions to remove thin layers of material. Generally, ALE can be performed using any suitable technique. The concept of an “ALE cycle” is relevant to the discussion of various embodiments herein. Typically, an ALE cycle is the minimum set of operations used to perform a single etching process (e.g., etching a single layer). The result of a single cycle is the etching of a fixed and predictable amount of film on the substrate surface. Typically, an ALE cycle includes modification operations for forming a modified layer, followed by removal operations for removing or etching only that modified layer. The cycle may include certain auxiliary operations, such as scavenging one of the reactants or byproducts. Typically, the cycle contains an example of an operational sequence. For example, an ALE cycle may include the following operations: (i) delivering a reactant gas to the chamber; (ii) purging the reactant gas from the chamber; (iii) delivering a removal gas and optionally plasma; and (iv) purging the chamber. In some embodiments, etching may be performed non-conformally.

[0030] According to the disclosed method, precise etch rate control, damage-free MTJ, and conformal preservation and etch uniformity of MRAM features can be achieved. As described herein, typically, materials such as Si are reacted with halogens such as Cl and metal ions in a substantially stoichiometric manner to form, for example, M-SiCl. x Such substances can form volatile etching byproducts, where M can be Co, Fe, Mn, Ni, Pt, Pd, or Ru. In some embodiments, this is accompanied by silyl (-SiCl) x ) Attached to the metal, M-SiCl x The melting / boiling point of the substance decreases significantly, and the partial pressure increases markedly, especially in a vacuum.

[0031] Using essentially stoichiometric amounts of reactants avoids negative processing effects. For example, if there is excessive silicon (Si) flux in the plasma, Si deposition may occur, potentially preventing the formation of, for example, M-SiCl during the reaction. x Such substances. Conversely, for example, if too little Si is present, it will be due to M-SiCl x The formation of the substance is hindered, thus suppressing the etching rate. Similarly, adding excess chlorine (Cl) to the metal surface will lead to the formation of non-volatile (boiling point above 1200°C) metal chlorides, such as cobalt(II) chloride (CoCl2) or ferric chloride (FeCl3).

[0032] According to one embodiment, atomic layer deposition (ALD) is performed in a chamber to deposit substantially stoichiometric amounts of material on a metal (e.g., CoFe) surface that is reactive with halide and / or halogen gases and the metal to form volatile substances. Examples include silicon nitride (SiN), silicon oxide (SiO2), Si, or titanium dioxide (TiO2). The ALE process activates the deposited Si layer and the metal surface using Cl in the form of chlorine (Cl2) or boron trichloride (BCl3). Excess Cl2 is then extracted from the chamber. In some embodiments, argon (Ar) desorption can be performed, which involves bombarding and further activating the chlorinated surface to allow the formation of volatile metallic silanes, which are then extracted from the chamber. The etching rate reaches its maximum when the Si and Cl reactants are stoichiometrically matched. In some embodiments, ALE and ALD operations can be performed without breaking the vacuum, either in the same chamber or in different chamber modules of a tool.

[0033] In some of the disclosed embodiments, no non-volatile etch products are formed (e.g., MCl). x (A standard halogen plasma-based treatment system reacts with metals to form non-volatile MCl). x The substance reacts with the damaging magnesium oxide (MgO). Certain disclosed embodiments involving the use of SiCl4 plasma allow the etching reaction to form a volatile substance having a metal-silo complex, which may have the chemical formula M-SiCl4. x Metal-silicon composites are volatile byproducts that improve chemical etching. This breakthrough will depend on the transformation of “non-volatile metals” based on physical sputtering processes into the realm of plasma etching.

[0034] Reaction 1 below shows the non-volatile etch product formed in the sputtering process.

[0035] M + Cl → MClx(s) (non-volatile) (1)

[0036] The reaction 2 below shows a volatile etching profile formed in some of the disclosed embodiments.

[0037] M+SiCl x →M-SiCl x (Volatile) (2)

[0038] In various embodiments, the metal designated as M in the chemical formula described herein may be any one or more of Co, Pt, Pd, Fe, Cr, and Ir.

[0039] SiCl4-based etching chemicals can also be incorporated into the ALE process for MRAM patterning to minimize damage to the MTJ. The SiCl4-based ALE process comprises two cyclic operations. These operations include an adsorption operation using SiCl4-plasma to modify the metal surface, forming a modified metal surface; and ion bombardment to remove the modified metal surface by forming volatile etching byproducts. This ALE process removes the modified surface, thereby resetting the etch front and sidewall surfaces after each ALE cycle. The metal surface is etched layer-by-layer rather than continuously exposed to the chemical reactants, reducing damage to the MTJ layer.

[0040] Other types of plasma chemicals can also be used as different precursors to supply Si and Cl substances. Non-limiting examples of Si precursors include silanes, such as silane (SiH4), SixRy (where R is Cl, fluorine (F), bromine (Br), or iodine (I)), and Si i H j R ky = 2x + 2, where i is an integer between 1 and 4, j is an integer between 1 and 10, and k is an integer between 1 and 10. In some cases, x is an integer between 1 and 10, and y = 2x + 2. In some embodiments, the substituents on the silicon atoms of the silane include at least one halogen, while the remaining substituents are any one or more of hydrogen, chlorine, fluorine, bromine, and iodine. The silane can be a cyclosilane or a linear silane. Any suitable halosilane can be used. Halosilanes include at least one halogen group and may or may not include hydrogen and / or carbon groups. Examples of halosilanes are iodosilanes, bromosilanes, chlorosilanes, hydrochlorosilanes, and fluorosilanes. However, when the plasma is ignited, halosilanes (especially fluorosilanes) may form reactive halide substances that can etch silicon materials; therefore, in some embodiments, halosilanes may not be directed into the chamber when the plasma is ignited, thus slowing down the formation of reactive halide substances from the halosilanes. Specific chlorosilanes include tetrachlorosilane, trichlorosilane, dichlorosilane, monochlorosilane, chloropropenesilane, chloromethylsilane, dichloromethylsilane, dichlorodimethylsilane, chloroethylsilane, tert-butylchlorosilane, di(tert-butyl)chlorosilane, chloroisopropylsilane, chlorosec-butylsilane, tert-butyldimethylchlorosilane, tert-hexyldimethylchlorosilane, SiHCl-(N(CH3)2)2, etc.

[0041] This process can also be used for etching other non-volatile materials beyond MRAM stacks, as well as for device processing.

[0042] In some embodiments, certain disclosed embodiments offer various advantages. One advantage is that certain disclosed embodiments minimize metal redeposition of residues. The selected etching chemicals form volatile byproducts that minimize sputtering caused by redeposition compared to physical sputtering treatments that result in redeposition on sidewalls. Simultaneously, chemical etching removes the metal layer and overcomes the problem of metal residues retained or redeposited at the etch lead.

[0043] Another advantage is that some of the disclosed embodiments can utilize minimized loading effects to pattern MRAM stacks. SiCl4-plasma-associated ALE chemical etching allows for minimal loading during MRAM patterning. IBE processes typically etch out uniformly dense, more efficient, and concentrated arrays. SiCl4-based ALE enables aspect ratios to be independent of recesses in the MRAM pillars.

[0044] Another advantage is that some of the disclosed embodiments can be extended to tight pitches, which can be narrower than 200 nm, or narrower than 100 nm, or narrower than 50 nm, or narrower than 20 nm, or narrower than 10 nm, or narrower than 5 nm. For physical sputtering processes from IBE, a major challenge is the difficulty in extending this process to the fabrication of devices with tighter pitches. When the pitch reaches a geometric feature equal to the ion beam angle, the pattern transfer efficiency in ion beam patterning during pattern transfer decreases significantly. In contrast, SiCl4-ALE chemical etching opens a patterning window without the limitations imposed by ion masking.

[0045] The disclosed implementation scheme will now be further described with reference to some specific implementation schemes. Figure 2 It provides a process flow chart for the execution of operations based on the disclosed implementation plan. Figures 3A-3G This is a schematic diagram of an etched exemplary stack provided according to the disclosed embodiments. Figures 4A-4K This is a schematic diagram illustrating an exemplary etching mechanism provided according to the disclosed implementation. It should be noted that, although... Figures 4A-4K The example provided depicts the etching of a metal layer, but the disclosed embodiments can be used to etch various materials, including semiconductors, conductors, and dielectric materials. Furthermore, Figures 4A-4K Exemplary mechanisms are depicted, and it should be understood that the scope of this disclosure or the claims is not limited to any particular operational theory. These figures will be discussed together.

[0046] Reference Figure 2 In operation 202, a substrate is provided. This substrate may be a silicon wafer and a stack of various layers above the silicon wafer. The silicon wafer may be a 200mm, 300mm, or 450mm wafer. The stack may have one or more material layers, such as dielectric, conductive, or semiconductor materials deposited thereon. In various embodiments, the substrate is patterned. The patterned substrate may have “features,” such as pillars, poles, trenches, vias, or contact holes, which may be characterized as narrow and / or re-entrant openings, contractions within the feature, and one or more of high aspect ratios. These features may be formed in one or more of the aforementioned layers. One example of a feature is a pillar or pole in a layer on a semiconductor wafer or wafer. Another example is a trench in a substrate or layer. In various embodiments, the feature may have a lower layer, such as a barrier layer or an adhesion layer. Non-limiting examples of the underlying layer include dielectric layers and conductive layers, such as silicon oxide, silicon nitride, silicon carbide, metal oxide, metal nitride, metal carbide, and metal layers.

[0047] In some embodiments, features such as pillars may have aspect ratios of at least about 1:1, at least about 2:1, at least about 4:1, at least about 6:1, at least about 10:1, or higher. Features may also have dimensions near the opening, such as an opening diameter or linewidth between about 10 nm and 500 nm, for example, between about 25 nm and about 300 nm. The disclosed methods can be performed on a substrate having features with openings less than about 150 nm. Vias, trenches, or other recessed features may be referred to as unfilled features or features. According to various embodiments, the feature profile may gradually narrow and / or include protrusions located at the feature opening. A concave profile is a profile that narrows from the bottom, closed end, or interior of the feature toward the feature opening. Concave profiles are created by protrusions resulting from asymmetric etch kinetics during patterning and / or from non-conformal film steps in previous film deposition (e.g., deposition of diffusion barriers). In many examples, the feature may have a width at the top of the opening that is smaller than the width at the bottom of the feature.

[0048] In some embodiments, the patterned substrate may include various topography features located across the entire substrate. In some embodiments, partially processed gates may be present on the substrate. In many embodiments, the substrate may include multiple layers of metal, dielectric, and semiconductor materials suitable for etching the MRAM stack in subsequent processing. For example, some substrates may include MRAM designs in which the memory element comprises an MTJ. As described elsewhere herein, an MTJ memory element includes two electrodes separated by a thin tunneling barrier. The two electrodes may be ferromagnetic thin film layers, wherein the thin film layers may be elliptical. In some embodiments, the MTJ memory element includes an additional magnetic layer. For example, the MTJ memory element may also include a pair of ferromagnetic layers sandwiching a thin metal layer, these ferromagnetic layers may be referred to as an artificial antiferromagnet and an antiferromagnetic layer. Further description of the shape and design of exemplary MRAM memory elements that can be fabricated on a substrate using the methods described herein is provided in “Cell Shape and Patterning Considerations for Magnetic Random Access Memory (MRAM) Fabrication” by Ditizio, Robert et al., published in “Semiconductor Manufacturing Magazine” pp. 90-96.

[0049] Back Figure 2 During operation 202, a wet etching process is used to fabricate the substrate. For example, in... Figure 3BIn this process, wet etching is performed to etch through the first metal layer 315 on the substrate. In some embodiments, wet etching is not performed.

[0050] Figure 3A An example of an MRAM stack is shown, which may be presented as part of the substrate described herein. It should be noted that while exemplary chemicals for each stack are indicated in the figures, any other suitable materials may be present, not necessarily the chemicals provided, or in combination with the provided chemicals. For example, the disclosed embodiments can be used to etch materials with different patterns (e.g., non-MRAM patterns). It should be noted that although in Figures 3A-3G An exemplary layer is depicted, but the disclosed embodiments can be used to etch other materials on the surface while slowing the redeposition of non-volatile byproducts onto the components of the substrate.

[0051] Substrate 300 includes a SiO2 etch stop layer 301. It should be noted that the etch stop layer 301 may be located on top of other layers (not shown) in substrate 300. In this stack, a thin tantalum nitride (TaN) barrier layer 303 is located on top of the etch stop layer 301. On top of the TaN barrier layer 303 is a metal layer 305 comprising ruthenium (Ru). In some embodiments, the metal layer 305 may have a thickness of about 8 nm. On top of the Ru metal layer 305 is a metal, or a metal alloy layer 307 that may comprise cobalt-platinum (CoPt). In some embodiments, the metal alloy layer 307 may comprise PtMn. As used herein, layer 307 may be referred to as “fixed layer” 307. In some embodiments, the fixed layer 307 may have a thickness of about 10-30 nm. Figure 3A It is also shown that a dielectric barrier layer 309 may include MgO. Hereinafter, the dielectric barrier layer 309 may be referred to as “dielectric layer” 309. In some embodiments, the dielectric barrier layer 309 may be quite thin, for example having a thickness of about 1.5 nm or less.

[0052] On top of the dielectric layer 309 is a metal alloy layer 311, which may include cobalt-iron (CoFe). The metal alloy layer 311 may include CoFeB. Hereinafter, the metal alloy layer 311 may be referred to as the "free layer". On top of the free layer 311 is a tantalum (Ta) barrier layer 313. On top of the Ta barrier layer 313 is a Ru metal layer 315. In the embodiments disclosed herein, the Ru metal layer 315 may be referred to as the "first metal layer", and the Ru metal layer 305 may be referred to as the "second metal layer". Figure 3AAs shown, the Ta hard mask 317 can be deposited and etched into a pattern. It should be noted that the hard mask 317 does not have to be a tantalum hard mask. Other suitable hard masks include, for example, carbon-containing hard masks, nitrogen-containing hard masks, and oxygen-containing hard masks.

[0053] Back Figure 2 In operation 204, material is optionally conformally deposited on the substrate. This material is reactive with halide-containing and / or halogen gases and the substrate material to form a volatile substance. In some embodiments, the material is reactive with one or more halide-containing and / or halogen gases and one or more substrate materials to form a volatile substance. For example, the material may react with cobalt-containing metals and mixtures of BCl3 and Cl2 to form a volatile substance. This material provides a source of both the volatile substance and the protective layer for forming on the substrate. For the purposes described below, this conformal material may be referred to as a "protective layer," but it should be understood that the protective layer comprises a material that reacts with halide-containing and / or halogen gases and the material on the substrate to form a volatile substance and may be conformally conformal.

[0054] The optional protective layer deposited in operation 202 includes elements capable of forming volatile substances using metal halides. This protective layer may include any material containing a group IV transition metal. For example, the protective layer may be a silicon-containing layer, a titanium-containing layer, a germanium-containing layer, a tin-containing layer, a carbon-containing layer, or any combination thereof. Examples of silicon-containing layers include silicon oxide, silicon nitride, amorphous silicon, polycrystalline silicon, and mixtures thereof. Examples of titanium-containing layers include titanium oxide, titanium nitride, titanium, and mixtures thereof. In some embodiments, the protective layer is a dielectric material.

[0055] The protective layer can be deposited by any suitable method, including chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), spin coating, and sputtering. In some embodiments, the protective layer provides a material source for reacting with halide and / or halogen and metal-containing compounds to form volatile substances. For example, a Si source can be directed onto the MRAM surface for reaction by methods other than ALD (e.g., PVD, PECVD, or spin coating), using gases such as SiH4 or SiCl4, or liquids such as orthosilicate compounds (e.g., tetraethyl orthosilicate (TEOS), spin-coated glass (SOG), hexamethyldisilazane (HMDS)).

[0056] For example, the protective layer can be deposited via PECVD. One example involves simultaneously exposing the substrate to a silicon-containing precursor and a nitrogen-containing reactant using plasma. For example, the substrate can be simultaneously exposed to silane and nitrogen plasma. Any suitable precursor and reactant capable of depositing a protective layer can be used to deposit the protective layer, wherein the protective layer contains any of the aforementioned chemicals.

[0057] exist Figure 3C In this illustration, a protective layer 320 is shown deposited on a substrate 300. While the protective layer 320 is depicted, it should be noted that in some embodiments this layer may be optional. In some embodiments, the protective layer 320 may be a first protective layer (e.g., in some operations another protective layer 320 may also be deposited). It should be noted that in this depiction, the protective layer 320 is conformal. In some embodiments, the protective layer 320 does not necessarily have to be conformal. In some embodiments, portions of the protective layer 320 may be sacrificial layers.

[0058] Figure 4A This is another example of a schematic diagram of a portion of substrate 400. In this example, substrate 400 includes a metal layer 411, which may include, for example, Co, Fe, Mn, Pd, Pt, alloys thereof, and combinations thereof. Here, the first metal layer Ru has been wet-etched, and a silicon-containing protective layer 420 (e.g., a Si source) has been deposited over a tantalum hard mask and metal layer 411. While a silicon-containing protective layer 420 is provided, it may be optional in some embodiments, particularly in embodiments where the etching chemicals used during modification include silicon. It should be noted that although with Figure 3C Similar, but Figure 4A The substrate in the illustration has had the tantalum barrier layer removed for illustrative purposes. Although in Figure 4A Specific examples of layers are depicted, but any suitable metal can be located beneath the hard mask, and any composition of the hard mask can be presented. Additionally, any suitable protective layer 420 can be used in the disclosed embodiments, and such protective layer is not limited to… Figure 4A The silicon-containing layer shown in the image.

[0059] Back Figure 2During operation 206, the substrate is exposed to a halogen-containing reactant to modify its surface. In various embodiments, during operation 206, the substrate is exposed to a plasma containing a group IV element (e.g., silicon) and a halogen. That is, in various embodiments, a silicon-containing and halogen-containing plasma is used in operation 206 without prior deposition of a protective layer, or a halogen-containing reactant is used in operation 206 after deposition of a protective layer. One advantage of using a silicon-containing and halogen-containing plasma instead of depositing a protective layer is the reduction of operations performed to achieve layer-by-layer etching. Therefore, metal surfaces can be etched without first depositing a protective layer, resulting in more efficient processing during the patterning of MRAM stacks.

[0060] Silicon- and halogen-containing plasmas can be generated by introducing a silicon- and halogen-containing gas (e.g., a halosilane) and igniting the plasma. In some embodiments, the plasma is generated remotely. In some embodiments, the plasma is generated in situ. The plasma can be generated using ICP or CCP plasma.

[0061] The plasma can be generated using a plasma power between about 100 watts (W) and 900 W. Exposure can be performed for a period sufficient to adsorb at least 60%, 70%, 80%, 90%, or 100% of the substrate surface. The temperature during this operation can be between about 60°C and about 200°C. The chamber pressure during this operation can be between about 1 millitor (mTorr) and about 500 mTorr. The flow rate of the silicon- and halogen-containing precursors can be between about 5 standard cubic centimeters per minute (sccm) and 200 sccm. In some embodiments, a carrier gas such as helium can be used. The flow rate of the carrier gas can be between about 50 sccm and about 500 sccm. In some embodiments, the silicon- and halogen-containing precursors may include helium. Some embodiments may provide a bias voltage. In some embodiments, the bias voltage can be pulsed. The bias voltage range can be from 100V to 2000V.

[0062] Non-limiting examples of Si precursors include silanes, such as SiH4, Si x R y (where R is Cl, F, Br, or I) and Si i H j R kIn some cases, x is an integer between 1 and 10, inclusive, and y = 2x + 2. In some embodiments, the substituents on the silicon atoms of the silane include at least one halogen, while the remaining substituents are any one or more of hydrogen, chlorine, fluorine, bromine, and iodine. The silane can be a cyclosilane or a linear silane. Any suitable halosilane can be used. Halosilanes include at least one halogen group and may or may not include hydrogen and / or carbon groups. Examples of halosilanes are iodosilanes, bromosilanes, chlorosilanes, and fluorosilanes. However, when the plasma is ignited, halosilanes (especially fluorosilanes) may form reactive halide substances that can be etched onto silicon materials. Therefore, in some embodiments, halosilanes may not be directed into the chamber when the plasma is ignited, thus slowing down the formation of reactive halide substances from the halosilanes. Specific chlorosilanes include tetrachlorosilane, trichlorosilane, dichlorosilane, monochlorosilane, chloropropenesilane, chloromethylsilane, dichloromethylsilane, dichlorodimethylsilane, chloroethylsilane, tert-butylchlorosilane, di(tert-butyl)chlorosilane, chloroisopropylsilane, chlorosec-butylsilane, tert-butyldimethylchlorosilane, tert-hexyldimethylchlorosilane, SiHCl-(N(CH3)2)2, etc.

[0063] exist Figure 4G In this process, a cobalt-containing surface (e.g., CoPt) is exposed to a silicon- and halogen-containing plasma generated using SiCl4 in an optional helium environment. Regardless of specific theories, it is believed that this plasma dissociates SiCl4 molecules to produce chlorine and Si-Cl substances. A bias voltage is applied in a pulsed manner to etch the cobalt-containing surface, thereby forming volatile CoSiCl4. x Matter, such as Figure 4HAs shown in the diagram. This bias voltage is pulsed using a specific duty cycle to improve the synergy of the ALE response. A voltage between 100V and 2000V can be used to apply the bias. The duty cycle is a duration for which the bias is turned on for one cycle. The bias voltage can be pulsed between the ON and OFF states, or between high and low states. The high state can have a voltage between approximately 200V and approximately 2000V. The low state can have a voltage between approximately, or practically 0V, and approximately 200V. It should be understood that bias pulsed voltage involves periodic repetition, with each cycle lasting for a duration T. This duration T, within a given cycle, includes the duration of the pulse ON time (the duration of the bias in the ON state) and the duration of the bias OFF time (the duration of the bias in the OFF state). The pulse frequency will be understood as 1 / T. For example, for a bias pulse period T = 100μs, the frequency is 1 / T = 1 / 100μs or 10 kHz. The duty cycle is the percentage or proportion of the bias voltage being in the ON state within one cycle T, such that the duty cycle is the pulse ON time divided by T. For example, for a bias pulse period T = 100 μs, if the pulse ON time is 70 μs (making the bias voltage in the ON state for a duration of 70 μs in one cycle) and the pulse OFF time is 30 μs (making the bias voltage in the OFF state for a duration of 30 μs in one cycle), then the duty cycle is 70%. Figure 7 Examples of the experimental data obtained are shown, in which bias voltage was modulated to compare the etching rates of SiCl4-He exposure and helium sputtering on CoPt surfaces using only bias pulsed pulses and the overall percentage of synergistic effect of these treatments. Overall, bias pulses reduced the sputtering rate and increased the chemical etching composition of SiCl4.

[0064] Figure 4I The use of SiCl was shown x Plasma adsorbs SiCl on the cobalt surface x Example. As shown in the figure, SiCl is ignited. x Reactive substances generated by plasma are adsorbed onto the cobalt surface. In some embodiments, a bias voltage is applied during this adsorption operation. Figure 4J In this process, a bias voltage is used to guide the activated argon to... Figure 4K The modified surface was removed as shown, which resulted in the formation of the volatile metal-silicon composite byproduct CoSiCl. x . Figure 4L Examples of volatile byproducts of metal-silicon composites formed using certain disclosed embodiments are shown. The silicon composite comprises at least one metal atom, at least one silicon atom, and at least one halogen atom.

[0065] In some embodiments, the halogen-containing reactant does not include silicon atoms. In many such embodiments, the silicon source is provided via a protective layer of silicon-containing material. This silicon-free halogen-containing reactant may include boron-containing halogen gases, halogen gases, halide gases, and combinations thereof. Examples include BCl3, boron tribromide (BBr3), boron triiodide (BI3), Cl2, fluorine (F2), bromine (Br2), and iodine (I2). An example of a gas combination may be BCl3 / Cl2. The halogen-containing reactant may react with and / or adsorb onto the protective layer. For example, a silicon protective layer may react with the halogen-containing reactant to form a silicon halide on the substrate surface. It should be noted that in some embodiments, the halogen-containing reactant may cover at least about 90% or at least about 99% of the substrate. In some embodiments, the halogen-containing reactant may be conformally adsorbed onto the substrate surface. In one example, chlorine atoms and / or molecules may adsorb onto the surface of the silicon-containing protective layer.

[0066] Figure 4B An example of a schematic description of chlorine molecule 450a is shown, wherein the example comes from Cl2 reacting with protective layer 420 and adsorbing onto the surface of protective layer 420 to form adsorbed layer 450b on the surface. Figure 4B The schematic substrate 400 in the diagram shows multiple arrows that depict the orientation of Cl2 molecules 450a moving toward the surface of substrate 400 to adsorb onto or react with the surface of substrate 400. A bias voltage of less than about 100V or less than about 60V, for example, about 50V, can be supplied.

[0067] exist Figure 2 In operation 208, the substrate is exposed to an activating gas to etch the modified surface of the substrate. In various embodiments, the activating gas may include one or more inert gases (e.g., argon), carbon dioxide, ammonia, hydrogen-containing gases, and combinations thereof. During operation 208, an activation source, such as plasma, is generated to activate the activating gas, providing the activated gas for etching the substrate. In various embodiments, the activated gas is provided by at least one of: forming plasma from the activated gas, forming an ion beam from the activated gas, and thermally activating the activated gas. Figure 2 In operation 208, the surface having adsorbed halogen-containing compounds and being etched perpendicular to the bias etching direction can be completely etched. In some embodiments, a low bias voltage can be applied to directionally etch the substrate. For example, the bias voltage can be supplied at a power of less than about 100V, such as about 50V. The plasma power can be between about 500W and about 1500W.

[0068] existFigure 4C In this process, the etched compound, including silicon chloride 470, is removed from the horizontal surface of the field region of the tantalum hard mask, and simultaneously the deposited conformal or protective layer 420 is removed to expose the exposed metal layer 411. It should be noted that, as Figure 4C As shown, some protective layers deposited on the sidewalls of the hard mask and the first metal layers (Ta and Ru, respectively) are retained on the sidewalls. This retained protective layer serves as a layer to continuously protect the hard mask from damage or degradation by any possible byproducts from the etching reaction.

[0069] therefore, Figure 3C The substrate in the middle can have after performing operations 206 and 208. Figure 3D The structure depicted in the diagram. Directional etching can be performed, allowing some protective layers 322 to... Figure 3D The dielectric layer 309 is left on the sidewall of the feature while one or more underlying layers (e.g., tantalum barrier layer 313 and most of the CoFe free layer 311) are etched. It should be noted that in many embodiments, the CoFe free layer 311 is not completely etched to avoid easy etching of the dielectric layer 309 and etching into the sidewall of the feature. For example, in cases where the substrate includes the dielectric layer 309 and the dielectric layer 309 includes MgO adjacent to the free layer 311, the free layer 311 can be etched to leave it on the substrate at a depth of approximately [missing information]. With the agreement Between. It should be noted that in many embodiments, various operations are performed cyclically to etch the substrate through these layers.

[0070] For example, such as Figure 2 As shown, in operation 210, operations 206-208 may optionally be repeated. In some embodiments, the repetition of 206 and 208 may constitute a loop. For example, in some embodiments, operations 206 and 208 may be repeated two or more loops. Each loop may be performed such that each loop etches at a time between approximately With the agreement Between, for example, each cycle is approximately Therefore, in some implementations, multiple cyclic pairs of operations 206 and 208 can be used. Figure 3C The substrate shown is etched to etch through a surface of the substrate, wherein this surface of the substrate is perpendicular to the direction of directional etching performed by applying a bias voltage. For example, as Figure 3CAs shown, operations 206 and 208 can be repeated to etch through the conformal or protective layer 320, the tantalum barrier layer 313, and most of the CoFe / CoFeB free layer 311. As described above, the cycle of operations 206 and 208 can be stopped before the CoFe / CoFeB free layer 311 is completely etched to protect the MgO dielectric layer 309, or the cycle of operations 206 and 208 can continue to completely etch through the MgO dielectric layer 309.

[0071] exist Figure 3E In this embodiment, operation 208 can be performed without exposing the substrate to a halogen-containing gas to etch a thin layer through the CoFe / CoFeB free layer 311 and etch the MgO dielectric layer 309. In some embodiments, operation 208 is performed by exposing the substrate to a halogen-free gas. In many embodiments, the dielectric layer is etched by sputtering argon gas using a bias voltage to avoid performing harsh etching chemical processes on the dielectric layer. In some embodiments, harsh etching chemical processes applied to the dielectric layer may etch the dielectric layer under the mask, resulting in potential degradation and device malfunction problems. In some embodiments, a bias voltage is applied during dielectric etching. For example, the bias voltage can be supplied at a power of less than about 100V, such as about 50V.

[0072] Figures 4D-4F A schematic diagram of an exemplary etching mechanism is shown, which is derived from... Figure 4C Continue, so that Figure 2 Operations 206 and 208 are repeated in operation 210. Figure 4D The substrate 400 is shown undergoing repeated operation 206. Figure 4C After the metal layer 411 is exposed, Figure 4D The substrate is exposed to Cl2 450a to modify its surface. As shown, Cl2 can be adsorbed onto the surface of substrate 400 or react with the surface of the substrate to form a chlorine adsorption layer 450b. It should be noted that since the protective layer 420 is retained on the sidewalls during the previous deposition of the silicon-containing material, some chlorine 450b can be adsorbed onto or react with the protective layer 420, while some chlorine 450b can be adsorbed onto or react with the metal surface 411.

[0073] Figure 4E A substrate is shown undergoing repeated operation 208. As shown, argon (e.g., an activation gas) 440 is directed to the substrate, and plasma is ignited to etch the substrate. In various embodiments, such as Figure 4EAs indicated by the arrow, a bias voltage is applied to directionally etch the substrate. The presence of the silicon-containing protective layer 420 utilizes the adsorbed chlorine 450b to form a composite 475 with the metal from the metal surface 411. It should be noted that not all composites 475 can have the same chemical structure. However, in this example, the protective layer 420 provides silicon to form a volatile substance 475 that can be removed from the chamber processing the substrate. In various embodiments, the protective layer 420 may additionally or alternatively include other materials, such as titanium, germanium, and other materials that are reactive with metals and halides and / or halogen gases to form volatile substances.

[0074] In some implementations, a SiO2 / SiN protective layer is deposited on the MRAM metal surface during Si-assisted ALE etching (e.g., Figure 4A The protective layer 420 in the middle). Next, the Si-doped metal surface (e.g., chlorine molecules 450a) is coated with BCl3 / Cl2 gas. Figure 4B (As shown in the figure) activation to form an adsorbed chlorine layer (450b). A directional Ar ion beam of Ar gas (440) bombards the modified layer, breaking it during the process and allowing the formation of new bonds, ultimately resulting in the volatile etch product (M-SiCl). x (475) Released into the gas phase.

[0075] In summary, an exemplary activation reaction can be as follows:

[0076]

[0077] An exemplary desorption / recombination reaction may be as follows:

[0078]

[0079] M-SiCl x The composite is stable and volatile, and can survive Ar sputtering desorption without decomposing into a metallic form. Therefore, redeposition on the sidewalls is reduced or avoided.

[0080] The disclosed embodiments involve depositing materials that are reactive with halides and / or halogen gases and metals to form volatile substances. Examples include silicon-containing materials, titanium-containing materials, germanium-containing materials, tin-containing materials, carbon-containing materials, and combinations thereof. In some embodiments, the deposited material may be a silicon-containing material, such as amorphous silicon, polycrystalline silicon, silicon oxide, or silicon nitride. In some embodiments, the deposited material may be titanium or titanium oxide.

[0081] The disclosed embodiments are also suitable for etching the anchor layer; CoPt, CoPd, PtMn, and various other materials, including Co, Fe, Mn, Pt, Ru, and Ta. This principle applies to all other transition metals in the first, second, and third rows (e.g., Group IV, Group V, and Group VI transition metals), including metals such as Cu. Other stable gaseous complexes within the same Group IV (e.g., Ge and Sn) may exhibit the same behavior.

[0082] Besides Si, other members of group IV in the periodic table (e.g., C, Ge, Sn) can also be used to form similar volatile etching products to form M-CCl in plasma. X Stable and volatile substances such as M-GeClX and M-SnClX. These reactants can be directed as halide gases, such as CClX, SiClX, GeClX, and SnClX (where X is a halogen, such as F, Cl, or Br in various stoichiometry), or other sources that allow these elements to be deposited onto the MRAM metal surface.

[0083] The activation, formation, and desorption of volatile metal etched products can be achieved using methods other than ALE; these methods include reactive ion etching (RIE), electron cyclotron resonance (ECR) etching, or thermal desorption, and in some embodiments, UV treatment may also be used. The disclosed embodiments can also be integrated with wet etching and / or reactive ion etching processes.

[0084] Figure 4F The substrate after etching of a metal surface 411 is shown. It should be noted that some of the protective layer 420 may be etched when operations 206 and 208 are performed in various cycles.

[0085] Therefore, in Figure 2 In operation 212, operations 204-210 may optionally be repeated, such that operation 204 forms a first conformal material, and the repeated operation of operation 204 forms a second conformal material, which is deposited on the substrate to provide further material that is reactive with halide and / or halogen gases and metals on the substrate to form volatile substances.

[0086] Figure 3F An example substrate corresponding to operation 212 is shown. As shown, operation 204 is repeated to further deposit a second protective layer 324 over the substrate. This protective layer 324 can be used to further protect the Ta barrier layer 313, the CoFe free layer 311, and the etched MgO dielectric layer 309.

[0087] Therefore, operations 206 and 208 can be repeated cyclically until the remaining substrate is etched to the etch stop layer. Figure 3G An etched substrate is shown, in which operations 206 and 208 have been cyclically repeated to etch through the CoPt retaining layer 307, the second Ru metal layer 305, and the TaN barrier layer 303. Note that substrate 300 shows residual protective layers 322 and 324 located on the sidewalls. In various embodiments, these layers may be reduced or removed after the stack has been processed. In some embodiments, some or portions of these layers may also be etched when the disclosed embodiments are performed.

[0088] While this disclosure is not theoretically limited, it is believed that the deposition-etching mechanism for MRAM metals (e.g., Co, Fe, Mn, Pd, and Pt) can proceed as follows. This mechanism involves dry chemical etching of these metals via the introduction of Si during the ALE of Cl (e.g., provided by BCl3 and / or Cl2) and Ar, without redeposition of the metal on the sidewalls. As stated above, without being limited to any particular theory, it is believed that the presence of Si or other materials reactive with halide-containing compounds and / or halogen gases and metals leads to volatile etching products such as Co-SiCl. x or Fe-SiCl x The volatile etching products have a high partial pressure in the etching chamber and can be easily pumped out and removed.

[0089] Device

[0090] Inductively coupled plasma (ICP) reactors will now be described, which in some embodiments are suitable for atomic layer etching (ALE) operations and atomic layer deposition (ALD) operations. Such ICP reactors are also described in U.S. Patent Application Publication No. 2014 / 0170853, filed December 10, 2013, entitled “IMAGE REVERSAL WITH AHM GAP FILL FOR MULTIPLE PATTERNING,” which is incorporated herein by reference in its entirety and for all purposes. Although ICP reactors are described herein, it should be understood that capacitively coupled plasma reactors may also be used in some embodiments.

[0091] Figure 5 A schematic cross-sectional view of an inductively coupled plasma integrated etching and deposition apparatus 500 suitable for implementing certain embodiments of this document is shown, an example of which is... The reactor is manufactured by LamResearch Corp., Fremont, California. The inductively coupled plasma device 500 includes a total processing chamber 524 structurally defined by chamber walls 501 and windows 511. Chamber walls 501 may be made of stainless steel or aluminum. Windows 511 may be made of quartz or other dielectric materials. An optional internal plasma grid 550 divides the entire processing chamber into an upper sub-chamber 502 and a lower sub-chamber 503. In most embodiments, the plasma grid 550 can be removed, thereby utilizing the chamber space formed by sub-chambers 502 and 503. A chuck 517 is positioned in the lower sub-chamber 503 near its bottom inner surface. The chuck 517 is configured to receive and hold a semiconductor substrate or wafer 519 on which etching and deposition processes are performed. The chuck 517 may be an electrostatic chuck used to support the wafer 519 when it is present. In some embodiments, an edge ring (not shown) surrounds the chuck 517 and has an upper surface that is substantially coplanar with the top surface of the wafer 519 (when the wafer is present above the chuck 517). The chuck 517 also includes electrostatic electrodes for clamping and releasing the wafer 519. Filters and DC clamping power sources (not shown) may be provided for this purpose. Other control systems may also be provided for lifting the wafer 519 away from the chuck 517. The chuck 517 can be charged with an RF power supply 523. The RF power supply 523 is connected to a matching circuit 521 via a connector 527. The matching circuit 521 is connected to the chuck 517 via a connector 525. In this way, the RF power supply 523 is connected to the chuck 517.

[0092] The element used for plasma generation includes a coil 533 located above window 511. In some embodiments, the disclosed embodiments do not use a coil. The coil 533 is made of a conductive material and includes at least one full turn. Figure 5 The example of coil 533 shown includes three turns. The cross-section of coil 533 is indicated by symbols; coils with an "X" symbol indicate coils extending rotatably into the page, while coils with a "●" symbol indicate coils extending rotatably out of the page. The elements for plasma generation also include an RF power supply 541 configured to provide RF power to coil 533. Generally, RF power supply 541 is connected to matching circuit 539 via connector 545. Matching circuit 539 is connected to coil 533 via connector 543. In this way, RF power supply 541 is connected to coil 533. An optional Faraday shield 549 is positioned between coil 533 and window 511. Faraday shield 549 is held in a spaced-apart relationship relative to coil 533. Faraday shield 549 is positioned directly above window 511. Coil 533, Faraday shield 549, and window 511 are each configured to be substantially parallel to each other. The Faraday shield prevents metal or other substances from depositing on the dielectric window of the processing chamber 524.

[0093] Process gases (e.g., halide gases, halogen-containing gases, silicon- and halogen-containing gases, germanium- and halogen-containing gases, tin- and halogen-containing gases, silicon tetrachloride, chlorine, argon, silicon tetrachloride, oxygen, nitrogen, etc.) may flow into the processing chamber via one or more main gas inlets 560 located in the upper sub-chamber 502 and / or via one or more side gas inlets 570. Similarly, although not explicitly shown, similar gas inlets may be used to supply process gases to the capacitively coupled plasma processing chamber. A vacuum pump, such as a single- or two-stage dry mechanical pump and / or turbomolecular pump 540, may be used to extract process gases from the processing chamber 524 and maintain pressure within the processing chamber 524. For example, during ALD purging operations, the vacuum pump may be used to evacuate the lower sub-chamber 503. Valve-controlled conduits may be used to fluidly connect the vacuum pump to the processing chamber 524 to selectively control the application of the vacuum environment provided by the vacuum pump. During plasma processing, this can be achieved using closed-loop controlled flow limiting devices such as throttle valves (not shown) or pendulum valves (not shown). Similarly, vacuum pumps and valves that are fluidly connected in a controlled manner to the capacitively coupled plasma processing chamber can also be used.

[0094] During operation of the device 500, one or more processing gases may be supplied through gas inlets 560 and / or 570. In some embodiments, the processing gas may be supplied only through the main gas inlet 560 or only through the side gas inlet 570. In some cases, the gas inlets shown in the figure may be replaced by more complex gas inlets, such as one or more nozzles. The Faraday shield 549 and / or optional grid 550 may include internal channels and orifices that allow the processing gas to be delivered to the processing chamber 524. One or both of the Faraday shield 549 and optional grid 550 may serve as nozzles for delivering the processing gas. In some embodiments, a liquid evaporation and delivery system may be located upstream of the processing chamber 524, such that once the liquid reactant or precursor is evaporated, the evaporated reactant or precursor is introduced into the processing chamber 524 through gas inlets 560 and / or 570.

[0095] Radio frequency (RF) power is supplied from RF power supply 541 to coil 533 to allow RF current to flow through coil 533. The RF current flowing through coil 533 generates an electromagnetic field around coil 533. This electromagnetic field generates an induced current within upper sub-chamber 502. The generated ions and free radicals interact physically and chemically with wafer 519 to etch features of the wafer and deposit layers on wafer 519.

[0096] If a plasma grid 550 is used such that both an upper sub-chamber 502 and a lower sub-chamber 503 are present, an induced current acts on the gas present in the upper sub-chamber 502 to generate an electron-ion plasma in the upper sub-chamber 502. An optional internal plasma grid 550 limits the number of thermionic electrons in the lower sub-chamber 503. In some embodiments, the device 500 is designed and operated such that the plasma present in the lower sub-chamber 503 is an ion-ion plasma.

[0097] Both the upper electron-ion plasma and the lower ion-ion plasma can contain both cations and anions, but the ion-ion plasma will have a greater anion-to-cation ratio. Volatile etching and / or deposition byproducts can be removed from the lower sub-chamber 503 through port 522. The chuck 517 disclosed herein can operate in a temperature range ranging from about 10°C to about 250°C. This temperature will depend on the processing operation and specific formulation.

[0098] When installed in a cleanroom or manufacturing plant, device 500 can be coupled to facilities (not shown). Facilities include piping that provides process gases, vacuum, temperature control, and environmental particulate control. These facilities are coupled to device 500 when installed in the target manufacturing plant. Additionally, device 500 can be coupled to a transfer chamber, allowing for the use of typical automation, such as robotic arms, to transfer semiconductor wafers in and out of device 500.

[0099] In some embodiments, system controller 530 (which may include one or more physical or logic controllers) controls some or all of the operation of processing chamber 524. System controller 530 may include one or more memory devices and one or more processors. In some embodiments, device 500 includes a switching system for controlling flow rate and duration when performing the disclosed embodiments. In some embodiments, device 500 may have a switching time of up to about 500 ms or up to about 750 ms. The switching time may depend on the flowing chemical substance, formulation selection, reactor architecture, and other factors.

[0100] In some implementations, system controller 530 is part of a system, which may be part of the examples described above. Such a system may include semiconductor processing equipment, comprising one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of semiconductor wafers or substrates. Electronics may be integrated into controller 530, which may control various components or sub-components of one or more systems. Depending on processing parameters and / or system type, system controller 530 may be programmed to control any of the processes disclosed herein, including controlling the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, entry / exit tools and other delivery tools, and / or wafer delivery of loading locks connected to or interfaced with a specific system.

[0101] In a broad sense, the system controller 530 can be defined as an electronic device having various integrated circuits, logic, memory, and / or software for receiving instructions, issuing instructions, controlling operations, enabling cleaning operations, enabling endpoint measurements, etc. Integrated circuits may include chips in the form of firmware storing program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions delivered to the controller in the form of various individual settings (or program files), which define operating parameters for performing specific processes on or for a semiconductor wafer or system. In some embodiments, operating parameters may be part of a recipe defined by a process engineer to complete one or more processing steps during the fabrication and removal of one or more layers, materials, metals, oxides, silicon, silica, surfaces, circuits, and / or wafer dies.

[0102] In some implementations, system controller 530 may be part of or coupled to a computer integrated with, coupled to, or otherwise networked to the system or a combination thereof. For example, the controller may be in the “cloud” or in whole or in part of a fab host system, allowing remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of manufacturing operations, examine the history of past manufacturing operations, study trends or performance standards from multiple manufacturing operations, change parameters of the current processing, set processing steps to follow the current processing, or initiate a new processing. In some examples, a remote computer (e.g., a server) may provide processing recipes to the system via a network (which may include a local network or the Internet). The remote computer may include a user interface that enables input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, system controller 530 receives instructions in the form of data specifying parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of processing to be performed and the type of tool to which the controller is configured to interface with or control the tool. Therefore, as described above, the system controller 530 can be distributed, for example, by including one or more discrete controllers networked together and operating toward a common purpose (such as the processing and control described herein). An example of a distributed controller for such a purpose is one or more integrated circuits on a room that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer), which are combined to control processing on the room.

[0103] Exemplary systems may include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, rotary rinsing chambers or modules, metal plating chambers or modules, cleaning chambers or modules, chamfering edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, ALD chambers or modules, ALE chambers or modules, ion implantation chambers or modules, orbital chambers or modules, and any other semiconductor processing systems that may be associated with or used in the manufacture and / or preparation of semiconductor wafers.

[0104] As described above, depending on one or more processing steps to be performed by the tool, the controller may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the plant, a host computer, another controller, or tools used in the transport of materials to and from the tool location and / or loading port in the semiconductor manufacturing plant.

[0105] Figure 6A semiconductor processing cluster architecture with various modules interfaced with a vacuum transfer module 638 (VTM) is depicted. The arrangement of various modules “transferring” wafers between multiple storage facilities and processing modules can be referred to as a “cluster tooling architecture” system. An airlock 630 (also called a load lock or transfer module) interfaces with the VTM 638, which in turn interfaces with four processing modules 620a-620d, which can be individually optimized to perform various manufacturing processes. For example, processing modules 620a-620d can be implemented to perform substrate etching, deposition, ion implantation, wafer cleaning, sputtering, and / or other semiconductor processes. In some embodiments, ALD and ALE are performed in the same module. In some embodiments, ALD and ALE are performed in different modules within the same tooling. One or more substrate etching processing modules (any of 620a-620d) can be implemented as disclosed herein, i.e., for depositing conformal films, selectively depositing films via ALD, etching patterns, and other suitable functions according to the disclosed embodiments. The airlock 630 and processing modules 620a-620d can be referred to as "stations". Each station has a facet 636 that interfaces the station with the VTM 638. Within each facet, sensors 1-18 are used to detect the passage of the wafer 626 as it moves between the stations.

[0106] A robotic arm 622 transfers wafers 626 between stations. In one embodiment, the robotic arm 622 has one arm, and in another embodiment, the robotic arm 622 has two arms, each with an end effector 624 to pick up wafers (e.g., wafer 626) for transport. In the Atmospheric Transfer Module (ATM) 640, a front-end robotic arm 632 is used to transfer wafers 626 from a cassette or front-opening standard cassette (FOUP) 634 in the Load Port Module (LPM) 642 to the airlock 630. A module center 628 within processing modules 620a-620d is a location for placing wafers 626. An aligner 644 in the ATM 640 is used to align the wafers.

[0107] In an exemplary processing method, a wafer is placed within one of the FOUPs 634 in an LPM 642. A front-end robot 632 transfers the wafer from the FOUP 634 to an alignment unit 644, allowing the wafer 626 to be properly centered before etching or processing. After alignment, the wafer 626 is moved by the front-end robot 632 into an airlock 630. Because the airlock 630 has the ability to match the environments between the ATM 640 and VTM 638, the wafer 626 can move between the two pressure environments without damage. From the airlock 630, the wafer 626 is moved by the robot 622 via the VTM 638 and into one of the processing modules 620a-620d. To achieve this wafer movement, the robot 622 uses end effectors 624 located on each of its arms. Once the wafer 626 has been processed, it is moved by the robot 622 from the processing modules 620a-620d into the airlock 630. From here, the chip 626 can be moved by the front-end robot 632 to one of the FOUPs 634 or to the aligner 644.

[0108] It should be noted that the computer controlling the movement of the chip can be local to the cluster architecture, or it can be located outside the cluster architecture in the manufacturing facility or in a remote location, connected to the cluster architecture via a network. The above regarding... Figure 5 The described controller can utilize Figure 6 This can be achieved using tools within the framework.

[0109] experiment

[0110] Experiment 1

[0111] One experiment involved modifying a CoPt surface by exposing it to SiCl4-He plasma; and then exposing the modified surface to activated helium under a bias voltage for sputtering using a bias pulse alone. This experiment was conducted at various bias voltages, and the etching rate of the CoPt surface was evaluated. The synergistic effect of these etching treatments was also determined. In some embodiments, the synergistic effect of ALE (Alternating Etching Effect) ranged between 65% and 80%.

[0112] Figure 7 The experimental data obtained are shown, in which the bias voltage was adjusted to compare the etching rates of SiCl4-He exposure and helium sputtering on CoPt surfaces using only bias pulses, and the overall synergistic percentage of these treatments. Overall, the bias pulses decreased the sputtering rate and increased the chemical etching component of SiCl4.

[0113] Figure 8Another example of a plasma processing chamber system 800 that can be used in an embodiment is schematically depicted. The plasma processing chamber system 800 includes a plasma reactor 802, within which a plasma processing confinement chamber 804 is provided. A plasma power supply 806, adjusted by a plasma matching network 808, provides power to a transformer-coupled plasma (TCP) coil 810 located near a dielectric induction power window 812 to generate plasma 814 within the plasma processing confinement chamber 804 by providing inductively coupled power. A peak 872 extends from the chamber wall 876 of the plasma processing confinement chamber 804 to the dielectric induction power window 812, forming a peak ring. The peak 872 is angled relative to the chamber wall 876 and the dielectric induction power window 812 such that the interior angle between the peak 872 and the chamber wall 876, and the interior angle between the peak 872 and the dielectric induction power window 812, are each greater than 90° and less than 180°. As shown, the peak 872 provides an angled ring near the top of the plasma processing confinement chamber 804. The TCP coil (power supply) 810 can be configured to produce a uniform diffusion profile within the plasma processing confinement chamber 804. For example, the TCP coil 810 can be configured to produce a ring-shaped power distribution in the plasma 814. A dielectric induction power window 812 is provided to isolate the TCP coil 810 from the plasma processing confinement chamber 804 while allowing energy to be transferred from the TCP coil 810 to the plasma processing confinement chamber 804. A wafer bias power supply 816, adjusted by a bias matching network 818, provides power to electrodes 820 to set the bias voltage on the substrate 866. The substrate 866 is supported by electrodes 820. A controller 824 controls the plasma power supply 806 and the wafer bias power supply 816.

[0114] The plasma power supply 806 and the wafer bias power supply 816 can be configured to operate at specific radio frequencies, such as 13.56 MHz, 27 MHz, 2 MHz, 60 MHz, 400 kHz, 2.54 GHz, or combinations thereof. The plasma power supply 806 and the wafer bias power supply 816 can be appropriately sized to supply a range of power to achieve desired processing performance. For example, in one embodiment, the plasma power supply 806 can supply power ranging from 50 to 5000 watts, while the wafer bias power supply 816 can supply a bias ranging from 20 to 2000 volts (V). Additionally, the TCP coil 810 and / or electrode 820 can include two or more sub-coils or sub-electrodes. Furthermore, the TCP coil 810 is an electrode type used to provide RF power within the plasma processing confinement chamber 804. The sub-coils or sub-electrodes can be powered by a single power supply or by multiple power supplies.

[0115] like Figure 8As shown, the plasma processing chamber system 800 also includes a gas source / gas supply mechanism 830. In this embodiment, the gas source 830 includes: a halogen-containing gas source 832, wherein the halogen-containing gas comprises elements selected from the group consisting of silicon, germanium, carbon, titanium, and tin; an activation gas source 834; a group IV element-containing gas source 836; and a dielectric etching gas source 838. The gas source 830 is fluidly connected to the plasma processing confinement chamber 804 via a gas inlet, for example, a gas injector 840. The gas injector 840 can be located in any advantageous position within the plasma processing confinement chamber 804 and can be in any form for injecting gas. However, it is preferable that the gas inlet be configured to produce an "adjustable" gas injection profile. An adjustable gas injection profile allows for independent adjustment of the corresponding gas flow rates to multiple regions within the plasma processing confinement chamber 804. More preferably, the gas injector 840 is mounted to a dielectric induction power window 812. The gas injector 840 can be mounted on, within, or formed part of the dielectric induction power window 812. Processing gases and byproducts are removed from the plasma processing confinement chamber 804 via a pressure control valve 842 and a pump 844. The pressure control valve 842 and pump 844 also maintain a specific pressure within the plasma processing confinement chamber 804. The pressure control valve 842 can maintain a pressure of less than 1 Torr during processing. An edge ring 860 is positioned around the substrate 866. The gas source / gas supply mechanism 830 is controlled by a controller 824. A Kiyo manufactured by Lam Research Corp. (Fremont, CA) can be used in practical implementations.

[0116] Figure 9 This is a high-level block diagram of a computer system 900, which is adapted to be used in the implementation scheme. Figure 8The controller 824. Computer systems can take many physical forms, ranging from integrated circuits, printed circuit boards, and small handheld devices to supercomputers. Computer system 900 includes one or more processors 902, and may further include an electronic display device 904 (for displaying graphics, text, and other data), main memory 906 (e.g., random access memory (RAM)), storage device 908 (e.g., hard disk drive), removable storage device 910 (e.g., optical disc drive), user interface device 912 (e.g., keyboard, touchscreen, keypad, mouse, or other positioning device), and communication interface 914 (e.g., wireless network interface). Communication interface 914 enables software and data to be transferred between computer system 900 and external devices via a link. The system may also include communication infrastructure 916 (e.g., communication bus, cross-over bar, or network) to which the aforementioned devices / modules are connected.

[0117] Information transmitted via communication interface 914 may be in the form of signals that can be received by communication interface 914 via a communication link. These signals may be, for example, electronic, electromagnetic, optical, or other signals. The communication link carries the signals and may be implemented using wires or cables, optical fibers, telephone lines, cellular telephone links, radio frequency links, and / or other communication channels. Using such a communication interface, it is anticipated that one or more processors 902 may receive information from the network or output information to the network during the implementation of the above method steps. Furthermore, the method implementation may be executed solely on the processor or may be executed in conjunction with a remote processor on a network such as the Internet, with the remote processor sharing some processing capabilities.

[0118] The term "non-transitory computer-readable medium" generally refers to media such as main memory, secondary storage, removable storage devices, and storage devices (e.g., hard disks, flash memory, hard disk drive storage, CD-ROMs, and other forms of permanent storage), and should not be construed as encompassing transient objects such as carrier waves or signals. Examples of computer code include machine code, such as machine code generated by a compiler, and files containing higher-level code that is executed by a computer using an interpreter. Computer-readable media can also be computer code that is transmitted via computer data signals embodied in a carrier wave and represented as a sequence of instructions executable by a processor.

[0119] Such a computer-readable medium may contain computer-readable code for exposing a substrate placed indoors to a halogen-containing gas and igniting a plasma to modify the surface of the substrate, thereby forming a modified surface (step 206), wherein the halogen-containing gas comprises an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin. The computer-readable medium may also contain computer-readable code for exposing the substrate to an activated gas to etch at least a portion of the modified surface (step 208).

[0120] In another embodiment, an ion beam processing chamber can be used. In this embodiment, a substrate having a memory stack is placed in the ion beam processing chamber. Ion beam etching is provided by flowing a halogen-containing gas into the ion beam processing chamber, wherein the halogen-containing gas comprises an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin. The halogen-containing gas is converted into plasma to modify the surface of the memory stack on the substrate, forming a modified surface of the stack on the substrate. While the halogen-containing gas is flowing into the ion beam processing chamber and plasma is formed, an activated gas is provided to etch the modified surface. In this embodiment, the activated gas is argon. The argon gas is activated by forming an ion beam directed to the substrate.

[0121] In another embodiment, a capacitively coupled plasma (CCP) chamber can be used. In this embodiment, a substrate having a memory stack is placed in the CCP chamber. Etching is provided by flowing a halogen-containing gas into the CCP chamber, wherein the halogen-containing gas comprises an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin. The halogen-containing gas is converted into plasma to modify the surface of the memory stack on the substrate, and a modified surface of the stack on the substrate is formed. While the halogen-containing gas is flowing into the CCP chamber and plasma is formed, an activated gas is provided to etch the modified surface. In this embodiment, the activated gas is argon. The argon gas is activated by CCP energy, and a bias voltage is applied to accelerate the activated argon gas toward the substrate.

[0122] in conclusion

[0123] While the above embodiments have been described in detail for clarity, it will be apparent that certain variations and modifications may be implemented within the scope of the appended claims. It should be noted that many alternative processes, systems, and apparatuses exist for carrying out the embodiments of the invention. Therefore, the embodiments of the invention should be considered illustrative rather than restrictive, and are not limited to the details given herein.

Claims

1. A method for etching a metal-containing substrate, comprising: a) Exposing a metal-containing substrate placed indoors to a halogen-containing gas and igniting a plasma to modify the surface of the metal-containing substrate, thereby forming a modified surface of a composite consisting of a halogen, a metal from the metal-containing substrate, and at least one of silicon, germanium, carbon, titanium, and tin, wherein the halogen-containing gas includes elements selected from the group consisting of silicon, germanium, carbon, titanium, and tin. as well as b) Exposing the metal-containing substrate to an activated activation gas to etch at least a portion of the modified surface, wherein exposing the metal-containing substrate to the activated activation gas to etch at least a portion of the modified surface forms volatile byproducts, wherein the volatile byproducts are complexes comprising halogens, metals from the metal-containing substrate, and at least one of silicon, germanium, carbon, titanium, and tin.

2. The method according to claim 1, wherein the halogen-containing gas is silicon tetrachloride.

3. The method according to claim 1, wherein the halogen-containing gas is selected from the group consisting of chlorosilanes, bromosilanes, iodosilanes, hydrochlorosilanes and fluorosilanes.

4. The method of claim 1, wherein exposing the substrate to the activated activation gas comprises applying a bias voltage.

5. The method of claim 4, wherein the bias voltage is pulsed.

6. The method of claim 4, wherein the bias voltage is applied using a voltage between 100V and 2000V.

7. The method of claim 1, wherein exposing the substrate to the halogen-containing gas and igniting the plasma comprises: Apply a bias voltage.

8. The method of claim 1, wherein the substrate is exposed to the activated activation gas to produce a volatile metal-silicon composite.

9. The method according to claim 1, further comprising depositing a layer of group IV element material on the substrate prior to step a).

10. The method according to claim 1, wherein step a and step b are performed simultaneously.

11. The method of claim 1, wherein step a is performed prior to step b in a plurality of cycles of atomic layer etching.

12. The method of claim 1, wherein the activated gas is selected from the group consisting of plasma formed from the activated gas and ion beam formed from the activated gas.

13. The method of claim 1, wherein step b includes providing an ion beam during step a.

14. The method of claim 13, wherein the ion beam is an argon ion beam.

15. The method of claim 1, wherein the metal-containing substrate comprises at least one layer selected from one or more layers of the group consisting of group IV transition metals, group V transition metals, group VI transition metals, and combinations thereof.

16. The method of claim 15, wherein the metal-containing substrate comprises a dielectric material layer.

17. The method of claim 1, further comprising etching one or more layers of the metal-containing substrate by reactive ion etching.

18. The method of claim 1, wherein the metal-containing substrate comprises one or more metal layers, a free layer, a dielectric barrier layer, and a fixed layer, wherein the dielectric barrier layer is disposed between the free layer and the fixed layer, and the free layer, the dielectric barrier layer, and the fixed layer are disposed between the one or more metal layers.

19. An apparatus for etching features in a metal-containing substrate, comprising: Plasma chamber; A delivery system for delivering gas to the plasma chamber; One or more gas sources for supplying the gas to the delivery system; At least one RF generator; and A controller, controllably connected to the one or more gas sources and the at least one RF generator, wherein the controller includes one or more processors configured to: A halogen-containing gas is flowed from one or more gas sources into the plasma chamber, wherein the halogen-containing gas comprises elements selected from the group consisting of silicon, germanium, carbon, titanium, and tin; Plasma is ignited from one or more gas sources to modify the surface of the metal-containing substrate and form a modified surface of a composite consisting of halogen, metal from the metal-containing substrate, and at least one of silicon, germanium, carbon, titanium, and tin. The activation gas flows from one or more gas sources into the plasma chamber; as well as The activation gas from one or more gas sources is activated into an activated gas to etch at least a portion of the modified surface, wherein the activated gas reacts with the halogen-containing gas and the metal-containing substrate to form volatile byproducts, wherein the volatile byproducts are complexes comprising halogens, metals from the metal-containing substrate, and at least one of silicon, germanium, carbon, titanium, and tin.

20. The apparatus of claim 19, wherein the one or more gas sources comprise silicon tetrachloride gas sources.

21. The apparatus of claim 19, wherein the one or more gas sources comprise at least one of a chlorosilane gas source, a bromosilane gas source, an iodosilane gas source, a hydrochlorosilane gas source, and a fluorosilane gas source.

22. The apparatus of claim 19, further comprising a bias power supply, wherein the controller is further configured to control the bias power supply to activate the activating gas.

23. The apparatus of claim 19, further comprising a bias power supply, wherein the controller is further configured to control the bias power supply to apply a bias when the plasma is ignited.

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