A method for fine-grained switching of data cache attributes

Abstract

The present invention discloses a method for fine-grained switching of data cache attributes, comprising the following steps: S1: compile option identification: identifying the ‑fdynamic‑uncache‑symbols option from a compile command of a program, and if the identification is successful, enabling a compiler cache dynamic configuration mechanism; S2: looping and processing program declared data to determine the default cache attribute of the data; S3.1: for data with a default attribute of being cacheable, assuming that its symbol is "xxx", the compiler performs compile instruction processing; S3.2: for data with a default attribute of being non-cacheable, assuming that its symbol is "xxx", the compiler performs compile instruction processing. The present invention improves the overall utilization rate of user program data to cache space, thereby improving program running performance.

Description

Technical Field

[0001] The present invention relates to a method for fine-grained switching of data cache attributes, belonging to the technical field of high-performance computing. Background Art

[0002] The performance of processors has been continuously increasing. However, the performance of applications is still affected by the storage system. People have adopted various solutions from both software and hardware perspectives to improve the access performance of memories. The most widely used is the cache memory Cache. Around the application of Cache, many access scheduling, data mapping, space allocation and other strategies have emerged. Among them, the cache coherence protocol that ensures data consistency among multiple caches is an important part.

[0003] With the development of multi-core / many-core processors, there may be its own local cache on each core, and maintaining the coherence of numerous caches has become a thorny problem. To balance the hardware overhead, the cache coherence protocol is usually not particularly strict and often adopts a weak coherence protocol.

[0004] In some processors equipped with Cache, both cacheable access and non-cacheable access are supported. Cacheable access can utilize the low latency of Cache to improve the overall execution performance of the program. However, due to the possible copy correctness problems caused by the incomplete cache coherence mechanism, in some scenarios, non-cacheable access must be used to directly access the main memory, such as atomic operations, lock operations, synchronization operations, coexistence of memory access and DMA access, etc.

[0005] In processors that support both cache access and non-cache access, the access attributes of data are usually described in the form of keywords, that is, the cacheable access and non-cacheable access data are distinguished. The data described by non-cacheable access keywords always adopts the way of directly accessing the main memory during the running of the user program. Another situation is that through compiler analysis, non-cacheable access instructions are generated for specific program segments and data access methods, or non-cacheable access instructions are inserted in the form of embedded assembly. The above methods all have certain limitations. The form of keywords is not flexible enough. The data declared in the non-cacheable way can only access the main memory all the time. In fact, there is still a possibility of accessing the cache during its life cycle. Such processing reduces the utilization rate of the cache. The processing of the compiler is too biased towards the machine bottom layer, and it is not easy for upper-layer users to directly participate. It is not convenient to combine according to their own ideas and with the actual application topics. At the same time, the analysis of the compiler will also have certain risks and cannot achieve a good balance between correctness and practicality. Summary of the Invention

[0006] The object of the present invention is to provide a method for fine-grained switching of data cache attributes, which improves the overall utilization rate of the Cache space by user program data, thereby improving the program running performance.

[0007] To achieve the above object, the technical solution adopted by the present invention is: to provide a method for fine-grained switching of data cache attributes, including the following steps:

[0008] S1: Compilation option recognition: Identify the -fdynamic-uncache-symbols option from the compilation command of the program. If the recognition is successful, enable the compiler cache dynamic configuration mechanism and enter S2. If the -fdynamic-uncache-symbols option is not recognized, then exit.

[0009] S2: Process the data declared by the program in a loop to determine the default Cache attribute of the data: Query the syntax tree information of the processed data to obtain the default Cache access attribute. If the default Cache access attribute is Cacheable access, enter S3.1. If the default Cache access attribute is non-Cacheable access, enter S3.2. If all the data has been processed, then exit.

[0010] S3.1: For the data with the default attribute of Cacheable access, assuming its symbol is "xxx", the compiler performs compilation directive processing, and the specific operations are as follows:

[0011] S3.1.1: Identify the compilation directive of #pragma uncache "xxx". If the recognition is successful, enter S3.1.2. If the recognition is unsuccessful, then enter S3.1.3.

[0012] S3.1.2: Identify the compilation directive of #pragma resume_cache "xxx". If the recognition is successful, then identify the code text between #pragma uncache "xxx" and #pragma resume_cache "xxx" as the transformation area. Otherwise, identify the code text from after #pragma uncache "xxx" to the end of this program file as the transformation area, and enter S3.1.5.

[0013] S3.1.3: Identify the compilation directive of #pragma uncache "xxx@@foo", where foo is a function name in the program file. If the recognition is successful, enter S3.1.4. If the recognition is unsuccessful, then enter S2 to process the next data.

[0014] S3.1.4. Identify the code text of the foo function in the program file as the transformation area and proceed to S3.1.5;

[0015] S3.1.5. Use the non-cacheable access mechanism or instructions provided by the processor to replace all accesses to the symbol xxx within the transformation area with non-cacheable access forms, then proceed to S2 to process the next data;

[0016] S3.2: For data with the default attribute of non-cacheable access, assuming its symbol is "xxx", the compiler performs compilation directive processing. The specific operations are as follows:

[0017] S3.2.1. Identify the compilation directive #pragma cache "xxx". If successful, proceed to S3.2.2; if not, proceed to S3.2.3;

[0018] S3.2.2. Identify the compilation directive #pragma resume_uncache "xxx". If successful, identify the code text between #pragma cache "xxx" and #pragma resume_uncache "xxx" as the transformation area; otherwise, identify the code text from after #pragma cache "xxx" to the end of this program file as the transformation area, and then proceed to S3.2.5;

[0019] S3.2.3. Identify the compilation directive #pragma cache "xxx@@foo", where foo is a function name in the program file. If successful, proceed to S3.2.4; if not, proceed to S2 to process the next data;

[0020] S3.2.4. Identify the code text of the foo function in the program file as the transformation area and proceed to S3.2.5;

[0021] S3.2.5. Use the cacheable access mechanism or instructions provided by the processor to replace all accesses to the symbol xxx within the transformation area with cacheable access forms, then proceed to S2 to process the next data.

[0022] Due to the application of the above technical solutions, the present invention has the following advantages compared with the prior art:

[0023] Based on the characteristics of a processor architecture that supports both cache access and non-cacheable access simultaneously, the present invention proposes a method for fine-grained switching of data cache attributes. The user identifies the data cache attributes through compilation directives, configures the memory space for data access (cacheable space / non-cacheable space) by modifying the instruction sequence, and assists the user in fine-grained management and control of data access attributes, improving the overall utilization rate of the cache space for user program data and thus enhancing the program running performance. Description of the Drawings

[0024] Appendix Figure 1 It is a schematic diagram of a method for fine-grained switching of data cache attributes of the present invention. Detailed Embodiment

[0025] Embodiment: The present invention provides a method for fine-grained switching of data cache attributes, including the following steps:

[0026] S1: Compilation option recognition: Identify the -fdynamic-uncache-symbols option from the compilation command of the program. If the recognition is successful, enable the compiler cache dynamic configuration mechanism and proceed to S2. If the -fdynamic-uncache-symbols option is not recognized, then exit.

[0027] S2: Process the data declared in the program in a loop and determine the default cache attribute of the data: Query the syntax tree information of the data being processed to obtain the default cache access attribute. If the default cache access attribute is cacheable access, proceed to S3.1. If the default cache access attribute is non-cacheable access, proceed to S3.2. If all the data has been processed, then exit.

[0028] S3.1: For the data with a default attribute of cacheable access, assuming its symbol is "xxx", the compiler performs compilation directive processing, and the specific operations are as follows:

[0029] S3.1.1: Identify the compilation directive #pragma uncache "xxx". If the identification is successful, proceed to S3.1.2. If the identification is unsuccessful, then proceed to S3.1.3.

[0030] S3.1.2. Identify the pragma directive #pragma resume_cache “xxx”. If successful, identify the code text between #pragma uncache “xxx” and #pragma resume_cache “xxx” as the transformation area; otherwise, identify the code text from after #pragma uncache “xxx” to the end of this program file as the transformation area, and proceed to S3.1.5;

[0031] S3.1.3. Identify the pragma directive #pragma uncache “xxx@@foo”, where foo is a function name in the program file. If successful, proceed to S3.1.4; if not, proceed to S2 to process the next data;

[0032] S3.1.4. Identify the code text of the foo function in the program file as the transformation area, and proceed to S3.1.5;

[0033] S3.1.5. Use the non-cacheable access mechanism or instructions provided by the processor to replace all accesses to symbol xxx within the transformation area with non-cacheable access forms, then proceed to S2 to process the next data;

[0034] S3.2: For data with the default attribute of non-cacheable access, assuming its symbol is “xxx”, the compiler performs pragma directive processing as follows:

[0035] S3.2.1. Identify the pragma directive #pragma cache “xxx”. If successful, proceed to S3.2.2; if not, proceed to S3.2.3;

[0036] S3.2.2. Identify the pragma directive #pragma resume_uncache “xxx”. If successful, identify the code text between #pragma cache “xxx” and #pragma resume_uncache “xxx” as the transformation area; otherwise, identify the code text from after #pragma cache “xxx” to the end of this program file as the transformation area, and proceed to S3.2.5;

[0037] S3.2.3. Identify the pragma directive #pragma cache “xxx@@foo”, where foo is a function name in the program file. If successful, proceed to S3.2.4; if not, proceed to S2 to process the next data;

[0038] S3.2.4. Identify the code text of the foo function in the program file as the transformation area, and proceed to S3.2.5;

[0039] S3.2.5. Utilize the Cache-accessible mechanism or instructions provided by the processor to replace all accesses to the symbol xxx within the transformation area with Cache-accessible forms, then proceed to S2 to process the next data.

[0040] The further explanation of the above embodiments is as follows:

[0041] The present invention proposes a method for fine-grained switching of data Cache attributes, designs and implements a dynamic Cache configuration mechanism based on compilation options and compilation directive statements. The flowchart is as Figure 1 shown, mainly consisting of three parts: compilation option recognition, data default Cache attribute determination, and compilation directive processing.

[0042] When adopting the above method for fine-grained switching of data cache attributes, based on the characteristics of the processor structure that supports both Cache access and non-Cache access, a method for fine-grained switching of data cache attributes is proposed. The user identifies the data cache attributes through compilation directive words, configures the memory space (Cacheable space / non-Cacheable space) for data access by modifying the instruction sequence, assisting the user in fine-grained management and control of data access attributes, improving the overall utilization rate of the Cache space for user program data, and thus improving the program running performance.

[0043] To facilitate a better understanding of the present invention, the terms used in this article will be briefly explained below:

[0044] Cache: High-speed cache memory, located between the processor and the main memory, with a small scale and a very fast access speed.

[0045] Cache-accessible: In a processor equipped with a Cache, the access to data or instructions will first access the Cache. If the Cache is hit, the data in the Cache will be accessed. If the Cache is not hit, the main memory will be accessed, and at the same time, the corresponding Cache line will be loaded from the main memory into the Cache.

[0046] Non-Cache-accessible: In a processor equipped with a Cache, data or instructions directly access the main memory without passing through the Cache.

[0047] Cache Coherence: Each processor or each core of a multi-core / many-core processor may have its own cache and share the same main memory. When modifying the same memory area, ensuring the consistency of the shared data in their respective caches is called cache coherence.

[0048] DMA: direct memory access, which is a data exchange mode that directly accesses data from memory without going through the CPU.

[0049] The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose is to enable those who are familiar with this technology to understand the content of the present invention and implement it accordingly. It should not be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit and essence of the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for fine-grained switching of data cache attributes, characterized in that: The following steps are involved: S1: Compile option identification: Identify the -fdynamic-uncache-symbols option from the program's compile command. If the identification is successful, enable the compiler cache dynamic configuration mechanism and enter S2. If the -fdynamic-uncache-symbols option is not identified, exit. S2: Loop through the data declared by the program to determine the default cache attribute of the data: query the syntax tree information of the processed data to obtain the default cache access attribute. If the default cache access attribute is cacheable, enter S3.

1. If the default cache access attribute is not cacheable, enter S3.

2. If all data are processed, exit. S3.1: For data with the default attribute of cacheable, assuming its symbol is "xxx", the compiler performs compilation instruction processing. The specific operations are as follows: S3.1.1, identify the compilation instruction #pragma uncache "xxx", if the recognition is successful, go to S3.1.2, if the recognition is unsuccessful, go to S3.1.3; S3.1.2, identify the compilation instruction #pragma resume_cache "xxx". If the identification is successful, mark the code text between #pragmauncache "xxx" and #pragma resume_cache "xxx" as the transformation area. Otherwise, mark the code text from after #pragma uncache "xxx" to the end of this program file as the transformation area, and go to S3.1.

5. S3.1.3, identify the compilation instruction #pragma uncache "xxx@@foo", where foo is the name of a function in the program file. If the recognition is successful, go to S3.1.

4. If the recognition is unsuccessful, go to S2 to process the next data; S3.1.4, identify the code text of the foo function in the program file as a transformation area, and proceed to S3.1.5; S3.1.

5. Use the non-cacheable access mechanism or instruction provided by the processor to replace all accesses to symbol xxx within the transformation area with non-cacheable access forms, enter S2, and process the next data; S3.2: For data with the default attribute of non-cacheable, assuming its symbol is "xxx", the compiler performs compilation instruction processing. The specific operations are as follows: S3.2.

1. Identify the compilation instruction #pragma cache "xxx". If the identification is successful, go to S3.2.

2. If the identification is unsuccessful, go to S3.2.

3. S3.2.2, identify the compilation instruction #pragma resume_uncache "xxx". If the identification is successful, mark the code text between #pragmacache "xxx" and #pragma resume_uncache "xxx" as the transformation area. Otherwise, mark the code text from after #pragma cache "xxx" to the end of this program file as the transformation area, and go to S3.2.

5. S3.2.3, identify the compilation instruction #pragma cache "xxx@@foo", where foo is the name of a function in the program file. If the identification is successful, go to S3.2.

4. If the identification is unsuccessful, go to S2 to process the next data. S3.2.4, identify the code text of the foo function in the program file as a transformation area, and proceed to S3.2.5; S3.2.

5. Use the cacheable access mechanism or instruction provided by the processor to replace all accesses to the symbol xxx within the transformation area with cacheable access forms, enter S2, and process the next data.

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