Branch prediction device

Abstract

The present application proposes a branch prediction device, wherein the system includes: a signal input terminal, an address decoder, and a prefetch controller; wherein the signal input terminal is used to input a first signal; the address decoder includes a register and a first processing unit; wherein the first processing unit is used to receive the first signal and process the first signal to obtain a second signal and send it to the prefetch controller; the prefetch controller is used to receive and detect the signal state of the second signal and multiplex the second signal to obtain a target branch strategy and a target branch address. The present application no longer relies on the addition of large logic circuits, but makes full use of the signals inside the microprocessor. By completing most of the instruction decoding operations in the address decoder, the requirements for the logic circuits in the prefetch controller are greatly reduced, thereby reducing the cost and overhead of branch prediction while ensuring the accuracy and reliability of branch prediction.

Description

Technical Field

[0001] The present application relates to the field of automatic control technology, and in particular to a branch prediction device. Background Art

[0002] Currently, processors (central processing units, CPUs) generally use a pipeline mechanism to process instructions in parallel to improve instruction processing efficiency. However, when processing branch instructions (also known as jump instructions or conditional jump instructions), it is often impossible to directly access the next instruction. In this case, if the relevant operations must wait until the processor confirms the next instruction before executing, the pipeline function will be greatly reduced, resulting in a loss of CPU performance.

[0003] To address the aforementioned issues, processors often employ branch prediction technology. However, in related art, branch prediction is typically performed by decoding program code from completed instruction fetch operations within a flash controller. However, successful branch prediction with this approach requires a deep understanding of the microcontroller's architecture. This lack of understanding of the microcontroller's architecture can significantly reduce branch prediction accuracy. Furthermore, this approach often requires the addition of large logic circuits, which inevitably increases the hardware cost of branch prediction.

[0004] Therefore, how to ensure the accuracy and reliability of branch prediction while reducing the additional overhead has become an urgent problem that needs to be solved. Summary of the Invention

[0005] The present application aims to solve one of the technical problems in the related art at least to a certain extent.

[0006] To this end, a first objective of the present application is to provide a branch prediction device that can reduce additional overhead while ensuring the accuracy and reliability of branch prediction.

[0007] To achieve the above-mentioned purpose, the first embodiment of the present application proposes a branch prediction device, including: a signal input end, an address decoder and a prefetch controller; wherein the signal input end is used to input a first signal, wherein the first signal is an internal input signal of the address decoder; the address decoder includes a register and a first processing unit; wherein the input end of the first processing unit is connected to the signal input end, the first output end of the first processing unit is connected to the prefetch controller, and the second output end of the first processing unit is connected to the input end of the register, the first processing unit is used to receive the first signal and process the first signal to obtain a second signal to send to the prefetch controller; the prefetch controller is used to receive and detect the signal state of the second signal, and multiplex the second signal to obtain a target branch strategy and a target branch address.

[0008] The branch prediction device of the embodiment of the present application includes: a signal input terminal, an address decoder and a prefetch controller; wherein the signal input terminal is used to input a first signal; the address decoder includes a register and a first processing unit; wherein the first processing unit is used to receive the first signal and process the first signal to obtain a second signal and send it to the prefetch controller; the prefetch controller is used to receive and detect the signal state of the second signal and multiplex the second signal to obtain the target branch strategy and the target branch address. The present application no longer relies on the addition of large logic circuits, and makes full use of the signals inside the microprocessor. By completing most of the instruction decoding operations in the address decoder, the requirements for the logic circuits in the prefetch controller are greatly reduced, so as to reduce the cost and overhead of branch prediction while ensuring the accuracy and reliability of branch prediction.

[0009] According to one embodiment of the present application, the address decoder further includes: a second processing unit; wherein the input end of the second processing unit is connected to the output end of the register; the second processing unit is used to process the second signal to obtain the address signal HADDR.

[0010] According to one embodiment of the present application, the second processing unit includes: a first processing sub-unit and a second processing sub-unit, wherein the input end of the first processing sub-unit is connected to the output end of the register; the input end of the second processing sub-unit is connected to the output end of the register; the first processing sub-unit is used to obtain the target address source signal according to the second signal; and the second processing sub-unit is used to obtain the target immediate signal according to the second signal.

[0011] According to one embodiment of the present application, the second processing unit further includes: a third processing sub-unit, wherein the first input end of the third processing sub-unit is connected to the first output end of the first processing sub-unit, and the second input end of the third processing sub-unit is connected to the output end of the second processing sub-unit; the third processing sub-unit is used to obtain the address signal HADDR according to the target address source signal and the target immediate signal.

[0012] According to one embodiment of the present application, the first processing sub-unit includes: a first logic gate and a first data selector, wherein the input end of the first logic gate is connected to the output end of the register, the first output end of the first logic gate is connected to the first input end of the first data selector, and the second output end of the first logic gate is connected to the first input end of the third processing sub-unit; the second input end of the first data selector is connected to the output end of the register, and the output end of the first data selector is connected to the second input end of the third processing sub-unit; the first logic gate is used to obtain an address source signal according to the second signal, and send the address source signal to the first data selector and the third processing sub-unit; the first data selector is used to obtain the target address source signal according to the second signal and the address source signal, and send the target address source signal to the third processing sub-unit.

[0013] According to one embodiment of the present application, the second processing sub-unit includes: a second logic gate and a second data selector, wherein the input end of the second logic gate is connected to the output end of the register, and the output end of the second logic gate is connected to the first input end of the second data selector; the second input end of the second data selector is connected to the output end of the register, and the output end of the second data selector is connected to the third input end of the third processing sub-unit; the second logic gate is used to obtain the immediate number signal and the instruction type corresponding to the branch operation instruction according to the second signal, and send the immediate number signal and the instruction type corresponding to the branch operation instruction to the second data selector; the second data selector is used to obtain the target immediate number signal according to the second signal, the immediate number signal and the instruction type corresponding to the branch operation instruction, and send the target immediate number signal to the third processing sub-unit.

[0014] According to one embodiment of the present application, the third processing subunit includes: a third logic gate.

[0015] According to one embodiment of the present application, the prefetch controller includes: a third processing unit and a fourth processing unit, wherein the input end of the third processing unit is connected to the first output end of the first processing unit, and the output end of the third processing unit is connected to the fourth processing unit; the third processing unit is used to receive the second signal and multiplex the second signal to obtain a target branch strategy and a target branch address; the fourth processing unit is used to obtain the signal state of the second signal according to the target branch strategy and the target branch address to detect the signal state.

[0016] According to one embodiment of the present application, the third processing unit includes: a fourth logic gate and a fifth logic gate, wherein the input end of the fourth logic gate is connected to the first output end of the first processing unit, and the output end of the fourth logic gate is connected to the first input end of the fourth processing unit; the input end of the fifth logic gate is connected to the first output end of the first processing unit, and the output end of the fifth logic gate is connected to the second input end of the fourth processing unit; the fourth logic gate is used to obtain a branch enable signal according to the second signal, so as to determine whether to perform a branch operation according to the branch enable signal and obtain a target sequential address; the fifth logic gate is used to obtain a branch address signal according to the second signal, so as to obtain the target branch address according to the branch address signal.

[0017] According to one embodiment of the present application, the fourth logic gate is further used to: obtain a historical sequential address prefetch result, and obtain a prefetch address according to the historical sequential address prefetch result; and obtain the target sequential address according to the prefetch address.

[0018] According to one embodiment of the present application, the fourth processing unit includes: a third data selector.

[0019] According to one embodiment of the present application, the prefetch controller further includes: a buffer component for storing a prefetch success operation record corresponding to a first prefetch success operation instruction in response to detecting a first prefetch success operation instruction for any branch operation instruction.

[0020] According to one embodiment of the present application, the buffer component is also used to: in response to detecting a second prefetch success operation for other branch operation instructions, obtain the target branch address corresponding to the other branch operation instruction according to the second prefetch success operation; and update the prefetch success operation record according to the target branch address. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic diagram of a branch prediction device according to an embodiment of the present application;

[0022] Figure 2 is a schematic diagram of an address decoder according to an embodiment of the present application;

[0023] Figure 3 is a schematic diagram of a branch prediction device according to another embodiment of the present application;

[0024] Figure 4 is a schematic diagram of a branch prediction device according to another embodiment of the present application;

[0025] Figure 5 is a schematic diagram of a branch prediction device according to another embodiment of the present application;

[0026] Figure 6 is a schematic diagram of an address decoder according to an embodiment of the present application;

[0027] Figure 7 is a schematic diagram of a branch prediction device according to another embodiment of the present application;

[0028] Figure 8 is a schematic diagram of a branch prediction device according to another embodiment of the present application;

[0029] Figure 9 is a schematic diagram of a prefetch controller according to one embodiment of the present application;

[0030] Figure 10 is a schematic diagram of a branch prediction device according to another embodiment of the present application;

[0031] Figure 11 is a timing diagram of a prefetch operation according to one embodiment of the present application;

[0032] Figure 12 is a timing diagram of a prefetch operation according to another embodiment of the present application;

[0033] Figure 13 is a schematic diagram of a branch prediction device according to another embodiment of the present application;

[0034] Figure 14 is a schematic diagram of a buffer assembly according to an embodiment of the present application. DETAILED DESCRIPTION

[0035] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0036] The following describes the motor closed-loop switching method, device, electronic device and storage medium of the embodiments of the present application in conjunction with the accompanying drawings.

[0037] Figure 1 2 is a schematic diagram of a branch prediction device according to an embodiment of the present application.

[0038] like Figure 1 As shown, the branch prediction device 1000 according to the embodiment of the present application includes: an address decoder 100 , a prefetch controller 200 and a signal input terminal 300 .

[0039] The signal input terminal 300 is used to input a first signal, wherein the first signal is an internal input signal of the address decoder 100 .

[0040] The address decoder 100 includes a first processing unit 11 and a register 12. Optionally, an input terminal 11-1 of the first processing unit 11 is connected to the signal input terminal 300, a first output terminal 11-2 of the first processing unit 11 is connected to the prefetch controller 200, and a second output terminal 11-3 of the first processing unit 11 is connected to the input terminal 12-1 of the register 12.

[0041] The first processing unit 11 is configured to receive a first signal and process the first signal to obtain a second signal and send the second signal to the prefetch controller 200 .

[0042] In an embodiment of the present application, the first processing unit 11 located before the register 12 may include at least one logic gate (Logic Gate), wherein multiple logic gates may be connected in a cascade manner to obtain a first signal and process the first signal to obtain a second signal and send it to the prefetch controller 200.

[0043] Logic gates are the basic components of integrated circuits. Simple logic gates can be made up of transistors. These transistors combine to generate a high or low signal after passing through them, representing the high and low levels of two signals. These high and low levels can represent logical "true" and "false," or binary 1 and 0, respectively, thus enabling logical operations.

[0044] It should be noted that the first signal may include multiple signals. After being input into the address decoder 100, the first signal may be processed by the multi-stage logic gates of the first processing unit 11. Accordingly, the second signal may also include multiple signals.

[0045] For example, if Figure 2As shown, the first processing unit 11 includes five logic gates (2-1 to 2-5). After the first signal is input to the address decoder 100, it can be processed by multiple stages of logic gates to obtain a second signal including multiple signals.

[0046] It should be noted that since the first processing unit 11 is located before the register 12, that is, after the first signal is input to the address decoder 100, before being sent to the register, the first signal first passes through the logic gates in the first processing unit 11 to obtain the second signal. As a result, the time when the second signal is obtained is advanced by one clock cycle.

[0047] The prefetch controller 200 is configured to receive and detect a signal state of the second signal, and perform multiplexing processing on the second signal to obtain a target branch strategy and a target branch address.

[0048] It should be noted that pre-fetch refers to a technology that issues a pre-fetch request before the cache may fail by overlapping calculation and memory access so that the data block can be put into the cache in advance when the data is actually used, thereby avoiding processor pauses caused by cache failure.

[0049] It should be noted that branch prediction technology can predict the branch prediction results of branch instructions, including branch direction, so as to promote the processor to perform the next instruction fetch operation and avoid pipeline delays caused by waiting for the execution results of branch instructions.

[0050] Furthermore, branch prediction technology is mainly used to process branch instructions (also known as jump instructions or conditional jump instructions). Among them, an indispensable part of program logic is if-else, which is reflected in the processor as a jump instruction. When executing an instruction, the first step in the processor pipeline is usually IF (Instruction Fetch). For non-jump instructions, IF is relatively simple and can directly obtain the next instruction. However, due to the special nature of conditional jump instructions, it is impossible to directly obtain the next instruction. If the processor waits until the next instruction is confirmed, the function of the pipeline will be greatly reduced, resulting in performance loss. Therefore, a jump prediction technology, namely branch prediction technology, came into being.

[0051] In an embodiment of the present application, when the address decoder 100 sends the second information to the prefetch controller 200, the prefetch controller 200 can obtain the signal state of the second signal, detect the signal state of the second signal, and multiplex the second signal to obtain the target branch strategy and the target branch address.

[0052] Therefore, the branch prediction device proposed in the present application includes: a signal input terminal, an address decoder and a prefetch controller; wherein the signal input terminal is used to input a first signal; the address decoder includes a register and a first processing unit; wherein the first processing unit is used to receive the first signal and process the first signal to obtain a second signal and send it to the prefetch controller; the prefetch controller is used to receive and detect the signal state of the second signal and multiplex the second signal to obtain the target branch strategy and the target branch address. The present application no longer relies on the addition of large logic circuits, but makes full use of the signals inside the microprocessor. By completing most of the instruction decoding operations in the address decoder, the requirements for the logic circuits in the prefetch controller are greatly reduced, so as to reduce the cost and overhead of branch prediction while ensuring the accuracy and reliability of branch prediction.

[0053] In some embodiments of the present application, Figure 3 As shown, the address decoder 100 of the embodiment of the present application further includes: a second processing unit 13 , wherein an input terminal 13 - 1 of the second processing unit 13 is connected to an output terminal 12 - 2 of the register 12 .

[0054] The second processing unit 13 is configured to process the second signal to obtain an address signal HADDR.

[0055] It should be noted that the address signal HADDR (hereinafter referred to as HADDR) is the final output signal of the address decoder 100. HADDR refers to an internal AHB (Advanced High Performance Bus) address line signal that needs to be converted to an external memory.

[0056] In the embodiment of the present application, the output signal of the register is processed by the second processing unit 13 to obtain the address signal decoded by the address decoder 100, namely HADDR. Furthermore, the second processing unit 13 can send the HADDR to the register 12 for storage and send it to the target processor bus at the same time.

[0057] In the embodiment of this application, Figure 4 As shown, the second processing unit 13 includes: a first processing sub-unit 131 and a second processing sub-unit 132, wherein the input end 131-1 of the first processing sub-unit 131 is connected to the output end 12-2 of the register 12; the input end of the second processing sub-unit 132 is connected to the output end 12-2 of the register 12 of 132-1.

[0058] In the embodiment of this application, Figure 4As shown, the second processing unit 13 also includes: a third processing sub-unit 133, wherein the first input terminal 133-1 of the third processing sub-unit 133 is connected to the first output terminal 131-2 of the first processing sub-unit 131, and the second input terminal 133-2 of the third processing sub-unit 133 is connected to the output terminal 132-2 of the second processing sub-unit 132.

[0059] The first processing sub-unit 131 is used to obtain a target address source signal according to the second signal; and the second processing sub-unit 132 is used to obtain a target immediate value signal according to the second signal.

[0060] The third processing sub-unit 133 is configured to obtain an address signal HADDR according to the target address source signal and the target immediate value signal.

[0061] In the embodiment of this application, Figure 5 As shown, the first processing sub-unit 131 includes: a first logic gate 1311 and a first data selector 1312, the input end 1311-1 of the first logic gate 1311 is connected to the output end 12-2 of the register 12, the first output end 1311-2 of the first logic gate 1311 is connected to the first input end 1312-1 of the first data selector 1312, and the second output end 1311-3 of the first logic gate 1311 is connected to the first input end 133-1 of the third processing sub-unit 133; the second input end 1312-2 of the first data selector 1312 is connected to the output end 12-2 of the register 12, and the output end 1312-3 of the first data selector 1312 is connected to the second input end 133-2 of the third processing sub-unit 133.

[0062] In the embodiment of this application, Figure 5 As shown, the second processing sub-unit 132 includes: a second logic gate 1321 and a second data selector 1322, wherein the input terminal 1321-1 of the second logic gate 1321 is connected to the output terminal 12-2 of the register 12, and the output terminal 1321-2 of the second logic gate 1321 is connected to the first input terminal 1322-1 of the second data selector 1322; the second input terminal 1322-2 of the second data selector 1322 is connected to the output terminal 12-2 of the register 12, and the output terminal 1322-3 of the second data selector 1322 is connected to the third input terminal of the third processing sub-unit 133 (the third input terminal 1331-3 of the third logic gate 1331).

[0063] In the embodiment of this application, Figure 5 As shown, the third processing sub-unit 133 includes: a third logic gate 1331 .

[0064] Among them, the first logic gate 1311 is used to obtain the address source signal according to the second signal, and send the address source signal to the first data selector 1312 and the third processing sub-unit 133; the first data selector 1312 is used to obtain the target address source signal according to the second signal and the address source signal, and send the target address source signal to the third processing sub-unit 133.

[0065] Among them, the second logic gate 1321 is used to obtain the instruction type corresponding to the immediate number signal and the branch operation instruction according to the second signal, and send the instruction type corresponding to the immediate number signal and the branch operation instruction to the second data selector 1322; the second data selector 1322 is used to obtain the target immediate number signal according to the second signal, the immediate number signal and the instruction type corresponding to the branch operation instruction, and send the target immediate number signal to the third processing sub-unit 133.

[0066] A multiplexer is a device that receives multiple input signals and synthesizes them into a single output signal in a recoverable manner. A multiplexer is a comprehensive system that typically contains a certain number of data inputs and has a single output.

[0067] The "immediate" value is the number given in an immediate addressing mode instruction. It can be 8, 16, or 32 bits and is stored immediately after the opcode. If the immediate value is 16 or 32 bits, it is stored in a "high-high-low-low" order.

[0068] The structure and working process of the address encoder 100 proposed in this application are explained below by taking an ARM Cortex-M controller as an example.

[0069] The internal logic circuit of HADDR of ARM Cortex-M core is as follows Figure 6 As shown, that is, Figure 6 The flow of signals within the address decoder 100 before HADDR output is shown.

[0070] Optionally, the first data selector 1312 obtains the target address source signal based on the second signal and the address source signal, and sends the target address source signal to the third logic gate 1331 in the third processing sub-unit 133; at the same time, the second data selector 1322 obtains the target immediate signal based on the second signal, the immediate signal and the instruction type corresponding to the branch operation instruction, and sends the target immediate signal to the third processing sub-unit 133; the first logic gate 1311 obtains the address source signal based on the second signal, and sends the address source signal to the first data selector 1312 and the third logic gate 1331 in the third processing sub-unit 133; the second logic gate 1321 obtains the immediate signal and the instruction type corresponding to the branch operation instruction based on the second signal, and sends the immediate signal and the instruction type corresponding to the branch operation instruction to the second data selector 1322.

[0071] The input signal of the first logic gate 1311 helps to prompt the occurrence of the branch operation; the second logic gate 1321 determines the type of the branch operation according to the immediate value source.

[0072] It should be noted that the inputs to the first data selector 1312 and the second data selector 1322 and the signals to the first logic gate 1311 and the second logic gate 1321 all come from register 12. By analyzing the signals before register 12, the occurrence of a branch can be predicted one clock cycle in advance. Furthermore, the target address can also be constructed.

[0073] It should be noted that in this application, before obtaining the second signal used to predict the target address of the branch operation, it is necessary to analyze the inputs of the first data selector 1312 and the second data selector 1322, and the signals at the first logic gate 1311 and the second logic gate 1321. This is because the first data selector 1312 generates a portion of the target address for instruction fetching. In order to obtain the final address (HADDR), it is necessary to combine the outputs of the first data selector 1312 and the second data selector 1322.

[0074] In some embodiments of the present application, Figure 7 As shown, the prefetch controller 200 of the embodiment of the present application includes: a third processing unit 21 and a fourth processing unit 22. The input terminal 21-1 of the third processing unit 21 is connected to the first output terminal 11-2 of the first processing unit 11, and the output terminal 21-2 of the third processing unit 21 is connected to the fourth processing unit 22, and optionally, is connected to the input terminal 22-1 of the fourth processing unit 22.

[0075] Among them, the third processing unit 21 is used to receive the second signal and multiplex the second signal to obtain the target branch strategy and the target branch address; the fourth processing unit 22 is used to obtain the signal state of the second signal according to the target branch strategy and the target branch address to detect the signal state.

[0076] It should be noted that the specific selection of the signal state of the second signal is not limited in this application and can be selected according to actual conditions. Optionally, it can include at least one of the following: an internal state of a microprocessor, a memory state, a peripheral memory state, etc.

[0077] In some embodiments of the present application, Figure 8 As shown, the third processing unit 21 includes a fourth logic gate 211 and a fifth logic gate 212 .

[0078] Among them, the input end 211-1 of the fourth logic gate 211 is connected to the first output end 11-2 of the first processing unit 11, and the output end 211-2 of the fourth logic gate 211 is connected to the first input end 22-1 of the fourth processing unit 22; the input end 212-1 of the fifth logic gate 212 is connected to the first output end 11-2 of the first processing unit 11, and the output end 212-2 of the fifth logic gate 212 is connected to the second input end 22-2 of the fourth processing unit 22.

[0079] Among them, the fourth logic gate 211 is used to obtain the branch enable signal according to the second signal, so as to determine whether to perform the branch operation according to the branch enable signal and obtain the target sequential address; the fifth logic gate 212 is used to obtain the branch address signal according to the second signal, so as to obtain the target branch address according to the branch address signal.

[0080] The target address of the branch operation only comes from the logic circuit that constitutes the branch address.

[0081] Furthermore, the fourth logic gate 211 is further configured to: obtain a historical sequential address prefetch result, and obtain a prefetch address according to the historical sequential address prefetch result; and obtain a target sequential address according to the prefetch address.

[0082] The fourth processing unit 22 includes a third data selector 221 .

[0083] like Figure 9As shown, the second signal output by the address decoder 100 in the ARM Cortex-M controller can be input to the prefetch controller 200 in the flash controller, so that the fourth logic gate 211 and the fifth logic gate 212 in the third processing unit 21 and the third data selector 221 in the fourth processing unit 22 in the prefetch controller 200 detect and process the second signal. The second signal can indicate the occurrence of a branch and predict an address.

[0084] The structure and workflow of the prefetch controller 200 proposed in this application are explained below using an ARM Cortex-M controller as an example.

[0085] like Figure 10 As shown, after the second signal output by the address decoder 100 in the ARM Cortex-M controller is input into the prefetch controller 200 in the flash memory controller, the third processing unit 21 is used to receive the second signal and multiplex the second signal to obtain the target branch strategy and the target branch address; at the same time, the fourth processing unit 22 is used to obtain the signal state of the second signal according to the target branch strategy and the target branch address to detect the signal state.

[0086] The following explanation is given by taking whether the prefetch operation adopts branch prediction as an example.

[0087] Branch prediction is used for prefetch operations, and the timing diagram is as follows Figure 11 shown.

[0088] Among them, 11-1 is the timing diagram corresponding to the bus clock (HCLK).

[0089] Among them, 11-2 is the timing diagram corresponding to HADDR.

[0090] Figures 11-3 are the timing diagram for HREADY (the signal line for slave devices in the AHB). The prefetch address is determined by using the sequential address corresponding to the last successful prefetch operation. When the bus is idle, this address (0x04) is used as the flash memory read address.

[0091] 11-4 is a timing diagram corresponding to the pre-fetch address.

[0092] 11-5 is the timing diagram corresponding to the flash address (Flash Address).

[0093] 11-6 is the timing diagram corresponding to the flash data (Flash Data).

[0094] Optionally, when a branch jump instruction occurs, the instruction address appearing in HADDR is non-sequential; the flash memory controller compares HADDR with the prefetch address and finds that the prefetch operation is unsuccessful; therefore, the prefetch address is discarded and the flash memory address uses the normal instruction address HADDR.

[0095] Branch prediction is not used for prefetch operations, and the timing diagram is as follows Figure 12 shown.

[0096] exist Figure 11 Based on the above, the timing of the branch enable signal is increased. Figure 11-4 .

[0097] Optionally, when a branch jump occurs, a non-continuous instruction address appears in HADDR; the branch prediction function takes effect, the branch enable signal is set to 1, and the prefetch address is switched to the instruction address of the branch jump; the flash memory controller compares HADDR with the prefetch address and finds that the prefetch operation is successful; the flash memory address is switched to the prefetch address, the flash memory read operation continues, and the comparison is successful. Figure 11 The situation shown in is completed one clock cycle early.

[0098] Therefore, the branch prediction device proposed in this application can be used to determine whether a branch operation will occur in the next clock cycle based on the signal state of a portion of the second signal. This allows the operation to be performed one clock cycle earlier than HADDR based on the analysis of the second signal before the register. Furthermore, the prefetch controller continuously monitors the signal state of the second signal to predict whether a branch operation will occur in the next state, further ensuring the accuracy and reliability of branch prediction and reducing the cost and overhead of branch prediction.

[0099] Furthermore, since prediction can only be performed one clock cycle in advance, adding a buffer register can further improve performance.

[0100] In some embodiments of the present application, Figure 13 As shown, the prefetch controller 200 of the embodiment of the present application further includes: a buffer component 15.

[0101] The buffer component 15 is configured to: in response to detecting a first successful prefetch operation instruction for any branch operation instruction, store a successful prefetch operation record corresponding to the first successful prefetch operation instruction.

[0102] Furthermore, the buffer component 15 is also used to: in response to detecting a second prefetch success operation for other branch operation instructions, obtain the target branch address corresponding to the other branch operation instruction according to the second prefetch success operation; and update the prefetch success operation record according to the target branch address.

[0103] It should be noted that the main function of the buffer component 15 is to store data from the last prefetch operation. Optionally, if the kernel attempts to perform a fetch of a previously read address again (via a prefetch operation), the data in the buffer component 15 can be used, that is, there is no need to perform a read from the flash memory again.

[0104] It should be noted that the buffer component 15 includes at least one buffer register (Buffer), and the specific number of the buffer registers is not limited and can be set according to actual conditions.

[0105] For example, if Figure 14 As shown, the buffer component 15 can be configured to include four buffer registers. The prefetch address is two bits. In this example, bits [3:2] are used to select the target buffer (buffer register) to store program data in the flash memory. After the buffer is filled, if a prefetch operation is performed on a different address, the buffer contents from the address with the same address bits [3:2] can be replaced.

[0106] Therefore, the branch prediction device proposed in the present application is provided with a buffer component including at least one buffer register for storing prefetch success operation records and supporting updating of prefetch success operation records, so that it can replace the method of reading data in the flash memory by supporting reading data in the buffer component, shorten the operation time, further ensure the accuracy and reliability of branch prediction, and reduce the cost and overhead of branch prediction.

[0107] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0108] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A branch prediction device, characterized in that: include: signal input terminal, address decoder and prefetch controller; wherein, The signal input terminal is used to input a first signal, wherein the first signal is an internal input signal of the address decoder; The address decoder includes a register and a first processing unit; wherein, The input end of the first processing unit is connected to the signal input end, the first output end of the first processing unit is connected to the prefetch controller, and the second output end of the first processing unit is connected to the input end of the register. The first processing unit is used to receive a first signal and process the first signal to obtain a second signal and send it to the prefetch controller, wherein the first processing unit includes at least one logic gate, and multiple logic gates are connected in a cascade manner to obtain the first signal, process the first signal, obtain the second signal and send it to the prefetch controller; The prefetch controller is configured to receive and detect a signal state of the second signal, and perform multiplexing processing on the second signal to obtain a target branch strategy and a target branch address; The address decoder further includes: a second processing unit; wherein the input end of the second processing unit is connected to the output end of the register; The second processing unit is configured to process the second signal to obtain an address signal HADDR; The second processing unit includes: a first processing subunit, a second processing subunit, and a third processing subunit, wherein the input end of the first processing subunit is connected to the output end of the register; the input end of the second processing subunit is connected to the output end of the register; the first input end of the third processing subunit is connected to the first output end of the first processing subunit, and the second input end of the third processing subunit is connected to the output end of the second processing subunit. The first processing subunit is used to obtain a target address source signal according to the second signal, and the first processing subunit includes: a first logic gate and a first data selector. The second processing subunit is used to obtain a target immediate signal according to the second signal, and the second processing subunit includes: a second logic gate and a second data selector. The third processing subunit is used to obtain the address signal HADDR according to the target address source signal and the target immediate signal, and the third processing subunit includes: a third logic gate; The prefetch controller comprises: a third processing unit and a fourth processing unit, wherein an input end of the third processing unit is connected to the first output end of the first processing unit, and an output end of the third processing unit is connected to the fourth processing unit; The third processing unit is used to receive the second signal and perform multiplexing processing on the second signal to obtain a target branch strategy and a target branch address. The third processing unit includes: a fourth logic gate and a fifth logic gate; The fourth processing unit is configured to obtain the signal state of the second signal according to the target branch strategy and the target branch address to detect the signal state. The fourth processing unit includes a third data selector.

2. The branch prediction device according to claim 1, wherein: The input end of the first logic gate is connected to the output end of the register, the first output end of the first logic gate is connected to the first input end of the first data selector, and the second output end of the first logic gate is connected to the first input end of the third processing subunit; the second input end of the first data selector is connected to the output end of the register, and the output end of the first data selector is connected to the second input end of the third processing subunit; The first logic gate is used to obtain an address source signal according to the second signal, and send the address source signal to the first data selector and the third processing sub-unit; The first data selector is configured to obtain the target address source signal according to the second signal and the address source signal, and send the target address source signal to the third processing sub-unit.

3. The branch prediction device according to claim 1, wherein: The input end of the second logic gate is connected to the output end of the register, and the output end of the second logic gate is connected to the first input end of the second data selector; the second input end of the second data selector is connected to the output end of the register, and the output end of the second data selector is connected to the third input end of the third processing sub-unit; The second logic gate is used to obtain the immediate signal and the instruction type corresponding to the branch operation instruction according to the second signal, and send the immediate signal and the instruction type corresponding to the branch operation instruction to the second data selector; The second data selector is used to obtain the target immediate signal according to the second signal, the immediate signal and the instruction type corresponding to the branch operation instruction, and send the target immediate signal to the third processing sub-unit.

4. The branch prediction device according to claim 1, wherein: The input end of the fourth logic gate is connected to the first output end of the first processing unit, and the output end of the fourth logic gate is connected to the first input end of the fourth processing unit; the input end of the fifth logic gate is connected to the first output end of the first processing unit, and the output end of the fifth logic gate is connected to the second input end of the fourth processing unit; The fourth logic gate is used to obtain a branch enable signal according to the second signal, to determine whether to perform a branch operation according to the branch enable signal, and to obtain a target sequential address; The fifth logic gate is configured to obtain a branch address signal according to the second signal, so as to obtain the target branch address according to the branch address signal.

5. The branch prediction device according to claim 4, wherein: The fourth logic gate is further configured to: Obtaining a historical sequential address prefetch result, and obtaining a prefetch address according to the historical sequential address prefetch result; The target sequential address is obtained according to the prefetch address.

6. The branch prediction device according to claim 1, wherein: The prefetch controller further includes: The buffer component is configured to, in response to detecting a first successful prefetch operation instruction for any branch operation instruction, store a successful prefetch operation record corresponding to the first successful prefetch operation instruction.

7. The branch prediction device according to claim 6, wherein: The buffer assembly is further used for: In response to detecting a second successful prefetch operation for the other branch operation instruction, obtaining a target branch address corresponding to the other branch operation instruction according to the second successful prefetch operation; The prefetch success operation record is updated according to the target branch address.

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