An inter-process memory sharing method and device

Abstract

A method and apparatus for inter-process memory sharing, the method comprising: sending a first memory address to a second process, the first memory address being a memory address in a first process mapped to a first part of a first file; after learning that the second process cannot access the first memory address, establishing, in the second process, a mapping between the first memory address and the first part of the first file.

Description

Technical Field

[0001] The embodiments of this specification belong to the field of computer technology, and in particular, relate to a method and device for inter-process memory sharing. Background Art

[0002] A computing device often includes multiple processes. For example, when the computing device is a service platform or a blockchain platform, different services provided in the platform correspond to different processes. Processes can communicate with each other through the way of Inter-Process Communication (IPC). The IPC method on a single machine includes the way of inter-process communication through shared memory. In the related art, the virtual addresses mapped by different processes to the same shared memory area are usually different. Summary of the Invention

[0003] The purpose of this specification is to provide a more effective inter-process memory sharing solution.

[0004] The first aspect of this specification provides a method for inter-process memory sharing, including:

[0005] Sending a first memory address to a second process, where the first memory address is the memory address mapped to the first part of a first file in a first process;

[0006] After learning that the second process cannot access the first memory address, establishing a mapping between the first memory address and the first part of the first file in the second process.

[0007] The second aspect of this specification provides an inter-process memory sharing device, including:

[0008] A sending unit, configured to send a first memory address to a second process, where the first memory address is the memory address mapped to the first part of a first file in a first process;

[0009] A mapping unit, configured to establish a mapping between the first memory address and the first part of the first file in the second process after learning that the second process cannot access the first memory address.

[0010] The third aspect of this specification provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed on a computer, the computer is made to execute the method described in the first aspect.

[0011] The fourth aspect of this specification provides a computing device, including a memory and a processor. An executable code is stored in the memory. When the processor executes the executable code, the method described in the first aspect is implemented.

[0012] Through the solution provided by the embodiments of this specification, the virtual addresses of different processes mapped to the same shared memory are the same. Thus, an application can store an address pointer related to the virtual address corresponding to the shared memory obtained by this application in this shared memory area, and the capacity of the shared memory area is not fixed, and the memory can be dynamically allocated and released. Description of the Drawings

[0013] To more clearly illustrate the technical solutions of the embodiments of this specification, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0014] Figure 1 Schematic structural diagram of the host 100 in an embodiment of this specification;

[0015] Figure 2 Flowchart of the inter-process memory sharing method in an embodiment of this specification;

[0016] Figure 3 Schematic diagram of the recorded content in the shared area 1 in an embodiment of this specification;

[0017] Figure 4 Architectural diagram of the inter-process memory sharing device in an embodiment of this specification. Detailed Embodiments

[0018] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only a part of the embodiments of this specification, rather than all the embodiments. Based on the embodiments in this specification, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this specification.

[0019] Figure 1 Schematic structural diagram of the host 100 in an embodiment of this specification. As Figure 1As shown, the host 100 includes a processor 11, a memory 12, and a hard disk 13. Processes p1 and p2 are also running in the host 100. A process is an execution activity of a program with certain independent functions on a data set. That is to say, a process is a process or a task in a computer that is executed by a processor (CPU). For example, when the host 100 receives a service request from a user as a server, the host 100 creates a process to provide the service requested by the user (such as a computing service, etc.). A process can contain several threads. Multiple threads in a process can allow the process to perform multiple operations simultaneously. For example, one thread writes a file to the disk, and another thread receives user information, etc. Each process is allocated its own address space when created. This address space is, for example, a 4G virtual address space. The virtual address spaces allocated to each process when created are different from each other.

[0020] As Figure 1 shown, the memory 12 may include a physical memory space shared by processes, Figure 1 in which shared area 1, shared area 2, shared area 3, etc. are schematically shown. In the related art, taking linux providing shared memory as an example, linux provides three functions: shmget, shmat, and shmdt. Suppose process p1 shares memory with process p2. Process p1 can use the shmget function to obtain / create a certain shared memory area. Process p2 can use the shmat function to map the shared memory area obtained by shmget into its own virtual address space. The shmdt function is used to cancel the mapping of the shared memory area. This method has the following problems: 1. When different processes map the same shared memory area through the shmat function, since each process uses its own virtual address space to map the shared memory area, the virtual addresses of these processes mapped to the shared memory area are usually different. Therefore, the application cannot store the address pointer related to the virtual address corresponding to the shared memory obtained by this application in this shared memory area; 2. The capacity of the shared memory area is fixed and cannot be scaled; 3. It is not suitable for dynamically allocating and releasing memory.

[0021] The embodiments of this specification provide a solution for sharing memory between processes. Refer to Figure 1, process p1 first maps the address a1 in the preset virtual address range to a part s1 of the file f1 pre-stored in disk 13 through the mmap function, thereby creating a shared area (such as shared area 3) corresponding to the address a1, and recording the mapping relationship between the address a1 and the part s1 in another shared area (such as shared area 1). Among them, only part s0 of the file f1 has data, and other parts are empty parts without data (such as part s1). Therefore, only part s0 of the file f1 is actually stored in the disk, and this file f1 can also be called a hole file. By using a hole file for shared memory mapping, disk storage space is saved. When process p1 shares memory with process p2, process p1 sends the virtual address a1 to process p2. Process p2 can read the mapping relationship between the address a1 and the part s1 from shared area 1, and establish the mapping between the address a1 and the part s1 in process p2 through the mmap function, thereby allocating the address a1 in the address space of process p2, that is, the shared area 3 can be accessed through the address a1. At the same time, process p1 can expand or shrink the size of the shared area by calling the mremap function.

[0022] Through the solution provided by the embodiments of this specification, the virtual addresses mapped by process p1 and process p2 to shared area 3 are the same. Therefore, an application can store an address pointer related to the virtual address corresponding to the shared memory obtained by this application in this shared memory area, and the capacity of the shared memory area is not fixed, and memory can be dynamically allocated and released.

[0023] The solution for inter-process shared memory provided by the embodiments of this specification will be described in detail below.

[0024] Figure 2 It is a flowchart of an inter-process memory sharing method in an embodiment of this specification. This method is executed by, for example, Figure 1 the host 100 shown, and includes:

[0025] Step S201, after obtaining the allocation instruction of the memory on the heap for process p1, allocate a shared memory address a1 for process p1 in the preset shared memory address segment, and establish a mapping between the shared memory address a1 and a part s1 of the pre-generated file f1 in process p1, and the part s1 currently does not contain content;

[0026] Step S203, send the shared memory address a1 to process p2;

[0027] Step S205, after learning that process p2 cannot access the shared memory address a1, establish a mapping between the shared memory address a1 and the part s1 in process p2.

[0028] The following will describe in detail Figure 2 each step in the method shown.

[0029] First, in step S201, after obtaining the allocation instruction for the memory on the heap of process p1, allocate a shared memory address a1 for process p1 in a preset shared memory address segment, and establish a mapping between the shared memory address a1 and a part s1 of a pre-generated file f1 in process p1, where the part s1 currently does not contain content.

[0030] Step S201 is used to create a shared memory area in one process for sharing with other processes.

[0031] To execute this step, the host 100 can pre-store a shared memory usage library, and each process that needs to perform memory sharing needs to link in the shared memory usage library. The shared memory usage library includes new functions for replacing the memory allocation / free functions in the C library. Among them, the memory allocation functions in the C library include functions such as the malloc function and the free function. Taking the malloc function as an example, assume that the shared memory usage library includes a newshm function for replacing the malloc function. After the host 100 starts to execute process p1, the thread (such as thread th1) belonging to process p1 runs the code in process p1. Assume that when thread th1 executes to the malloc function in process p1, it intercepts the malloc function and replaces it with the newshm function in the shared memory usage library.

[0032] After starting to run the newshm function, thread th1 first reads a preset shared area (such as Figure 1 shared area 1 in it), and determines whether there is a disk file for mapping the shared memory. If not, create a hole file for storing on the disk and store the hole file on the disk. If there is, for example, referring to Figure 1 , thread th1 reads the file f1 mapped to the address space of other processes in shared area 1, and there is still a part of file f1 that has not been mapped to the process address space, and the size of this part is greater than or equal to the address space size required by the malloc function. Thus, thread th1 can create shared memory through file f1. At the same time, thread th1 allocates the required address space (virtual address) for thread p1 in a preset shared memory address segment (virtual address segment), such as address a1. Among them, the length of address a1 needs to be greater than or equal to the address length requested by the malloc function. In the host 100, for example, when each process starts, it can notify the process of the shared memory address segment available for allocating shared memory through the environment variable of the process. For example, an address segment of 100G - 200G can be preset as the shared memory address segment. Thread th1 can learn this shared memory address segment by reading this environment variable, and can learn the unallocated addresses in this shared memory address segment by reading shared area 1, so as to allocate address a1 for process p1 in this unallocated address.

[0033] After that, thread th1 executes the mmap function called in the newshm function, mmap(void* start, size_t length, int prot, int flags, int fd, off_t offset). Among them, the parameter start is used to indicate the starting address of the shared memory to be mapped, that is, the starting address of the address allocated to process p1 in the shared memory address segment, that is, the starting address of address a1; the parameter length is used to indicate the length of the shared memory to be mapped, that is, the length of address a1 to be allocated to process p1; the parameter prot is used to indicate the protection method of the shared memory to be mapped, and this protection method includes, for example: executable, readable, writable, non-accessible, etc. ways, and here it is set to a writable mapping method, for example; the parameter flag is used to indicate the characteristics of the shared memory to be mapped. In this embodiment, flag is set to shared mapping (MAP_SHARED) to copy the written data in the mapped area back to the file; the parameter fd is used to indicate the file descriptor to be mapped to memory, and this file descriptor is used to indicate file f1, for example; the parameter offset is used to indicate the offset of the file to be mapped, and this offset is used to indicate the starting position of the part of the file to be mapped (for example, part s1 in file f1).

[0034] After thread th1 executes the above mmap function, address a1 is added to the address space of process p1, and address a1 is mapped to part s1 of file f1 stored on the disk. This address a1 corresponds to, for example, Figure 1 shared area 3 in. Among them, in order to save disk space, part s1 is initially an empty part, that is, there is no data. Before process p1 writes data to address a1, the host 100 does not allocate physical memory space to address a1 either. Only after process p1 starts to write data to address a1 does the host 100 allocate physical memory space to address a1, so that process p1 can write data in the allocated physical memory space, and the allocated physical memory space constitutes shared area 3.

[0035] After thread th1 establishes the mapping between address a1 and part s1, it records the mapping relationship between address a1 and part s1 in shared area 1. Figure 3 It is a schematic diagram of the record content in shared area 1 in an embodiment of this specification. As Figure 3As shown, the mapping relationships recorded by thread th1 in shared area 1 include, for example: address a1 (starting address, length), the identifier of file f1 (such as file name, etc.), the offset of part s1 in file f1 (such as offset1), etc. Thread th1 can also record in shared area 1 the access permissions allowed by process p1 for other processes to address a1 (i.e., shared area 3), such as read-only permissions. Shared area 1 can be created, for example, through existing shared memory technologies. Thread th1 records the above content in shared area 1 for providing to other processes, so that other processes can share access to shared area 3. It can be understood that thread th1 is not limited to providing the above information to other processes by recording in the shared area, but can provide the above information to other processes through existing inter-thread communication methods.

[0036] In step S203, the shared memory address a1 is sent to process p2.

[0037] Process p2 is run by thread th2, for example. When thread th1 in the process of process p1 needs to share the information stored in shared area 3 with process p2, it can send a function (such as function share()) to thread th2. The incoming parameters of the share function include address a1, so as to send address a1 to thread th2. Thread th1 can send the share function to thread th2 through any inter-process communication method.

[0038] In step S205, after learning that process p2 cannot access the shared memory address a1, a mapping between the shared memory address a1 and part s1 is established in process p2.

[0039] After receiving the share function, thread th2 of process p2 executes the share function. After executing the share function, thread th2 accesses address a1 according to the instructions of the function. Since address a1 has not been allocated to the address space of process p2 yet, at this time, when thread th2 accesses address a1, it will find that address a1 does not exist, and thus receive an exception signal (such as the segment fault signal in Linux). After receiving the exception signal, thread th2 obtains the error address (i.e., address a1) according to the exception scene, and reads shared area 1 to determine the mapping situation of address a1. Thread th2 can read from shared area 1 that process p1 maps address a1 to part s1 of file f1, and the access permission allowed for other processes to address a1 is read-only permission.

[0040] After that, according to the call to the mmap function in the share function, thread th2 can start executing mmap(void* start, size_t length, int prot, int flags, int fd, off_t offset). Similarly to the above, the parameter start is used to indicate the starting address of address a1; the parameter length is used to indicate the length of address a1; the parameter prot is used to indicate the protection mode of the shared memory to be mapped, which is set to a readable mapping mode according to the records in shared area 1 here; the parameter flag is set to a shared mapping; the parameter fd is used to indicate file f1; the parameter offset is used to indicate the starting position of part s1 in file f1. By executing the mmap function, thread th2 maps address a1 into the address space of process p2 and makes process p2 have a read-only mapping to address a1. After thread th2 maps address a1 in the address space of process p2, referring to Figure 3 , thread th2 can record the mapping between process p2, address a1, and part s1 in shared area 1. After the exception handling ends, thread th2 of process p2 returns to the instruction that caused the exception (i.e., the aforementioned instruction accessing address a1), so that thread th2 can read the data shared by process p1 to process p2 from address a1 without changing the data.

[0041] After thread th2 maps address a1 in the address space of process p2, if it is necessary to share shared area 3 with other processes (such as process 3, Figure 1 and Figure 3 not shown in the figure), the share function can also be sent to the thread of process 3 similarly, so that address a1 is mapped in the address space of process 3.

[0042] After process 3 maps address a1 in its own address space similarly to process 2, after the thread in process 3 determines that no other process will map file f1, it can delete file f1 on the hard disk to save disk storage space. For example, currently there are only three processes and file f1 has been fully mapped to all three processes, so it can be determined that no other process will map file f1.

[0043] In one implementation, process p1 may expect to receive the return data from process p2 for the data in shared area 3. Thus, thread th1 can create a shared area 2 in memory 12 similarly to creating shared area 3 in advance. The virtual address of this shared area 2 is, for example, address a2 in the shared memory address segment. This shared area 2 is mapped to a part of file f2 ( Figure 1 not shown in the figure) and referring to Figure 3, thread th1 records the mapping relationship between address a2 and a part (offset2) in file f2 in shared area 1, and records the access permission of other processes to address a2 as writable permission. Thus, when thread th1 sends the above share function to thread th2, it can also include address a2 in the input parameters of the share function. Thread th2 can then map address a2 in the address space of process p2 according to the instructions of the share function to write the returned data to address a2, referring to Figure 3 , thread th2 also records the mapping of process p2 to address a2 in shared area 1. After thread th2 writes the returned data to address a2, thread th1 can read the returned data of process p2 from address a2. After thread th1 reads the returned data, in the case where it is determined that shared area 2 will no longer be used, it can unmap address a2 through the mremap function, and after unmapping, delete the mapping relationship between address a2 of process p1 and the part in file f2 in shared area 1. Thread th2 can trigger the recycling mechanism after the shared memory it uses reaches a preset threshold. After thread th2 determines that process p2 no longer needs to use shared area 2, it determines whether other processes still have a mapping to address a2 according to the records in shared area 1. After determining that all other processes have unmapped address a2, it can unmap address a2.

[0044] In another implementation, assume that thread th2 needs to create shared area 4 ( Figure 1 not shown in the figure) during the execution of process p2, and determines through reading shared area 1 that there are still unmapped parts in file f1. When thread th2 determines part s2 of file f1 corresponding to shared area 4, referring to Figure 1 , it can set the offset address offset3 of part s2 to a preset length from the offset address offset1 of part s1, so that there is an unmapped part of a certain length between part s1 and part s2, to allow process p1 to expand the size of shared area 3. For example, host 100 can set the preset length in the environment variables of each process, so that thread th2 can determine the offset address offset3 of part s2 by reading this environment variable. Or, host 100 can set the address range in the shared memory address segment available to each process in the environment variables of each process, so that thread th2 can determine the above preset length according to the address range available to process p1, and thus determine the offset address offset3.

[0045] When the size of the shared area 3 needs to be expanded in process p1, when thread th1 determines that the length of address a1 is insufficient to store the data to be shared, in one implementation, thread th1 can execute the mremap function, so as to update the mapping of address a1 and part s1 to the mapping of address a1 and a section of address after address a1 and part s1 and a part after part s1 in file f1, thereby expanding the shared area 3. After expanding the shared area 3, thread th1 can update the mapping relationship between address a1 and part s1 in the shared area 1. In another implementation, thread th1 can execute the mmap function to establish the mapping between address a4 and part s3 in file f1, where address a4 is a section of address consecutive with address a1 after address a1, and part s3 is a part consecutive with part s1 after part s1, thereby expanding the shared area 3. After this expansion, thread th1 can record the mapping relationship between address a4 and file s3 in the shared area 1( Figure 3 not shown).

[0046] When thread th1 executes the memory release request in process p1, intercept the memory release request, and correspondingly execute the function of releasing shared memory in the shared memory usage library. This function calls the mremap function or the munmap function, so as to release the mapping of the address of the shared area 3 in process p1 and delete this mapping relationship in the shared area 1.

[0047] Figure 4 This is the architecture diagram of the inter-process memory sharing device in an embodiment of this specification, including:

[0048] A sending unit 41, configured to send a first memory address to a second process, where the first memory address is the memory address mapped to the first part of the first file in the first process;

[0049] A mapping unit 42, configured to establish the mapping between the first memory address and the first part of the first file in the second process after learning that the second process cannot access the first memory address.

[0050] In one implementation, the mapping unit 42 is further configured to: after obtaining the allocation instruction for the memory on the heap of the first process, allocate a first memory address for the first process in a preset memory address segment, and establish the mapping between the first memory address and the first part of the pre-generated first file in the first process, where the first part currently does not contain content.

[0051] In one embodiment, the mapping unit 42 is further configured to: when it is determined that the length of the first memory address is insufficient, in the first process, update the mapping between the first memory address and the first part to a mapping between a second memory address and a second part of the first file, where the second memory address includes the first memory address and an address consecutive with the first memory address in the preset memory address segment, and the second part includes the first part and a part of the first file consecutive with the first part.

[0052] In one embodiment, the mapping unit 42 is further configured to: when it is determined that the length of the first memory address is insufficient, establish a mapping between a second memory address and a second part of the first file in the first process, where the second memory address is an address consecutive with the first memory address in the preset memory address segment, and the second part is a part of the first file consecutive with the first part.

[0053] In one embodiment, the apparatus further includes: a recording unit 43, configured to record a first mapping relationship between the first memory address in the first process and the first part of the first file pre-generated in the third memory address after establishing the mapping between the first memory address and the first part of the first file pre-generated in the first process;

[0054] The mapping unit 42 is further configured to: after learning that the second process cannot access the first memory address, read the first mapping relationship between the first memory address in the first process and the first part of the first file from the third memory address, and establish a mapping between the first memory address and the first part of the first file in the second process according to the first mapping relationship.

[0055] In one embodiment, the recording unit 43 is further configured to: after recording the first mapping relationship between the first memory address of the first process and the first part of the first file in the third memory address, record the access permission of other processes allowed by the first process to the first part of the first file in the third memory address.

[0056] In one embodiment, the mapping unit 42 is further configured to establish a mapping between the first memory address and the first part of the first file in the second process according to the access permission of other processes to the first part of the first file recorded in the third memory address.

[0057] In one embodiment, the sending unit 41 is further configured to: send a fourth memory address to the second process, instructing to write the return data corresponding to the first part of the first file of the second process into the fourth memory address, where the fourth memory address is the memory address of the partial mapping of the first process and the second file.

[0058] In one embodiment, after the first file is generated, it is stored in a disk. The apparatus further includes a deleting unit 44, configured to, after establishing the mapping between the first memory address and the first part of the first file in the second process, and after determining that no other process will establish a mapping with the first file, delete the first file in the disk.

[0059] In one embodiment, the apparatus further includes a releasing unit 45, configured to, after obtaining a release instruction of the first process for the memory on the heap, release the first memory address in the first process.

[0060] In one embodiment, the releasing unit 45 is further configured to, after determining to release the first memory address in the first process, release the first memory address in the second process.

[0061] An embodiment of this specification further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed on a computer, the computer is made to execute the method as Figure 2 shown.

[0062] An embodiment of this specification further provides a computing device, including a memory and a processor. An executable code is stored in the memory. When the processor executes the executable code, the method as Figure 2 shown is implemented.

[0063] In the 1990s, it was quite obvious to distinguish whether an improvement in a technology was an improvement in hardware (e.g., improvement in circuit structures such as diodes, transistors, switches, etc.) or an improvement in software (improvement in method flows). However, with the development of technology, many improvements in method flows today can be regarded as direct improvements in hardware circuit structures. Almost all designers obtain the corresponding hardware circuit structures by programming the improved method flows into the hardware circuits. Therefore, it cannot be said that an improvement in a method flow cannot be implemented with a hardware entity module. For example, a Programmable Logic Device (PLD) (such as a Field Programmable Gate Array (FPGA)) is such an integrated circuit whose logic function is determined by the user programming the device. Designers can program by themselves to "integrate" a digital system on a piece of PLD without asking a chip manufacturer to design and fabricate a dedicated integrated circuit chip. Moreover, nowadays, instead of manually fabricating integrated circuit chips, this programming is mostly implemented using "logic compiler" software, which is similar to the software compiler used in program development and writing. The original code before compilation also has to be written in a specific programming language, which is called a Hardware Description Language (HDL). And there is not only one type of HDL, but many types, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. Currently, the most commonly used ones are VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also be clear that as long as the method flow is slightly logically programmed with the above-mentioned several hardware description languages and programmed into the integrated circuit, it is easy to obtain the hardware circuit that implements the logical method flow.

[0064] The controller can be implemented in any suitable manner. For example, the controller can take the form of, for example, a microprocessor or a processor and a computer-readable medium storing computer-readable program code (such as software or firmware) executable by the (micro)processor, logic gates, switches, an Application Specific Integrated Circuit (ASIC), a programmable logic controller, and an embedded microcontroller. Examples of the controller include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. The memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art also know that in addition to implementing the controller in the form of pure computer-readable program code, the controller can be implemented in the form of logic gates, switches, ASICs, programmable logic controllers, and embedded microcontrollers by logically programming the method steps to achieve the same function. Therefore, such a controller can be considered a hardware component, and the devices included therein for implementing various functions can also be regarded as the structures within the hardware component. Or even, the devices for implementing various functions can be regarded as either software modules for implementing the method or the structures within the hardware component.

[0065] The systems, devices, modules, or units illustrated in the above embodiments can be specifically implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a server system. Of course, this application does not exclude that with the development of future computer technologies, the computers for implementing the functions of the above embodiments can be, for example, personal computers, laptop computers, in-vehicle human-machine interaction devices, cellular phones, camera phones, smart phones, personal digital assistants, media players, navigation devices, email devices, game consoles, tablet computers, wearable devices, or any combination of these devices.

[0066] Although one or more embodiments of this specification provide method operation steps as described in the embodiments or flowcharts, more or fewer operation steps may be included based on conventional or non-creative means. The order of steps listed in the embodiments is only one way among many execution orders of steps and does not represent the only execution order. When the actual device or terminal product is executed, it may be executed in the order of the method shown in the embodiments or the drawings or executed in parallel (for example, in an environment of parallel processors or multi-threaded processing, or even in a distributed data processing environment). The term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, product or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, product or device. Without further limitation, there is no exclusion of additional identical or equivalent elements in the process, method, product or device comprising the said elements. For example, if terms such as first and second are used to denote names, they do not denote any particular order.

[0067] For convenience of description, when describing the above device, it is divided into various modules according to functions for separate description. Of course, when implementing one or more of this specification, the functions of each module may be implemented in the same or multiple software and / or hardware, or the modules implementing the same function may be realized by a combination of multiple sub-modules or sub-units, etc. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other may be through some interfaces, and the indirect coupling or communication connection of the device or unit may be in electrical, mechanical or other forms.

[0068] The present invention is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate a device for realizing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0069] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufacture including an instruction device that implements the functions specified in one process Figure 1 or a plurality of processes and / or blocks Figure 1 or a plurality of blocks specified in the block.

[0070] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are performed on the computer or other programmable device to generate a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one process Figure 1 or a plurality of processes and / or blocks Figure 1 or a plurality of blocks specified in the block.

[0071] In a typical configuration, a computing device includes one or more processors (CPUs), an input / output interface, a network interface, and memory.

[0072] The memory may include non-permanent memory in the form of computer-readable media, random access memory (RAM) and / or non-volatile memory such as read-only memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.

[0073] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology for information storage. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette tapes, magnetic tape magnetic disk storage, graphene storage or other magnetic storage devices, or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media, such as modulated data signals and carrier waves.

[0074] Those skilled in the art should understand that one or more embodiments of this specification can be provided as a method, a system, or a computer program product. Therefore, one or more embodiments of this specification can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, one or more embodiments of this specification can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0075] One or more embodiments of this specification can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. One or more embodiments of this specification can also be practiced in a distributed computing environment where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0076] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and reference can be made to the corresponding parts of the method embodiments for the relevant content. In the description of this specification, the description of reference terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this specification. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0077] The above is only the embodiment of one or more embodiments of this specification and is not used to limit one or more embodiments of this specification. For those skilled in the art, one or more embodiments of this specification can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this specification shall be included within the scope of the claims.

Claims

1. An inter-process memory sharing method, comprising: After obtaining an allocation instruction for memory on the heap of the first process, allocate a first memory address for the first process in a preset memory address segment, and establish a mapping between the first memory address and a first part of a pre-generated first file in the first process through the mmap function, where the first part currently does not contain content; Send the first memory address to the second process, where the first memory address is the memory address in the first process that is mapped to the first part of the first file; After learning that the second process cannot access the first memory address, establish a mapping between the first memory address and the first part of the first file in the second process.

2. The method according to claim 1 further comprises: In the case where it is determined that the length of the first memory address is insufficient, in the first process, update the mapping between the first memory address and the first part to a mapping between a second memory address and a second part of the first file, where the second memory address includes the first memory address and an address consecutive with the first memory address in the preset memory address segment, and the second part includes the first part and a part of the first file consecutive with the first part.

3. The method according to claim 1 further includes, in the case where it is determined that the length of the first memory address is insufficient, establishing, in the first process, a mapping between a second memory address and a second part of the first file, where, The second memory address is an address consecutive with the first memory address in the preset memory address segment, and the second part is a part of the first file consecutive with the first part.

4. The method according to claim 1, further comprising: After establishing a mapping between the first memory address and a first part of a pre-generated first file in the first process, record a first mapping relationship between the first memory address and the first part of the first file in the first process in a shared third memory address; The step of, after learning that the second process cannot access the first memory address, establishing a mapping between the first memory address and the first part of the first file in the second process includes: after learning that the second process cannot access the first memory address, read the first mapping relationship from the third memory address, and establish a mapping between the first memory address and the first part of the first file in the second process according to the first mapping relationship.

5. The method according to claim 4, further comprising: After recording the first mapping relationship in the third memory address, record the access permissions of other processes allowed by the first process to the first part of the first file in the third memory address.

6. The step of, in the second process, establishing a mapping between the first memory address and the first part of the first file according to claim 5 includes establishing a mapping between the first memory address and the first part of the first file in the second process according to the access permissions of other processes to the first part of the first file recorded in the third memory address.

7. The method according to claim 6, further comprising: Send a fourth memory address to the second process, instructing the second process to write return data corresponding to the first part of the first file into the fourth memory address, where the fourth memory address is the memory address in the first process that is mapped to a part of a second file.

8. The method according to claim 1, wherein the first file is stored in a disk after being generated, and the method further includes, after establishing a mapping between the first memory address and the first part of the first file in the second process, and after determining that no other process will establish a mapping with the first file, deleting the first file in the disk.

9. The method according to claim 1, further including, after obtaining a release instruction of the memory on the heap in the first process, releasing the first memory address in the first process.

10. The method according to claim 9, further including, after determining that the first memory address is released in the first process, releasing the first memory address in the second process.

11. An inter-process memory sharing device, comprising: a sending unit, configured to send a first memory address to a second process, where the first memory address is a memory address mapped to a first part of a first file in a first process; a mapping unit, configured to establish a mapping between the first memory address and the first part of the first file in the second process after learning that the second process cannot access the first memory address; The mapping unit is further configured to: after obtaining an allocation instruction of the memory on the heap in the first process, allocate a first memory address for the first process in a preset memory address segment, and establish a mapping between the first memory address and the first part of a pre-generated first file in the first process through a mmap function, where the first part currently does not contain content.

12. The apparatus according to claim 11, wherein the mapping unit is further configured to: in the case where it is determined that the length of the first memory address is insufficient, in the first process, update the mapping between the first memory address and the first part to a mapping between a second memory address and a second part of the first file, where The second memory address includes the first memory address and an address consecutive with the first memory address in the preset memory address segment, and the second part includes the first part and a part consecutive with the first part in the first file.

13. The apparatus according to claim 11, wherein the mapping unit is further configured to, when determining that the length of the first memory address is insufficient, establish a mapping between a second memory address and a second part of the first file in the first process, where The second memory address is an address consecutive with the first memory address in the preset memory address segment, and the second part is a part consecutive with the first part in the first file.

14. The device according to claim 11, further including: a recording unit, configured to record a first mapping relationship between the first memory address and the first part of the first file in the first process in a shared third memory address after establishing a mapping between the first memory address and the first part of the pre-generated first file in the first process; The mapping unit is further configured to: after learning that the second process cannot access the first memory address, read the first mapping relationship in the third memory address, and establish a mapping between the first memory address and the first part of the first file in the second process according to the first mapping relationship.

15. For the device according to claim 14, the recording unit is further configured to: after recording the first mapping relationship between the first memory address and the first part of the first file in the first process in the third memory address, record access permissions of other processes allowed by the first process to the first part of the first file in the third memory address.

16. The apparatus according to claim 15, wherein the mapping unit is further configured to establish a mapping between the first memory address and the first part of the first file in the second process according to the access right of other processes to the first part of the first file recorded in the third memory address.

17. The apparatus according to claim 16, wherein the sending unit is further configured to send a fourth memory address to the second process, and instruct the second process to write the return data corresponding to the first part of the first file into the fourth memory address, where the fourth memory address is the memory address of the first process that is partially mapped to the second file.

18. The apparatus according to claim 11, wherein the first file is stored in a disk after being generated, and the apparatus further includes a deletion unit, configured to delete the first file in the disk after establishing the mapping between the first memory address and the first part of the first file in the second process and determining that no other process will establish a mapping to the first file.

19. The apparatus according to claim 11, further includes a release unit, configured to release the first memory address in the first process after obtaining a release instruction of the first process for the memory on the heap.

20. The apparatus according to claim 19, wherein the release unit is further configured to release the first memory address in the second process after determining that the first memory address is released in the first process.

21. A computer-readable storage medium, on which a computer program is stored, and when the computer program is executed on a computer, the computer is made to execute the method according to any one of claims 1-10.

22. A computing device, including a memory and a processor, wherein the memory stores executable code, and when the processor executes the executable code, the method according to any one of claims 1-10 is implemented.

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