A multi-core cache refresh method based on handshake protocol

Abstract

The present invention discloses a multi-core cache refresh method based on a handshake protocol, comprising the following steps: an initiating core initiates a cache refresh request to other cores via an inter-core interrupt; the initiating core waits and polls other cores to see if the cache refresh operation has been completed and counts the time; after receiving the cache refresh request from the initiating core, the other cores interrupt and enter the cache refresh function entry to complete the cache refresh; the other cores inform the initiating core that the cache refresh task is completed and wait and poll the initiating core for the next command; the other cores receive the task exit command from the initiating core, send a task completion reply to the initiating core, and terminate the refresh task. The method of the present invention can ensure that the state of all processor multi-core caches is clean within a certain period of time after the operating system completes the method, thereby avoiding deadlock problems caused by resource competition between the multi-cores.

Description

Technical Field

[0001] The present invention relates to a multi-core cache refresh method based on a handshake protocol, and belongs to the technical field of high-performance computing. Background Art

[0002] As an operating system that supports the SMP architecture, a high-performance operating system needs to clear the cache of all processors during operation. That is, it needs to complete the following actions: after the initiating core sends a cache refresh request to other cores, all cores can continue to complete other work only after all other cores that have received the request have completed the cache refresh task.

[0003] A high-performance operating system provides a multi-core cache refresh method based on inter-core interrupts. This method allows a core to send cache refresh requests to other cores. However, it does not restrict other cores from receiving interrupts or completing other tasks during this period. Therefore, it cannot guarantee that the cache is completely clean, and subsequent hardware configuration changes to the system cannot be completed. Adding a dead-wait polling method to this method does not address the above requirements, because the "dead-waiting" behavior of other cores when processing cache refresh requests is very dangerous. It is possible that after one core initiates a message request, another core obtains a competing resource and enters the message request processing, then begins dead-wait polling. While the other cores are still competing for the occupied resources, they are unable to respond to the message request sent by the first processor core, thus causing deadlock.

[0004] To summarize, the multi-core synchronous cache refresh method implemented on a high-performance operating system needs to ensure synchronization while also addressing resource competition issues among multiple cores to avoid deadlock. However, the multi-core cache refresh in the current high-performance computing operating system does not have a synchronization function and cannot guarantee a clean cache state. Summary of the Invention

[0005] The purpose of the present invention is to provide a multi-core cache refresh method based on a handshake protocol to solve the problems existing in the existing method and avoid the occurrence of deadlock.

[0006] To achieve the above object, the technical solution adopted by the present invention is to provide a multi-core cache refresh method based on a handshake protocol, which includes the following steps for the initiating core:

[0007] S1. The initiating core initiates a cache refresh request to other cores through an inter-core interrupt;

[0008] S2: Initiate a core death and poll other cores to see if they have completed the cache refresh operation and set the time;

[0009] S3. If the cache flush completion status of all other cores is not determined within the specified time, the following steps are performed:

[0010] S31, the initiating core sends a task completion message to other cores and waits for task completion replies from all other cores;

[0011] S32. After receiving task completion replies from all other cores, the initiating core records the number of failures. If the number of failures is less than the set threshold, the operation in step S1 is repeated; if the number of failures is greater than the set threshold, an error is directly reported and the process exits.

[0012] S4. If the cache flushing status of all other cores is determined to be complete within the specified time, the following steps are executed:

[0013] S41, the initiating core refreshes its own cache;

[0014] S42. When all core caches, including the initiating core and all other cores, are in a clean state, the required operations are completed.

[0015] S43: The initiating core sends a task execution end command to all other cores and waits for task completion replies from all other cores;

[0016] S44: After the initiating core receives task completion replies from all other cores, the entire task is completed;

[0017] For other kernels, the following steps are included:

[0018] S1. After receiving the cache refresh request from the initiating core, other cores interrupt and enter the cache refresh function entry to complete the cache refresh;

[0019] S2. Other cores notify the initiating core that the cache flush task is complete and wait for the next command from the initiating core.

[0020] S3. Other cores receive the task exit command from the initiating core, send a task end reply to the initiating core, and end the refresh task.

[0021] The further improved scheme in the above technical scheme is as follows:

[0022] 1. The operations required to be performed in the above S42 include setting the hardware memory control register and collecting the process memory status.

[0023] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art:

[0024] The present invention proposes a multi-core cache refresh method based on a handshake protocol, which is used to implement multi-core cache refresh and ensure that the status of all processor multi-core caches is clean within a certain period of time after the operating system completes the method, so as to facilitate subsequent operations such as setting hardware memory control registers and collecting process memory status, thereby avoiding deadlock problems caused by resource competition among multiple cores. DETAILED DESCRIPTION

[0025] Embodiment: The present invention provides a multi-core cache refresh method based on a handshake protocol, which includes the following steps for an initiating core:

[0026] S1. The initiating core initiates a cache refresh request to other cores through an inter-core interrupt;

[0027] S2: Initiate a core death and poll other cores to see if they have completed the cache refresh operation and set the time;

[0028] S3. If the cache flush completion status of all other cores is not determined within the specified time, the following steps are performed:

[0029] S31. The initiating core may determine that there is a deadlock of resource competition in the system, and send a task completion message to other cores, and wait for task completion replies from all other cores;

[0030] S32. After receiving task completion replies from all other cores, the initiating core records the number of failures. If the number of failures is less than the set threshold, the operation in step S1 is repeated. If the number of failures is greater than the set threshold, it is proved that the system is not suitable for continuing the operation, and an error is directly reported and the system exits.

[0031] S4. If the cache flushing status of all other cores is determined to be complete within the specified time, the following steps are executed:

[0032] S41: The initiating core refreshes its own cache. At this point, the caches of all core groups are in a clean state.

[0033] S42. When all core caches, including the initiating core and all other cores, are in a clean state, the required operations are completed.

[0034] S43: The initiating core sends a task execution end command to all other cores and waits for task completion replies from all other cores;

[0035] S44: After the initiating core receives task completion replies from all other cores, the entire task is completed;

[0036] For other kernels, the following steps are included:

[0037] S1. After receiving the cache refresh request from the initiating core, other cores interrupt and enter the cache refresh function entry to complete the cache refresh;

[0038] S2. Other cores notify the initiating core that the cache flush task is complete and wait for the next command from the initiating core.

[0039] S3. Other cores receive the task exit command from the initiating core, send a task end reply to the initiating core, and end the refresh task.

[0040] The operations required to be performed in the above S42 include setting the hardware memory control register and collecting the process memory status.

[0041] The above embodiment is further explained as follows:

[0042] The present invention provides a method for a high-performance operating system to clear the cache after startup and keep the cache clean for a period of time;

[0043] It uses a handshake protocol to establish a complete synchronization response mechanism to ensure the consistency of inter-core synchronization; then it uses the theoretical running time of the multi-core synchronous cache refresh process to formulate a method timeout threshold, and designs a timeout handling method based on this to ensure that the solution will not cause deadlock in the system, providing general SMP architecture chips with a fast, robust, and universal method for multi-core synchronous cache refresh and keeping the cache clean.

[0044] The cache refresh method of the present invention is based on inter-core interrupts to implement multi-core task requests. In order to ensure that the status of all caches is clean within a certain period of time after the operating system completes the method, the cache refresh request and completion between the multiple cores are synchronized using a handshake protocol. Before the task is completed, it is guaranteed that all core groups will not perform other tasks. The inter-core synchronous cache refresh process theoretically does not take too long. If the initiating core does not receive a reply message from all other cores for more than a period of time, the initiating core can determine whether a deadlock has occurred based on the cache refresh completion status of other cores. The deadlock problem caused by resource competition is resolved through a timeout retry scheme combined with the handshake protocol. The specific process is as follows:

[0045] For the initiator core:

[0046] 1. The initiating core initiates a synchronous cache refresh request to other cores through an inter-core interrupt;

[0047] 2. Initiate a core death and poll other cores to see if they have completed the cache refresh operation and set the time;

[0048] 3. If the cache refresh completion status of all other cores is not determined within the specified time:

[0049] 3-1. The initiating core can determine that there is a deadlock caused by resource competition in the system, send a task completion message to other cores, and wait for task completion replies from all other cores;

[0050] 3-2. After receiving responses from all other cores, record the number of failures. If the number of failures is less than the set threshold, repeat the operation in step 1. If the number of failures is greater than the set threshold, it proves that the system is not suitable for continuing the operation, and directly reports an error and exits.

[0051] 4. If the cache refresh status of all other cores is determined to be complete within the specified time:

[0052] 4-1, then refresh the cache itself, and the cache of all core groups is in a clean state;

[0053] 4-2. Complete the required operations when all core caches are clean.

[0054] 4-3. The initiating core then sends a task termination command to other cores and waits for task termination replies from all other cores.

[0055] 4-4. After receiving the reply that other nuclear tasks have been completed, the entire task is completed.

[0056] For other cores:

[0057] 1. After receiving the cache refresh request, other cores interrupt and enter the cache refresh function entry to complete the cache refresh;

[0058] 2. Other cores inform the initiating core that the refresh task is completed and wait for the next command from the polling initiating core;

[0059] 3. Other cores receive the task exit command from the initiating core, send a task end reply to the initiating core, and end the refresh task.

[0060] By following the above process, the refresh function of the entire core cache can be completed safely and stably, and the state of the entire core cache can be guaranteed to be clean within a period of time.

[0061] When the above-mentioned multi-core cache refresh method based on the handshake protocol is adopted, it is used to implement multi-core cache refresh, ensuring that the state of the multi-core cache of all processors is clean within a certain period of time after the operating system completes the method, so as to perform subsequent hardware configuration changes and avoid deadlock problems caused by resource competition between multiple cores.

[0062] To facilitate a better understanding of the present invention, the following briefly explains the terms used herein:

[0063] High-performance computing operating system: A preemptive general-purpose operating system that supports high-performance computing and supports multi-core SMP architecture.

[0064] Cache flush: Clears all temporary contents in the CPU cache.

[0065] Deadlock: refers to a blocking phenomenon caused by competition for resources or communication between two or more processes during execution.

[0066] Inter-core interrupt: A special type of interrupt in a multi-core processor where one processor sends an interrupt to another processor if the processor requires action from the other processor.

[0067] Dead-wait polling: turn off interrupts and wait in an infinite loop until the condition is met and then exit.

[0068] The above embodiments are intended only to illustrate the technical concepts and features of the present invention. Their purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any equivalent changes or modifications made in accordance with the spirit of the present invention are intended to be covered by the scope of protection of the present invention.

Claims

1. A multi-core cache refresh method based on a handshake protocol, characterized by: For the initiating core, do the following: S1. The initiating core initiates a cache refresh request to other cores through an inter-core interrupt; S2: Initiate a core death and poll other cores to see if they have completed the cache refresh operation and set the time; S3. If the cache flush completion status of all other cores is not determined within the specified time, the following steps are performed: S31, the initiating core sends a task completion message to all other cores and waits for task completion replies from all other cores; S32. After receiving task completion replies from all other cores, the initiating core records the number of failures. If the number of failures is less than the set threshold, the operation in step S1 is repeated; if the number of failures is greater than the set threshold, an error is directly reported and the process exits. S4. If the cache flushing status of all other cores is determined to be complete within the specified time, the following operations are performed: S41, the initiating core refreshes its own cache; S42. When all core caches, including the initiating core and all other cores, are in a clean state, the required operations are completed. S43: The initiating core sends a task execution end command to all other cores and waits for task completion replies from all other cores; S44: After the initiating core receives task completion replies from all other cores, the entire task is completed; For other cores, do the following: S1. After receiving the cache refresh request from the initiating core, other cores interrupt and enter the cache refresh function entry to complete the cache refresh; S2. Other cores notify the initiating core that the cache flush task is complete and wait for the next command from the initiating core. S3. Other cores receive the task exit command from the initiating core, send a task end reply to the initiating core, and end the refresh task.

2. The multi-core cache refresh method based on the handshake protocol according to claim 1, characterized in that: The operations required to be performed in S42 include setting hardware memory control registers and collecting process memory status.