Chip package structure and chip package method

Abstract

The application provides a chip packaging structure, which comprises a wafer, a light shielding layer, a bottom protection layer, an insulating layer, a wiring layer, a light transmission layer, a pad and a solder ball. The top surface of the wafer is a photosensitive surface, the bottom surface of the wafer is covered by the light shielding layer, the bottom surface of the light shielding layer is covered by the bottom protection layer, the wiring layer, the insulating layer, the light transmission layer, the pad and the solder ball are arranged on the top of the wafer, the complex etching process on the bottom surface of the wafer is avoided, the packaging process of the chip is simplified, the bonding force of the whole packaging structure is enhanced, and the interference of stray light is reduced. The application further provides a chip packaging method.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging, and more particularly to chip packaging structures and chip packaging methods. Background Technology

[0002] Currently, most automotive CMOS image sensors (CIS) typically have numerous protection and control circuits around the photosensitive area to meet chip reliability and demanding application requirements, and the photosensitive area itself is relatively small. Current chip packaging uses ball bearings on the back of the chip; however, the more complex the chip, the more difficult it is to etch the back side.

[0003] Therefore, it is necessary to develop a new chip packaging structure and chip packaging method to solve the above-mentioned problems in the existing technology. Summary of the Invention

[0004] The purpose of this invention is to provide a chip packaging structure and a chip packaging method to simplify the chip packaging process and enhance the overall bonding strength of the packaging structure.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a chip packaging structure, including a wafer, a light-shielding layer, a bottom protective layer, an insulating layer, a wiring layer, a light-transmitting layer, pads, and solder balls. The top surface of the wafer is a photosensitive surface; the light-shielding layer covers the bottom surface of the wafer; the bottom protective layer covers the bottom surface of the light-shielding layer; the insulating layer covers a portion of the top surface of the wafer so that the central top surface of the wafer is exposed as a photosensitive area; the insulating layer has a groove structure; the insulating layer also has a stepped lower insulating layer; the wiring layer is disposed within the groove structure; metal interconnects are disposed within the wiring layer; the light-transmitting layer spans the central top surface of the wafer and covers the top surface of the lower insulating layer; the pads are disposed on the top surface of the wiring layer and are in electrical contact with the metal interconnects; and the solder balls are disposed on the pads and are in electrical contact with the pads.

[0006] The beneficial effects of the chip packaging structure of the present invention are as follows: the light-shielding layer covers the bottom surface of the wafer, so that the wafer can be protected from stray light interference and prevent stress from causing the wafer to fail; the bottom protective layer covers the bottom surface of the light-shielding layer, which can further prevent stress from causing the wafer to fail; the insulating layer, the wiring layer, the light-transmitting layer, the pads and the solder balls are all disposed on the photosensitive surface of the wafer, avoiding the complex etching process on the bottom surface of the wafer, simplifying the chip packaging process and enhancing the bonding strength of the chip packaging structure.

[0007] Optionally, the surface of the lower insulating layer has several raised structures to diffusely reflect light incident on the photosensitive area by increasing surface roughness, thereby preventing stray light interference. The beneficial effect is that the raised structures on the surface of the lower insulating layer can increase the surface roughness of the lower insulating layer, thereby enabling diffuse reflection of light incident on the photosensitive area and preventing stray light interference.

[0008] Optionally, the insulating layer further comprises a remaining initial insulating layer, wherein the sidewall of the remaining initial insulating layer in contact with the lower insulating layer has a plurality of protruding structures. The beneficial effect is that the protruding structures of the sidewall in contact with the lower insulating layer increase the surface roughness of the sidewall, thereby enabling diffuse reflection of light incident on the photosensitive area and preventing stray light interference.

[0009] Optionally, the width of the metal interconnect is 30-50 micrometers. This has the advantage of preventing the metal interconnect from being exposed in the wiring layer while protecting the metal interconnect.

[0010] Optionally, the width of the lower insulating layer is less than or equal to 0.5 mm. This has the advantage of allowing the light-transmitting layer to adhere to the top surface of the lower insulating layer without affecting the layout of the wiring layer.

[0011] Optionally, the metal interconnects have at least two layers, and the different metal layers are electrically insulated from each other. This provides sufficient space for the metal interconnects while preventing short circuits between them.

[0012] Optionally, the chip packaging structure further includes a top protective layer covering the wiring layer, wherein the top protective layer and the bottom protective layer have the same constituent material. Its advantage is that it protects the wiring layer and its internal metal interconnect layers, preventing the metal interconnects from being exposed or short-circuited.

[0013] In a second aspect, the present invention also provides a chip packaging method, the chip packaging method comprising the following steps:

[0014] S1: Provide a wafer with a photosensitive top surface, and deposit a light-shielding layer on the bottom surface of the wafer;

[0015] S2: An initial insulating layer is formed on the top surface of the wafer, exposing the middle top surface of the wafer as the photosensitive area; the initial insulating layer has a groove structure.

[0016] S3: A wiring layer is formed in the groove structure, and a pad is formed on the top surface of the wiring layer that is in electrical contact with the metal interconnects in the wiring layer. Then, it is checked whether the metal interconnects meet the wiring requirements.

[0017] S4: Remove a portion of the top surface of the initial insulating layer near the center of the wafer to form a stepped lower insulating layer. The lower insulating layer and the remaining initial insulating layer together constitute an insulating layer.

[0018] S5: A light-transmitting layer is formed across the top surface of the middle portion of the wafer, covering the top surface of the bottom insulating layer;

[0019] S6: After depositing and forming a bottom protective layer on the bottom surface of the light-shielding layer, ball-mounting is performed on the pads.

[0020] The beneficial effects of the chip packaging method of the present invention are as follows: depositing a light-shielding layer on the bottom surface of the wafer can prevent stray light interference and prevent stress from causing wafer failure; depositing a bottom protective layer on the bottom surface of the light-shielding layer can further prevent stress from causing wafer failure; the insulating layer, the wiring layer, the light-transmitting layer, the pads, and the solder balls are all disposed on the photosensitive surface of the wafer, avoiding the complex etching process on the bottom surface of the wafer, simplifying the chip packaging process, and enhancing the bonding strength of the chip packaging structure.

[0021] Optionally, step S3, the step of forming a wiring layer within the groove structure, includes:

[0022] S31: Deposit a metal layer within the groove structure to form the metal interconnect covering the bottom of the groove structure, and then form a metal protective layer covering the metal layer;

[0023] S32: Deposit an insulating layer on the top surface of the metal protective layer;

[0024] S33: If the metal interconnect does not meet the wiring requirements, the metal layer is deposited again on the top surface of the insulating isolation layer, and then a metal protective layer covering the metal layer is formed;

[0025] S34: When the metal interconnects meet the wiring requirements, a top protective layer is formed covering the wiring layer. Its beneficial effects are: preventing the metal interconnects from being exposed, and simultaneously protecting the metal interconnects.

[0026] Optionally, removing a portion of the top surface of the initial insulating layer near the center of the wafer to form a stepped bottom insulating layer includes:

[0027] S41: A plurality of raised structures are formed on the surface of the lower insulating layer, and then a plurality of raised structures are formed on the sidewall where the remaining initial insulating layer is in contact with the lower insulating layer.

[0028] S42: Control the width of the lower insulating layer to be less than or equal to 0.5 mm. The beneficial effect is that the several protruding structures formed on the surface of the lower insulating layer and on the sidewall where the remaining initial insulating layer contacts the lower insulating layer increase the surface roughness of the lower insulating layer and the sidewall where the remaining initial insulating layer contacts the lower insulating layer, thereby enabling diffuse reflection of light incident on the photosensitive area and preventing stray light interference. Controlling the width of the lower insulating layer to be less than or equal to 0.5 mm allows the light-transmitting layer to adhere to the top surface of the lower insulating layer without affecting the layout of the wiring layer.

[0029] Optionally, step S3 further includes:

[0030] The width of the metal interconnect is controlled to be 30-50 micrometers. This has the advantage of protecting the metal interconnect from exposure and preventing short circuits. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the chip packaging structure according to an embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram of the structure obtained after forming an insulating layer and a protrusion structure on the top surface of a wafer according to an embodiment of the present invention;

[0033] Figure 3 This is a top view of the structure obtained after forming a lower insulating layer, the remaining initial insulating layer, and a first metal layer on the top surface of a wafer, according to an embodiment of the present invention.

[0034] Figure 4 This is a schematic flowchart of a chip packaging method according to an embodiment of the present invention;

[0035] Figure 5 This is a schematic diagram of the structure obtained after forming a light-shielding layer on the bottom surface of a wafer in an embodiment of the present invention;

[0036] Figure 6 In order to be in Figure 5 A schematic diagram of the structure obtained after depositing the first insulating layer on the structure shown;

[0037] Figure 7 In order to be in Figure 6 A schematic diagram of the structure obtained by removing part of the first insulating layer from the structure shown.

[0038] Figure 8 In order to be in Figure 7 A schematic diagram of the structure obtained by etching the second insulating layer based on the structure shown.

[0039] Figure 9 This is a schematic diagram of the structure obtained after step S31 of this embodiment of the invention;

[0040] Figure 10 This is a schematic diagram of the structure obtained after step S32 of this embodiment of the invention;

[0041] Figure 11 This is a schematic diagram of the structure obtained after step S34 of this embodiment of the invention;

[0042] Figure 12 In order to be in Figure 11 A schematic diagram of the structure obtained after forming pads on the structure shown;

[0043] Figure 13 This is a schematic diagram of the structure obtained after step S4 of this embodiment of the invention;

[0044] Figure 14 This is a schematic diagram of the structure obtained after step S5 of this embodiment of the invention;

[0045] Figure 15 This is a schematic diagram of the structure obtained after step S6 of an embodiment of the present invention. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0047] To address the problems existing in the prior art, embodiments of the present invention provide a chip packaging structure and a chip packaging method to simplify the chip packaging process, while enhancing the overall bonding strength of the packaging structure, reducing stray light interference, and improving the heat dissipation of the overall module.

[0048] The chip packaging structure of this invention includes a wafer, a light-shielding layer, a bottom protective layer, an insulating layer, a wiring layer, a light-transmitting layer, solder pads, and solder balls.

[0049] Figure 1 This is a schematic diagram of the chip packaging structure according to an embodiment of the present invention.

[0050] In this embodiment of the invention, reference is made to Figure 1The chip packaging structure includes a wafer 11, a light-shielding layer 12, a bottom protective layer 123, an insulating layer 51, a wiring layer 151, a light-transmitting layer 111, pads 91, and solder balls 121. The wiring layer 151, the insulating layer 51, the pads 91, and the solder balls 121 are arranged around the center of the wafer 11, and the top surface of the wafer 11 is a photosensitive surface.

[0051] In some embodiments, the wiring layer 151 is a ring structure.

[0052] In some embodiments, the wiring layer 151 has two layers.

[0053] In some embodiments, the insulating layer 51 has a ring structure.

[0054] In some embodiments, the number of insulating layers 51 is 2.

[0055] In some embodiments, the number of pads 91 is at least 2.

[0056] In some embodiments, the number of solder balls 121 is at least 2.

[0057] Reference Figure 1 The light-shielding layer 12 covers the bottom surface of the wafer 11; the bottom protective layer 123 covers the bottom surface of the light-shielding layer 12; the insulating layer 51 covers part of the top surface of the wafer 11 so that the middle top surface of the wafer 11 is exposed as a photosensitive area 110, the insulating layer 51 has a groove structure 112, and the insulating layer 51 also has a stepped lower insulating layer 61; the wiring layer 151 is disposed in the groove structure 112, and the wiring layer 151 has metal interconnects disposed therein; the light-transmitting layer 111 is disposed across the middle top surface of the wafer 11 and covers the top surface of the lower insulating layer 61; the pad 91 is disposed on the top surface of the wiring layer 151 and is in electrical contact with the metal interconnects; the solder ball 121 is disposed on the pad 91 and is in electrical contact with the pad 91.

[0058] In some embodiments, the wafer 11 is an automotive back-side illumination (BSI) chip.

[0059] In some embodiments, the thickness of the wafer 11 is greater than 180 micrometers.

[0060] In some embodiments, the thickness of the light-shielding layer 12 is greater than 5 micrometers.

[0061] In some embodiments, the material of the light-shielding layer 12 is a metal, such as Al.

[0062] In some embodiments, the light-transmitting layer 111 is glass.

[0063] Figure 2 This is a schematic diagram of the structure obtained after forming an insulating layer and a raised structure on the top surface of a wafer in an embodiment of the present invention.

[0064] In some embodiments, reference is made to Figure 2 The surface of the lower insulating layer 61 has several raised structures 22 to diffusely reflect light incident on the photosensitive area by increasing the surface roughness, thereby preventing stray light interference.

[0065] In some embodiments, the insulating layer further has a remaining initial insulating layer, the remaining initial insulating layer having a plurality of protruding structures on the sidewall in contact with the lower insulating layer.

[0066] In some embodiments, reference is made to Figure 2 The lower insulating layer 61 and the remaining initial insulating layer 413 together constitute the insulating layer 51. The height of the lower insulating layer 61 is a first height h1, and the height of the remaining initial insulating layer 413 is a second height h2. The first height h1 is less than the second height h2. The sidewall of the remaining initial insulating layer 413 that is in contact with the lower insulating layer 61 has a plurality of protruding structures 22.

[0067] In some embodiments, the protrusion structure 22 is shaped as a hemisphere, pyramid, cone, etc.

[0068] Figure 3 This is a top view of the structure obtained after forming a lower insulating layer, the remaining initial insulating layer, and a first metal layer on the top surface of a wafer, according to an embodiment of the present invention.

[0069] In some embodiments, the width of the metal interconnect is 30-50 micrometers.

[0070] In some embodiments, reference is made to Figure 3 The width of the metal interconnect (not shown in the figure) within the first metal layer 71 is a first width d1, which is 30-50 micrometers.

[0071] In some embodiments, the width of the metal interconnect is 40 micrometers.

[0072] In some embodiments, reference is made to Figure 3 The width of the lower insulating layer 61 is a second width d2, which is less than or equal to 0.5 mm.

[0073] In some embodiments, the number of layers of the metal interconnects is at least two, and the metal interconnects are electrically insulated from each other.

[0074] In some embodiments, epoxy resin is filled between the metal wires to achieve electrical insulation between the metal wires.

[0075] In some embodiments, reference is made to Figure 1 The chip packaging structure also includes a top protective layer (not shown) covering the wiring layer 151. The top protective layer (not shown) and the bottom protective layer 123 have the same constituent materials.

[0076] In some embodiments, both the top protective layer and the bottom protective layer are made of epoxy resin.

[0077] In some embodiments, the present invention also provides a chip packaging method.

[0078] Figure 4 This is a schematic flowchart of a chip packaging method according to an embodiment of the present invention. (Refer to...) Figure 4 The chip packaging method includes the following steps:

[0079] S1: Provide a wafer with a photosensitive top surface, and deposit a light-shielding layer on the bottom surface of the wafer;

[0080] S2: An initial insulating layer is formed on the top surface of the wafer, exposing the middle top surface of the wafer as the photosensitive area; the initial insulating layer has a groove structure.

[0081] S3: A wiring layer is formed in the groove structure, and a pad is formed on the top surface of the wiring layer that is in electrical contact with the metal interconnects in the wiring layer. Then, it is checked whether the metal interconnects meet the wiring requirements.

[0082] S4: Remove a portion of the top surface of the initial insulating layer near the center of the wafer to form a stepped lower insulating layer. The lower insulating layer and the remaining initial insulating layer together constitute an insulating layer.

[0083] S5: A light-transmitting layer is formed across the top surface of the middle portion of the wafer, covering the top surface of the bottom insulating layer;

[0084] S6: After depositing and forming a bottom protective layer on the bottom surface of the light-shielding layer, ball-mounting is performed on the pads.

[0085] Figure 5 This is a schematic diagram of the structure obtained after forming a light-shielding layer on the bottom surface of a wafer in an embodiment of the present invention. Figure 6 In order to be in Figure 5 A schematic diagram of the structure obtained after depositing the first insulating layer on the structure shown.

[0086] In step S1, refer to Figure 5 A light-shielding layer 12 is formed on the bottom surface of the wafer 11, covering the bottom surface of the wafer 11. Further, in step S2, referring to... Figure 6 A first insulating layer 41 is formed on the top surface of the wafer 11.

[0087] In some embodiments, the thickness of the first insulating layer is 20-30 micrometers.

[0088] In some embodiments, the first insulating layer is composed of epoxy resin.

[0089] Figure 7 In order to be in Figure 6 A schematic diagram of the structure obtained by removing part of the first insulating layer based on the structure shown.

[0090] In step S2, refer to Figure 6 and Figure 7 A portion of the first insulating layer 41 on the top surface of the wafer 11 is removed, exposing the central top surface of the wafer 11 as the photosensitive area 110, to form a second insulating layer 411, which surrounds the central part of the wafer 11.

[0091] Figure 8 In order to be in Figure 7 A schematic diagram of the structure obtained by etching the second insulating layer based on the structure shown.

[0092] In step S2, refer to Figure 7 Etch a portion of the top of the second insulating layer 411, further referring to... Figure 8 To form an initial insulating layer 412 including a groove structure 112, which is an annular structure.

[0093] In some embodiments, step S3, the step of forming a wiring layer within the groove structure, includes:

[0094] S31: Deposit a metal layer within the groove structure to form the metal interconnect covering the bottom of the groove structure, and then form a metal protective layer covering the metal layer;

[0095] S32: Deposit an insulating layer on the top surface of the metal protective layer;

[0096] S33: If the metal interconnect does not meet the wiring requirements, the metal layer is deposited again on the top surface of the insulating isolation layer, and then a metal protective layer covering the metal layer is formed;

[0097] S34: When the metal interconnects meet the wiring requirements, a top protective layer is formed covering the wiring layer.

[0098] Figure 9 This is a schematic diagram of the structure obtained after step S31 of an embodiment of the present invention.

[0099] In some embodiments, in step S3, reference is made to... Figure 8 and Figure 9A first metal layer 71 is deposited in the groove structure 112, metal interconnects are formed in the first metal layer 71, and then a first metal protective layer 701 is formed covering the first metal layer 71.

[0100] In some embodiments, the first metal layer 71 has a ring structure.

[0101] In some embodiments, step S3 further includes:

[0102] The width of the metal interconnect is controlled to be 30-50 micrometers.

[0103] In some embodiments, reference is made to Figure 3 The width of the metal interconnect is a first width d1, and the first width d1 is controlled to be 30-50 micrometers.

[0104] In some embodiments, the width of the metal interconnect is 40 micrometers.

[0105] Figure 10 This is a schematic diagram of the structure obtained after step S32 of an embodiment of the present invention.

[0106] In some embodiments, in step S3, reference is made to... Figure 9 and Figure 10 An insulating isolation layer 81 is deposited on the top surface of the first metal protective layer 701.

[0107] Figure 11 This is a schematic diagram of the structure obtained after step S34 of an embodiment of the present invention.

[0108] In some embodiments, in step S33, reference is made to... Figure 11 If the metal interconnects formed in the first metal layer 71 do not meet the wiring requirements, a second metal layer 161 is deposited on the top surface of the insulating isolation layer 81, and then a second metal protective layer 702 covering the second metal layer 161 is formed. In step S34, if the metal interconnects formed in the second metal layer 161 meet the wiring requirements, a top protective layer 703 is deposited on the top surface of the second metal protective layer 702.

[0109] In some embodiments, the first metal protective layer 701, the second metal protective layer 702, and the top protective layer 703 are all made of epoxy resin.

[0110] Figure 12 In order to be in Figure 11 A schematic diagram of the structure obtained after forming pads on the structure shown.

[0111] In some embodiments, in step S3, reference is made to... Figure 11 and Figure 12A pad 91 is formed on the top surface of the top protective layer 703, and the pad 91 has a ring structure.

[0112] In some embodiments, reference is made to Figure 12 The pad 91 covers a portion of the top surface of the initial insulating layer 412.

[0113] In some embodiments, the pads cover the top surface of the top protective layer, and the pads do not contact the initial insulating layer.

[0114] In some embodiments, removing a portion of the top surface of the initial insulating layer near the center of the wafer to form a stepped bottom insulating layer includes:

[0115] S41: A plurality of raised structures are formed on the surface of the lower insulating layer, and then a plurality of raised structures are formed on the sidewall where the remaining initial insulating layer is in contact with the lower insulating layer.

[0116] S42: Control the width of the lower insulating layer to be less than or equal to 0.5 mm.

[0117] Figure 13 This is a schematic diagram of the structure obtained after step S4 of an embodiment of the present invention.

[0118] In some embodiments, in step S41, reference is made to... Figure 12 and Figure 13 The top surface of the initial insulating layer 412 near the middle of the wafer 11 is removed to form a stepped lower insulating layer 61. The lower insulating layer 61 and the remaining initial insulating layer 413 together constitute the insulating layer 51. Then, a plurality of protrusion structures 22 are formed on the surface of the lower insulating layer 61. Then, a plurality of protrusion structures 22 are formed on the sidewall where the remaining initial insulating layer 413 is connected to the lower insulating layer 61.

[0119] In some embodiments, in step S42, reference is made to... Figure 3 The width of the lower insulating layer 61 is a second width d2, and the second width d2 is controlled to be less than or equal to 0.5 mm.

[0120] Figure 14 This is a schematic diagram of the structure obtained after step S5 of an embodiment of the present invention.

[0121] In some embodiments, in step S5, reference is made to... Figure 13 and Figure 14 A light-transmitting layer 111 is attached across the top surface of the middle portion of the wafer 11, covering the top surface of the bottom insulating layer 61.

[0122] Figure 15 This is a schematic diagram of the structure obtained after step S6 of an embodiment of the present invention.

[0123] In some embodiments, in step S6, reference is made to... Figure 15 A bottom protective layer 123 is formed on the bottom surface of the light-shielding layer 12. Further, solder balls are welded onto the surface of the pad 91 to form solder balls 121, which are arranged around the center of the wafer 11, but are not limited thereto.

[0124] In summary, the chip packaging structure and chip packaging method of the present invention simplify the chip packaging process by forming the solder balls on the top surface of the wafer and simultaneously forming a stepped bottom insulating layer on the top surface of the wafer, while enhancing the overall bonding strength and heat dissipation capacity of the packaging structure. The surface of the bottom insulating layer and the sidewalls of the insulating layer that are in contact with the bottom insulating layer are provided with several protruding structures, which can reduce stray light interference.

[0125] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A chip packaging method, characterized in that, Includes the following steps: S1: Provide a wafer with a photosensitive top surface, and deposit a light-shielding layer on the bottom surface of the wafer; S2: An initial insulating layer is formed on the top surface of the wafer, exposing the middle top surface of the wafer as a photosensitive area; the initial insulating layer has a groove structure. S3: A wiring layer is formed in the groove structure, and a pad is formed on the top surface of the wiring layer that is in electrical contact with the metal interconnects in the wiring layer. Then, it is checked whether the metal interconnects meet the wiring requirements. S4: Remove a portion of the top surface of the initial insulating layer near the center of the wafer to form a stepped lower insulating layer. The lower insulating layer and the remaining initial insulating layer together constitute an insulating layer. S5: A light-transmitting layer is formed across the top surface of the middle portion of the wafer, covering the top surface of the bottom insulating layer; S6: After depositing and forming a bottom protective layer on the bottom surface of the light-shielding layer, ball-mounting is performed on the pads.

2. The chip packaging method according to claim 1, characterized in that, In step S3, the step of forming a wiring layer within the groove structure includes: S31: Deposit a metal layer within the groove structure to form the metal interconnect covering the bottom of the groove structure, and then form a metal protective layer covering the metal layer; S32: Deposit an insulating layer on the top surface of the metal protective layer; S33: If the metal interconnect does not meet the wiring requirements, the metal layer is deposited again on the top surface of the insulating isolation layer, and then a metal protective layer covering the metal layer is formed; S34: When the metal interconnects meet the wiring requirements, a top protective layer is formed covering the wiring layer.

3. The chip packaging method according to claim 1, characterized in that, The step of removing a portion of the top surface of the initial insulating layer near the center of the wafer to form a stepped bottom insulating layer includes: S41: A plurality of raised structures are formed on the surface of the lower insulating layer, and then a plurality of raised structures are formed on the sidewall where the remaining initial insulating layer is in contact with the lower insulating layer. S42: Control the width of the lower insulating layer to be less than or equal to 0.5 mm.

4. The chip packaging method according to claim 1, characterized in that, Step S3 further includes: The width of the metal interconnect is controlled to be 30-50 micrometers.

5. A chip packaging structure, prepared using the chip packaging method according to any one of claims 1 to 4, characterized in that, The chip packaging structure includes: A wafer, wherein the top surface of the wafer is a photosensitive surface; A light-shielding layer covering the bottom surface of the wafer; A bottom protective layer covers the bottom surface of the light-shielding layer; An insulating layer covers a portion of the top surface of the wafer so that the central top surface of the wafer is exposed as a photosensitive area. The insulating layer has a groove structure and also has a stepped lower insulating layer. A wiring layer is disposed within the groove structure, and metal interconnects are disposed within the wiring layer; A light-transmitting layer is disposed across the top surface of the middle portion of the wafer and covers the top surface of the bottom insulating layer; The pads are disposed on the top surface of the wiring layer and are in electrical contact with the metal interconnects; Solder balls are disposed on the solder pads and are in electrical contact with the solder pads.

6. The chip packaging structure according to claim 5, characterized in that, The surface of the lower insulating layer has several raised structures to diffusely reflect light incident on the photosensitive area by increasing surface roughness, thereby preventing stray light interference.

7. The chip packaging structure according to claim 6, characterized in that, The insulating layer also has a remaining initial insulating layer, and the sidewall of the remaining initial insulating layer that is in contact with the lower insulating layer has a plurality of protruding structures.

8. The chip packaging structure according to claim 5, characterized in that, The width of the metal interconnect is 30-50 micrometers, and the width of the bottom insulating layer is less than or equal to 0.5 millimeters.

9. The chip packaging structure according to claim 5, characterized in that, The number of layers of the metal interconnects is at least 2, and the layers of different metal interconnects are electrically insulated from each other.

10. The chip packaging structure according to claim 5, characterized in that, It also includes a top protective layer covering the wiring layer, and the top protective layer and the bottom protective layer have the same constituent materials.

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