Silicon carbide MOSFET device with integrated SBD and its fabrication method

Abstract

This invention discloses a silicon carbide MOSFET device with integrated source contact resistance (SBD) and its fabrication method, comprising a substrate, an N-epitaxial layer, a P-well region, a P+ region of a junction field-effect region (JFET), P+ and N+ regions of a source trench region, a first ohmic contact metal layer, a first Schottky contact metal layer, a second ohmic contact metal layer, and a second Schottky contact metal layer. The P+ region of the JFET is located on the side of the P-well region away from the N+ region. The second ohmic contact metal layer covers the side of the P+ region of the JFET that faces away from the N-epitaxial layer. The first Schottky contact metal layer is located on the side of the second ohmic contact metal layer away from the P-well region. The second Schottky contact metal layer is disposed on the side of the second ohmic contact metal layer that faces away from the P+ region of the JFET and is parallel to the P+ region of the JFET. This invention can reduce the source contact resistance, improve the current carrying capacity of the silicon carbide device, and enhance the reliability of the silicon carbide device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a silicon carbide MOSFET device with integrated SBD and its fabrication method. Background Technology

[0002] Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) possess characteristics such as low on-resistance, fast switching speed, and high temperature resistance, offering significant advantages in applications such as high-voltage frequency conversion, new energy vehicles, and rail transportation. To improve the current carrying capacity of SiC MOSFETs, the cell size is often compressed to increase the current-carrying area. However, as the cell size is continuously compressed, the source hole contact area also decreases, leading to a significant increase in source contact resistance, which is detrimental to reducing the overall resistance of the device.

[0003] Meanwhile, in applications such as motor drives and traction inverters, the traditional approach is to connect a Schottky diode in parallel with the SiC MOSFET, utilizing the low on-state voltage drop of the external anti-parallel diode to achieve reverse freewheeling capability. However, this increases the package area and reduces the overall current carrying capacity of the device module. Another approach is to utilize the body diode integrated within the SiC MOSFET itself for freewheeling during reverse conduction. However, since the body diode is a PIN structure device, it generates a high turn-on voltage drop and reverse recovery loss. Furthermore, the conduction of the SiC bipolar device induces electron-hole recombination, causing the bulk stack to expand, increasing the device voltage drop and reverse bias leakage current, which is detrimental to the reliability of silicon carbide devices.

[0004] Therefore, how to increase the source contact area, reduce the source contact resistance, improve the current carrying capacity of silicon carbide devices, and enhance the reliability of silicon carbide devices without changing the cell size is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The main objective of this invention is to provide a silicon carbide MOSFET device with integrated SBD and its fabrication method, so as to increase the source contact area, reduce the source contact resistance, improve the current carrying capacity of the silicon carbide device, and improve the reliability of the silicon carbide device without changing the cell size.

[0006] To address the aforementioned problems, this invention provides a silicon carbide MOSFET device with integrated SBD, comprising a plurality of cell structures, wherein each cell structure includes a substrate, an N-epitaxial layer formed on the substrate; a P-well region, a P+ region of a junction field-effect region, a P+ region of a source trench region, and an N+ region located within the N-epitaxial layer; and a first ohmic contact metal layer, a first Schottky contact metal layer, a second ohmic contact metal layer, and a second Schottky contact metal layer located on the N-epitaxial layer.

[0007] Wherein, the P-well region and the P+ region of the source trench region are adjacent, the N+ region is located within the P-well region, and the P+ region and the N+ region of the source trench region are adjacent.

[0008] The first portion of the first ohmic contact metal layer covers a portion of the N+ region facing away from the N- epitaxial layer, the first portion of the first ohmic contact metal layer covers a portion of the N+ region facing the P+ region of the source trench region, and the first portion of the first ohmic contact metal layer covers the P+ region of the source trench region facing away from the N- epitaxial layer.

[0009] The P+ region of the junction field-effect region is located on the side of the P-well region away from the N+ region; the second ohmic contact metal layer covers the side of the P+ region of the junction field-effect region away from the N- epitaxial layer; the first Schottky contact metal layer and the second ohmic contact metal layer are arranged side by side, and the first Schottky contact metal layer is located on the side of the second ohmic contact metal layer away from the P-well region; the second Schottky contact metal layer is disposed on the side of the second ohmic contact metal layer away from the P+ region of the junction field-effect region, and is parallel to the P+ region of the junction field-effect region.

[0010] Furthermore, in the silicon carbide MOSFET device with integrated SBD described above, the cell structure further includes a gate oxide layer located on the N-epitaxial layer;

[0011] The gate oxide layer is located between the first portion of the first ohmic contact metal layer and the second Schottky contact metal layer;

[0012] A polycrystalline silicon gate electrode is formed on the gate oxide layer, and the outer periphery of the polycrystalline silicon gate electrode is covered with an interlayer dielectric.

[0013] The gate oxide layer covers the surface of the P-well region, and the two sides of the gate oxide layer respectively cover a portion of the surface of the N+ region and a portion of the surface of the junction field-effect region.

[0014] Furthermore, in the silicon carbide MOSFET device with integrated SBD described above, the cell structure further includes a source and a drain.

[0015] The source electrode covers the interlayer dielectric, the first ohmic contact metal layer, the first Schottky contact metal layer, the second ohmic contact metal layer, and the second Schottky contact metal layer;

[0016] The drain is located on the side of the substrate away from the N-epitaxial layer.

[0017] Furthermore, in the silicon carbide MOSFET device with integrated SBD described above, the depth of the junction field-effect trench corresponding to the junction field-effect region is 0.25μm to 0.35μm.

[0018] Furthermore, in the silicon carbide MOSFET device with integrated SBD described above, the depth of the source trench corresponding to the source trench region is 0.25μm to 0.35μm.

[0019] Furthermore, in the silicon carbide MOSFET device with integrated SBD described above, the depth of the N+ region is 0.3 μm to 0.4 μm;

[0020] The depth of the P-well region is 1.0 μm to 1.5 μm.

[0021] Furthermore, in the silicon carbide MOSFET device with integrated SBD described above, the depth of the P+ region of the junction field-effect region is 1.0 μm to 1.6 μm.

[0022] Furthermore, in the aforementioned silicon carbide MOSFET device with integrated SBD,

[0023] The depth of the P+ region in the source trench is 1.0 μm to 1.6 μm.

[0024] This invention also provides a method for fabricating a silicon carbide MOSFET device with integrated SBD, comprising:

[0025] An N-epitaxial layer is formed on the substrate;

[0026] On the side of the N-epitaxial layer away from the substrate, an oxide layer is deposited, and a P-well implantation window is formed by photolithography and etching. The oxide layer is used as an ion implantation mask, and Al ions are implanted to form the P-well region.

[0027] On the side of the N- epitaxial layer away from the substrate, an oxide layer is deposited again, and an oxide layer sidewall is formed by reverse etching; using the oxide layer sidewall as an ion implantation mask, N ions are implanted to form an N+ region;

[0028] On the side of the N-epitaxial layer away from the substrate, an oxide layer is deposited again. The etching windows for the source trench and the junction field-effect trench are formed by photolithography and etching. The oxide layer is used as a barrier layer to perform SiC dielectric etching, and the source trench and the junction field-effect trench are formed on the surface of the N-epitaxial layer.

[0029] The junction field-effect trench is subjected to oxide deposition, photolithography, and etching. The middle region of the junction field-effect trench is covered by oxide layer to form an implantation barrier layer. Al ions are implanted into the source trench to form the P+ region of the source trench region. Al ions are implanted into the junction field-effect trench to form the P+ region of the junction field-effect region.

[0030] Remove all oxide layers on the N-epitaxial layer and perform an activation annealing process at a first preset temperature to activate the implanted Al and N ions;

[0031] A gate oxide layer is formed on the P-well region, a polysilicon gate electrode is formed on the gate oxide layer, an interlayer dielectric is deposited on the polysilicon gate electrode, and ohmic contact holes are formed by etching to expose the P+ region of the junction field-effect region, the P+ region of the source trench region, and the N+ region.

[0032] A nitride layer is deposited, and the non-ohmic alloy region in the junction field-effect trench is covered and protected by photolithography and etching.

[0033] Metal is deposited on the side of the N-epitaxial layer away from the substrate, and an annealing process is performed at a second preset temperature to form a first ohmic contact metal layer in the P+ region of the source trench region and a second ohmic contact metal layer in the P+ region of the junction field-effect region.

[0034] The nitride layer is removed by etching, and metal is deposited again. Then, the metal is annealed at a third preset temperature to form a first Schottky contact metal layer and a second Schottky contact metal layer in the P+ region of the junction field-effect region.

[0035] Furthermore, the fabrication method of the silicon carbide MOSFET device with integrated SBD described above also includes:

[0036] Metal is deposited on the side of the N-epitaxial layer away from the substrate to form a source, and metal is deposited on the side of the substrate away from the N-epitaxial layer to form a drain.

[0037] Compared with the prior art, one or more embodiments of the above solutions may have the following advantages or beneficial effects:

[0038] The present invention relates to a silicon carbide MOSFET device with integrated SBD and its fabrication method. By integrating a SiC SBD within the SiC MOSFET cell structure, the SiC SBD is used as a freewheeling diode under reverse bias to suppress the turn-on of the body diode and increase the reliability of the chip during long-term operation. When the SBD structure is integrated into the MOSFET cell structure, the SBD part and the MOSFET part can share part of the active region and termination region area, which greatly improves the overall power density of the chip and reduces the module packaging cost. By utilizing the trench-type source trench region structure, the contact area of ​​the source via is increased in three-dimensional space, reducing the influence of the source contact resistance on the overall resistance of the device and facilitating the output of larger current capacity.

[0039] Other features and advantages of the invention will be set forth in the description which follows, and will become apparent in part from the adjustments made thereto, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0040] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0041] Figure 1 This is a top view of the silicon carbide MOSFET device with integrated SBD according to the present invention;

[0042] Figure 2 for Figure 1 A cross-sectional view along the XY direction;

[0043] Figure 3 This is a flowchart illustrating an embodiment of the method for fabricating a silicon carbide MOSFET device with integrated SBD according to the present invention;

[0044] Figure 4 This is the first state diagram formed after steps 300 and 301;

[0045] Figure 5 This is the second state diagram formed after step 302;

[0046] Figure 6 This is the third state diagram formed after step 303;

[0047] Figure 7 This is the fourth state diagram formed after step 304;

[0048] Figure 8 This is the fifth state diagram formed after step 305;

[0049] Figure 9This is the sixth state diagram formed after step 306;

[0050] Figure 10 This is the seventh state diagram formed after step 307;

[0051] Figure 11 This is the eighth state diagram formed after steps 308 and 309. Detailed Implementation

[0052] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples, so that the process of how the present invention uses technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly. It should be noted that, as long as there is no conflict, the various embodiments and features in the various embodiments of the present invention can be combined with each other, and the resulting technical solutions are all within the protection scope of the present invention.

[0053] Figure 1 This is a top view of the silicon carbide MOSFET device with integrated SBD according to the present invention. Figure 2 for Figure 1 A cross-sectional view along the XY direction. For example... Figures 1-2 As shown, the silicon carbide MOSFET device with integrated SBD in this embodiment may include a plurality of cell structures. The cell structure includes a substrate 10, an N-epitaxial layer 11 formed on the substrate 10; a P-well region 12, a P+ region 13 of the junction field-effect region (hereinafter referred to as the JFET region), a P+ region 14 of the source trench region, and an N+ region 15 located within the N-epitaxial layer 11; a first ohmic contact metal layer 16, a first Schottky contact metal layer 17, a second ohmic contact metal layer 18, and a second Schottky contact metal layer 19 located on the N-epitaxial layer 11.

[0054] Wherein, the P-well region 12 and the P+ region 14 of the source trench region are adjacent, the N+ region 15 is located within the P-well region 12, and the P+ region 14 and the N+ region 15 of the source trench region are adjacent.

[0055] The first portion of the first ohmic contact metal layer 16 covers a portion of the N+ region 15 facing away from the N- epitaxial layer 11, the first portion of the first ohmic contact metal layer 16 covers a portion of the N+ region 15 facing the P+ region 14 of the source trench region, and the first portion of the first ohmic contact metal layer 16 covers the P+ region 14 of the source trench region facing away from the N- epitaxial layer 11.

[0056] The P+ region 13 of the JFET region is located on the side of the P-well region 12 away from the N+ region 15; the second ohmic contact metal layer 18 covers the side of the P+ region 13 of the JFET region away from the N-epipolar layer 11; the first Schottky contact metal layer 17 and the second ohmic contact metal layer 18 are arranged side by side, and the first Schottky contact metal layer 17 is located on the side of the second ohmic contact metal layer 18 away from the P-well region 12; the second Schottky contact metal layer 19 is disposed on the side of the second ohmic contact metal layer 18 away from the P+ region 13 of the JFET region, and is parallel to the P+ region 13 of the JFET region.

[0057] In a specific implementation, the integrated SiC SBD is located in the JFET region, which effectively utilizes the area of ​​the JFET region, resulting in higher cell structure integration and reduced cell structure volume.

[0058] In one specific implementation, the integrated SiC SBD is a trench structure, which effectively protects the electric field of the JFET region of the SiC MOSFET and the electric field of the Schottky contact of the SiC SBD, thereby improving the blocking capability of the SiC MOSFET device. Furthermore, in the trench-shaped JFET region, three-dimensional integration (i.e., the second Schottky contact metal layer 19) is performed on the sidewall, increasing the current-carrying area of ​​the Schottky contact and reducing the diode's forward voltage drop.

[0059] In one specific implementation, the SiC MOSFET source 22 is designed with a groove structure, and the groove sidewalls of the source via are used to increase the contact surface of the source 22. Figure 1 The design structure of the first ohmic contact metal layer 16 increases the current path for electrons to enter and exit the source 22, reduces the contact resistance of the source 22, and improves the current carrying capacity of the silicon carbide device.

[0060] In one specific implementation, deep well injection is performed using the P+ region 14 formed by the slot structure to create the source slot region, which better achieves the short circuit with the N+ region 15 and enhances the suppression of parasitic NPN transistors.

[0061] In a specific implementation process, the JFET trench in the JFET region, the source trench in the source trench region, and each P+ deep well are formed using a synchronous process. The depth of the P+ deep well has consistent adjustability, which is beneficial for simultaneously optimizing the internal body diode electric field and SBD electric field.

[0062] The silicon carbide MOSFET device with integrated SBD in this embodiment integrates SiC SBD within the SiC MOSFET cell structure. The SiC SBD serves as a freewheeling diode under reverse bias, suppressing the turn-on of the body diode and increasing the long-term reliability of the chip. When the SBD structure is integrated into the MOSFET cell structure, the SBD and MOSFET portions can share some of the active and terminal area, significantly improving the overall power density of the chip while reducing module packaging costs. The trench-type source trench structure increases the contact area of ​​the source via in three-dimensional space, reducing the impact of source contact resistance on the overall device resistance and facilitating output with greater current capacity.

[0063] like Figure 1 As shown, the cell structure also includes a gate oxide layer (not shown in the figure) located on the N-epipolar layer 11; the gate oxide layer is located between the first part of the first ohmic contact metal layer 16 and the second Schottky contact metal layer 19; a polysilicon gate electrode 20 is formed on the gate oxide layer, and the periphery of the polysilicon gate electrode 20 is covered with an interlayer dielectric 21; the gate oxide layer covers the surface of the P-well region 12, and the two sides of the gate oxide layer respectively cover a portion of the surface of the N+ region 15 and a portion of the surface of the JFET region.

[0064] In one specific implementation, the polysilicon gate electrode 20 of the SiC MOSFET adopts a split gate structure, which effectively reduces the gate capacitance and input capacitance and improves the switching characteristics of the device.

[0065] like Figure 2 As shown, the cell structure further includes a source 22 and a drain 23; the source 22 covers the interlayer dielectric 21, the first ohmic contact metal layer 16, the first Schottky contact metal layer 17, the second ohmic contact metal layer 18, and the second Schottky contact metal layer 19; the drain 23 is located on the side of the substrate 10 away from the N-epitaxial layer 11.

[0066] In one specific implementation, the depth of the junction field-effect trench corresponding to the JFET region is 0.25 μm to 0.35 μm. The depth of the source trench corresponding to the source trench region is 0.25 μm to 0.35 μm. The depth of the N+ region 15 is 0.3 μm to 0.4 μm; the depth of the P-well region 12 is 1.0 μm to 1.5 μm. The depth of the P+ region 13 of the JFET region is 1.0 μm to 1.6 μm. The depth of the P+ region 14 of the source trench region is 1.0 μm to 1.6 μm.

[0067] Figure 3 A flowchart illustrating an embodiment of the fabrication method of the silicon carbide MOSFET device with integrated SBD according to the present invention is shown below. Figure 3As shown, the method may include the following steps:

[0068] 300. An N-epitaxial layer 11 is formed on the substrate 10;

[0069] Specifically, an N-epitaxial layer 11 is prepared, the N-epitaxial layer 11 having a doping concentration of 1E18cm. -3 ~1E19cm -3 An N+ substrate 10 is provided, and an N- epitaxial layer 11 is disposed on the N+ substrate 10, the N- epitaxial layer 11 having a concentration of approximately 1E14 cm⁻¹. -3 ~5E16cm -3 The specific optimization needs to be based on the chip's voltage tolerance.

[0070] 301. On the side of the N-epitaxial layer 11 away from the substrate 10, an oxide layer A is deposited, and a P-well implantation window is formed by photolithography and etching. The oxide layer is used as an ion implantation mask, and Al ions are implanted to form a P-well region 12.

[0071] Specifically, in this step, the thickness of oxide layer A can be 1.5 μm to 3.0 μm, and the depth of P-well region 12 can be 1.0 μm to 1.5 μm.

[0072] Figure 4 This is the first state diagram formed after steps 300 and 301. (Example) Figure 4 As shown, the silicon carbide MOSFET device in this state may include a substrate 10, an N-epitaxial layer 11, an oxide layer A, and a P-well region 12.

[0073] 302. On the side of the N- epitaxial layer 11 away from the substrate 10, an oxide layer A is deposited again, and an oxide layer sidewall B is formed by reverse etching; using the oxide layer sidewall B as an ion implantation mask, N ions are implanted to form the N+ region 15.

[0074] In one specific implementation, the depth of the N+ region 15 can be 0.3 μm to 0.4 μm. This oxide layer A can be the same as or different from the oxide layer in step 1. For example, it can be silicon oxide.

[0075] It should be noted that the oxide layer sidewall B can be used to achieve a precisely controllable 0.25μm to 0.8μm self-aligned channel according to actual needs. This greatly reduces the channel length and improves the device's current output capability.

[0076] Figure 5 This is the second state diagram formed after step 302. For example... Figure 5 As shown, the silicon carbide MOSFET device in this state... Figure 4 Based on the above, oxide layer sidewall B and N+ region 15 were added.

[0077] 303. On the side of the N-epitaxial layer 11 away from the substrate 10, an oxide layer A is deposited again. The etching windows of the source trench C and the junction field effect trench D are formed by photolithography and etching. The oxide layer is used as a barrier layer to perform SiC dielectric etching to form the source trench C and the junction field effect trench D on the surface of the N-epitaxial layer 11.

[0078] In one specific implementation, the thickness of oxide layer A in this step can be 1.0 μm to 2.0 μm. The depth of the junction field-effect trench D corresponding to the JFET region is 0.25 μm to 0.35 μm. The depth of the source trench C corresponding to the source trench region is 0.25 μm to 0.35 μm.

[0079] Figure 6 This is the third state diagram formed after step 303. For example... Figure 6 As shown, the silicon carbide MOSFET device in this state... Figure 5 Based on the above, source trench C and junction field effect trench D were added, oxide sidewall B was reduced, and the position of oxide layer A was changed.

[0080] 304. Deposit oxide layer, perform photolithography and etching on junction field effect trench D. The middle region of junction field effect trench D is covered by oxide layer A to form implantation barrier layer. Perform Al ion implantation on the source trench to form P+ region 14 of source trench region. Perform Al ion implantation on the junction field effect trench D to form P+ region 13 of JFET region.

[0081] The depth of the P+ region 13 in the JFET region is 1.0 μm to 1.6 μm. The depth of the P+ region 14 in the source trench region is 1.0 μm to 1.6 μm.

[0082] Figure 7 This is the fourth state diagram formed after step 304. For example... Figure 7 As shown, the silicon carbide MOSFET device in this state... Figure 6 Based on the above, a partial oxide layer A, a P+ region 14 of the source trench region, and a P+ region 13 of the JFET region are added. The material of the added oxide layer A can be the same as or different from that of the original oxide layer A.

[0083] 305. Remove all oxide layers on the N-epipolar layer 11 and perform an activation annealing process at a first preset temperature to activate the implanted Al and N ions;

[0084] The first preset temperature can be 1700℃~1800℃. The activation annealing process time can be 10min~40min.

[0085] Figure 8This is the fifth state diagram formed after step 305. For example... Figure 8 As shown, the silicon carbide MOSFET device in this state... Figure 7 Based on the above, all oxide layers were removed.

[0086] 306. A gate oxide layer is formed on the P-well region 12, a polysilicon gate electrode 20 is formed on the gate oxide layer, an interlayer dielectric 21 is deposited on the polysilicon gate electrode 20, and an ohmic contact hole is formed by etching to expose the P+ region 13 of the JFET region, the P+ region 14 of the source trench region and the N+ region 15.

[0087] Figure 9 This is the sixth state diagram formed after step 306. For example... Figure 9 As shown, the silicon carbide MOSFET device in this state... Figure 8 Based on the above, a gate oxide layer (not shown in the figure), a polysilicon gate electrode 20, and an interlayer dielectric 21 are added.

[0088] 307. Deposit nitride layer E, and cover and protect the non-ohmic alloy region in the junction field effect trench by photolithography and etching;

[0089] The thickness of the nitride layer E can be 0.5 μm to 1.0 μm, and it can be silicon nitride.

[0090] Figure 10 This is the seventh state diagram formed after step 307. For example... Figure 10 As shown, the silicon carbide MOSFET device in this state... Figure 9 Based on the diagram shown, a nitrided layer E was added.

[0091] 308. Deposit metal on the side of the N-epipolar layer 11 away from the substrate 10, and perform an annealing process at a second preset temperature to form a first ohmic contact metal layer 16 in the P+ region 14 of the source trench region and a second ohmic contact metal layer 18 in the P+ region 13 of the JFET region.

[0092] The second preset temperature can be 900℃ to 1000℃. The annealing process time for this step can be 2 min to 5 min. The metal used in this step can be at least one of Ni, Ti, Al, etc.

[0093] 309. By etching away the nitride layer, metal is deposited again, and annealing is performed at a third preset temperature to form a first Schottky contact metal layer 17 and a second Schottky contact metal layer 19 in the P+ region 13 of the JFET region.

[0094] The third preset temperature can be 400℃ to 600℃. The annealing process time for this step can be 5 min to 10 min. The metal used in this step can be at least one of Ti, Mo, etc.

[0095] Figure 11 This is the eighth state diagram formed after steps 308 and 309. (Example) Figure 11 As shown, the silicon carbide MOSFET device in this state... Figure 10 Based on the previous design, the nitride layer was reduced. A first Schottky contact metal layer 17, a second Schottky contact metal layer 19, a first ohmic contact metal layer 16, and a second ohmic contact metal layer 18 were added.

[0096] 310. Deposit metal on the side of the N-epipolar layer 11 away from the substrate 10 to form a source 22, and deposit metal on the side of the substrate 10 away from the N-epipolar layer 11 to form a drain 23.

[0097] Specifically, Al metal can be deposited on the side of the N-epitaxial layer 11 away from the substrate to form a source electrode, leading out the source electrode structure and the gate electrode. The electrode can be formed by annealing at 900℃~1000℃ for 2min~5min. See details. Figure 1 .

[0098] It is understood that the same or similar parts in the above embodiments can be referred to each other, and the contents not described in detail in some embodiments can be referred to the same or similar contents in other embodiments.

[0099] It should be noted that in the description of this invention, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means at least two.

[0100] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0101] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0102] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes in form and detail of the implementation without departing from the spirit and scope disclosed herein; however, the scope of protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A silicon carbide MOSFET device with integrated SBD, characterized in that, It includes several cellular structures, each cellular structure including a substrate and an N-epitaxial layer formed on the substrate; a P-well region, a P+ region of a junction field-effect region, a P+ region of a source trench region, and an N+ region located within the N-epitaxial layer; and a first ohmic contact metal layer, a first Schottky contact metal layer, a second ohmic contact metal layer, and a second Schottky contact metal layer located on the N-epitaxial layer. Wherein, the P-well region and the P+ region of the source trench region are adjacent, the N+ region is located within the P-well region, and the P+ region and the N+ region of the source trench region are adjacent. The first portion of the first ohmic contact metal layer covers a portion of the N+ region facing away from the N- epitaxial layer, the first portion of the first ohmic contact metal layer covers a portion of the N+ region facing the P+ region of the source trench region, and the first portion of the first ohmic contact metal layer covers the P+ region of the source trench region facing away from the N- epitaxial layer. The P+ region of the junction field-effect region is located on the side of the P-well region away from the N+ region; the depth of the P+ region of the junction field-effect region is the same as the depth of the P+ region of the source trench region; the second ohmic contact metal layer covers the side of the P+ region of the junction field-effect region away from the N-epitaxial layer; the first Schottky contact metal layer and the second ohmic contact metal layer are arranged side by side, and the first Schottky contact metal layer is located on the side of the second ohmic contact metal layer away from the P-well region; the second Schottky contact metal layer is disposed on the side of the second ohmic contact metal layer away from the P+ region of the junction field-effect region, and is parallel to the P+ region of the junction field-effect region; the second ohmic contact metal layer is used to block the connection between the first Schottky contact metal layer and the second Schottky contact metal layer; the P+ region of the junction field-effect region is in contact with the second ohmic contact metal layer, and the P+ region of the junction field-effect region is not in contact with either the first Schottky contact metal layer or the second Schottky contact metal layer.

2. The silicon carbide MOSFET device with integrated SBD according to claim 1, characterized in that, The cellular structure also includes a gate oxide layer located on the N-epitaxial layer; The gate oxide layer is located between the first portion of the first ohmic contact metal layer and the second Schottky contact metal layer; A polycrystalline silicon gate electrode is formed on the gate oxide layer, and the outer periphery of the polycrystalline silicon gate electrode is covered with an interlayer dielectric. The gate oxide layer covers the surface of the P-well region, and the two sides of the gate oxide layer respectively cover a portion of the surface of the N+ region and a portion of the surface of the junction field-effect region.

3. The silicon carbide MOSFET device with integrated SBD according to claim 2, characterized in that, The cell structure also includes a source and a drain; The source electrode covers the interlayer dielectric, the first ohmic contact metal layer, the first Schottky contact metal layer, the second ohmic contact metal layer, and the second Schottky contact metal layer; The drain is located on the side of the substrate away from the N-epitaxial layer.

4. The silicon carbide MOSFET device with integrated SBD according to claim 1, characterized in that, The depth of the junction field-effect groove corresponding to the junction field-effect region is 0.25μm~0.35μm.

5. The silicon carbide MOSFET device with integrated SBD according to claim 1, characterized in that, The depth of the source trench corresponding to the source trench region is 0.25μm~0.35μm.

6. The silicon carbide MOSFET device with integrated SBD according to claim 1, characterized in that, The depth of the N+ region is 0.3 μm to 0.4 μm; The depth of the P-well region is 1.0 μm to 1.5 μm.

7. The silicon carbide MOSFET device with integrated SBD according to claim 1, characterized in that, The depth of the P+ region of the junction field-effect region is 1.0 μm to 1.6 μm.

8. The silicon carbide MOSFET device with integrated SBD according to claim 1, characterized in that, The depth of the P+ region in the source trench is 1.0 μm to 1.6 μm.

9. A method for fabricating a silicon carbide MOSFET device with integrated SBD, characterized in that, include: An N-epitaxial layer is formed on the substrate; On the side of the N-epitaxial layer away from the substrate, an oxide layer is deposited, and a P-well implantation window is formed by photolithography and etching. The oxide layer is used as an ion implantation mask, and Al ions are implanted to form the P-well region. On the side of the N- epitaxial layer away from the substrate, an oxide layer is deposited again, and an oxide layer sidewall is formed by reverse etching; using the oxide layer sidewall as an ion implantation mask, N ions are implanted to form an N+ region; On the side of the N-epitaxial layer away from the substrate, an oxide layer is deposited again. The etching windows for the source trench and the junction field-effect trench are formed by photolithography and etching. The oxide layer is used as a barrier layer to perform SiC dielectric etching, and the source trench and the junction field-effect trench are formed on the surface of the N-epitaxial layer. The junction field-effect trench is subjected to oxide deposition, photolithography, and etching, with the central region of the junction field-effect trench covered by the oxide layer to form an implantation barrier layer. Al ions are implanted into the source trench to form the P+ region of the source trench region, and Al ions are implanted into the junction field-effect trench to form the P+ region of the junction field-effect region. The P+ regions of the junction field-effect region and the P+ regions of the source trench region are formed using a simultaneous process. The depth of the P+ region of the junction field-effect region is the same as the depth of the P+ region of the source trench region. Remove all oxide layers on the N-epitaxial layer and perform an activation annealing process at a first preset temperature to activate the implanted Al and N ions; A gate oxide layer is formed on the P-well region, a polysilicon gate electrode is formed on the gate oxide layer, an interlayer dielectric is deposited on the polysilicon gate electrode, and ohmic contact holes are formed by etching to expose the P+ region of the junction field-effect region, the P+ region of the source trench region, and the N+ region. A nitride layer is deposited, and the non-ohmic alloy region in the junction field-effect trench is covered and protected by photolithography and etching. Metal is deposited on the side of the N-epitaxial layer away from the substrate, and an annealing process is performed at a second preset temperature to form a first ohmic contact metal layer in the P+ region of the source trench region and a second ohmic contact metal layer in the P+ region of the junction field-effect region. The nitride layer is removed by etching, and metal is deposited again. The annealing process is carried out in the third preset temperature environment to form the first Schottky contact metal layer and the second Schottky contact metal layer in the P+ region of the junction field effect region. The second ohmic contact metal layer is used to block the connection between the first Schottky contact metal layer and the second Schottky contact metal layer; the P+ region of the junction field-effect region is in contact with the second ohmic contact metal layer, and the P+ region of the junction field-effect region is not in contact with either the first Schottky contact metal layer or the second Schottky contact metal layer.

10. The method for fabricating a silicon carbide MOSFET device with integrated SBD according to claim 9, characterized in that, Also includes: Metal is deposited on the side of the N-epitaxial layer away from the substrate to form a source, and metal is deposited on the side of the substrate away from the N-epitaxial layer to form a drain.

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