Nanowire / sheet devices with alternative sidewalls, fabrication methods, and electronic devices

Abstract

A nanowire / sheet device, a method for manufacturing the same, and an electronic device including such a nanowire / sheet device are disclosed. According to an embodiment, the nanowire / sheet device may include: a substrate; nanowires / sheets spaced apart from the surface of the substrate and extending along a first direction; source / drain layers located at opposite ends of the nanowires / sheets in the first direction and in contact with the nanowires / sheets; a gate stack extending along a second direction intersecting the first direction to surround the nanowires / sheets; and a first sidewall disposed on the sidewall of the gate stack, wherein the first sidewall comprises a continuously extending material layer having a first portion along the surface of the nanowire / sheet, a second portion along the source / drain layers facing the sidewall of the gate stack, and a third portion along the sidewall of the gate stack facing the source / drain layers, with a gap or interface between the second and third portions.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductors, and more particularly, to a nanowire / sheet device with a replacement sidewall and a method of manufacturing the same, and an electronic device including the same. BACKGROUND

[0002] Nanowire or nanosheet (hereinafter, simply referred to as "nanowire / sheet") devices, particularly, nanowire / sheet based gate-all-around (GAA) metal-oxide-semiconductor field-effect transistors (MOSFETs), can well control short channel effects and enable further scaling of devices. In addition, it is desirable to epitaxially grow source / drain, for example, to increase the source / drain to facilitate making contacts to the source / drain, or to implement stress engineering, etc. However, as the scaling continues, it is difficult to grow high quality source / drain. SUMMARY

[0003] In view of the above, it is at least in part an object of the present disclosure to provide a nanowire / sheet device with improved performance and a method of manufacturing the same, and an electronic device including the same.

[0004] According to an aspect of the present disclosure, there is provided a nanowire / sheet device, including: a substrate; a nanowire / sheet spaced apart from a surface of the substrate and extending in a first direction; source / drain layers located at opposite ends of the nanowire / sheet in the first direction and in contact with the nanowire / sheet; a gate stack extending in a second direction intersecting the first direction to surround the nanowire / sheet; and a first sidewall disposed on a sidewall of the gate stack, wherein the first sidewall includes a continuously extending material layer having a first portion along a surface of the nanowire / sheet, a second portion along a sidewall of the gate stack facing the source / drain layers, and a third portion along a sidewall of the source / drain layers facing the gate stack, with a gap or an interface between the second portion and the third portion.

[0005] According to another aspect of the present disclosure, there is provided a method of manufacturing a nanowire / sheet device, including: disposing a nanowire / sheet spaced apart from a surface of a substrate and extending in a first direction on the substrate; forming a dummy gate extending in a second direction intersecting the first direction and surrounding the nanowire / sheet on the substrate, with a first sidewall formed on a sidewall of the dummy gate; growing source / drain layers at opposite ends of the nanowire / sheet in the first direction; replacing the first sidewall with a second sidewall in the presence of the source / drain layers and at least part of the dummy gate; and forming a gate stack inside the second sidewall, wherein the second sidewall includes a continuously extending material layer having a first portion along a surface of the nanowire / sheet, a second portion along a sidewall of the gate stack facing the source / drain layers, and a third portion along a sidewall of the source / drain layers facing the gate stack, with a gap or an interface between the second portion and the third portion.

[0006] According to another aspect of the present disclosure, there is provided an electronic device comprising the nanowire / sheet device described above.

[0007] According to embodiments of the present disclosure, an alternative spacers process is employed. A first spacer can be initially formed that is conducive to crystal growth to facilitate growth of a high crystal quality source / drain layer. Subsequently, the first spacer can be replaced with a second spacer. Advantageously, the second spacer can have a low dielectric constant, for example to reduce parasitic capacitance. BRIEF DESCRIPTION OF DRAWINGS

[0008] The above and other objects, features and advantages of the present disclosure will be more apparent from the following description in conjunction with the accompanying drawings, in which:

[0009] Figures 1 to 21(b) Some stages in a flow of manufacturing a nanowire / sheet device according to embodiments of the present disclosure are schematically illustrated;

[0010] Figures 22(a) to 23 Source / drain growth according to a comparative example is schematically illustrated;

[0011] Figures 24(a) to 31 Some stages in a flow of manufacturing a nanowire / sheet device according to another embodiment of the present disclosure are schematically illustrated;

[0012] Figure 32 A nanowire / sheet device according to another embodiment of the present disclosure is schematically illustrated,

[0013] wherein,

[0014] Figure 2(a) , 2(b) , 5(a), 6(a), 16(a), 17(a), 20(a), 24(a), 25(a) are top views, the positions of the AA' line and the BB' line are shown in Fig. 2(a), the position of the CC' line is shown in 20(a), the positions of the DD' line and the EE' line are shown in 24(a),

[0015] Figure 1 , 3(a) , 4(a), 5(b), 6(b), 7, 8, 9(a), 10(a), 10(b), 11(a), 12(a), 13(a), 14(a), 15(a), 16(b), 17(b), 18, 19, 20(b), 21(a), 22(a), 23, 24(b), 25(b), 26(a), 27 to 32 are cross-sectional views along the AA' line,

[0016] Figure 3(b) , 4(b)Fig. 9(b) is a cross-sectional view along the line BB' of Fig. 9(a),

[0017] Fig. 20(c) is a cross-sectional view along the line CC' of Fig. 20(b),

[0018] Fig. 25(c) is a cross-sectional view along the line DD' of Fig. 25(b),

[0019] Figure 25(d) 26(c) Fig. 26(c) is a cross-sectional view along the line EE' of Fig. 26(b),

[0020] Figure 9(c) 22(b) Fig. 26(d) is a cross-sectional view taken along a sidewall of the sidewall. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it is to be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0022] Various structural diagrams according to embodiments of the present disclosure are illustrated in the accompanying drawings. These diagrams are not drawn to scale in which certain details are exaggerated for clarity of presentation and can omit certain details for the same reason. The shapes of various regions, layers, and relative sizes and positional relationships among them shown in the drawings are only exemplary and can be varied as actual desired. A person skilled in the art can additionally design regions / layers having different shapes, sizes, and relative positions to those shown as actual desired. In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or there can be an intervening layer / element therebetween. Also, if a layer / element is on another layer / element in one orientation, it can be under the other layer / element in the reversed orientation when the orientation is reversed.

[0023] ​​According to embodiments of the present disclosure, a nanowire / sheet device is provided. Specifically, the device can include one or more nanowires or nanosheets to serve as a channel. The nanowires / sheets can be suspended with respect to a substrate and can extend substantially parallel to a surface of the substrate. The nanowires / sheets are aligned in a vertical direction (e.g., a direction substantially perpendicular to the surface of the substrate). The nanowires / sheets can extend in a first direction, and opposite ends in the first direction can be connected to source / drain layers. The source / drain layers can include a different semiconductor material than the nanowires / sheets in order to enable stress engineering. Additionally, a gate stack can extend in a second direction that intersects (e.g., is perpendicular to) the first direction to intersect the nanowires / sheets and thus can surround a periphery of the nanowires / sheets, forming a gate-all-around (GAA) structure.

[0024] A sidewall can be formed on a sidewall of the gate stack. The sidewall can isolate the gate stack from the source / drain layers. As described below, the sidewall can be formed by a replacement sidewall process. In the replacement sidewall process, at least a portion of the sidewall (referred to as a "first portion"), specifically, a portion that overlaps the nanowires / sheets in the vertical direction, can be filled into a confined space. The filling of the confined space can result in a gap (e.g., an air gap) or an interface or a surface, and thus the portion of the sidewall in the confined space can be O-shaped or U-shaped. For example, the first portion of the sidewall can include a continuously extending layer of material having a first portion along a surface of the nanowire / sheet, a second portion along the sidewall of the gate stack facing the source / drain layer, and a third portion along the sidewall of the gate stack facing the source / drain layer, with a gap or an interface between the second portion and the third portion. Due to such a gap, the sidewall can have a reduced dielectric constant, and thus can improve device performance.

[0025] An isolation portion can be provided between the gate stack and the substrate. The isolation portion can be self-aligned to the gate stack and can be substantially aligned with the nanowires / sheets in the vertical direction.

[0026] Such a semiconductor device can be fabricated, for example, as follows. Nanowires / sheets extending in a first direction can be disposed on a substrate with a surface of the substrate spaced apart, and a dummy gate extending in a second direction that intersects (e.g., is perpendicular to) the first direction to surround the nanowires / sheets can be formed. A first sidewall can be formed on a sidewall of the dummy gate. The first sidewall can be replaced with a second sidewall (i.e., a replacement sidewall process) after source / drain layers are grown on opposite ends of the nanowires / sheets in the first direction. In the replacement sidewall process, there is a confined space defined by the dummy gate (at least a portion thereof), the source / drain layers, and the nanowires / sheets. Thus, the second sidewall can have a gap or an interface or a surface due to such a confined space as described above.

[0027] The first side wall can facilitate growth of the source / drain layer. For example, the first side wall can have substantially the same crystal structure as the nanowire / sheet at least in a region adjacent to the nanowire / sheet. Thus, the source / drain layer can grow with the end of the nanowire / sheet in the first direction and the region of the first side wall as seeds. This can help to reduce defects in the source / drain layer and thus improve the crystal quality of the source / drain layer.

[0028] An isolation portion defining layer can be provided on the substrate, and the nanowire / sheet can be provided on the isolation portion defining layer. The isolation portion defining layer can be patterned to be self-aligned to the shape of the nanowire / sheet, which can be achieved by etching the isolation portion defining layer with the nanowire / sheet (or a (hard) mask used to form the nanowire / sheet) as a mask. Thereafter, the self-aligned isolation portion can be formed by replacing the isolation portion defining layer with a dielectric material.

[0029] To provide the nanowire / sheet, one or more gate defining layers and one or more nanowire / sheet defining layers can be alternately provided on the isolation portion defining layer to form a stack. The stack can be patterned to be a preliminary nanowire / sheet extending in the first direction. The preliminary nanowire / sheet can have a length in the first direction greater than a length in the first direction of the nanowire / sheet to be finally formed, so as to form the nanowire / sheet self-aligned to the dummy gate later. In this patterning step, the isolation portion defining layer can also be patterned. Thus, the isolation portion defining layer can be self-aligned to the preliminary nanowire / sheet. At this point, the gate defining layers also have the shape of the nanowire / sheet. To form the fully surrounding gate, another gate defining layer can also be formed and patterned to be a bar extending in the second direction. A first sub-side wall can be formed on the sidewall of the bar-shaped other gate defining layer, which can also be formed on the sidewall of the stack. The preliminary nanowire / sheet below can be patterned with the bar-shaped other gate defining layer and the first sub-side wall as masks. Thus, the bar-shaped other gate defining layer together with the other gate defining layers forms a dummy gate extending in the second direction, the nanowire / sheet defining layers are patterned to be nanowires / sheets self-aligned to the dummy gate, and the nanowire / sheets are surrounded by the dummy gate. In this patterning step, the isolation portion defining layer can also be patterned. Thus, the isolation portion defining layer can be self-aligned to the nanowire / sheet.

[0030] In addition, the gate defining layers can be selectively etched so that the sidewalls thereof are recessed inwardly with respect to the sidewalls of the nanowire / sheet, and a second sub-side wall can be formed in the thus-formed recess. Thus, the second sub-side wall can be self-aligned to the gate defining layers. The first sub-side wall and the second sub-side wall can constitute the above-described first side wall. The second sub-side wall can facilitate growth of the source / drain layer.

[0031] In an alternative sidewall process, another gate-defining layer can be removed to expose the first sub-sidewall, the first sub-sidewall can be removed to expose the end of the second sub-sidewall in the second direction, the second sub-sidewall can be removed, and a second sidewall can be formed. The second sidewall can fill into the space (confined space) where the second sub-sidewall originally was.

[0032] The present disclosure can be presented in various forms, some examples of which will be described below. In the following description, the selection of various materials is involved. The selection of materials is considered in addition to its function (for example, semiconductor material is used to form active region, dielectric material is used to form electrical isolation) and etching selectivity. In the following description, the required etching selectivity can be indicated, or it can not be indicated. Those skilled in the art should understand that when the following refers to etching a certain material layer, if it is not mentioned that other layers are also etched or the figure does not show that other layers are also etched, then such etching can be selective, and the material layer can have etching selectivity with respect to other layers exposed to the same etching formula.

[0033] Figures 1 to 21(b) Some stages in the process of manufacturing nanowire / sheet devices according to embodiments of the present disclosure are schematically shown.

[0034] As shown in Figure 1 A substrate 1001 is provided. The substrate 1001 can be various forms of substrates, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, etc. In the following description, bulk Si substrates are described for convenience of illustration. Here, a silicon wafer is provided as the substrate 1001.

[0035] On the substrate 1001, an isolation portion-defining layer 1003 can be formed to define the position of the isolation portion to be formed later. On the isolation portion-defining layer 1003, an etching stop layer 1005 can be formed. The etching stop layer 1005 can set a stop position when the isolation portion-defining layer 1003 is etched later, especially in the case where the isolation portion-defining layer 1003 and the gate-defining layer (for example, 1007) formed later do not have etching selectivity or have low etching selectivity. Alternatively, in the case where the isolation portion-defining layer 1003 and the gate-defining layer have etching selectivity, the etching stop layer 1005 can be omitted.

[0036] On the etch stop layer 1005, a stack of gate defining layers 1007, 1011, 1015 and nanowire / sheet defining layers 1009, 1013 can be formed in alternating arrangements. The gate defining layers 1007, 1011, 1015 define the positions of the gate stack to be formed subsequently, and the nanowire / sheet defining layers 1009, 1013 define the positions of the nanowires / sheets to be formed subsequently. In this stack, the uppermost layer can be the gate defining layer 1015, such that each nanowire / sheet defining layer 1009, 1013 is covered above and below by the gate defining layer, so as to subsequently form a gate-all-around configuration. In this example, two nanowire / sheet defining layers 1009, 1013 are formed, and thus two nanowires / sheets are formed in the final device. However, this disclosure is not limited to this; the number of nanowire / sheet defining layers to be formed and the number of gate defining layers to be formed can be determined according to the number of nanowires / sheets to be formed (which can be one or more).

[0037] The isolation layer 1003, etch stop layer 1005, gate limiting layers 1007, 1011, 1015, and nanowire / wafer limiting layers 1009, 1013 can be semiconductor layers formed on the substrate 1001 by, for example, epitaxial growth. Thus, the nanowire / wafer limiting layers 1009, 1013 can have good crystal quality and can be a single-crystal structure to subsequently provide single-crystal nanowires / wafers for use as channels. Adjacent semiconductor layers can have etch selectivity so that they can be processed differently subsequently. For example, the etch stop layer 1005 and nanowire / wafer limiting layers 1009, 1013 can include Si, while the isolation layer 1003 and gate limiting layers 1007, 1011, 1015 can include SiGe (the atomic percentage of Ge is, for example, about 10% to 40%, and can be gradually varied to reduce defects). Each semiconductor layer can have a substantially uniform thickness, thus extending substantially parallel to the surface of the substrate 1001. For example, the thickness of the isolation layer 1003 can be about 30 nm to 80 nm, the thickness of the etch stop layer 1005 can be about 3 nm to 15 nm, the thickness of the gate limiting layers 1007, 1011, and 1015 can be about 20 nm to 40 nm, and the thickness of the nanowire / sheet limiting layers 1009 and 1013 can be about 5 nm to 15 nm.

[0038] Next, nanowires / sheets can be patterned. For example, such as... Figure 2(a) and 2(b)As shown, photoresist 1017a or 1017b can be formed on the above stack, and the photoresist 1017a or 1017b can be patterned into nanowires (Fig. 2(a)) or nanosheets (Fig. 2(b)) by photolithography. In the case of nanosheets, the width W of the nanosheet can determine the device width that provides current to the device. In the following description, the case of nanowires is mainly used as an example, but these descriptions are equally applicable to the case of nanosheets. Then, as Figure 3(a) and 3(b) As shown, photoresist 1017a or 1017 can be used as an etching mask, and each layer on substrate 1001 can be selectively etched sequentially by reactive ion etching (RIE) in the vertical direction, for example, until the etching stops at substrate 1001. In this way, each layer on substrate 1001 is patterned into prepared nanowires or nanosheets corresponding to photoresist 1017a or 1017b. Here, the length of the prepared nanowires / sheets (vertical dimension, i.e., the length in the horizontal direction under the orientation of FIG. 3(a)) can be greater than the length of the nanowires / sheets to be formed as channels, in order to subsequently obtain nanowires / sheets self-aligned with the dummy gate (gate stack) for use as channels. Afterwards, photoresist 1017a or 1017b can be removed.

[0039] For electrical isolation purposes, such as Figure 4(a) and 4(b) As shown, an isolation portion 1019, such as shallow trench isolation (STI), can be formed on the substrate 1001. For example, the STI 1019 can be formed by depositing an oxide (e.g., silicon oxide) on the substrate, planarizing the deposited oxide by a process such as chemical mechanical polishing (CMP), and then etching back the planarized oxide by a process such as wet etching, vapor phase etching, or dry etching. Additionally, on the surface of the substrate 1001 where semiconductor layers have been patterned as a stack of nanowires / sheets, a thin etch stop layer 1019' (e.g., with a thickness of about 1 nm to 5 nm) can be formed by deposition, for example. Here, the etch stop layer 1019' can also include oxide and is therefore shown as a thin layer integral with the STI 1019.

[0040] As described above, gate limiting layers 1007, 1011, and 1015 are located above and below nanowire / sheet limiting layers 1009 and 1013, respectively. To form a fully encircling gate, another gate limiting layer can also be formed on the left and right sides in the orientation shown in Figure 4(b). For example, as Figure 5(a) and 5(b)As shown, a gate defining layer 1021 can be formed on STI 1019 and etch stop layer 1019'. For example, gate defining layer 1021 can be formed by depositing a material that is substantially the same or similar to the previous gate defining layers 1007, 1011, and 1015 (thus having substantially the same or similar etch selectivity for processing together), and planarizing the deposited material using a process such as CMP. In this example, gate defining layer 1021 may comprise SiGe with a Ge atomic percentage substantially the same or similar to that of gate defining layers 1007, 1011, and 1015.

[0041] On the gate defining layer 1021, a hard mask layer 1023 can be formed, for example, by deposition, to facilitate patterning. For example, the hard mask layer 1023 may include silicon carbide with a thickness of about 100 nm – 250 nm.

[0042] The gate defining layer 1021 (and 1007, 1011, 1015) can be patterned as a pseudo-gate extending along a direction intersecting, for example, perpendicular to, the extension direction of the prepared nanowire / wafer (referred to as the "first direction," e.g., the horizontal direction in Figures 5(a) and 5(b)) (referred to as the "second direction," e.g., the vertical direction in Figure 5(a), and the direction perpendicular to the plane of the paper in Figure 5(b)). For example, photoresist 1025 can be formed on the hard mask layer 1023 and patterned into stripes extending along the second direction by photolithography. Then, using the photoresist 1025 as an etching mask, the hard mask layer 1023 and the gate defining layer 1021 can be selectively etched by, for example, RIE, with the etching stopping at the etch stop layer 1019'. Afterward, the photoresist 1025 can be removed.

[0043] In conventional techniques, after patterning the gate defining layer 1021, the lower gate defining layers 1007, 1011, and 1015 are patterned using photoresist 1025 as an etching mask, thus forming a dummy gate together (and therefore the nanowire / wafer defining layers 1009 and 1013 can also be patterned in the same way to form nanowires / wafers, and the etch stop layer 1005 and the isolation defining layer 1003 can also be patterned in the same way). Selective etching can be used to make the gate defining layers 1007, 1011, 1015, and 1021 (and the isolation defining layer 1003) laterally recessed, forming sidewalls 1027a of dielectric material self-aligned to both sides of the dummy gate within the recesses, thereby defining the space for forming the gate stack, such as... Figure 22(a) and 22(b)As shown. However, this can cause problems during the subsequent growth of the source / drain layer. As shown in Figure 22(b), the sidewall 1027a extends continuously with openings through which nanowires / sheets 1009, 1013 (and the etch stop layer 1005) can be exposed. Due to the presence of the dielectric sidewall 1027a (which is generally not a good crystal growth seed), the nanowires / sheets 1009, 1013 (and the etch stop layer 1005, substrate 1001) acting as crystal growth seeds form discrete growth points. Thus, the grown source / drain layer (see Figure 22(b)) becomes a discrete growth point. Figure 23 In section 1033a), there may be numerous defects, such as dislocations or interfaces. For example, crystals grown from different seeds (exposed sidewalls of nanowires / sheets 1009 and 1013, exposed sidewalls of etch stop layer 1005, and exposed surface of substrate 1001) may converge to form interfaces, such as... Figure 23 The dashed lines in the diagram illustrate this.

[0044] According to embodiments of this disclosure, at least a portion of the sidewalls formed prior to the growth of the source / drain layers can have the same or substantially the same crystal structure as the nanowire / sheet defining layers 1009, 1013, thereby facilitating crystal growth. This portion of the sidewalls can form a substantially consistent and continuous crystal growth surface with at least a portion of the sidewalls of the nanowire / sheet defining layers 1009, 1013 (and the sidewalls of the etch stop layer 1005, since growth also occurs on its sidewalls).

[0045] According to embodiments of this disclosure, the sidewalls can be formed in stages. The advantages of forming the sidewalls in stages will be specifically described below in conjunction with subsequent processes. Of course, this disclosure is not limited thereto, and the sidewalls can also be formed in such a manner. Figure 22(a) and 22(b) The difference in the primary formation is that the sidewalls can have the same or substantially the same crystal structure as the nanowire / sheet-defined layers 1009 and 1013, which is conducive to crystal growth.

[0046] For example, such as Figure 6(a) and 6(b) As shown, a first sub-sidewall 1027 can be formed on the sidewalls of a gate defining layer 1021 patterned as a strip extending along a second direction. Various methods exist in the art for forming sidewalls. For example, a sidewall material layer, such as a nitride (e.g., silicon nitride) with a thickness of about 3 nm to 15 nm, can be deposited in a generally conformal manner, and the lateral extensions of the sidewall material layer can be removed by, for example, a vertical RIE, leaving its vertical extensions, thereby forming the sidewall. Here, the etch-back depth can be controlled so that the first sub-sidewall 1027 is also formed on the sidewalls of the semiconductor layer stack, which helps guide the growth of the source / drain layers. Figure 22(a) and22(b) In the case shown, it is impossible to form the first sub-sidewall for this type of guided source / drain layer growth.

[0047] After the first sub-sidewall 1027 is formed, it can be similar to Figure 22(a) and 22(b) A second sub-sidewall is formed on the sidewalls of the gate limiting layers 1007, 1011, and 1015.

[0048] For example, such as Figure 7 As shown, the hard mask layer 1023 and the first sub-sidewall 1027 can be used as etching masks to selectively etch the etch stop layer 1019' and each layer in the semiconductor layer stack, such as RIE. The etching can stop at the substrate 1001 (or there can be some over-etching). As a result, the nanowire / sheet defining layers 1009 and 1013 are formed into nanowires or nanosheets that can subsequently be used to provide channels (hereinafter, the nanowire / sheet defining layers 1009 and 1013 are referred to as nanowires / sheets 1009 and 1013), and are surrounded by gate defining layers 1007, 1011, 1015, and 1021 (together forming a "dummy gate"). The nanowires / sheets 1009 and 1013 can be self-aligned to the dummy gate.

[0049] To ensure that the gate lengths above and below nanowires / sheets 1009 and 1013 are identical, a self-alignment technique can be used to form the second sub-sidewall. For example, as... Figure 8 As shown, the gate defining layers 1007, 1011, and 1015 (in this example, SiGe) can be selectively etched relative to the nanowires / sheets 1009 and 1013 (Si in this example), such that their sidewalls are recessed inward to a certain depth in the lateral direction relative to the sidewalls of the nanowires / sheets 1009 and 1013. Preferably, the recessed depths of the gate defining layers 1007, 1011, and 1015 are substantially the same, and the recessed depths on both the left and right sides are substantially the same (and can be substantially equal to the thickness of the first sidewall 1027). For example, atomic layer etching (ALE) can be used to achieve good etching control. In this example, the isolation defining layer 1003 is also SiGe, so it can also be recessed to substantially the same depth. Thus, after etching, the corresponding sidewalls of the gate defining layers 1007, 1011, and 1015 (and the isolation defining layer 1003, and even the gate defining layer 1021) can be substantially coplanar.

[0050] A second sub-sidewall can be formed within this recess. For example... Figure 9(a) , 9(b)As shown in 9(c), a semiconductor material layer with a thickness sufficient to fill the aforementioned recess (e.g., about 3 nm to 15 nm) can be formed, for example, by epitaxial growth. This semiconductor material layer can be retained in the recess by, for example, a vertically oriented RIE, thereby forming the second sub-sidewall 1027'. The second sub-sidewall 1027', together with the first sub-sidewall 1027, defines a space for gate stacking. The outer sidewall of the second sub-sidewall 1027' can be substantially coplanar with the outer sidewall of the first sub-sidewall 1027 (and the sidewalls of the nanowires / sheets 1009, 1013), and the inner sidewall of the second sub-sidewall 1027' can be substantially flat (thus defining substantially the same gate length above and below the nanowires / sheets 1009, 1013). The second sub-sidewall 1027' can comprise a material having substantially the same crystal structure as the nanowires / sheets 1009, 1013, such as SiGe. Considering etching selectivity, the Ge content of SiGe in the second sub-sidewall 1027' is higher than the Ge content of SiGe in the gate limiting layers 1007, 1011, 1015, and 1021, for example, by approximately 20% to 60% atomically. Figure 9(a) and 9(c) As shown, on opposite sides in the first direction, substantially continuous and substantially consistent crystal growth surfaces (the outer wall of the second sub-sidewall 1027' + the sidewalls of nanowires / sheets 1009 and 1013) can be formed, rather than some discrete growth points as shown in Figure 22(b).

[0051] Here, a second sub-sidewall 1027' that is conducive to crystal growth is formed by epitaxial growth of semiconductor material. Considering that the nanowires / sheets 1009, 1013 and the gate limiting layers 1007, 1011, 1015 (as well as the isolation limiting layer 1003 and the etch stop layer 1005) are all semiconductor materials and can be formed by epitaxial growth, it helps to form a substantially consistent crystal structure.

[0052] According to other embodiments of this disclosure, a non-semiconductor material, such as a dielectric material, can be used to form the second sub-sidewall 1027'. Unlike dielectric materials used for conventional sidewalls, such as oxides, nitrides, oxynitrides, etc., the dielectric material used for the second sub-sidewall 1027' here can have a substantially identical crystal structure to the nanowires / sheets 1009, 1013, and can be filled in the recess by epitaxial growth or deposition followed by RIE. The second sub-sidewall 1027' can form a eutectic with the nanowires / sheets 1009, 1013 or the subsequently formed source / drain layer. For example, the second sub-sidewall 1027' can include a single-crystal dielectric material having a lattice matching capability with the nanowires / sheets 1009, 1013, such as oxides or nitrides of materials such as strontium (Sr), titanium (Ti), lanthanum (La), aluminum (Al), neodymium (Nd), lutetium (Lu), gadolinium (Gd), or combinations thereof. For example, the second sub-sidewall 1027' may include at least one of SrTiO3, LaAlO3, NdAlO3, GdAlO3, etc. According to embodiments, the lattice constant of the second sub-sidewall 1027' without strain deviates from the lattice constant of the nanowires / sheets 1009 and 1013 without strain within ±2%. The description of the crystal structure and lattice constant also applies to cases where the second sub-sidewall 1027' comprises a semiconductor material.

[0053] As shown in Figure 10(a), the outer wall of the second sub-sidewall 1027' and the exposed sidewalls of the nanowires / sheets 1009, 1013 (and the etch stop layer 1005) (and the surface of the exposed substrate 1001) can be used as seeds to form a source / drain layer 1033 by, for example, selective epitaxial growth. As described above, the first sub-sidewall 1027 can guide the growth of the source / drain layer 1033. The source / drain layer 1033 can be formed to be in contact with the exposed sidewalls of all nanowires / sheets 1009, 1013. The source / drain layer 1033 can include various suitable semiconductor materials. To enhance device performance, the source / drain layer 1033 can contain a semiconductor material with a lattice constant different from that of the nanowires / sheets to apply stress to the nanowires / sheets in which the channel region will be formed. For example, for n-type devices, the source / drain layer 1033 may comprise Si:C (with a C atomic percentage of, for example, about 0.1% to 3%) to apply tensile stress; for p-type devices, the source / drain layer 1033 may comprise SiGe (with a Ge atomic percentage of, for example, about 20% to 80%) to apply compressive stress. Additionally, the source / drain layer 1033 may be doped to the desired conductivity type (n-type doping for n-type devices and p-type doping for p-type devices) by, for example, in-situ doping or ion implantation.

[0054] Due to the presence of continuously extending and substantially uniform crystal growth surfaces as shown in Figure 9(c), the grown source / drain layer 1033 can have good crystal quality, with little or no crystal density compared to…Figure 23 (As shown in the diagram) Crystal defects such as dislocations or interfaces. Additionally, good crystal quality also helps to increase the stress level when stress is applied.

[0055] Additionally, as shown in Figure 9(c), in the second direction, besides the crystal growth surface in the middle, there are first sub-sidewalls 1027 on both sides. This can limit the growth range of the source / drain layer in the second direction, thereby avoiding unnecessary connection between the source / drain layers of adjacent devices in the second direction (to reduce unnecessary etching steps).

[0056] Furthermore, considering the following alternative sidewall processes, in order to better provide an etch stop location when removing the second sub-sidewall 1027' (and the first sub-sidewall 1027) (to avoid affecting the grown source / drain layer 1033), an etch stop layer can be provided on the sidewall of the second sub-sidewall 1027'. For example, if the second sub-sidewall 1027' comprises SiGe and the source / drain layer 1033 also comprises SiGe, a thin layer of Si (with a thickness of, for example, about 2 nm – 5 nm) can be formed on the crystal growth surface first as an etch stop layer by selective epitaxial growth, as shown by the dashed box in Figure 10(a). Of course, if the second sub-sidewall 1027' has high etch selectivity relative to other material layers, especially the source / drain layer 1033, for example, if it comprises the aforementioned dielectric material, then such an etch stop layer may not be formed.

[0057] In the embodiment shown in Figure 10(a), the source / drain layer grown from the sidewall of the nanowire / sheet is connected to the source / drain layer grown from the surface of the substrate 1001. This facilitates heat dissipation or enhances stress in the channel, thereby improving device performance.

[0058] According to another embodiment of this disclosure, as shown in FIG10(b), before growing the source / drain layer 1033, an isolation portion 1019" such as STI can be formed on the substrate 1001 to electrically isolate the subsequently grown source / drain layer 1033 from the substrate 1001 and suppress leakage current. For example, the isolation portion 1019" can be formed by depositing oxide, planarizing the deposited oxide such as CMP, and etching back the planarized oxide.

[0059] The following description will primarily focus on the scenario shown in Figure 10(a), but these descriptions are equally applicable to the scenario shown in Figure 10(b).

[0060] like Figure 11(a) and 11(b)As shown, an interlayer dielectric layer 1035 can be formed on substrate 1001. For example, the interlayer dielectric layer 1035 can be formed by depositing oxide, planarizing the deposited oxide (e.g., CMP), and etching back the planarized oxide. The interlayer dielectric layer 1035 may expose the hard mask layer 1023 but cover the source / drain layer 1033. The interlayer dielectric layer 1035 exposes the area where the dummy gate is located and covers the remaining area, thereby facilitating subsequent replacement sidewall and gate processes.

[0061] Before forming the interlayer dielectric layer 1035, the source / drain layer 1033 may be optionally etched back according to the height of the top surface of the previously grown source / drain layer 1033, in order to, for example, avoid short circuits caused by overgrowth of the source / drain layer 1033.

[0062] Here, considering the formation of the isolation portion below the bottommost gate limiting layer 1007, the isolation portion limiting layer 1003 can be processed first, specifically, replaced with the isolation portion. For this purpose, a processing channel to the isolation portion limiting layer 1003 can be formed.

[0063] For example, the hard mask layer 1023 can be removed by selective etching to expose the gate limiting layer 1021. Selective etching can also reduce the height of the gate limiting layer 1021 so that its top surface is below the top surface of the isolation layer limiting layer 1003, while still maintaining a certain thickness to accommodate the subsequent formation of the mask layer (see [link]). Figure 12(a) and 12(b) The 1037 layer can shield all gate limiting layers 1007, 1011, and 1015 above the top surface of the isolation limiting layer 1003, while exposing the isolation limiting layer 1003. For example, an ALE (Alternating Layer Etching) can be used to better control the etching depth. Here, due to the presence of the etching stop layer 1019', the other gate limiting layers 1007, 1011, and 1015 can remain unaffected.

[0064] Then, as Figure 12(a) and 12(b)As shown, a mask layer, such as photoresist 1037, can be formed on the gate limiting layer 1021. The photoresist 1037 can be patterned into a strip extending along the extension direction of the nanowire / wafer using photolithography, and can mask the nanowire / wafer and the outer surfaces of the gate limiting layers 1007, 1011, and 1015 (with an etch stop layer 1019' sandwiched between them). Due to the presence of the gate limiting layer 1021, a portion of the surface of the isolation limiting layer 1003 is not masked by the photoresist 1037. Subsequently, selective etching can be used to sequentially remove the gate limiting layer 1021, remove a portion of the etch stop layer 1019' exposed by the removal of the gate limiting layer 1021, and remove the isolation limiting layer 1003 exposed by the removal of that portion of the etch stop layer 1019'. Thus, a void is formed below the etch stop layer 1005. Since the isolation layer 1003 and the upper nanowires / wafers and gate limiting layers are defined by the same hard mask layer, the isolation layer 1003 and the upper nanowires / wafers and gate limiting layers are aligned in the vertical direction. Therefore, the gap caused by the removal of the isolation layer 1003 can be self-aligned with the upper nanowires / wafers and gate limiting layers. Afterwards, the photoresist 1037 can be removed.

[0065] Here, when etching the SiGe isolation layer 1003, the second sub-sidewall 1027', which is also SiGe (although with a different Ge concentration), on the sidewall of the isolation layer 1003 can also be removed. The first sub-sidewall 1027 can remain substantially unaffected by etching, thus effectively defining the space for gate stacking. Of course, in this etching step, the second sub-sidewall 1027' can also be largely unaffected or minimally affected, and replaced in a subsequent sidewall replacement process.

[0066] In this example, the etch stop layer 1005 is also a semiconductor material and is connected between the opposing source / drain layers, which results in a leakage path. Therefore, as... Figure 13(a) and 13(b) As shown, the etch stop layer 1005 can be removed by selective etching, such as wet etching using TMAH solution or ALE. In this example, both the etch stop layer 1005 and the substrate 1001 comprise silicon, so a portion of the substrate 1001 can also be etched away. Thus, the gap between the bottommost gate limiting layer 1007 and the substrate 1001 can be increased, but it can still maintain substantial alignment with the nanowires / wafers and the gate limiting layer above. Furthermore, Figure 13(a) also shows the expansion of the gap to both sides, which is, for example, due to etching of the etch stop layer as described above (see the dashed box in Figure 10(a)) or over-etching of the source / drain layer 1033.

[0067] like Figure 14(a) and 14(b)As shown, a dielectric material, such as a low-k dielectric material, can be filled into the voids thus formed to form the isolation portion 1039. Considering etching selectivity (e.g., relative to the interlayer dielectric layer 1035, STI 1019, first sub-sidewall 1027, second sub-sidewall 1027', etc.), the isolation portion 1039 may include oxide nitride (e.g., silicon oxynitride). For example, the isolation portion 1039 can be formed by depositing sufficient oxide nitride on the substrate 1001 and etching back the oxide nitride deposited as in RIE. The isolation portion 1039 thus formed can be self-aligned with the respective nanowires / sheets and gate defining layers above. As shown in FIG14(b), the isolation portion 1039 is connected to the STI 1019 in a second direction.

[0068] According to another embodiment, such as Figure 15(a) and 15(b) As shown, when depositing dielectric material, due to the limited space of the aforementioned voids, the isolation portion 1039' can form a hollow structure. In this case, the dielectric constant of the isolation portion 1039' can be further reduced.

[0069] Next, alternative sidewall construction methods can be implemented.

[0070] like Figure 16(a) , 16(b) As shown in Figure 16(c), the thin etch stop layer 1019' can be removed by selective etching to expose the underlying gate defining layer. Here, in the top view, for illustrative purposes only, the relatively protruding portion of the isolation portion 1039 is not shown (see Figure 16(c), where the isolation portion 1039 protrudes relatively on the left and right sides). Then, as... Figure 17(a) and 17(b) As shown, the first sub-sidewall 1027 can be removed by selective etching. Here, ALD can be used to achieve good etching control to minimize the erosion of the first sub-sidewall 1027 beneath the interlayer dielectric layer 1035.

[0071] Next, as Figure 18 As shown, the residual etch stop layer 1019' can be removed by selective etching, such as RIE, to expose the second sub-sidewall 1027' (the sidewall in the second direction). In cases where the gate defining layers 1007, 1011, 1015 and the source / drain layer 1033 also comprise SiGe as the second sub-sidewall 1027', they can exhibit etching selectivity due to, for example, differences in Ge concentration (or, Ge atomic percentage). The second sub-sidewall 1027' can then be removed by selective etching, such as wet etching. In the presence of the etch stop layer as described above (see...), Figure 10(a) , 10(b)In the case of the dashed box in the figure, etching can stop at the etching stop layer. Thus, space is left between the gate limiting layers 1007, 1011, 1015 and the source / drain layer 1033 for the sidewalls.

[0072] Sidewalls can be formed using sidewall forming processes. For example, such as... Figure 19 As shown, a dielectric layer 1037 can be formed in a generally conformal manner by deposition. Considering etching selectivity (e.g., relative to the interlayer dielectric layer 1035, STI 1019, and the oxynitride isolation portion 1039 of oxides), the dielectric layer 1037 may include nitrides. The dielectric layer 1037 fills the gaps between the gate defining layers 1007, 1011, 1015 and the source / drain layer 1033, thereby self-aligning with each gate defining layer. These gaps are small, so the dielectric layer 1037 may form gaps, interfaces, or surfaces internally as it fills these gaps. Due to such gaps, interfaces, or surfaces, the dielectric layer may locally (around the gaps, interfaces, or surfaces) be O-shaped or U-shaped. Specifically, deposition can begin at each surface, with the material layers deposited on each surface approaching each other as the deposition thickness increases. Gaps, interfaces, or surfaces can be formed between the surfaces of the material layers that are close to each other (not necessarily fully converged due to the confined space). Then, as... Figure 20(a) , 20(b) As shown in 20(c), the deposited dielectric layer 1037 can be selectively etched, such as by a vertical RIE, to remove a portion of the dielectric layer 1037 on the top surface of the interlayer dielectric layer 1035, thereby forming a sidewall, which is still referred to as 1037 here.

[0073] More specifically, the sidewall 1037 may include a first portion overlapping the nanowires / sheets 1009 and 1013 in the vertical direction (which may correspond to the second sub-sidewall 1027' and possibly the portion of the first sub-sidewall 1027 overlapping the nanowires / sheets 1009 and 1013 in the vertical direction, see FIG. 9(c)) and a second and third portion extending from the first portion on opposite sides in the second direction (which may correspond to the portions of the first sub-sidewall 1027 on opposite sides of the semiconductor layer stack in the second direction, see FIG. 9(c)). During formation, the first portion of the sidewall 1037 is prone to forming gaps or air gaps internally because it needs to fill the narrow space defined by the gate defining layer, source / drain layer, and nanowires / sheets, thereby reducing the dielectric constant of the sidewall. In the narrow space, the filling begins from the sidewall of the narrow space. Thus, the material layer of the formed first portion of the sidewall 1037 can take the shape along the sidewall of the narrow space. For example, the first portion of sidewall 1037 may have a first portion along the surface of the nanowire / sheet, a second portion along the source / drain layer facing the dummy gate, a third portion along the dummy gate facing the source / drain layer (e.g., U-shaped), and optionally a fourth portion opposite the first portion (e.g., along the surface of an adjacent nanowire / sheet or along the surface of the isolation portion 1039) and connecting the second and third portions (e.g., O-shaped). Without considering the anisotropy of the dielectric layer filling, the film thickness from each sidewall can be substantially the same; that is, the first, second, and third portions (and the fourth portion) can have substantially uniform film thickness (in the same cross-section perpendicular to the second direction). Furthermore, the second and third portions of sidewall 1037 do not have this narrow space constraint, thus virtually eliminating gaps.

[0074] It should be noted that although the gap is shown as a rectangle in Figure 20(c), the gap may be in other shapes, such as olive-shaped (with a small gap on both sides and a large gap in the middle).

[0075] Next, an alternative gate process can be implemented.

[0076] For example, such as Figure 21(a) and 21(b)As shown, the gate limiting layers can be removed by selective etching. Thus, a gate trench (corresponding to the space originally occupied by each gate limiting layer) is formed inside the sidewall 1037, above the STI 1019 and the isolation portion 1039. In this formed gate trench, the gate dielectric layer 1041 and the gate electrode 1043 can be formed sequentially to obtain the final gate stack. For example, the gate dielectric layer 1041 may include a high-k gate dielectric such as HfO2, with a thickness of approximately 2 nm – 10 nm; the gate electrode 1043 may include a work function adjustment layer such as TiN, TiAlN, TaN, etc., and a gate conductor layer such as W, Co, Ru, etc. Before forming the high-k gate dielectric, an interface layer, such as an oxide formed by an oxidation process or deposition such as atomic layer deposition (ALD), with a thickness of approximately 0.3 nm – 2 nm, can also be formed.

[0077] like Figure 21(a) and 21(b) As shown, the nanowire / sheet device according to the embodiment may include nanowires / sheets 1009, 1013 (the number may be less or more) spaced apart from the substrate 1001 and a gate stack surrounding the nanowires / sheets 1009, 1013, the gate stack including a gate dielectric layer 1041 and a gate electrode 1043.

[0078] Sidewalls 1037 are formed on the sidewalls of the gate stack. The inner sidewalls of the sidewalls 1037 and the gate stack can be substantially coplanar in the vertical direction, thus providing the same gate length. Additionally, the outer sidewalls of the sidewalls 1037 can also be coplanar in the vertical direction, and can be coplanar with the sidewalls of the nanowires / sheets 1009 and 1013. As described above, the sidewalls 1037 can have gaps, interfaces, or surfaces, and therefore can locally have O-shapes or U-shapes.

[0079] The nanowire / sheet device may also include an isolation portion 1039. As described above, the isolation portion 1039 may be self-aligned to the gate stack or nanosheets 1009, 1013. Sidewalls 1037 may not be formed on the sidewalls of the isolation portion 1039.

[0080] In the above embodiments, to improve the growth quality of the source / drain layers, a first sub-sidewall 1027 and a second sub-sidewall 1027' are formed, respectively. However, this disclosure is not limited thereto. For example, it can be combined as described above. Figure 22(a) and 22(b) The pseudo-sidewalls are formed in one step. An alternative sidewall process can be performed after growing the source / drain layers. During sidewall formation, the presence of the source / drain layers and the pseudo-gates creates confined space, which can lead to gaps in the sidewalls, resulting in a reduced dielectric constant. Therefore, although the growth quality of the source / drain layers may not be improved, performance improvement is still achieved.

[0081] According to embodiments of this disclosure, pseudo-gates can also be used to form self-aligned isolation portions, such as shallow trench isolation (STI).

[0082] Figures 24(a) to 31 The illustration schematically depicts some stages in the fabrication process of nanowire / sheet devices according to another embodiment of this disclosure. The following will primarily describe the differences from the embodiments described above; for other processes not described in detail, please refer to the embodiments above.

[0083] As described above Figures 1 to 4(b) The semiconductor layers can be stacked on the substrate 1001 and patterned as pre-formed nanowires / sheets. An isolation portion 1019 can be formed around the pre-formed nanowires / sheets, and an etch stop layer 1019' can be formed on its surface.

[0084] like Figure 24(a) and 24(b) As shown, it can be combined as described above. Figure 5(a) and 5(b) The pseudo-gate is thus patterned. Here, the photoresist 1025 is patterned as a plurality (e.g., three) of stripes spaced apart (which may be substantially equal in spacing) in a first direction and extending along a second direction.

[0085] Next, the process can be carried out according to the above embodiments.

[0086] For example, such as Figures 25(a) to 25(d) As shown, it can be combined as described above. Figure 6(a) and 6(b) The first sub-sidewall 1027 is formed on the sidewall of the strip-shaped gate defining layer 1021. This first sub-sidewall 1027 can also be formed on the (bottom) sidewall of the semiconductor layer stack to guide the growth of the source / drain layer. Then, it can be combined as described above. Figures 7 to 9(c) As described above, a second sub-sidewall 1027' can be formed, such as Figures 26(a) to 26(d) As shown. Similarly, as shown in Figure 26(d), substantially continuous and substantially consistent crystal growth surfaces (outer wall of the second sub-sidewall 1027' + sidewalls of nanowires / sheets 1009, 1013) can be formed on opposite sides in the first direction. Then, as described above... Figure 10(a) and 10(b) As described above, a source / drain layer 1033 can be grown. Figure 27 The illustration shows a situation similar to that in Figure 10(a), but an isolation section can also be formed below the source / drain layer as shown in conjunction with Figure 10(b).

[0087] Here, a pseudo-gate can be used to create a self-aligned isolation section.

[0088] For example, such as Figure 28As shown, an interlayer dielectric layer 1035 can be formed on the substrate 1001. The interlayer dielectric layer 1035 can expose the hard mask layer 1023. Figure 29 As shown, the device area can be masked using photoresist 1051, while exposing the area where the isolation portion needs to be formed (in this example, Figure 29 The rightmost region where the dummy gate is located. In the area exposed by the photoresist 1051, the hard mask layer 1023, the gate defining layers 1021, 1015, 1011, and 1017, the nanowires / wafers 1013 and 1019, the isolation layer 1003 (and the etch stop layers 1019' and 1005) can be removed by selective etching such as RIE. Here, the first sub-sidewall 1027 can also be removed. Thus, a trench corresponding to the dummy gate is formed. Afterwards, the photoresist 1051 can be removed. Figure 30 As shown, a dielectric material such as oxide can be filled into the trench thus formed to form an isolation portion 1053. Here, since both the isolation portion 1053 and the interlayer dielectric layer 1035 comprise oxide, their interface is not shown. However, since they are formed separately, their interface can be observed. Alternatively, the isolation portion 1053 may have a second sub-sidewall 1027', nanowire / sheet residues, etc., on its sidewalls, thus defining the sidewalls of the isolation portion 1053. Alternatively, even if the second sub-sidewall 1027', nanowire / sheet residues, etc., on the trench sidewalls are almost completely removed and difficult to observe due to etching control or other reasons during the trench formation process, the presence of the source / drain layers on both sides of the isolation portion 1053 can still define the sidewalls of the isolation portion 1053.

[0089] Next, the process can be carried out according to the above embodiments, for example, performing a replacement sidewall process and a replacement gate process. When performing the replacement sidewall process, the area where the isolation portion 1053 is located is blocked by the isolation portion 1053, therefore the second sub-sidewall 1057' therein may not be replaced. Thus, the following can be obtained: Figure 31 The nanowire / sheet device shown.

[0090] In this example, the isolation portion 1053 is formed first, followed by the replacement sidewall and replacement gate processes. However, this disclosure is not limited to this. For example, the replacement sidewall and replacement gate processes can be performed first as described in the above embodiment, and then the isolation portion 1053 can be formed (except that during the etching of the trench, the gate defining layer has been replaced with a gate stack). Thus, a result can be obtained as follows: Figure 32 The nanowire / sheet device shown.

[0091] In the above embodiments, the sidewall 1037 is described as a single material layer (e.g., oxide). However, this disclosure is not limited thereto. For example, the sidewall 1037 may comprise a stack of multiple layers (e.g., a nitride layer and an oxide layer). For example, the layers in the stack may be deposited sequentially by an ALD.

[0092] The nanowire / chip devices according to embodiments of this disclosure can be applied to various electronic devices. For example, integrated circuits (ICs) can be formed based on such nanowire / chip devices, and electronic devices can be constructed therefrom. Therefore, this disclosure also provides an electronic device including the above-described nanowire / chip devices. The electronic device may also include components such as a display screen that mates with the integrated circuit and a wireless transceiver that mates with the integrated circuit. Examples of such electronic devices include smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, and power banks.

[0093] According to embodiments of this disclosure, a method for manufacturing a system-on-a-chip (SoC) is also provided. This method may include the methods described above. Specifically, multiple devices may be integrated on the chip, at least some of which are manufactured according to the methods of this disclosure.

[0094] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0095] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A nanowire / sheet device, comprising: a substrate; a nanowire / sheet spaced apart from a surface of the substrate and extending in a first direction; source / drain layers located at opposite ends of the nanowire / sheet in the first direction and interfacing the nanowire / sheet; a gate stack extending in a second direction intersecting the first direction to surround the nanowire / sheet; and a first sidewall disposed on a sidewall of the gate stack, wherein the first sidewall comprises a first portion sidewall overlapping the nanowire / sheet in a vertical direction and second and third portion sidewalls extending from the first portion sidewall on opposite sides of the first portion sidewall in the second direction, the first, second and third portion sidewalls having a continuous layer of material, the first portion sidewall having a first portion along a surface of the nanowire / sheet, a second portion facing a sidewall of the gate stack along the source / drain layers, and a third portion facing a sidewall of the gate stack along the source / drain layers, the second portion having a gap or interface with the third portion. The first portion sidewall further has a fourth portion opposite the first portion and connecting the second and third portions.

2. The nanowire / sheet device of claim 1, wherein, The first, second and third portions have substantially uniform film thickness.

3. The nanowire / sheet device of claim 1, wherein, The first, second, third and fourth portions have substantially uniform film thickness.

4. The nanowire / sheet device of claim 2, wherein, The gap is an air gap.

5. The nanowire / sheet device according to any one of claims 1 to 4, wherein, The source / drain layers have fewer growth defects than if grown separately seeded by the ends of the nanowire / sheet in the first direction.

6. The nanowire / sheet device according to any one of claims 1 to 4, wherein, The source / drain layers are substantially free of growth defects.

7. The nanowire / sheet device of claim 6, wherein, A plurality of the nanowire / sheets are provided, each of the nanowire / sheets extending substantially parallel to each other in the first direction and substantially aligned in the vertical direction, 8. The nanowire / sheet device of any one of claims 1 to 4, wherein, wherein between at least a pair of adjacent nanowire / sheets of the plurality of nanowire / sheets, the source / drain layers have a substantially uniform and continuous crystal surface. The crystal structure of the source / drain layers exhibits a crystal grown from a substantially uniform and continuous crystal surface extending vertically between the plurality of nanowire / sheets.

9. The nanowire / sheet device of claim 8, wherein, 10.The nanowire / sheet device of any one of claims 1 to 4, further comprising: an isolation portion between the gate stack and the substrate, wherein the isolation portion is self-aligned to the gate stack. The first sidewall is not formed between the isolation portion and the source / drain layers.

11. The nanowire / sheet device of claim 10, wherein, The isolation portion is self-aligned to the plurality of nanowire / sheets.

12. The nanowire / sheet device of claim 10, wherein, The isolation portion has a hollow structure.

13. The nanowire / sheet device of claim 10, wherein, 14.The nanowire / sheet device of any one of claims 1 to 4, further comprising: another sidewall on the substrate interfacing the first sidewall, the another sidewall defining a lower portion of the source / drain layers. The space defined by the another sidewall is aligned with the nanowire / sheet in the first direction.

15. The nanowire / sheet device of claim 14, wherein, 16.The nanowire / sheet device of any one of claims 1 to 4, further comprising: a semiconductor layer between the first sidewall and the source / drain layers, the semiconductor layer having etch selectivity with respect to the source / drain layers. ​ 17. The nanowire / sheet device of claim 10, further comprising: a further spacer disposed in at least one of the source / drain layers opposite the nanowire / sheet in the first direction, a bottom surface of the further spacer being lower than a top surface of the spacer; wherein the further spacer extends in the second direction.

18. The nanowire / sheet device of claim 17, further comprising: a second sidewall disposed on a sidewall of the further spacer.

19. The nanowire / sheet device of claim 18, wherein, the first sidewall including a first portion above the nanowire / sheet and a second portion below the nanowire / sheet, the second sidewall including a first portion substantially at a same height as the first portion of the first sidewall and a second portion substantially at a same height as the second portion of the first sidewall.

20. The nanowire / sheet device of claim 19, further comprising: a nanowire / sheet residue between the first portion and the second portion of the second sidewall and abutting the at least one of the source / drain layers.

21. The nanowire / sheet device of claim 20, wherein, the nanowire / sheet residue being substantially coplanar with the nanowire / sheet.

22. The nanowire / sheet device of claim 1, wherein, the first portion, the second portion, and the third portion being U-shaped.

23. The nanowire / sheet device of claim 2, wherein, the first portion, the second portion, the third portion, and the fourth portion being O-shaped.

24. The nanowire / sheet device of any one of claims 1 to 4, wherein, the first sidewall including a plurality of layers in a stack.

25. A method of fabricating a nanowire / sheet device, comprising: disposing a nanowire / sheet on a substrate spaced apart from a surface of the substrate and extending in a first direction; forming a dummy gate on the substrate extending in a second direction intersecting the first direction and surrounding the nanowire / sheet, a first sidewall being formed on a sidewall of the dummy gate; growing source / drain layers on opposite ends of the nanowire / sheet in the first direction with sidewalls of the nanowire / sheet in the first direction and outer sidewalls of the first sidewall as seeds; replacing the first sidewall with a second sidewall in the presence of the source / drain layers and at least part of the dummy gate; and forming a gate stack on an inner side of the second sidewall, wherein the second sidewall includes a first portion sidewall overlapping the nanowire / sheet in a vertical direction and second and third portion sidewalls extending from the first portion sidewall on opposite sides of the first portion sidewall in the second direction, the first, second, and third portion sidewalls having a continuous layer of material, the first portion sidewall having a first portion along a surface of the nanowire / sheet, a second portion along a sidewall of the source / drain layers facing the gate stack, and a third portion along a sidewall of the gate stack facing the source / drain layers, the second portion and the third portion having a gap or interface therebetween. the first portion sidewall further having a fourth portion opposite the first portion and connecting the second portion and the third portion.

26. The method of claim 25, wherein, the first portion, the second portion, and the third portion having substantially uniform film thicknesses.

27. The method of claim 25, wherein, the first portion, the second portion, the third portion, and the fourth portion having substantially uniform film thicknesses.

28. The method of claim 26, wherein, ​ 29. The method of any one of claims 25 to 28, wherein, The first sidewall has substantially the same crystal structure as the nanowire / sheet at least in a region adjacent to the nanowire / sheet.

30. The method of claim 29, wherein, A plurality of the nanowire / sheets are provided on the substrate, the plurality of nanowire / sheets being spaced apart from each other in a vertical direction, The region includes a region overlapping the plurality of nanowire / sheets in the vertical direction.

31. The method of claim 29, wherein, The first sidewall includes a semiconductor material or a dielectric material in the region.

32. The method of claim 31, wherein, The dielectric material includes an oxide or a nitride of strontium, titanium, lanthanum, aluminum, neodymium, lutetium, gadolinium, or a combination thereof.

33. The method of claim 32, wherein, The dielectric material includes at least one of SrTiO3, LaAlO3, NdAlO3, GdAlO3.

34. The method of any one of claims 25 to 28, wherein, Providing the nanowire / sheet includes: forming an isolation portion defining layer on the substrate; forming a stack of a first gate defining layer, a nanowire / sheet defining layer, and a second gate defining layer on the isolation portion defining layer; patterning the stack and the isolation portion defining layer into preliminary nanowire / sheets extending in the first direction; forming a third gate defining layer on the substrate to cover the stack and the isolation portion defining layer; patterning the third gate defining layer into strips extending in the second direction; forming a first sub-sidewall on a sidewall of the third gate defining layer in a strip shape; patterning the stack and the isolation portion defining layer into a line shape or a sheet shape with the third gate defining layer in a strip shape and the first sub-sidewall as masks, wherein the nanowire / sheet defining layer patterned into the line shape or the sheet shape forms the nanowire / sheet, wherein forming the dummy gate includes: selectively etching the first gate defining layer and the second gate defining layer such that sidewalls thereof are recessed inwardly with respect to sidewalls of the nanowire / sheet, wherein the first gate defining layer, the second gate defining layer, and the third gate defining layer together form the dummy gate, The method further includes: growing a second sub-sidewall in the recess with the first gate defining layer and the second gate defining layer as seeds, wherein the first sub-sidewall and the second sub-sidewall together form the first sidewall, wherein the first sidewall is replaced with the second sidewall in the presence of the first gate defining layer and the second gate defining layer and the source / drain layer.

35. The method of claim 34, wherein, The first sub-sidewall is also formed on a sidewall of the stack.

36. The method of claim 34, further comprising: forming an etching stop layer on the isolation portion defining layer, wherein the stack is formed on the etching stop layer, wherein after growing the source / drain layer, the method further includes: removing the isolation portion defining layer from opposite sides of the nanowire / sheet in the second direction by selective etching; removing the etching stop layer by selective etching; and filling a dielectric material in a space resulting from the removal of the isolation portion defining layer and the etching stop layer to form an isolation portion.

37. The method of claim 36, wherein, The isolation portion has a hollow structure.

38. The method of claim 34, wherein, Replacing the first sidewall with the second sidewall includes: removing the third gate defining layer; removing the first sub-sidewall to expose an end portion of the second sub-sidewall in the second direction; removing the second sub-side wall; and forming the second side wall, which fills into the space where the second sub-side wall was originally.

39. The method of claim 34, wherein, The bars include two bars, the method further comprising: forming an isolation after the growth of the source / drain layer at one of the two bars, the isolation self-aligned to the second side wall and passing through the nanowire / sheet.

40. An electronic device comprising the nanowire / sheet device of any one of claims 1 to 24.

41. The electronic device of claim 40, comprising a smartphone, a computer, a tablet, a wearable smart device, an artificial intelligence device, a mobile power supply.

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