A clock phase automatic adjustment circuit for LVDS data reception

Abstract

The present invention provides a clock phase automatic adjustment circuit for LVDS data reception. A multi-phase clock generation module receives a reference clock input from a host computer and divides the reference clock into 32-phase clocks. The 32-phase clocks are output to a clock selection module and a selection signal generation module. The selection signal generation module receives the reference clock and a control mode selection signal from the host computer and generates a clock selection signal. The clock selection module makes a selection based on the inputs of the multi-phase clock generation module and the selection signal generation module and outputs a clock. The present invention reduces the number of iterations required to determine a suitable delay parameter, reduces the size and complexity of the delay circuit, improves timing convergence speed, and can automatically find the appropriate delay parameter, eliminating the need for repeated iterative testing by the user. The circuit structure is simple and avoids the effects of PVT on the output phase.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a clock phase adjustment circuit, which can meet the requirement that an LVDS data transmission module can correctly receive data. Background Art

[0002] As LVDS signal transmission rates increase, the time window occupied by each bit of the signal continues to shrink, resulting in a decrease in the accuracy of the sampling clock sampling the signal within its valid interval. Furthermore, due to differences in transmission paths, the delay time between each data line and the sampling clock reaching the receiving end cannot be guaranteed to be completely consistent, resulting in skew between the clock and data signals. The LVDS delay circuit adjusts the data or clock delay to achieve relative phase alignment of the clock and data, achieving stable and accurate sampling.

[0003] To solve the problem of the LVDS data transmission module being able to correctly receive data, there are several solutions:

[0004] Solution 1: The National Time Service Center applied for a related invention patent in 2019, "An LVDS Delay Circuit with Adaptive Phase Adjustment" (Acceptance Number: 20191127969X), which independently delays all LVDS parallel data lines. This solution has the advantage of finding the optimal delay for all data lines. However, its disadvantages include the use of training codes to confirm the delay of each data bit, which requires the cooperation of the LVDS data transmitter. This has a complex operating mechanism and is significantly affected by external factors. Furthermore, the delay chain circuit lacks a feedback control mechanism, which is affected by PVT (process, voltage, temperature). This can cause significant variations in the delay unit's delay, disrupting the phase matching relationship of the data clock and leading to data sampling errors.

[0005] Solution 2: The invention patent application "A Method for Synchronizing ADC Data and Clock in a High-Speed LVDS Interface" (Application No. 202010336876.9), published by the State Intellectual Property Office in 2020, separates the high and low bits of parallel data to reduce the number of input delay adjustments. This solution has the advantage of being applicable to parallel LVDS data receiving circuits with a large number of data bits. However, its disadvantage is that it uses a fast Fourier transform to calculate the signal-to-noise ratio to determine the delay, resulting in significant data delay and making it unsuitable for systems with high real-time requirements. Summary of the Invention

[0006] To overcome the shortcomings of the prior art, the present invention provides an automatic clock phase adjustment circuit for LVDS data reception. Compatible with external phase selection control mechanisms, it can output a clock signal with a fixed phase difference from a reference clock signal as needed. Its circuit structure is simple and can avoid the effects of PVT on the output phase.

[0007] The technical solution adopted by the present invention to solve its technical problem is:

[0008] A clock phase automatic adjustment circuit for LVDS data reception includes a multi-phase clock generation module, a clock selection module, and a selection signal generation module. The multi-phase clock generation module receives a reference clock input from a host computer, divides the reference clock into 32-phase clocks, and transmits the 32-phase clocks as outputs to the clock selection module and the selection signal generation module respectively. The selection signal generation module receives the reference clock and control mode selection signal from the host computer, and then generates a 5-bit clock selection signal for the 32-phase clock provided by the multi-phase clock generation module. The clock selection module makes a selection based on the inputs of the multi-phase clock generation module and the selection signal generation module, and outputs a clock.

[0009] The multi-phase clock generation module is implemented through a delay phase-locked loop to generate several clock signals with the same phase frequency and equal phase difference. The reference clock signal passes through the phase detector, then passes through the charge pump, and then the output is given to the low-pass filter. Finally, it passes through the voltage-controlled oscillator to output a 32-phase clock. At the same time, the output signal of the voltage-controlled oscillator is fed back to the phase detector, and the reference clock is directly connected to the voltage-controlled oscillator.

[0010] The selection signal generating module compares the phase of the output of the multi-phase clock generating module with the reference clock given by the host computer, and generates a 5-bit clock selection signal according to the control mode selection signal given by the host computer. The selection signal generating module is composed of a sampling multiplexer, a signal comparator, a selection controller, a digital filter, and a mode selector. Its circuit structure is that the sampling multiplexer accepts the 32-phase clock generating module. Figure 3 As shown in the figure. After the 32-phase clock is input to the sampling multiplexer, the output signal is directed to the signal comparator. The signal comparator compares the reference clock with the signal selected by the sampling multiplexer and inputs it to the selection controller. The selection controller inputs the signal selection signal to the sampling multiplexer and the digital filter respectively. After filtering by the digital filter, the signal is input to the mode selector. At the same time, the external control signal and the control mode selection signal are simultaneously connected to the mode selector.

[0011] The clock selection module selects one phase from the multi-phase clock signal output by the multi-phase clock generation module according to the configuration signal input by the external host computer, and selects one phase according to the signal value generated by the selection signal generation module for data sampling processing by the LVDS data receiving module; its circuit is a 32-to-1 multiplexer, which is composed of a 16-level two-to-one MUX circuit, a 2-level eight-to-one circuit and a 2-level transmission gate, which are cascaded in a hierarchical selection signal manner. Figure 4 shown.

[0012] The circuit structure diagram of the subdivision device of the present invention is as follows Figure 5As shown in the figure, after the input clock signal passes through the delay-locked loop (DLL) circuit, it generates 32 clocks with the same frequency and equally spaced phases. The phase difference between two adjacent clocks is 11.25°. The multiplexer selects one of the 32 clocks as the sampling clock based on the sampling clock selector's sampling signal and the control mode selection signal from the host computer. The sampling clock selector outputs the appropriate phase selection signal for the sampling multiplexer. It can be divided into several functional modules: a phase comparator, an up / down counter, a filter, and an alignment multiplexer. The sampling clock selector's selection control code is generated by filtering the output of the up / down counter. The phase comparator compares the phase relationship between the synchronization signal provided by the host computer and the alignment signal generated by phase shifting, and outputs the phase difference between the two signals. The up / down counter converts the phase difference between the synchronization signal and the alignment signal into the selection control code for the alignment multiplexer. The alignment mechanism is such that if the synchronization signal phase leads the alignment clock, the up / down counter decreases the selection control code of the alignment multiplexer, selecting the alignment clock with the leading phase until the alignment clock signal and the synchronization signal are aligned. If the synchronization signal phase lags alignment, the adjustment process is just the opposite. The alignment multiplexer selects different alignment clocks according to different selection control codes, and the alignment clocks are then input into the signal comparator for comparison with the synchronization signal, thus forming a closed-loop feedback control loop.

[0013] The 32-to-1 multiplexer includes a 16-level two-to-one MUX circuit, a 2-level eight-to-one circuit, and a 2-level transmission gate. The 16-level two-to-one MUX circuit is divided into the first 8 levels and the last 8 levels. The internal circuits of the first two are connected in parallel and accept two input clock signals. One of them is selected for output according to the 5-bit clock selection signal output by the selection signal generation module. The transmission gate has the same function as the MUX circuit and also completes the signal selection function. Figure 4 shown.

[0014] The above-mentioned circuit structures can also be represented by other circuits with the same effect. Specifically, the 32-to-1 multiplexer can use the above-mentioned circuit structure, or it can be composed of 16-level two-to-one MUX circuit outputs connected to 8 two-to-one MUX circuit outputs, connected to 4 two-to-one MUX circuit outputs, and then connected to 1 two-to-one MUX. It is connected in a cascade manner, and the selector of each level performs selection step by step according to the clock selection signal.

[0015] The beneficial effects of the present invention are:

[0016] 1) Since the present invention adopts a clock delay method in the circuit generating a multi-phase clock, the number of iterations for determining appropriate delay parameters is reduced, the scale and complexity of the delay circuit are reduced, and the timing convergence speed is improved.

[0017] 2) Since the sampling clock selector of the present invention adopts an adaptive determination circuit structure, it can automatically find the appropriate delay parameter without the need for the user to repeatedly iterate the test.

[0018] 3) The clock phase automatic alignment circuit provided by the present invention can correctly and automatically output a clock signal with a fixed phase difference from a reference synchronization signal. The circuit structure is simple and can avoid the influence of PVT on the output phase. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 1 is a circuit block diagram of the present invention.

[0020] Figure 2 This is a block diagram of the multi-phase clock generation module used in the present invention.

[0021] Figure 3 This is a block diagram of the selection signal generation module used in the present invention.

[0022] Figure 4 This is a block diagram of the clock selection module used in the present invention.

[0023] Figure 5 This is a circuit structure diagram of the present invention.

[0024] Figure 6 This is the charge pump structure diagram.

[0025] Figure 7 This is the low-pass filter circuit diagram.

[0026] Figure 8 This is the simulation waveform. DETAILED DESCRIPTION

[0027] The present invention will be further described below with reference to the accompanying drawings and examples.

[0028] The clock phase automatic adjustment circuit for LVDS data reception provided by the present invention mainly integrates three parts: a multi-phase clock generation module, a clock selection module and a selection signal generation module. Figure 1 shown.

[0029] The multi-phase clock generation module is implemented by a delay phase-locked loop, which is used to generate 32 clock signals with the same frequency and a phase difference of 11.25° between adjacent phases. It consists of a phase detector, a charge pump, a low-pass filter, and a voltage-controlled oscillator. Figure 2 As shown, the phase detector, charge pump, low-pass filter, and voltage-controlled oscillator are universal electronic devices, and their connection relationship is that the signal of the universal reference clock passes through the phase detector, then passes through the charge pump, and then outputs to the low-pass filter, and finally passes through the voltage-controlled oscillator to output a 32-phase clock.

[0030] The clock selection module is implemented by a 32-to-1 multiplexer. According to the input 5-bit configuration signal, one phase of the appropriate clock is selected from the 32-phase clock output by the multi-phase clock generation module for data sampling and processing by the LVDS data receiving module. The circuit of the above-mentioned 32-to-1 multiplexer includes a 16-level two-to-one MUX circuit, a 2-level eight-to-one circuit and a 2-level transmission gate group. The 16-level two-to-one is specifically divided into the first 8 levels and the last 8 levels. The internal circuits of the first two are connected in parallel and accept two input clock signals. One of them is selected for output according to the 5-bit clock selection signal. Its structure is as follows Figure 3 shown.

[0031] The selection signal generating module compares the phase of the output of the multi-phase clock generating module with the reference clock given by the host computer, and generates a 5-bit clock selection signal according to the control mode selection signal given by the host computer. It consists of a sampling multiplexer, a signal comparator, a selection controller, a digital filter, and a mode selector. Its structure is as follows: Figure 4 shown.

[0032] Furthermore, each of the above-mentioned circuit structures can also be represented by other circuits with the same effect. Specifically, the 32-to-1 multiplexer can use the above-mentioned circuit structure, or it can be composed of a 16-level two-to-one MUX circuit output connected to 8 two-to-one MUX circuit outputs, connected to 4 two-to-one MUX circuit outputs, and then connected to 1 two-to-one MUX.

[0033] The clock phase automatic alignment circuit provided by the present invention can correctly and automatically output a clock signal that has a fixed phase difference from a reference synchronization signal. The circuit structure is simple and can avoid the influence of PVT on the output phase.

[0034] Its basic principle is as follows Figure 5As shown in the figure, after the input clock signal passes through the delay-locked loop (DLL) circuit, it generates 32 clocks with the same frequency and equally spaced phases. The phase difference between two adjacent clocks is 11.25°. The multiplexer selects one of the 32 clocks as the sampling clock based on the sampling clock selector's control mode selection signal, which is then passed through the host computer. The sampling clock selector primarily outputs the appropriate phase selection signal for the multiplexer. It can be divided into several functional modules: a phase comparator, an up / down counter, a filter, and an alignment multiplexer. The sampling clock selector's selection control code is generated by filtering the output of the up / down counter. The phase comparator compares the phase relationship between the synchronization signal and the alignment signal and outputs the phase difference between the two signals. The up / down counter converts the phase difference between the synchronization signal and the alignment signal into a selection control code for the alignment multiplexer. The alignment multiplexer selects different alignment clocks based on the selection control code. The alignment clock is then input into the signal comparator for comparison with the synchronization signal, thus forming a closed feedback control loop. If the synchronization signal phase leads the alignment clock, the up-down counter will reduce the selection control code of the alignment multiplexer and select the alignment clock with the leading phase until the alignment clock signal and the synchronization signal phase are consistent. If the synchronization signal phase lags the alignment, the adjustment process is exactly the opposite.

[0035] A working example of this circuit is as follows:

[0036] In an embedded on-chip processor, a multi-phase clock is first generated based on the input reference clock. The reference clock is used to input the phase detector, which transmits the input signal to the charge pump. After passing through a low-pass filter and a voltage-controlled delay line, a 32-phase clock signal with the same frequency and an 11.25° phase difference between adjacent phases is generated. The output results are respectively transmitted to the selection signal generation module and the clock selection module. The phase detector uses an exclusive OR gate (XOR), and its average output is proportional to the phase difference of the input signal. The charge pump uses a bootstrap reference current source as the bias current source of the circuit. Its schematic diagram is shown as follows. Figure 6 The low-pass filter circuit is mainly used to convert the output voltage Vctr of the charge pump into the control voltage Vpbb and Vnbb of the VCDL delay unit. The designed low-pass filter circuit is shown in Figure 7As shown, when Rst = 1, the outputs of all levels of the delay unit are zero. P5 and P7 are the inverted outputs of the 5th and 7th level delay units, so P5 and P7 are both continuously high. P5 and P7 output net1 through a two-input OR gate, so net1 is also high. Net4 is the Q non-output terminal of the D flip-flop DFF1, and net4 is low. Net2 is the Q terminal output of the D flip-flop DFF2. P7 is high, so net2 is also high. Similarly, net3 is also high. Net2 and net3 output net5 through a two-input XOR gate, so net5 is low. Net4 and net5 output low through a two-input AND gate. Therefore, when Rst = 1, the capacitor control circuit outputs a low level. When Rst = 0, the delay unit operates normally. The selection signal generation module is to pass the data input to the selection signal generation module through the sampling multiplexer and transmit the signal to the selection controller. After passing through the digital filter, the mode selector selects the signal according to the external 5-bit wide control signal and transmits it to the clock selection module. The clock selection module transmission channel primarily consists of 16 levels of 2-to-1, 2 levels of 8-to-1, and 2 levels of transmission gates. Control signals are transmitted through a 3-to-8 decoder and two buftree control signals. The 2-to-1 circuit primarily consists of two controllable switches, K1 and K2. When the enable signal, SE, is low, the switches close, outputting Y = A; when SE is high, the switches open. The 8-to-1 circuit primarily consists of eight controllable switches. During normal operation, only one of its eight control signals, S7-S0, should be low, with the other seven high. Otherwise, the output will short-circuit or become unstable. Through this process, the clock output of the embedded on-chip processor can be adaptively adjusted through data delay, and then serves as the clock input signal of the embedded on-chip processor to perform its corresponding function.

[0037] The simulation diagram of this example is as follows Figure 8 As shown in the figure, from top to bottom are the Comiparing Clock, Sampling Clock, and 90°Phase_shift Clock. Because the Comiparing Clock's rising edge is near the analog video signal's amplitude transition, and one Comiparing Clock cycle represents one pixel cycle, the Sapling Clock needs to be sampled in the middle of a pixel cycle. Therefore, optimal sampling is achieved when the Sampling Clock's rising edge is near the Comparing Clock's falling edge. This means that the Sampling Clock's phase needs to lag or exceed the Comparing Clock by 90°. This simulation demonstrates that, in embedded microprocessors, the solution described in this invention can effectively achieve automatic clock adjustment with a simple circuit structure and reduce circuit delay.

[0038] From the above analysis, it can be seen that compared with the traditional applications mentioned in the background technology, the traditional clock delay circuit is large in scale and highly complex, which brings about the problem of slow timing convergence. The circuit of the present invention adopts adaptive data delay, which reduces the scale and complexity of the delay circuit and improves the timing convergence speed.

Claims

1. A clock phase automatic adjustment circuit for LVDS data reception, comprising a multi-phase clock generation module, a clock selection module, and a selection signal generation module, characterized in that: The clock phase automatic adjustment circuit applied to LVDS data reception comprises a multi-phase clock generation module that receives the reference clock input transmitted by the host computer, divides the reference clock into 32-phase clocks, and transmits the 32-phase clocks as output to the clock selection module and the selection signal generation module respectively; the selection signal generation module receives the reference clock and control mode selection signal transmitted by the host computer, and then generates a 5-bit clock selection signal for the 32-phase clock provided by the multi-phase clock generation module; The clock selection module makes a selection based on the inputs of the multi-phase clock generation module and the selection signal generation module, and outputs the clock; After the input clock signal passes through the delay-locked loop circuit, it generates 32 clocks with the same frequency and equal phase difference. The phase difference between each two adjacent clocks is 11.25°. The multiplexer selects the signal according to the control mode of the host computer after sampling by the sampling clock selector, and selects one phase of the 32-phase clock as the sampling clock. The sampling clock selector outputs the appropriate phase selection signal for the sampling multiplexer. The selection control code of the sampling clock selector is generated by the output of the up-down counter after passing through the filter. The phase comparator compares the phase relationship between the synchronization signal provided by the host computer and the alignment signal generated by the phase shift, and outputs the phase difference information of the two signals. The up-down counter converts the phase difference between the synchronization signal and the alignment signal into a selection control code for the alignment multiplexer. If the synchronization signal phase leads the alignment clock, the up-down counter decreases the selection control code for the alignment multiplexer and selects the alignment clock with the leading phase until the alignment clock signal and the synchronization signal phase are consistent. If the synchronization signal phase lags alignment, the adjustment process is just the opposite; the alignment multiplexer selects different alignment clocks according to different selection control codes, and the alignment clocks are then input into the signal comparator for comparison with the synchronization signal, forming a closed-loop feedback control loop.

2. The clock phase automatic adjustment circuit for LVDS data reception according to claim 1, wherein: The multi-phase clock generation module is implemented through a delay phase-locked loop to generate several clock signals with the same phase frequency and equal phase difference. The reference clock signal passes through the phase detector, then passes through the charge pump, and then the output is given to the low-pass filter. Finally, it passes through the voltage-controlled oscillator to output a 32-phase clock. At the same time, the output signal of the voltage-controlled oscillator is fed back to the phase detector, and the reference clock is directly connected to the voltage-controlled oscillator.

3. The clock phase automatic adjustment circuit for LVDS data reception according to claim 1, wherein: The selection signal generating module compares the phase of the output of the multi-phase clock generating module with the reference clock provided by the host computer, and generates a 5-bit clock selection signal according to the control mode selection signal provided by the host computer. The selection signal generating module is composed of a sampling multiplexer, a signal comparator, a selection controller, a digital filter, and a mode selector. After the 32-phase clock is input into the sampling multiplexer, the output signal is input to the signal comparator. The signal comparator compares the reference clock with the signal selected by the sampling multiplexer and inputs it to the selection controller. The selection controller inputs the signal selection signal into the sampling multiplexer and the digital filter respectively. After the digital filter filters the signal, the signal is input into the mode selector. At the same time, the external control signal and the control mode selection signal are simultaneously connected to the mode selector.

4. The clock phase automatic adjustment circuit for LVDS data reception according to claim 1, wherein: The clock selection module selects one phase from the multi-phase clock signal output by the multi-phase clock generation module according to the configuration signal input by the external host computer, and uses the signal value generated by the selection signal generation module for data sampling and processing by the LVDS data receiving module; its circuit is a 32-to-1 multiplexer, which is composed of a 16-level two-to-one MUX circuit, a two-level eight-to-one circuit and a two-level transmission gate, which are cascaded in a hierarchical selection signal manner.

5. The clock phase automatic adjustment circuit for LVDS data reception according to claim 4, characterized in that: The 32-to-1 multiplexer includes a 16-level two-to-one MUX circuit, a two-level eight-to-one circuit, and a two-level transmission gate. The 16-level two-to-one MUX circuit is divided into the first 8 levels and the last 8 levels. The circuits inside the first two levels are connected in parallel and accept two input clock signals. One of the outputs is selected according to the 5-bit clock selection signal output by the selection signal generation module. The transmission gate has the same function as the MUX circuit and also completes the signal selection function.

6. The clock phase automatic adjustment circuit for LVDS data reception according to claim 4, wherein: The 32-to-1 multiplexer adopts a 16-level two-to-one MUX circuit output connected to 8 two-to-one MUX circuits, the 8 two-to-one MUX circuit outputs are connected to 4 two-to-one MUX circuits, and the 4 two-to-one MUX circuit outputs are connected to 1 two-to-one MUX. The connection is cascaded, and the selector of each level performs step-by-step selection according to the clock selection signal.

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