Data selection circuit for analog-to-digital converter

Abstract

The present invention relates to the field of microelectronics, and particularly to a data selection circuit for an analog-to-digital converter, comprising: a control selection unit; a first-stage selection circuit including a plurality of first data selectors connected in parallel, a first input terminal being used for connecting to the quantization output terminal of the analog-to-digital converter, a first control terminal being connected to the control selection unit, and the first data selector being used for selecting the quantization data input from a plurality of first input terminals and outputting the selected quantization data from a first output terminal; a second-stage selection circuit including a plurality of second data selectors connected in parallel, and the second data selector being used for selecting the input data from a plurality of second input terminals and outputting the selected data through a second output terminal. In a state where the analog-to-digital converter fails, the analog-to-digital converter can output quantization data, and the raw data is used to troubleshoot and locate the fault of the analog-to-digital converter without the need to use external devices, and the data selection circuit is simple and effective.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics, and particularly to a data selection circuit for an analog-to-digital converter. Background Art

[0002] An analog-to-digital converter (ADC) converts an analog signal that is continuous in time and amplitude into a digital signal that is discrete in both time and amplitude, including processes such as sampling, quantization, and encoding. When the ADC outputs data, there may be cases where the data is incorrect, and it is necessary to promptly check and locate problems existing inside the ADC.

[0003] When detecting the ADC, since the output of the ADC is encoded data and cannot be used to detect faults existing inside the ADC, an external device needs to be used. Summary of the Invention

[0004] Therefore, the present invention aims to solve the technical problem that an external device needs to be used when troubleshooting and locating faults in an ADC, and thus provides a data selection circuit for an ADC, including: a control selection unit;

[0005] A first-stage selection circuit, including a plurality of first data selectors connected in parallel. The first data selector includes a first output end, a first control end, and a plurality of first input ends. The first input ends are used to be connected to the quantization output end of the ADC. The first control end is connected to the control selection unit. The first data selector is used to select the quantization data input from the plurality of first input ends according to the control signal of the control selection unit received by the first control end, and output the selected quantization data from the first output end;

[0006] A second-stage selection circuit, including a plurality of second data selectors connected in parallel. The second data selector includes a second output end, a second control end, and a plurality of second input ends. Some of the second input ends of each second data selector are used to be connected to the encoded output end of the ADC, and some of the other second input ends are connected to the first output end. The second control end is connected to the control selection unit;

[0007] The second data selector is used to select the input encoded data or quantization data from the plurality of second input ends according to the control signal of the control selection unit received by the second control end, and output the selected encoded data or quantization data through the second output end; wherein, the encoded data is the data output from the encoded output end of the ADC, and the number of the second data selectors is equal to the precision bits of the ADC.

[0008] Preferably, it further includes: a plurality of first flip-flops, the plurality of first flip-flops corresponding one-to-one to a plurality of first data selectors, the first flip-flop including a first clock signal terminal, a third input terminal, and a third output terminal; the third input terminal is connected to the first output terminal of the corresponding first data selector, the third output terminal is connected to the second input terminal of the corresponding second data selector, and the first clock signal terminal is used to perform edge alignment on the quantization data output by the first-stage selection circuit.

[0009] Preferably, it further includes: a plurality of second flip-flops, the plurality of second flip-flops corresponding one-to-one to a plurality of second data selectors; the second flip-flop includes a second clock signal terminal, a fourth input terminal, and a fourth output terminal; the fourth input terminal is connected to the second output terminal of the corresponding second data selector, and the fourth output terminal is used to output the encoded data or quantization data selected by the second data selector, and the second clock signal terminal is used to perform edge alignment on the encoded data or quantization data.

[0010] Preferably, a part of the second input terminals of the second data selector is connected to DVDD.

[0011] The present invention also provides an analog-to-digital converter, further including: the above-mentioned data selection circuit, wherein the first input terminal of the data selection circuit is connected to the quantization output terminal of the analog-to-digital converter, a part of the second input terminals of the data selection circuit is connected to the encoded output terminal of the analog-to-digital converter, and another part of the second input terminals is connected to the first output terminal.

[0012] The present invention also provides a data output method for an analog-to-digital conversion device, applied to the above-mentioned analog-to-digital conversion device, including the following steps: determining the data type to be output by the digital-to-analog conversion device; wherein, the data type includes encoded data and quantization data; if the data type is encoded data, controlling the second output terminal of the second-stage selection circuit to selectively output the data of the second input terminal connected to the encoded output terminal of the analog-to-digital converter; if the data type is quantization data, controlling the second output terminal of the second-stage selection circuit to selectively output the data of the second input terminal connected to the first output terminal of the first-stage selection circuit.

[0013] Preferably, the second flip-flop includes a fourth input terminal, a second clock signal terminal, and a fourth output terminal, and the method further includes: when the second clock signal terminal is at a low level, the fourth input terminal receives the data output by the corresponding second data selector; when the second clock signal terminal is at a high level, the fourth output terminal outputs the received data; wherein, the clock signals of all the second flip-flops are kept consistent.

[0014] The present invention also provides a detection method for an analog-to-digital conversion device, which is applied to the above-mentioned analog-to-digital conversion device and includes the following steps: determining the serial number of the quantization output terminal to be output by the analog-to-digital converter, controlling the first output terminal of the first-stage selection circuit to output quantization data corresponding to the serial number; controlling the second output terminal of the second-stage selection circuit to output the data of the second input terminal connected to the first output terminal; comparing the data output by the second output terminal with the preset data to determine the quantization output terminal where the analog-to-digital converter has problems; wherein the preset data is the quantization data output by the corresponding quantization output terminal when the analog-to-digital converter is working normally.

[0015] Preferably, the first flip-flop includes a third input terminal, a first clock signal terminal, and a third output terminal. The method further includes: when the first clock signal terminal is at a low level, the third input terminal receives the quantization data of the corresponding first data selector; when the first clock signal terminal is at a high level, the third output terminal sends the received quantization data to the second input terminal of the second-stage selection circuit; wherein the clock signals of all the first flip-flops are kept consistent.

[0016] Preferably, the second flip-flop includes a fourth input terminal, a second clock signal terminal, and a fourth output terminal. The method further includes: when the second clock signal terminal is at a low level, the fourth input terminal receives the quantization data output by the corresponding second data selector; when the second clock signal terminal is at a high level, the fourth output terminal outputs the received quantization data; wherein the clock signals of all the second flip-flops are kept consistent.

[0017] The technical solution of the present invention has the following advantages:

[0018] The data selection circuit provided by the present invention can be directly connected to the quantization output terminal and the coding output terminal of the analog-to-digital converter. In the state where the analog-to-digital converter is working normally, it can enable the analog-to-digital converter to output coding data without affecting the normal use of the analog-to-digital converter. In the state where the analog-to-digital converter fails, it can enable the analog-to-digital converter to output quantization data, and use the raw data (i.e., the unencoded quantization data) to troubleshoot and locate the analog-to-digital converter without the need to use external devices. This data selection circuit is simple and effective. Description of the Drawings

[0019] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0020] Figure 1 It is the circuit diagram of the data selection circuit for the analog-to-digital converter in Embodiment 1 of the present invention;

[0021] Figure 2 It is a schematic structural diagram of one of the data selectors;

[0022] Figure 3 It is a schematic structural diagram of the analog-to-digital conversion device according to Embodiment 2 of the present invention;

[0023] Figure 4 It is a schematic structural diagram of one of the flip-flops;

[0024] Figure 5 It is a flowchart of the data output method of the analog-to-digital conversion device according to Embodiment 3 of the present invention;

[0025] Figure 6 It is a flowchart of the detection method of the analog-to-digital conversion device according to Embodiment 4 of the present invention. Detailed implementation manners

[0026] Next, the technical solutions of the present invention will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0027] In the description of the present invention, it should be noted that the terms "first", "second", and "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0028] Embodiment 1

[0029] This embodiment provides a data selection circuit for an analog-to-digital converter, as Figure 1 and Figure 2 shown, including a control selection unit (not shown), a first-stage selection circuit 10, and a second-stage selection circuit 20. The first-stage selection circuit 10 includes a plurality of first data selectors 101 connected in parallel, and the second-stage selection circuit 20 includes a plurality of second data selectors 201 connected in parallel. The first data selector 101 includes a first output end, a first control end, and a plurality of first input ends, and the second data selector 201 includes a second output end, a second control end, and a plurality of second input ends.

[0030] As Figure 2As shown, it shows a schematic structural diagram of a data selector. The data selector includes three input terminals, two control terminals, and one output terminal, namely input terminal 4011, input terminal 4012, input terminal 4013, control terminal 4021, control terminal 4022, and output terminal 403. Control terminal 4021 and control terminal 4022 are connected to a control selection unit, and the control selection unit controls the output terminal 403 to select and output the data of the input terminal. For example, when the combined control code value of control terminal 4021 and control terminal 4022 is 0, output terminal 403 outputs the data of input terminal 4011; when the combined control code value of control terminal 4021 and control terminal 4022 is 1, output terminal 403 outputs the data of input terminal 4012; when the combined control code value of control terminal 4021 and control terminal 4022 is 2, output terminal 403 outputs the data of input terminal 4013. It should be noted that the number of input terminals and the number of control terminals of the data selector can be reasonably selected according to the actual situation and are not limited here.

[0031] The working process of the analog-to-digital converter (ADC) includes sampling, holding, quantization, and encoding. The quantizer is used to quantize the analog signal and then send the quantized data to the encoder for encoding and output. As Figure 3 shown, the first input terminal of the first data selector 101 can be connected to the quantization output terminal of the analog-to-digital converter (i.e., the output terminal of the quantizer 30), and the first control terminal of the first data selector 101 is connected to a control selection unit (not shown). The control selection unit can send a control signal to the first control terminal of the first data selector 101 to select the quantized data input from the first input terminal among multiple first input terminals, so that the first output terminal of the first data selector 101 outputs the quantized data.

[0032] The second data selector 201 includes multiple second input terminals. Some of the second input terminals can be connected to the encoding output terminal of the analog-to-digital converter (i.e., the output terminal of the encoder 40), and some of the other second input terminals are connected to the first output terminal. The second control terminal is connected to a control selection unit (not shown).

[0033] The control selection unit sends a control signal to the second control terminal of the second data selector 201 to select the data to be output from among multiple second input terminals. Since some of the second input terminals of the second data selector 201 are connected to the encoder output terminal and some are connected to the first output terminal, it is possible to select to output the encoded data or the quantized data from the second output terminal. Among them, the number of second data selectors is equal to the number of precision bits of the analog-to-digital converter. For example, for an analog-to-digital converter with a 4-bit (bit) precision, the second data selector includes 4; for an analog-to-digital converter with a 5-bit (bit) precision, the second data selector includes 5; for an analog-to-digital converter with a 3-bit (bit) precision, the second data selector includes 3.

[0034] In the above embodiments, the data selection circuit can be directly connected to the quantization output terminal and the encoding output terminal of the analog-to-digital converter. When the analog-to-digital converter is operating normally, the analog-to-digital converter can output encoded data, without affecting the normal use of the analog-to-digital converter. When the analog-to-digital converter fails, the analog-to-digital converter can output quantization data, and the raw data (i.e., unencoded quantization data) is used to troubleshoot and locate the analog-to-digital converter. No external device is required, and the data selection circuit is simple and effective.

[0035] When the precision of the analog-to-digital converter is 4 bits (bit), as Figure 1 and Figure 3 shown, the quantizer 30 in the analog-to-digital converter can include 15, the first data selector 101 includes 5, and the second data selector 201 includes 4. Of course, the number of quantizers and the number of the first data selectors in the analog-to-digital converter can be reasonably selected according to the actual situation, and no specific limitation is made here.

[0036] In one or more embodiments, after the data signal passes through the first-stage selection circuit or the second-stage selection circuit, the signal edge may be misaligned to generate a phase difference. To ensure the strict synchronization of each data signal, alignment processing is required to ensure the strict timing relationship between the data and the clock signal on the same path. As Figure 1 shown, it further includes a plurality of first flip-flops 102 and / or a plurality of second flip-flops 202. The first flip-flop 102 includes a first clock signal terminal, a third input terminal, and a third output terminal. The second flip-flop 202 includes a second clock signal terminal, a fourth input terminal, and a fourth output terminal. The plurality of flip-flops 102 correspond to the plurality of first data selectors 101 one by one, and the plurality of second flip-flops 202 correspond to the plurality of second data selectors 201 one by one. As Figure 4 shown, it shows a schematic structural diagram of one of the flip-flops, including an input terminal 301, a clock signal terminal 302, and an output terminal 303. The quantization data or encoded data is input from the input terminal 301, and after being edge-aligned under the control of the clock signal terminal 302, it is output through the output terminal 303.

[0037] The third input terminal is connected to the first output terminal of the corresponding first data selector 101, and the third output terminal is connected to the second input terminal of the corresponding second data selector 201. The first clock signal terminals of the plurality of first flip-flops 102 receive unified allocation to edge-align the quantization data output by the first-stage selection circuit. The fourth input terminal is connected to the second output terminal of the corresponding second data selector 201, and the fourth output terminal outputs the encoded data or quantization data selected by the second data selector. The second clock signal terminals of the plurality of second flip-flops 201 receive unified allocation to edge-align the quantization data or encoded data output by the second-stage selection circuit.

[0038] In one or more embodiments, when some of the first input terminals in the first data selector 101 are not connected to the quantization output terminal, or some of the second input terminals in the second data selector 201 are not connected to the encoding output terminal and the first output terminal, the first input terminal and / or the second input terminal are connected to DVDD. Among them, DVDD can be the internal power supply when the analog-to-digital converter is working and is at a high level. The first input terminal and the second input terminal connected to DVDD cannot be selected for output.

[0039] Embodiment 2

[0040] This embodiment provides an analog-to-digital conversion device, as Figure 3 shown, including an analog-to-digital converter and the data selection circuit provided in Embodiment 1. The working process of the analog-to-digital converter includes sampling, holding, quantization, and encoding. A quantizer is used to quantize the collected analog signal to obtain quantization data. The output terminal of the quantizer outputs the quantization data to the encoder. The encoder encodes the quantization data to obtain encoded data, and then outputs the encoded data. It should be noted that, for the sake of simplicity in description, Figure 3 not all of the analog-to-digital converters in

[0041] As Figure 3 shown, the output terminal of the quantizer 30 is connected to the first input terminal and the input terminal of the encoder 40. Some of the second input terminals are connected to the output terminal of the encoder 40, and some of the other second input terminals are connected to the first output terminal. Multiple quantizers 30 output quantization data. The quantization data is received by the encoder 40 and multiple first data selectors 101. After the first data selector 101 selects the quantization data at the first input terminal, the selected quantization data is transmitted to some of the second input terminals of the second data selector 201. After the encoder 40 encodes the quantization data, the encoded data is transmitted to some of the second input terminals of the second data selector 201. After the second data selector 201 selects the data at the second input terminal, the encoded data or the quantization data is output from the second output terminal.

[0042] When a fault occurs in the analog-to-digital converter in the analog-to-digital conversion device, the data selection circuit can be used to select and output the quantization data of the analog-to-digital converter to locate the position where the analog-to-digital converter fails; when the analog-to-digital converter in the analog-to-digital conversion device is working normally, the data selection circuit can be used to select and output the encoded data of the analog-to-digital converter to maintain the normal operation of the analog-to-digital conversion device.

[0043] Embodiment 3

[0044] This embodiment provides a method for outputting data of an analog-to-digital conversion device, Figure 5It is a flowchart showing the data selection and output of the analog-to-digital conversion device provided in Embodiment 2 according to certain embodiments of the present invention. Although the processes described below include multiple operations that occur in a specific order, it should be clearly understood that these processes may also include more or fewer operations, and these operations may be executed sequentially or in parallel (e.g., using a parallel processor or a multi-threaded environment).

[0045] This embodiment provides a data output method for an analog-to-digital conversion device, which is used to output data of the analog-to-digital conversion device in Embodiment 2. As Figure 5 shown, the data output method includes:

[0046] S101. Determine the data type to be output by the digital-to-analog conversion device.

[0047] In the above implementation steps, the analog-to-digital conversion device includes an analog-to-digital converter and the data selection circuit provided in Embodiment 1. The quantizer in the analog-to-digital converter outputs quantization data, and the encoder encodes the quantization data to obtain encoded data. The data selection circuit includes a first-stage selection circuit and a second-stage selection circuit. The first-stage selection circuit includes a plurality of first data selectors connected in parallel, and the second-stage selection circuit includes a plurality of second data selectors connected in parallel. Some of the second input terminals of the second data selector are connected to the output terminal of the encoder, and some of the second input terminals are connected to the first output terminal of the first data selector. The control selection unit can control the second control terminal to select and output quantization data or encoded data. When the analog-to-digital conversion device needs to output quantization data, step S103 is executed; when the analog-to-digital conversion device needs to output encoded data, step S102 is executed.

[0048] S102. Control the second output terminal of the second-stage selection circuit to select and output the data of the second input terminal connected to the encoded output terminal of the analog-to-digital converter.

[0049] In the above implementation steps, the control selection unit controls the second control terminal to select and output the data of the second input terminal connected to the encoded output terminal of the analog-to-digital converter, so as to output the encoded data through the second output terminal.

[0050] S103. Control the second output terminal of the second-stage selection circuit to select and output the data of the second input terminal connected to the first output terminal of the first-stage selection circuit.

[0051] In the above implementation steps, the control selection unit controls the second control terminal to select and output the data of the second input terminal connected to the first output terminal of the first-stage selection circuit, so as to output the quantization data through the second output terminal.

[0052] When a failure occurs in the analog-to-digital conversion device, the control selection unit controls the second control end to select and output the quantization data, so as to determine the position where the analog-to-digital converter fails; when the analog-to-digital conversion device is working normally, the control selection unit controls the second control end to select and output the encoded data, so as to maintain the normal function of the analog-to-digital converter.

[0053] In one or more embodiments, the first flip-flop includes a third input terminal, a first clock signal terminal, and a fourth output terminal, and the second flip-flop includes a fourth input terminal, a second clock signal terminal, and a fourth output terminal. A plurality of first flip-flops correspond to a plurality of first data selectors one by one. When the first clock signal terminal is at a low level, the third input terminal receives the quantization data output from the first output terminal of the corresponding first data selector; when the first clock signal terminal is at a high level, the third output terminal outputs the received quantization data. To align the edges of all the quantization data, the clock signals of all the first flip-flops are kept consistent. As Figure 3 shown, the first clock signal terminals of the plurality of first flip-flops 102 are uniformly allocated by the clock signal CLK.

[0054] A plurality of second flip-flops correspond to a plurality of second data selectors one by one. When the second clock signal terminal is at a low level, the fourth input terminal receives the data output from the corresponding second data selector; when the second clock signal terminal is at a high level, the fourth output terminal outputs the received data; wherein, the data output from the fourth output terminal can be quantization data or encoded data. To align the edges of all the data, the clock signals of all the second flip-flops are kept consistent. As Figure 3 shown, the second clock signal terminals of the plurality of second flip-flops 202 are uniformly allocated by the clock signal CLK.

[0055] Embodiment 4

[0056] This embodiment provides a detection method for an analog-to-digital conversion device, Figure 6 which is a flowchart for data detection of the analog-to-digital conversion device provided in Embodiment 2 according to certain embodiments of the present invention. Although the processes described below include a plurality of operations that occur in a specific order, it should be clearly understood that these processes may also include more or fewer operations, and these operations may be executed sequentially or in parallel (for example, using a parallel processor or a multi-threaded environment).

[0057] S201. Determine the serial number of the quantization output terminal to be output by the analog-to-digital converter, and control the first output terminal of the first-stage selection circuit to output the quantization data corresponding to the serial number.

[0058] In the above implementation steps, the analog-to-digital conversion device includes an analog-to-digital converter and the data selection circuit provided in Embodiment 1. The quantizer in the analog-to-digital converter outputs quantization data, and the encoder encodes the quantization data and outputs encoded data. To locate the faulty quantizer in the analog-to-digital converter, it is necessary to output raw data (i.e., quantization data) to locate the faulty quantizer.

[0059] When the output terminal of the quantizer in the analog-to-digital converter is connected to the first input terminal of the first data selector, number the transformers to obtain the sequence number corresponding to each quantizer. When performing a fault detection on the analog-to-digital converter, determine the sequence number of the quantizer to be detected, and control the first output terminal of the first selection circuit to output the quantization data corresponding to the sequence number.

[0060] For example, the analog-to-digital converter includes 15 quantizers. Number all the quantizers to obtain numbers 1, 2, …, 15. When it is necessary to detect whether there are faults in the quantizers corresponding to numbers 3, 6, 9, and 12, control the first output terminal of the first-stage selection circuit to output the quantization data of the quantizers corresponding to numbers 3, 6, 9, and 12.

[0061] S202. Control the second output terminal of the second-stage selection circuit to output the data of the second input terminal connected to the first output terminal.

[0062] In the above implementation steps, to locate the faulty quantizer in the analog-to-digital converter, it is necessary to output quantization data, and control the second output terminal of the second-stage selection circuit to output the data of the second input terminal connected to the first output terminal, that is, output quantization data through the second output terminal.

[0063] S203. Compare the data output from the second output terminal with the preset data to determine the quantization output terminal where the analog-to-digital converter has problems.

[0064] In the above implementation steps, the preset data is the quantization data output from the corresponding quantization output terminal when the analog-to-digital converter is working normally. When the quantization data output from the second output terminal is inconsistent with the preset data, the quantizer corresponding to the quantization data is faulty.

[0065] For example, the quantization data output from the second output terminal corresponding to the quantizers numbered 3, 6, 9, and 12 are: 1, 0, 1, 0, respectively, while when the analog-to-digital converter is working normally, the quantization data output from the quantizers corresponding to numbers 3, 6, 9, and 12 should be: 1, 0, 1, 1. Then it can be determined that the encoder corresponding to number 12 is faulty.

[0066] In one or more embodiments, to ensure that there is no phase difference caused by incorrect edges in the finally output quantized data signal, a first flip-flop and a second flip-flop are used for alignment. The first flip-flop includes a third input terminal, a first clock signal terminal, and a third output terminal. The second flip-flop includes a fourth input terminal, a second clock signal terminal, and a fourth output terminal.

[0067] When the first clock signal terminal is at a low level, the third input terminal receives the quantized data corresponding to the first data selector; when the first clock signal terminal is at a high level, the third output terminal sends the received quantized data to the second input terminal of the second-stage selection circuit; wherein, the clock signals of all the first flip-flops are kept consistent. When the second clock signal terminal is at a low level, the fourth input terminal receives the quantized data output by the second data selector; when the second clock signal terminal is at a high level, the fourth output terminal outputs the received quantized data; wherein, the clock signals of all the second flip-flops are kept consistent. As Figure 3 shown, the second clock signal terminals of multiple first flip-flops 102 and second flip-flops 202 are uniformly allocated by the clock signal CLK.

[0068] Obviously, the above embodiments are merely examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present invention.

Claims

1. A data selection circuit for an analog-to-digital converter, characterized in that, Comprising: A control selection unit; A first-stage selection circuit, including a plurality of first data selectors connected in parallel. The first data selector includes a first output terminal, a first control terminal, and a plurality of first input terminals. The first input terminals are used to connect to the quantization output terminal of an analog-to-digital converter. The first control terminal is connected to the control selection unit. The first data selector is used to select the quantization data input from the first input terminals according to the control signal received from the control selection unit at the first control terminal and output it from the first output terminal; A second-stage selection circuit, including a plurality of second data selectors connected in parallel. The second data selector includes a second output terminal, a second control terminal, and a plurality of second input terminals. Some of the second input terminals of each second data selector are used to connect to the encoded output terminal of the analog-to-digital converter, and some of the other second input terminals are connected to the first output terminal. The second control terminal is connected to the control selection unit; The second data selector is used to select the input encoded data or quantization data from the plurality of second input terminals according to the control signal received from the control selection unit at the second control terminal and output the selected encoded data or quantization data through the second output terminal. Wherein, the encoded data is the data output from the encoded output terminal of the analog-to-digital converter, and the number of the second data selectors is equal to the number of precision bits of the analog-to-digital converter.

2. The data selection circuit for an analog-to-digital converter according to claim 1, characterized in that Further comprising: A plurality of first flip-flops, and the plurality of first flip-flops correspond to the plurality of first data selectors one by one. The first flip-flop includes a first clock signal terminal, a third input terminal, and a third output terminal; The third input terminal is connected to the first output terminal of the corresponding first data selector, the third output terminal is connected to the second input terminal of the corresponding second data selector, and the first clock signal terminal is used to perform edge alignment on the quantization data output by the first-stage selection circuit.

3. The data selection circuit for an analog-to-digital converter according to claim 2, wherein, Further comprising: A plurality of second flip-flops, and the plurality of second flip-flops correspond to the plurality of second data selectors one by one; The second flip-flop includes a second clock signal terminal, a fourth input terminal, and a fourth output terminal; The fourth input terminal is connected to the second output terminal of the corresponding second data selector, and the fourth output terminal is used to output the encoded data or quantization data selected by the second data selector. The second clock signal terminal is used to perform edge alignment on the encoded data or quantization data.

4. The data selection circuit for an analog-to-digital converter according to any one of claims 1-3, characterized in that Some of the second input terminals of the second data selector are connected to DVDD.

5. An analog-to-digital conversion device, characterized in that, Comprising an analog-to-digital converter, and further comprising: The data selection circuit according to any one of claims 1-4, wherein the first input terminal of the data selection circuit is connected to the quantization output terminal of the analog-to-digital converter, some of the second input terminals of the data selection circuit are connected to the encoded output terminal of the analog-to-digital converter, and some of the other second input terminals are connected to the first output terminal.

6. A data output method of an analog-to-digital conversion device, applied to the analog-to-digital conversion device described in claim 5, characterized in that, Comprising the following steps: Determine the data type to be output by the digital-to-analog conversion device; wherein, the data type includes encoded data and quantization data; If the data type is encoded data, then control the second output terminal of the second-stage selection circuit to select and output the data of the second input terminal connected to the encoded output terminal of the analog-to-digital converter; If the data type is quantized data, control the second output terminal of the second-level selection circuit to select and output the data of the second input terminal connected to the first output terminal of the first-level selection circuit.

7. The data output method of the analog-to-digital conversion device according to claim 6, characterized in that The second flip-flop includes a fourth input terminal, a second clock signal terminal, and a fourth output terminal. The method further includes: When the second clock signal terminal is at a low level, the fourth input terminal receives the data output by the corresponding second data selector. When the second clock signal terminal is at a high level, the fourth output terminal outputs the received data; wherein, the clock signals of all the second flip-flops are kept consistent.

8. A detection method for an analog-to-digital conversion device, applied to the analog-to-digital conversion device according to claim 5, characterized in that, The method includes the following steps: Determine the serial number of the quantized output terminal to be output by the analog-to-digital converter, and control the first output terminal of the first-level selection circuit to output the quantized data corresponding to the serial number. Control the second output terminal of the second-level selection circuit to output the data of the second input terminal connected to the first output terminal. Compare the data output by the second output terminal with the preset data to determine the quantized output terminal where the analog-to-digital converter has a problem; wherein, the preset data is the quantized data output by the corresponding quantized output terminal when the analog-to-digital converter is working normally.

9. The detection method of the analog-to-digital conversion device according to claim 8, characterized in that, The first flip-flop includes a third input terminal, a first clock signal terminal, and a third output terminal. The method further includes: When the first clock signal terminal is at a low level, the third input terminal receives the quantized data of the corresponding first data selector. When the first clock signal terminal is at a high level, the third output terminal sends the received quantized data to the second input terminal of the second-level selection circuit; wherein, the clock signals of all the first flip-flops are kept consistent.

10. The detection method of the analog-to-digital conversion device according to claim 8 or 9, characterized in that, The second flip-flop includes a fourth input terminal, a second clock signal terminal, and a fourth output terminal. The method further includes: When the second clock signal terminal is at a low level, the fourth input terminal receives the quantized data output by the corresponding second data selector. When the second clock signal terminal is at a high level, the fourth output terminal outputs the received quantized data; wherein, the clock signals of all the second flip-flops are kept consistent.

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