capability write address tracking

Abstract

An apparatus is provided that includes capability check circuitry (86) to perform a capability validity check operation to determine whether use of a capability satisfies one or more use restriction conditions. The capability includes a pointer and pointer use restriction information specifying the one or more use restriction conditions. The one or more use restriction conditions include at least an allowed address range for the pointer. In response to a capability write request requesting a write of a capability to a memory location associated with a capability write target address, a capability write address tracking circuit (200) updates a capability write address tracking structure (100) based on the capability write target address when capability write address tracking is enabled.

Description

[0001] This technology relates to the field of data processing.

[0002] Software executing on a data processing device can use pointers to control access to memory. However, pointers can sometimes provide a pathway for malicious attackers to compromise victim software. For example, a buffer overflow could be exploited to use the pointer to identify locations within a buffer, thereby gaining access to memory regions outside the buffer that would otherwise be inaccessible to the attacker. Some processor architectures may support capabilities that associate pointers with pointer usage restrictions specifying one or more usage constraints that limit the scenarios in which the pointer can be used effectively. These restrictions may include at least a defined range of allowed addresses for the pointer, enabling the signaling of an error if the pointer is used to access memory regions outside this range. This can help prevent certain forms of attacks.

[0003] At least some embodiments provide an apparatus comprising: a capability checking circuit for performing a capability checking operation to determine whether the use of a capability satisfies one or more usage restrictions, the capability including a pointer and pointer usage restriction information specifying the one or more usage restrictions, the one or more usage restrictions including at least a allowed address range for the pointer; and a capability write address tracking circuit that, in response to a capability write request requesting the write of a capability to a memory location associated with a capability write target address, updates a capability write address tracking structure based on the capability write target address when capability write address tracking is enabled.

[0004] At least some embodiments provide a method comprising: performing a capability check operation to determine whether the use of a capability satisfies one or more usage restrictions, the capability including a pointer and pointer usage restriction information specifying the one or more usage restrictions, the one or more usage restrictions including at least a allowed address range for the pointer; and updating a capability write address tracking structure based on the capability write target address in response to a capability write request requesting the capability to be written to a memory location associated with a capability write target address, when capability write address tracking is enabled.

[0005] At least some embodiments provide a computer program for controlling a host data processing device to provide an instruction execution environment for executing target code. The computer program includes: capability checking program logic for performing capability checking operations to check whether the use of a capability satisfies one or more usage restrictions, the capability including a pointer and pointer usage restriction information specifying the one or more usage restrictions, the one or more usage restrictions including at least a allowed address range for the pointer; and capability write address tracking program logic that, in response to a capability write request requesting the write of a capability to a memory location associated with a capability write target address, updates a capability write address tracking structure based on the capability write target address when capability write address tracking is enabled.

[0006] Computer programs can be stored on computer-readable recording media. The recording media can be transient or non-transient.

[0007] At least some embodiments provide a method comprising: enabling capability write address tracking via a capability write address tracking structure for tracking capability write target addresses of one or more capability write requests, wherein the capability write request includes a request to write a capability to a memory location associated with the capability write target address specified by the capability write request, and the capability includes a pointer and pointer usage restriction information specifying one or more usage restrictions, the one or more usage restrictions including at least a allowed address range for the pointer; scanning memory to invalidate invalid capabilities, the invalid capabilities including capabilities for which the allowed address range overlaps with one or more target regions of the address; and, after scanning the memory, rescanning one or more selected memory address regions corresponding to the addresses tracked by the capability write address tracking structure to invalidate invalid capabilities stored in the one or more selected memory address regions.

[0008] At least some embodiments provide a computer program for controlling a data processing apparatus to perform the method described above, the method including activation, scanning, and rescanning steps. The computer program may be stored on a computer-readable recording medium. The recording medium may be a transient or non-transient recording medium.

[0009] Further aspects, features, and advantages of this technology will become apparent from the following description, which is taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 An example of a data processing device is shown, which has multiple processor cores and the ability to write address tracking circuitry;

[0011] Figure 2 An example of a processor core is shown;

[0012] Figure 3 Examples of capabilities are shown, along with examples of how capabilities can be copied to multiple locations within the memory address space;

[0013] Figure 4 An example of using a capability-based reversal attack system is shown;

[0014] Figure 5 Several examples of write addresses for tracking capabilities are shown;

[0015] Figure 6 The flowchart illustrates the steps performed by software executing on a multiprocessor system to perform a scan for memory failure capabilities; and

[0016] Figure 7 A specific implementation of the available simulator is shown.

[0017] The data processing device includes a capability checking circuit that performs a capability checking operation to determine whether the use of a capability meets one or more usage restrictions. The capability includes a pointer and pointer usage restriction information specifying the one or more usage restrictions. The one or more usage restrictions may at least include a allowed address range for the pointer. The usage restrictions may also optionally include other conditions, such as whether the capability can be used to control writes to memory, or whether it allows the retrieval of instructions to be executed from a memory region accessed through the capability (for example). By providing the capability checking circuit, some hardware-based protection against malicious use of pointers is provided, which could otherwise be used to launch attacks against vulnerable software.

[0018] Such capabilities can be written to any address within the memory address space. If a capability that allows a range covering a given memory region resides in memory and is subsequently freed, it may be unsafe to reallocate the given region to a given software process before any capability in memory covering that given region has been invalidated. While it is possible to prevent freed memory from being reallocated while capabilities still exist that cover the freed region stored in the memory system for a period of time, this often leads to memory fragmentation and performance degradation. Not reusing memory is equivalent to a memory leak (loss of available memory address space due to failure to free memory), which, even if the address space is large, can eventually lead to overflow, thus impacting security. Therefore, while memory reallocation may be prevented for a period of time, it may eventually be desirable to be able to scan memory to identify its failed capabilities that allow address ranges to cover previously freed memory regions, allowing the freed regions to be reused for other purposes.

[0019] When performing such scans of memory for failed capabilities (typically software-controlled), there is a risk that other processor cores or threads might write capabilities to the scanned memory region while the scan is ongoing. This can be mitigated by stopping all other processor cores from continuing their processing while the scan is being performed on a given processor core, or by changing memory access permissions to prevent capability write operations from being allowed, but these methods have a significant impact on performance. Additionally, in such "stop-all" approaches, the scanning process will need to set configuration registers to specify that the scanning process must not be interrupted, thus preventing an attacker from interrupting the scan and copying capabilities to previously scanned memory before resuming the scan. However, this means that legitimate interrupt sources are also disabled, increasing interrupt handling latency, which may be undesirable for real-time systems that need to limit the maximum time interrupts can be handled.

[0020] In the technology described below, the apparatus includes capability write address tracking circuitry that, in response to a capability write request requesting the writing of a capability to a memory location associated with a capability write target address, updates the capability write address tracking structure based on the capability write target address when capability write address tracking is enabled. Thus, by providing tracking hardware that can track the addresses of written capabilities, this allows for the identification of addresses of written capabilities while a scan is ongoing, enabling a relatively efficient rescanning of any written locations after the main scan has completed, preventing the possibility of capabilities being written to already scanned memory. Therefore, the architecture of providing capability write address tracking circuitry in hardware enables more efficient scanning because it avoids requiring the scan process to halt all other kernel processing while a scan is ongoing, thereby significantly improving performance.

[0021] The tracking performed by the capability write address tracking circuitry can be targeted at specific capability write requests. Therefore, in response to a non-capability write request that requests to write information other than the capability to a memory location associated with the non-capability write target address, the capability write address tracking circuitry can ignore such non-capability write requests, so that the capability write address tracking structure is not updated based on the target address of the non-capability write request.

[0022] The capability write address trace structure can be accessed by software executing on the device. Therefore, when a software-controlled scan of a failed capability occurs, the software can identify locations in memory that should be rescanned based on the information in the capability write address trace structure.

[0023] Some systems can permanently enable capability write address tracking circuitry, allowing the recording of addresses that have been written to to be maintained during normal processing. However, in practice, this may require a relatively large capability write address tracking structure, and the circuit area, power, and performance overhead associated with permanently tracking the addresses of capability write requests may be unreasonable.

[0024] In other embodiments, enabling the storage element can be configured as a storage capability write address tracking enable indicator, which indicates whether capability write address tracking is enabled or disabled. When capability write address tracking is enabled, the capability write address tracking circuitry updates the capability write address tracking structure based on the capability write target address in response to a capability write request. Conversely, when the capability write address tracking enable indicator indicates that capability write address tracking is disabled, the capability write address tracking circuitry omits updating the capability write address tracking structure based on the capability write target address of any received capability write request. By providing the ability to enable or disable capability write address tracking, this allows for the use of a smaller capability write address tracking structure, since address tracking only needs to be enabled when it is important to know which addresses have been written to, and can otherwise be disabled to avoid capturing useless information.

[0025] The system may have processing circuitry for executing program instructions. The processing circuitry may have an instruction set architecture supporting at least one program instruction that controls the processing circuitry to update the capability write address tracking enable indication. For example, the program instruction may be a dedicated capability write address tracking enable or disable instruction, or a system register update instruction that controls the overall register update and specifies parameters identifying the register to be updated as a capability write address tracking enabled memory element. Thus, software can set whether the tracking of the capability write address tracking circuitry is enabled or disabled by executing program instructions that set or clear the capability write address tracking enable indication. For example, software controlling the scanning of failed capabilities, as described above, could enable capability write address tracking before starting the scan and then disable it again when the scan is complete, allowing detection of any addresses to which capabilities are written during the scan.

[0026] Capability write address tracking structures can track addresses at a coarser granularity than the target address specified in the capability write request. For example, a capability write address tracking structure can identify the page or address block in which the capability is written, rather than a specific address within that page / block. This reduces the storage overhead of the tracking structure.

[0027] The device may have a cache structure with multiple entries, each storing cached information associated with a corresponding memory address region. In response to a capability write request, when updating the capability write address tracking structure based on the capability write target address, the capability write address tracking circuit may also set a capability write indicator flag in the entry of the cache structure corresponding to the memory address region containing the capability write target address. Thus, the cache entry can be marked as an indication of whether any capability to write to the corresponding memory address region has been detected. In response to a capability write request, when capability write address tracking is enabled and the capability write target address corresponds to a memory address region for which the corresponding cache entry has already had its capability write indicator flag set, the capability write address tracking circuit may omit updating the capability write address tracking structure based on the capability write target address.

[0028] Therefore, by marking cache entries with information about whether at least one capability write request for the corresponding memory address region has been detected, redundant allocation of multiple capability write address trace update entries for the same region can be avoided, as can the updating of the capability write address trace structure when a subsequent capability write is made to the same region that has already been capability-written. This allows for more efficient use of capability write address trace structures with limited capacity.

[0029] The cache structure with a capability write indicator set can be one of a series of different types of cache structures. For example, the cache structure could be a data cache for caching data retrieved from memory, an instruction cache for caching instructions retrieved from memory, or a dedicated capability write address tracking cache with entries solely for capability write address tracking purposes. However, in one embodiment, it may be particularly useful where the cache structure includes an address translation cache for storing address translation information derived from page table structures in memory. For example, the cache structure may include a translation back buffer (TLB). A TLB can track address regions at a relatively large granularity, such as the page granularity defining page table structures in memory, and thus makes tracking capability write indicators more efficient than alternative cache structures that can track addresses at a finer granularity. Furthermore, unlike other cache structures, in implementation, capability write requests can always be looked up in the address translation cache to obtain the physical address of the region to which a write operation is accepted, and therefore the capability write indicator in the address translation cache entry can be checked relatively efficiently when a capability write request is received. However, other types of cache structures can also be used to track the write capability indicator of the corresponding memory address region.

[0030] When evicting an entry with a set of capability write indicators from the address translation cache (or, in a system with multi-level address translation caches, from the last level of the address translation cache), the address translation cache may discard the capability write indicators without writing them back to the page table structure in memory. While this may mean that information from previous capability write requests for that region is lost when an entry with a set of capability write indicators is evicted, and therefore, if a subsequent capability write request targets the same region again, it could result in multiple capability write address trace structure entries being allocated for that same region, which may be preferable to updating the page table structure with capability write indicators. The page table structure may already occupy a significant amount of memory space, and increasing the size of each page table entry by 1 bit could practically require allocating several additional bits of memory per page table entry because the alignment of page table entries has address size boundaries to the power of two. Therefore, increasing the size of page table entries to accommodate capability write indicators during implementation could have a significant impact on the size of the page table structure, which may be undesirable. Therefore, it may be preferable to occasionally allocate redundant entries in the capability write address tracking structure than to write the capability write indicator back to the page table structure.

[0031] The processing circuitry can handle instructions from one software process out of multiple software processes, each associated with a corresponding execution context identifier. For example, the TLB can use the execution context identifier to distinguish different sets of address translation information associated with a given software process. When capability write address tracking is enabled, this capability write address tracking circuitry can maintain execution context identifier tracking information to track one or more execution context identifiers associated with one or more capability write requests. This can be useful because it means that when the capability write address tracking structure is later used to control which memory regions need to be rescanned for their failed capabilities, the execution context identifier tracking information can be used to avoid some unnecessary rescanning of memory address regions that have not been written to in the same execution context but have virtual addresses overlapping with those used by the scanned process. This can improve the performance of scanning processes for failed capabilities.

[0032] The processing circuitry may also support a capability write address track reset instruction, which can be used to reset the capability write address track structure. For example, this instruction can be executed at the start of the scan process or at the end of the scan process. The capability write address track reset instruction can be the same instruction that enables or disables capability write address tracking, or it can be a separate instruction. When the capability write address track structure is reset, it can be reset to a state equivalent to indicating that no address accepts any capability write requests. This can be done, for example, by clearing all data entries in the capability write address track structure, or by allocating a new structure in memory and updating the address parameters of any locations that identify the new structure.

[0033] Capability write address tracking structures can be implemented in different ways. For example, the structure may include a separate memory cell located in the hardware. Thus, a dedicated unit implemented in hardware can be provided for tracking address information of the address that receives capability write operations.

[0034] Alternatively, the capability write address tracking structure may simply be a data structure stored in memory at a given set of addresses. In this case, the capability write address tracking circuitry may have hardware for updating and accessing the capability write address tracking structure, but the hardware may not have circuitry for storing the capability write address tracking information itself. While the capability write address tracking structure is maintained in memory, in one embodiment, the structure may be a buffer comprising multiple entries, each entry specifying the address of a memory region that accepts at least one capability write. The address tracking may have different granularities, for example, cache line or page-level granularity. In one embodiment, at least one tracking metadata storage element may be provided to help identify the location in memory where the capability write address tracking structure is stored. For example, the at least one tracking metadata storage element may store at least one of the following: the base address of the capability write address tracking structure; an indication of the next entry of the capability write address tracking structure to be updated; and a limit indication of the maximum allowed size of the capability write address tracking structure. Here, the indication of the next entry to be updated may be explicit or implicit; for example, the indication of the next entry may be identified by recognizing the previous entry written, which may implicitly identify which is the next entry. The indication of the next entry can be represented as a count value (which can be used to derive the address of the next entry to be updated by applying multiple increments to the base address, the number of increments being chosen based on the count value, and the increment corresponding to the size of an entry), or as an absolute address that identifies the location of the next entry or the previously written entry in memory.

[0035] Limitation indicators can be useful because they allow the write capability address trace circuitry to track whether so many entries have been allocated to the write capability address trace structure that the maximum allowed size has been exceeded or there is a risk of exceeding the maximum allowed size. This prevents the trace structure from overflowing into subsequent areas of memory that may contain other information.

[0036] In some embodiments, when capability write address tracking is enabled, the capability write address tracking structure can precisely track one or more capability write target addresses for one or more received capability write requests. For example, the tracking structure can maintain a list or similar cache structure that identifies the specific address associated with any received capability write request. As mentioned above, precise tracking can be performed at different granularities; for example, precise tracking can target page addresses rather than the address of a single cached line of a capability write request.

[0037] Alternatively, when capability write address tracking is enabled, the capability write address tracking structure may imprecisely track one or more capability write target addresses for one or more received capability write requests. Imprecise tracking may result in positive false recognitions (where queries to the capability write address tracking structure might incorrectly identify an address other than one of the received capability write target addresses as a member of the set of received capability write target addresses) but negative false recognitions (when one of the received capability write target addresses is not identified as a capability write target address) are not possible. For example, structures such as Bloom filters can be used. This imprecise tracking reduces the storage overhead required by the capability write address tracking structure, but at the cost of occasionally allowing positive false recognitions, so that some memory regions might be identified as regions to be rescanned when these regions do not actually correspond to regions that received capability write operations.

[0038] In response to the detection that the capability write address tracking structure has reached its capacity limit (e.g., based on a limit indication as described above), the capability write address tracking circuitry can trigger an exception signaling. In response to this exception, the software can either update the size of the address tracking structure to allow continued tracking, or stop scanning for any potentially ongoing failed capabilities and restart the scan. In some implementations, it may not be necessary to trigger an exception because it may not exceed the capacity of the tracking structure; for example, using a Bloom filter approach, any number of addresses can be folded into a Bloom filter without increasing its size. However, for other methods such as linked lists or buffers, the size may eventually exceed the capacity of the memory space allocated to the capability write address tracking structure. Therefore, it is useful to provide architectural features for detecting when the capacity limit has been reached and subsequently issuing an exception signaling.

[0039] In some embodiments, the data processing system may include multiple processor cores. Capability write address tracking structures can be shared among the cores. Capability write address tracking circuitry can also be shared among the cores. It is likely that situations requiring scanning of multiple cores will be relatively rare, so sharing the tracking structure may be sufficient. Furthermore, sharing the tracking among cores makes it easier to check if any core has issued a capability write request.

[0040] Alternatively, other methods may provide a separate capability write address trace structure for a single core, or provide some hardware for updating a shared trace structure for a specific individual core. For example, each core may individually update its TLB or other type of cache with an indicator specifying whether a capability write request is for a specific address region. Thus, the above circuitry can be implemented in a variety of ways in a multi-core system. The above embodiments describe hardware circuitry for performing capability checking operations and capability write address trace. A computer program that executes on a host data processing device may also be provided to control the host to provide an instruction execution environment for executing object code, such that the object code can be executed on the host data processing device as if it were executed on a target data processing device that may have a different architecture than the host. This can be used to enable legacy code written for different processor architectures to execute on a new platform, or to allow testing of processor architectures during development, or to allow development of software designed to run on a new processor architecture to begin before any hardware device supporting the new architecture is truly ready. Thus, a simulator computer program running on the host can effectively emulate the characteristics of the processor architecture of the target data processing device, enabling the target code to execute on the host as if it were executing on the target data processing device. Such a simulator computer program may include capability checking program logic and capability write address tracking program logic, which emulate the functionality of the aforementioned capability checking circuit and capability write address tracking circuit.

[0041] The above discussion has described the architectural features of a processing system set up in hardware, or the corresponding architecture of a simulator computer program, which enables software to use capability write requests to identify which addresses have been written, and which can be used to scan for failed capabilities. While particularly useful for this type of scanning, it remains to be seen whether software developers or compilers can discover other uses for capability write trace structures.

[0042] In a corresponding method, a method can be provided that uses a capability write address tracking structure to control the scan to invalidate failed capabilities. Thus, this software-controlled method may include enabling capability write address tracking by the capability write address tracking structure, then scanning memory to invalidate failed capabilities, wherein the failed capabilities are those capabilities that allow address ranges to overlap with one or more target regions of the address, and then, after scanning the memory, rescanning one or more selected memory address regions corresponding to the addresses tracked by the capability write address tracking structure to invalidate the failed capabilities stored in one or more rescanned selected memory address regions. Therefore, by using a capability write address tracking structure, the scanning process can avoid needing to stop processing of other processor cores or threads or prevent valid capability writes from continuing, which can improve performance because the tracking structure allows for targeted rescanning of memory regions that accept capability writes during the main scan.

[0043] A computer program may be provided for controlling a data processing apparatus to perform the above-described method. The computer program may be stored on a non-transitory computer-readable storage medium.

[0044] Figure 1 An example of a data processing system 2 comprising multiple processor cores (CPUs) 4 is illustrated schematically. In this example, four CPUs are used, but it should be understood that more or fewer CPUs can be configured. The CPUs access a shared memory system via interconnect 6, and in addition to routing transaction processing between the cores 4 and memory, they also manage the consistency of cached data within their respective processor cores 4. Although not explicitly stated... Figure 1 As shown, but the system may also include other types of master devices capable of initiating memory transactions, such as graphics processing units, display controllers, network controllers, or other types of devices. Transactions initiated by the master device are routed to slave devices via the interconnect. In this example, the slave device includes a memory controller 8 for controlling access to memory cells 10, 12. In this example, memory cell 10 is a dynamic random access memory (DRAM) cell and memory cell 12 is a non-volatile RAM cell. It should be understood that other types of memory may also be provided, as well as other types of slave devices, such as peripheral controllers, input / output units, etc. The interconnect 6 may have a shared cache 14 accessible from any of the CPUs 4 and caches data from the underlying memory system.

[0045] In this example, the interconnect also includes capability write address tracking circuitry 20, which is detailed below. In other examples, some or all of the capability write address tracking circuitry 20 may be distributed across a single processor core 4.

[0046] Figure 2 An example of a component within a given CPU 4 is shown. The processor core 4 may include a processing pipeline with multiple pipeline stages, including: a fetch stage 30 for fetching program instructions from an instruction cache 32; a decode stage 34 for decoding the fetched instructions to generate control signals for controlling the remaining pipeline stages to execute the actions represented by those instructions; a publish stage 36 for checking if any operands required by the instructions are available in register 38 and, if so, publishing the instructions for execution; an execution stage 39 for executing the published instructions to perform a corresponding type of processing operation based on the specific decoded instruction; and a write-back stage 40 for writing the result of the executed instructions back to register 38. In this example, the execution stage 39 includes multiple execution units for executing different types of instructions. For example, the execution unit may include: an arithmetic / logic unit (ALU) 42 for performing arithmetic or logical instructions on integer operands; a floating-point unit 44 for performing floating-point instructions on operands in floating-point format; and a load / store unit 46 for performing load operations to load data from the memory system into register 38 or for performing store operations to store data from register 38 into the memory system. It should be understood that other types of execution units may also be provided. Furthermore, this is merely one example of a possible pipelined architecture, and other types of pipeline stages may also be provided. For example, in a processor that supports out-of-order processing, the pipeline may also include a renaming stage for performing register renaming to map the architectural registers specified by the instructions to the physical registers provided in the hardware.

[0047] Processor core 4 also includes a memory management unit (MMU) 50, which manages access to memory upon request from load / store unit 46. MMU 50 performs address translation to convert virtual addresses provided by load / store unit 46 into physical addresses for identifying required data from the memory system. Address translation is performed with reference to address translation data in a page table structure stored in memory. MMU 50 includes one or more translation back buffers (TLBs) 52 that act as address translation caches to cache information derived from the page table structure. TLB 52 may cache the page table entries themselves and / or may cache information about the addresses of page table entries visible in memory for translating specific virtual addresses, such that address translation of addresses with relevant information cached within TLB 52 can be performed faster than addresses requiring page table traversal to locate the relevant address translation information within the page table structure in memory. In some embodiments, MMU 50 may include a single TLB. Alternatively, the MMU50 can have multiple levels of TLBs (52), where the virtual address is first searched in the first-level TLB. If it is not found in the first-level TLB, it can be searched in the second-level TLB to balance TLB capacity and latency. Additionally, although for simplicity... Figure 1 It is not shown in the diagram, but instructions fetched from instruction cache 32 can also be addressed using MMU 50 or a separate instruction-side MMU different from the data-side MMU 50.

[0048] The CPU 4 in this example may include a Level 1 data cache 54, accessed in response to load / store instructions based on physical addresses identified by the MMU 50, and a shared Level 2 cache 56 shared between data and instructions, accessible in case of misses in either the Level 1 instruction cache 32 or the Level 1 data cache 54. It should be understood that this is merely one example of a possible cache hierarchy, and other arrangements are possible. Furthermore, more than two levels of cache may be provided within the CPU 4 before being sent to memory in case of a miss in the last level of cache provided within the CPU. This allows for flexible modifications to the precise design of the CPU 4.

[0049] Register 38 includes various types of registers. Register 38 may include a set of N general-purpose registers 60, which are used to store operands of instructions and the results of executed instructions. General-purpose registers 60 may include integer registers and floating-point registers. Additionally, register 38 may include a control register 62, which stores control parameters that control the functionality of processor core 4. Several different types of control registers may exist, such as a program counter indicating the address corresponding to the current execution point, a status flag that can be set based on the results of previously executed instructions, and a current mode register indicating the current system operating mode. Figure 2 In the example, control register 62 is shown as including a current execution context identifier register 64, which can store an indication of the current execution context identifier associated with the execution context currently being executed by the processing pipeline. The processor can support the execution of different software procedures, and each software procedure can have a corresponding execution context identifier, more specifically, an address space identifier (ASID). The address space identifier can be used by MMU 50 to locate different sets of page table structures for the corresponding software procedures, and entries in TLB 52 can be marked with the corresponding ASID to ensure that address translation requests triggered by a given execution context can only match TLB entries corresponding to that execution context.

[0050] like Figure 2 As shown, processor core 4 may also have a set of capability registers 70 with storage capacity. In this example, M capability registers are provided, namely C0 to C10. M-1Each capability register 70 may store a capability including an address pointer 72 indicating a specific address in memory and associated pointer usage restriction information 74 that defines one or more conditions restricting the valid use of the pointer stored in the pointer field 72. The pointer usage restriction information includes indications of the allowed address range that defines the pointer 72. In this example, the allowed range is encoded by a base value 76 identifying the starting address of the allowed range and a limit value 78 implicitly or explicitly identifying the ending address of the allowed range (the limit value 78 may be encoded as an absolute address or as a size or offset to be applied to the base address 76). It should be understood that the allowed range information may be encoded in other ways, for example, by a range identifier that may then point to a separate table including the base value 76 and the limit value 78. In addition to the range information 76, 78, the capability register may also store permissions 80 that impose further usage restrictions on the pointer. For example, permission 80 may specify that the allowed address range corresponding to the capability is read-only or read-write. Additionally, permission 80 can specify whether to allow the fetching and execution of instructions stored at addresses within the corresponding address range. Furthermore, permissions can specify whether to allow the use of the corresponding capability to control the loading or storage of other capabilities. Another type of permission can specify whether a capability can be shared with other software processes or restricted to use only by the current software process. Additionally, permissions can specify which permission levels of the software are allowed to use the capability. It should be understood that any one or more of these additional usage restrictions can be imposed by permission 80, and all of these permissions need not be supported by the given processor architecture.

[0051] Thus, in general, by limiting one or more usage restrictions, including at least one allowed range of pointers 72, it means that the use of pointers 72 is restricted in its applicability, and this can be used to avoid common software attacks, such as buffer overflows or access to arbitrary memory addresses.

[0052] like Figure 3 As shown, when a capability is stored in the memory system, in addition to pointer 72 and usage restriction information 74, the capability may also have an associated tag value 82, which specifies whether the capability is valid. This tag 82 is used by hardware to distinguish the memory location storing the capability from the memory location storing regular non-capability data. The tag value 82 is software transparent, meaning it is not part of an address or memory, and therefore can be separated from the capability itself.

[0053] The instruction set architecture supported by the processing pipeline may include instructions that interact with capabilities. For example, the instruction set architecture may include support for: capability setting instructions for writing capabilities to a capability register in capability register 70; instructions for loading capabilities from memory into capability register 70; instructions for storing capabilities from capability register 70 into memory; and instructions for controlling access to memory using capabilities stored in capability register 70 to control data or instructions. When access to memory is controlled using capabilities stored in capability register 70, capability checking circuitry 86 checks the use of capabilities in a specified capability register to determine whether the scenario in which the capability is used is valid based on the range information 76, 78 and permission 80 of the capability specified in the referenced capability register 70. For example, capability checking circuitry 86 may check whether pointer value 72 is within the allowed range defined by range information 76, 78, and whether the requested operation type (e.g., read or write or instruction fetch) is permitted under a given specified permission 80. Therefore, the hardware of the capability checking circuit 86 ensures that attempts to access information outside the permitted address region using capabilities will fail, and attempts to perform inappropriate types of operations within the specified address region may also fail and potentially cause security anomalies. Memory permissions recorded in the page table structure of certain regions can support limiting certain regions to capability-only access (and prohibiting non-capability read / write operations), which can force the protection provided by capabilities to be prevented from being bypassed in certain regions. Additionally, some implementations can provide architectural support for an operating mode in which only capability-controlled access is allowed, and non-capability-controlled access to memory can be prohibited; this mode can be selected if it is desirable to ensure that all access to memory requires capability protection.

[0054] Therefore, an architecture that provides support capabilities can offer spatial protection against attacks. However, problems may still exist, because, for example... Figure 3 As shown in the upper part, the software has the ability to freely move, copy, and store capabilities, so the same capability C0 can be stored in multiple memory locations throughout the entire memory address space. For example, Figure 3 One scenario is illustrated where the capability C0 corresponding to address range A, specified by range information 76 and 78, is copied to three different locations B, C, and D within the address space. Even if memory address region A is subsequently released and freely available for use by other software processes, it is risky to allow other processes to use that region for potentially sensitive information if there is no guarantee that the faulty capability C0 is not still stored in other regions of the memory address space that have range information covering the previously referenced region A.

[0055] As an example of an attack that exploits this type of failure capability, Figure 4This illustrates a "use-after-release" attack between a victim application and an untrusted library. It assumes that the underlying code and data segments are spatially isolated from each other based on capabilities. The attack relies on the victim intentionally sharing a portion of its memory with the attacker in the form of capabilities C1 and C3. For example, an image processing application grants a filter library access to the memory where images are stored. The attacker hides C1 during the first call (by copying capability C1 to a memory region allocated to the attacker) and then restores it during the second call. Simultaneously, the victim process releases the area covered by capability C1 and allocates a new memory region covered by capability C2, which will be used to store some sensitive data. Since memory allocators typically reuse previously released memory, C2 may overlap with the memory covered by C1. Thus, although the attacker is not granted access to capability C2 and the victim may therefore expect C2 to be sufficient to prevent access to secrets, the attacker may use the disabled capability C1 to extract secret information stored in the area associated with C2.

[0056] One way to mitigate the attacks described above is to avoid reusing memory (i.e., prohibiting the reuse of the memory region associated with C1 after it has been freed). For systems with large virtual address spaces and applications that do not allocate large amounts of memory or perform frequent allocation-free cycles, implicit memory leaks may be acceptable. However, even those systems may suffer performance penalties due to cache pollution caused by inherent memory fragmentation. In any case, some form of revocation strategy may be needed to invalidate all instances of the freed capacity, thereby enabling safe reuse of memory.

[0057] For example, capabilities to be released can be added to an undo list. Memory covered by these capabilities is not reused until all instances of such capabilities have been invalidated from memory. Before triggering an undo scan, the undo policy can collect capabilities in the undo list that have reached a specific invalidated memory threshold (e.g., 25% of heap space). The scan will then:

[0058] - Search for all registers and memory currently accessible to the target application.

[0059] - Identify all disabled capabilities stored therein, allowing address ranges 76 and 78 to overlap with at least one region identified in the revocation list; and

[0060] - These failed capabilities are rendered invalid by removing the label 82 of the failed capabilities identified during the scan.

[0061] However, when performing such a scan, there is a risk that such other threads may write failure capabilities into the scanned memory region if other threads run in parallel with the scan thread (e.g., on other processor cores 4), or if the scan software is interrupted and then other code that was interrupted is executed before the scan software recovers from the interruption. This could result in the risk that some failure capabilities will not be found in the scan.

[0062] A naive approach to this problem is to "stop everything" during the scan, i.e., stop all other threads and disable interrupts. However, this approach has a highly undesirable impact on performance, and is even unacceptable for real-time applications.

[0063] One way to speed up undoing scans is to restrict the movement of capabilities. For example, a "per capability" permission bit can be used to determine whether a capability can be used as the base address for capability storage. The allocator can then exclude all memory regions from the scan because it does not have the permission bit set for at least one capability. Similar permission bits can also be assigned to pages. This could allow the operating system (OS) to exclude large memory regions from the scan because these regions cannot accommodate capabilities.

[0064] The "Storable Capabilities" permission bits restrict which memory regions can store capabilities. However, they do not provide any information about the actual contents of these regions; for example, even if a page is storeable, it may not contain any capabilities at runtime and therefore need not be scanned. To address this, a "Dirty Capabilities" bit can be associated with each page. It is set when a capability is first written to a particular page. The scanning algorithm can evaluate this bit to skip those pages during the scan.

[0065] However, the above method exhibits three key drawbacks:

[0066] a) Scaling

[0067] - Applications may exhibit large memory footprints, such as databases containing several trillion bytes;

[0068] - The scanning process may have to retrieve and evaluate permission bits corresponding to a large number of pages and / or capabilities;

[0069] This can lead to significant performance overhead, especially if the corresponding page table is not already in the cache at the start of the scan.

[0070] b) Number of pages that can be excluded from the scan

[0071] - Permission bits may depend on information available at compile time, and therefore may be too lenient;

[0072] Dirty bits are more dynamic, but may approach the same number of pages as permission bits over time; that is, the likelihood of capabilities being stored on a page increases over time. It is possible to clear dirty bits during a scan, but only pages known to no longer contain any capabilities can be cleared.

[0073] c) Provide information in the software to avoid having to "stop everything" during the scanning process.

[0074] - To allow for parallel threads or interruptions during the scan, it is possible to detect or prevent the writing of faulty capabilities to previously scanned memory.

[0075] - Page permissions can be used to temporarily prevent capabilities from being written to scanned pages. However, this will also affect regular capability writing to the area. Exception handling may be required to identify those cases.

[0076] Since dirty bits can only be cleared for pages that do not retain any capabilities, they are not suitable for writes that only track failed capabilities.

[0077] Therefore, the above methods have a significant performance impact. In contrast, such as Figure 1 and Figure 2 As shown, the method described below provides a capability write address tracking circuit 20 in hardware, which tracks the address that receives a capability write operation within the capability write address tracking structure 100. The capability write address tracking circuit 20 can be as follows: Figure 1 As shown, it is shared among multiple processor cores 4, or as... Figure 2 The setup shown is within a single processor core, or a combination of these methods, with some tracking hardware shared and others set up separately for each core 4. The capability write address tracking structure 100 itself can be a dedicated hardware storage unit or a data structure actually stored in the memory system and maintained by the capability write address tracking circuitry 20. The capability write address tracking circuitry 20 may be associated with: an enable register 102, which controls whether the address for tracking capability write operations (the operation of writing capabilities from capability register 70 to memory) is enabled or disabled; and multiple tracking metadata registers 104, which can identify the location of the tracking structure in memory in the specific implementation using the tracking structure stored in the memory system. For example, the metadata register 104 may include a base address 106 that identifies the starting address of the tracking structure, and a counter register 108 that marks the point within the tracking structure where the next entry will be written. Additionally, the metadata register may include a limit register 110 that can specify the maximum size allowed for the address tracking structure to prevent overflow. The various registers 102 and 104 can be updated by software.

[0078] Thus, by providing trace circuitry 20 in hardware, undo scans can be accelerated by avoiding the need for a "stop everything" scan. Capability writes to memory are tracked during the undo scan. At the end of the scan, this trace information can be used for selective rescanning to locate failed capabilities written by other threads or during scan interruptions. In some embodiments, capability write address tracking may use Translation Backing Buffer (TLB) 52. For example, the TLB may not track capability writes outside of undo scans. Capability write tracking can be enabled at the start of the scan. During the scan, the TLB 52 can set a dirty bit when a capability is written to the corresponding address page, and set it again when the dirty bit transitions from 0 to 1, recording the address and ASID of the dirty page in a structure 100 maintained in memory, whose address is identified by metadata register 104. The scan algorithm itself does not write any valid capabilities to memory; therefore, it does not set any dirty bits, and any dirty bits set may be caused by capability writes performed by other threads (which may execute in parallel with the scan algorithm or during scan interruptions). At the end of the scan, the scanning algorithm may check the capability write address trace structure 100 and selectively rescan pages indicated as dirty to locate and invalidate faulty capabilities written by other threads or during interruptions, and clear their records in the trace structure 100. Optionally, to prevent further writing of faulty capabilities to avoid subsequent rescans, the scanning algorithm may set storage capability permissions during the rescan process to prevent capability writes, or use a "stop everything" approach to stop processing by other threads.

[0079] Figure 5 A hardware example is shown that can be used to track pages that have been "tainted" by capability writes. TLB entries in the TLB52 can be expanded to each store a dirty bit (capability write indicator) 120. Note that this dirty bit 120 does not extend to the page table, therefore it does not affect the already large overhead associated with those tables (the dirty bit may simply be removed when the TLB entry is evicted from the last level of the TLB storing the dirty bit 120). Figure 5 As shown in decision box 122, the updating of the dirty bit 120 can be enabled / disabled by the enable control register 102 (set by software) to restrict the tracking of capability storage to certain periods selected by the software, such as when the software is performing a failed capability undo scan. Thus, the dirty bit will not be set when capability writes are not being tracked, even if a capability is written to a previously uncontaminated given page. Additionally, as... Figure 5 As shown in decision box 124, in the case of writing non-capability data, writing a page of a given type does not cause the dirty bit 120 to be set, and tracks specific capability write operations that request the capability to be written to the corresponding location in memory.

[0080] Additionally, when the dirty bit 120 of a given address page transitions from 0 to 1, the address of the corresponding page and its Address Space Identifier (ASID) are recorded in the write-to-address trace structure 100. While recording the ASID is not mandatory, it can be useful to allow software to avoid unnecessary rescanning of pages associated with different ASIDs that overlap with those used by the process being scanned.

[0081] Figure 5 Two examples are shown that can be used to write address / ASID information onto dirty pages into address trace structure 100. These examples are alternative solutions and it is not necessary to provide both simultaneously.

[0082] Figure 5 The top example illustrates a dirty page buffer that uses base address register 104 and counter register 108 to record information sequentially. When capability write tracking is enabled, each time a new page (not previously indicated as dirty in the corresponding TLB entry) is contaminated by a capability write operation, capability write address tracking circuitry 20 writes the ASID and page address of the dirty page to the entry at address "Dst," which is obtained by adding a specific number of increments of a given size to the base address in base address register 104, where the number of increments is selected based on counter register 108. Since the buffer may be stored in memory, a limit register 110 is used to prevent overflow, and an exception signaling is issued if the calculated address Dst exceeds the limit. In response to an exception, the exception handler may trap into the operating system or other monitoring code and may trigger various buffer overflow handling responses, including any of the following: (i) updating limit register 110 to expand the space available for the dirty page buffer (possibly after moving data from a memory region beyond the buffer to a different part of the address space); (ii) allocating a new memory block larger than the previously allocated buffer for the dirty page buffer, copying the entries of the current dirty page buffer to the newly allocated memory block, and then updating base address 106 and limit register 110 to correspond to the newly allocated memory block; or (iii) causing the scanning software to restart its scan, hoping that fewer capability writes will occur during the next scan. Metadata register 104 and buffer contents 100 can be restricted to access only by software with the necessary permissions (e.g., undo codes). This can be guaranteed, for example, by using data capabilities covering buffers not shared outside of undo codes and setting permission bit 80 in the code capabilities covering undo codes.

[0083] Assuming reasonable fast undo scans, multiple threads are unlikely to execute on the same kernel. Therefore, as... Figure 5As shown, storing ASIDs along with each buffer entry can be inefficient. As an alternative, the dirty page buffer 100 can record each page address contaminated by capability writes, but can maintain a smaller list of ASIDs, adding only unique ASIDs not previously observed in capability writes. Alternatively, instead of using an exact list of ASIDs, a single register can use a Bloom filter (separate from the exact list of dirty page addresses in the dirty page buffer) to track all observed ASIDs. This strikes a balance between reduced memory overhead and potential false positives and false negatives.

[0084] use Figure 5 The dirty page buffer method shown in the upper part offers some advantages:

[0085] • A counter can be used to determine the index of the last valid entry (counter – 1), so it is not necessary for each entry to contain a valid bit;

[0086] • The hardware complexity is limited because an adder can be used for address calculation and counter update.

[0087] • The TLB circuitry in the MMU 50 is then used to handle writes to the memory;

[0088] • The address recognition accuracy is high, so the software only needs to rescan pages that are known to have been corrupted by the ability to write.

[0089] Figure 5 The lower half of the diagram illustrates an alternative method that uses a Bloom filter as a replacement for the page buffer. Like the buffer, it updates as the dirty bit transitions from 0 to 1, but uses a hash of the page address and ASID, and sets any bits of the Bloom filter corresponding to the result of that hash (if not already set). This provides a less precise address trace. When reading trace structure 100 to determine which pages to rescan, the scanning software may assume that any page address that conflicts with the Bloom filter representation (i.e., the hash of the page address gives a value such that the bits within the matching hash values ​​set in all Bloom filter representations are 1) is likely one of the pages contaminated by capability writes. This can include some false positives where pages that are not actually contaminated by capability writes are detected as contaminated because the hash of their address aliased with the bit combinations set in response to capability writes to other pages. While such false positives can sometimes be costly (in terms of the performance cost of unnecessarily rescanning some pages), the risk depends on the hash algorithm used and the address distribution of dirty pages, and this risk may be acceptable for achieving other beneficial effects, such as:

[0090] • Reduces hardware complexity (because it only requires simple hash and OR circuitry, eliminating the need for full adders or memory accesses).

[0091] • Capable of handling an unlimited number of pages without the risk of buffer overflow;

[0092] • Do not use system memory

[0093] • No exceptions need to be set to increase the number of entries.

[0094] • Unaffected by duplicates (If the same TLB entry is evicted, re-fetched, and contaminated again, updating the Bloom filter based on the page address does not change the size of the structure or identify the page as needing to be rescanned. This is different from the dirty page buffer, where there is a risk of duplicate entries that need to be processed to eliminate duplicates or waste performance in unnecessary rescans).

[0095] Many other alternatives exist to the provided examples. For instance, the two examples could be combined into a table structure indexed based on the hash of the page address. Each entry could then maintain a Bloom filter to represent all pages that overlap with it. This mitigates the need to increase the buffer size at runtime and reduces the risk of misidentification. Alternatively, using a linked table instead of a Bloom filter for each entry could eliminate the risk of misidentification, but it would also increase the complexity of the structure. Note that the limited buffer size mentioned above is unlikely to be a significant factor, as the number of pages contaminated during undo scans is likely to be small.

[0096] In a multi-kernel environment, undoing a scan might require preventing or detecting writes of faulty capabilities to previously scanned memory, handling legitimate access to currently scanned pages, and locating faulty capabilities within registers and other memory structures relevant to other kernels. The aforementioned dirty page tracking structures can detect writes of faulty capabilities to previously scanned memory without halting other threads. Since they only detect, not prevent, such writes, rescanning dirty pages may be necessary. To avoid the need for subsequent iterations, the algorithm might halt everything during rescanning. Alternatively, it might temporarily clear the "storeable capability" permission bits of the pages being scanned. Therefore, parallel threads attempting to write capabilities to these pages will be trapped in the OS. The corresponding exception handlers will need to be clearly scanned. Outside of the scan, it will handle legitimate page permission violations. During the scan, it can delay returning until the scan is complete or return the thread immediately. The latter will trigger a replay of the attack capability storage, leading to further exceptions until the scan is completed by restoring the original page permissions. Even during continuous scanning, more complex handlers might allow threads to continue.

[0097] The tracing structure of this invention can be shared between kernels or copied for each individual kernel. Since initial page contamination is considered rare, sharing the associated hardware overhead between kernels may be feasible. In the case of a copied structure, the scanning algorithm can use ASID to skip structures irrelevant to the currently operating process. As mentioned above, the provision of ASID is optional.

[0098] One method for software to clear disabled capabilities from registers in another kernel is to identify the relevant thread based on their ASID, trigger a context switch, and evaluate the contents of the swapped-out registers in memory. These context switches can be performed at the end of the undo scan (i.e., when all disabled capabilities have been removed from memory). This allows for immediate return to the swapped-out thread without the risk of enabling it to retrieve disabled capabilities from memory.

[0099] Although Figure 5 The example illustrates tracking dirty pages in the TLB, but another type of cache (such as L1 data cache 54) could also be used to track address blocks accepting capability writes. Additionally, in some embodiments, it may not be necessary to use dirty bit 120 to track addresses accepting capability writes at all. In these embodiments, when capability write address tracking is enabled, after a capability is written to a given address, the tracking circuitry 20 can simply update the capability write address tracking structure 100, regardless of whether a capability write to the same address has already been completed. For example, in the Bloom filter example, the disadvantage of redundantly updating the structure multiple times for the same address may be minor, making the overhead of checking dirty bit 120 potentially unnecessary. On the other hand, for the dirty page buffer example, the use of dirty bit 120 is very useful for reducing the likelihood of duplicate entries being allocated to the buffer.

[0100] Figure 6 A flowchart is shown of a method for performing a scan of failed capabilities using the capability write address tracking structure 100 of the type described above. Figure 6 The method shown illustrates the steps performed by software that performs a memory scan to locate faulty capabilities. Figure 6 The method is not shown. The hardware will perform operations in the background, such as updating the capability write address trace structure 100 in response to the detection of capability write requests from various processor cores 4.

[0101] In step 200, optionally, the capability scanning software may reset the capability write address trace structure 100, for example, by clearing all addresses from the capability write address trace structure 100 and all dirty bits in the TLB or other caches used to mark pages that have accepted capability write operations. If it can be guaranteed that the capability write address trace structure has been cleared, for example, if the software always clears the capability write address trace structure 100 after use, a reset operation may not be necessary. Additionally, if the software has just allocated a brand new capability write address trace structure 100 and will therefore use that trace structure first (in a specific implementation where the capability write address trace structure is a region of memory that may be cleared due to allocation), a reset in step 200 may not be required.

[0102] In step 202, the scanning software executes instructions to set the enable register 102 to enable capability write address tracking of the capability write address tracking circuit 20. Thus, when the capability write address tracking circuit 20 detects a capability write operation performed on the corresponding page, it will begin marking entries in TLB 52 as dirty and write the address of any such dirty page to the capability write address tracking structure 100 (or, alternatively, update the imprecise representation of the page address receiving the capability write, for example, using a Bloom filter as described above). This capability write address tracking continues in the background during the scan.

[0103] In step 204, the memory address space is scanned to find faulty capabilities. In step 204, the scanning software reads the next memory address region to be scanned, and when the contents of that memory address region become available, in step 206, the software checks whether the read address region stores faulty capabilities. Here, if a capability's valid tag 82 is set, the capability is considered faulty, and the range information 76, 78 specified for that capability overlaps with any one or more memory address regions specified in the revocation list of address regions to be revoked. This revocation list may be updated when the memory region is released by the operating system, but the scan for faulty capabilities may be postponed until a sufficient number of regions are listed to avoid the performance cost of scanning every time an address region is released. If the read memory address region stores a faulty capability, in step 208, the faulty capability is invalidated by clearing its tag value 82. If the read memory address region does not store any faulty capabilities, step 208 is omitted. In step 210, the software checks whether there is at least one memory address region that still needs to be scanned. If so, the method returns to step 204 to loop through steps 204 to 210 until all required memory address regions have been scanned.

[0104] Once no more memory address regions are available to scan, the method proceeds to step 212. Because there is a risk that other threads or processor cores may have already written capabilities to previously scanned memory address regions, there is a risk that the memory address space may still contain some failed capabilities after the scanning process has checked those regions to see if they store any failed capabilities. Therefore, a selective rescan is performed to check if the address regions indicated by the capability write address trace structure 100 store failed capabilities. However, to ensure that no further capability writes are performed during the rescan, in step 212, before performing the rescan, the scanning software takes measures to make it impossible to perform capability write operations on the rescanned memory. This can be done in different ways. One example might be to simply use a "stop everything" approach, in which all processing by other cores is stopped. However, while the "stop everything" approach does impact performance, as it is only used during the rescan of the small number of memory address regions indicated in the capability write address trace structure 100, its performance impact is far less than the performance impact of stopping everything during the entire main scan cycle from steps 204 to 210. Alternatively, instead of halting other kernel processes, the software can update memory permissions for already scanned memory address spaces to indicate that they are temporarily unavailable for storage capacity during a rescan.

[0105] In step 214, the scan process also disables capability write address tracking by clearing enable register 102, since tracking capability write operations is no longer required.

[0106] In step 216, the scanning software then rescans any memory address regions indicated in the capability write address trace structure 100 and invalidates any faulty capabilities found in those regions. It should be understood that step 216 itself may comprise a loop similar to steps 204 through 210 performed for the main scan operation, but this loop typically requires far fewer iterations than the main loop because it only examines the selected regions as indicated in the capability write address trace structure 100. In the example using the dirty page buffer as described above, once a given region has been rescanned, the corresponding portion of the capability write address trace structure can be cleared. With respect to Bloom filters or other imprecise representations, a rescan may cover any addresses that are hit when the filter representation of that address is queried, which may include some false positives that did not actually receive a capability write operation during the capability write address trace but are still rescanned because their addresses are aliased with bit patterns in the filter representation that are set as a result of capability write operations to other addresses.

[0107] Once the rescanning process 216 is complete, in step 218, the scanning software can re-enable write operations to the scanned memory, for example, by resuming processing of other processor cores or by updating the "Storable Capabilities" permission to allow the capability to be stored in the scanned memory area again.

[0108] Step 212 is optional, and an alternative is to not block capability writes during memory rescanning, capability write address tracking can remain enabled during rescanning, and then multiple iterations of the rescanning process 216 can be performed until no additional addresses are recorded in the capability write address tracking structure 100 before the rescanning is completed.

[0109] If, during a main scan or rescan when capability write address tracking is enabled, capability write address tracking structure 100 reaches or exceeds the maximum capacity specified by limit register 110, an exception may be triggered. The exception handler may then respond to the exception in different ways. The exception handler may update metadata register 104 and allocate additional memory space for tracking structure 100, or the exception handler may simply make... Figure 6 The scanning process was restarted from the beginning, with the hope that fewer write operations would occur during the next scan.

[0110] Thus, in summary, by providing a capability write address tracking circuit 20 in the hardware to maintain tracking information that identifies the selected address to accept capability write operations, it means that the scanning software does not need to stop everything during the main scan of the entire memory address space, which can greatly improve performance.

[0111] Figure 7A specific implementation of a usable simulator is illustrated. While the previously described embodiments implement the invention in terms of means and methods for operating specific processing hardware supporting the technologies involved, it is also possible to provide an instruction execution environment according to the embodiments described herein, which is implemented using a computer program. Such computer programs are generally referred to as simulators, in part because they provide a software-based implementation of a hardware architecture. Types of simulator computer programs include emulators, virtual machines, models, and binary converters, including dynamic binary converters. Typically, the simulator implementation can run on a host processor 330 that supports the simulator program 310, which optionally runs a host operating system 320. In some arrangements, multiple emulation layers may exist between the hardware and the provided instruction execution environment and / or multiple different instruction execution environments provided on the same host processor. Historically, powerful processors were required to provide simulator implementations that execute at a reasonable speed, but this approach may be reasonable in certain situations, such as when it is desirable to run code native to another processor for compatibility or reuse reasons. For example, the simulator implementation may provide additional functionality to the instruction execution environment that is not supported by the host processor hardware, or provide an instruction execution environment that is typically associated with a different hardware architecture. An overview of the simulation is given in the following literature: “Some Efficient Architecture Simulation Techniques”, Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0112] With respect to the embodiments previously described with reference to specific hardware constructions or features, in simulated embodiments, equivalent functionality may be provided by suitable software constructions or features. For example, specific circuitry may be implemented as computer program logic in simulated embodiments. Similarly, memory hardware such as registers or cache memory may be implemented as software data structures in simulated embodiments. One or more hardware elements referenced in the previously described embodiments are present in an arrangement on host hardware (e.g., host processor 330), and where appropriate, some simulated embodiments may utilize the host hardware.

[0113] The simulator program 310 may be stored on a computer-readable storage medium (which may be a non-transitory medium) and provides a program interface (instruction execution environment) to the target code 300 (which may include application programs, operating systems, and management programs), the same as the application interface of the hardware architecture modeled by the simulator program 310. Therefore, the simulator program 310 can be used to execute program instructions of the target code 300 (including instructions that interact with the capabilities described above) from within the instruction execution environment, enabling a host computer 330, which does not actually possess the hardware features of the aforementioned device 2, to emulate these features.

[0114] Simulator code 310 may include instruction decoding program logic 312, which decodes the program instructions of target code 300 and maps them to the corresponding instruction sets defined in the local instruction set of host processor 330. Additionally, simulator code 310 may include register emulation program logic 314, which manages data structures in the host hardware's memory that emulate registers 38, 102, and 104 of the target architecture being simulated. Furthermore, capability validity checking program logic 316 may be provided to perform checks on the capability checking circuit 86 described above, determining whether the requested capability is permitted given its range 76, range 78, and permission 80. Additionally, capability write address tracking program logic 318 may be provided, which, when tracking is enabled, detects capability writes to memory and maintains a capability write tracking structure to provide indication of which pages have accepted capability writes. Thus, simulator code 310 can present target code with architectural features equivalent to the previously described hardware implementation example, allowing the target code to perform a fail capability scan on the host data processing device (which itself may not include capability write address tracking circuitry) in the same manner as if the target code were executed on a device that does have capability write address tracking circuitry 20.

[0115] In this application, the phrase "configured as..." is used to mean that the elements of the device have a configuration capable of performing the defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operation.

[0116] While exemplary embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and various changes and modifications can be made therein by those skilled in the art without departing from the scope of the invention as defined by the appended claims.

Claims

1. An apparatus, the apparatus comprising: A capability checking circuit is configured to perform a capability checking operation to determine whether the use of a capability satisfies one or more usage restrictions, the capability including a pointer and pointer usage restriction information specifying the one or more usage restrictions, the one or more usage restrictions including at least a allowed address range for the pointer; as well as A capability write address tracking circuit, in response to a capability write request that requests a capability to be written to a memory location associated with a capability write target address, updates a capability write address tracking structure based on the capability write target address when capability write address tracking is enabled. The capability write address tracking structure is used to track the capability write target addresses of one or more capability write requests.

2. The apparatus of claim 1, the apparatus further comprising an enable storage element to store a write address tracking enable indication, the write address tracking enable indication indicating whether the write address tracking capability is enabled or disabled.

3. The apparatus of claim 2, wherein in response to the capability write request, when the capability write address tracking enable indication indicates that capability write address tracking is disabled, the capability write address tracking circuitry is configured to update the capability write address tracking structure based on the capability write target address omission of the capability write request.

4. The apparatus according to any one of claims 2 and 3, wherein the apparatus includes processing circuitry to execute program instructions; and The capability to write address tracking enable indication can be updated by the processing circuit in response to program instructions executed by the processing circuit.

5. The apparatus of claim 1, wherein the apparatus comprises a cache structure, the cache structure comprising a plurality of entries, each entry storing cache information associated with a corresponding memory address region; and In response to the capability write request, when the capability write address tracking structure is updated based on the capability write target address, the capability write address tracking circuit is configured to set a capability write indication flag in the entry of the cache structure corresponding to the memory address region containing the capability write target address.

6. The apparatus of claim 5, wherein, in response to the capability write request, when capability write address tracking is enabled and the capability write target address corresponds to a memory address region for which the capability write indicator has been set in the corresponding cache entry, the capability write address tracking circuit is configured to update the capability write address tracking structure based on the capability write target address omission.

7. The apparatus according to any one of claims 5 and 6, wherein the cache structure includes an address translation cache for storing address translation information derived from a page table structure in memory.

8. The apparatus of claim 7, wherein when an entry with the capability write indicator set is evicted from the address translation cache, the address translation cache is configured to discard the capability write indicator without writing the capability write indicator back to the page table structure in memory.

9. The apparatus according to any one of claims 1 to 3, the apparatus comprising processing circuitry to process instructions from one of a plurality of software processes, each software process being associated with a corresponding execution context identifier; and When capability write address tracking is enabled, the capability write address tracking circuitry is configured to maintain execution context identifier tracking information for tracking one or more execution context identifiers associated with one or more capability write requests.

10. The apparatus according to any one of claims 1 to 3, wherein the apparatus includes processing circuitry to execute program instructions; In response to a capability write address track reset instruction, the processing circuit is configured to reset the capability write address track structure.

11. The apparatus according to any one of claims 1 to 3, wherein the write-capable address tracking structure comprises a storage cell provided in hardware separate from the memory.

12. The apparatus according to any one of claims 1 to 3, wherein the capability write address tracking structure comprises a data structure stored in memory.

13. The apparatus of claim 12, wherein the apparatus includes at least one tracking metadata storage element for storing at least one of the following: The capability is written to the base address of the address tracking structure; The capability to be updated is indicated in the next entry of the address tracking structure; and This indicates a limit on the maximum allowed size of the write capability to the address tracking structure.

14. The apparatus according to any one of claims 1 to 3, wherein when capability write address tracking is enabled, the capability write address tracking structure precisely tracks one or more capability write target addresses of one or more received capability write requests.

15. The apparatus according to any one of claims 1 to 3, wherein when capability write address tracking is enabled, the capability write address tracking structure does not precisely track one or more capability write target addresses of the received one or more capability write requests, such that a query on the capability write address tracking structure may allow an address other than the one or more capability write target addresses to be incorrectly identified as one of the one or more capability write target addresses.

16. The apparatus according to any one of claims 1 to 3, wherein the capability write address tracking circuitry is configured to trigger an abnormal signaling in response to detecting that the capability write address tracking structure has reached its capacity limit.

17. The apparatus according to any one of claims 1 to 3, wherein the apparatus comprises a plurality of processor cores; and The ability to write address tracking structures is shared among the multiple processor cores.

18. A method, the method comprising: A capability check operation is performed to determine whether the use of a capability meets one or more usage restrictions, the capability including a pointer and pointer usage restriction information specifying the one or more usage restrictions, the one or more usage restrictions including at least the allowed address range of the pointer; as well as In response to a capability write request that requests to write capability to a memory location associated with a capability write target address, when capability write address tracking is enabled, the capability write address tracking structure is updated based on the capability write target address, the capability write address tracking structure being used to track the capability write target addresses of one or more capability write requests.

19. A computer program for controlling a host data processing device to provide an instruction execution environment for executing object code, the computer program comprising: Capability checking program logic, which is used to perform capability checking operations to check whether the use of a capability meets one or more usage restrictions, the capability including a pointer and pointer usage restriction information specifying the one or more usage restrictions, the one or more usage restrictions including at least the allowed address range for the pointer; as well as Capability write address tracking logic, in response to a capability write request that requests a capability to be written to a memory location associated with a capability write target address, updates a capability write address tracking structure based on the capability write target address when capability write address tracking is enabled. The capability write address tracking structure is used to track the capability write target addresses of one or more capability write requests.

20. A method, the method comprising: Capability write address tracking is enabled by a capability write address tracking structure for tracking capability write target addresses of one or more capability write requests, wherein the capability write request includes a request to write a capability to a memory location associated with the capability write target address specified by the capability write request, and the capability includes a pointer and pointer usage restriction information specifying one or more usage restrictions, the one or more usage restrictions including at least a allowed address range for the pointer; The memory is scanned to invalidate failure capabilities, which include the ability for which the allowed address range overlaps with one or more target regions of the address; as well as After scanning the memory, one or more selected memory address regions corresponding to the addresses tracked by the capability write address tracking structure are rescanned to invalidate the invalid capabilities stored in the one or more selected memory address regions.

21. A computer program for controlling a data processing apparatus to perform the method according to claim 20.

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