Microelectronic devices, electronic systems, and related methods including an oxide material between adjacent stacked groups

Abstract

This application relates to microelectronic devices, electronic systems, and related methods that include an oxide material between adjacent stacks. A microelectronic device includes: a stack including alternating layers of a conductive material and an insulating material, the stack including pillars that include a channel material extending through the alternating layers of the conductive material and the insulating material; a conductive contact located between adjacent stacks and in electrical communication with the channel material of the adjacent stacks; and an oxide material located between the adjacent stacks, the oxide material extending between the uppermost layer of a first stack and the lowermost layer of a second stack adjacent to the first stack. Related electronic systems and methods of forming the microelectronic devices and electronic systems are also disclosed.

Description

[0001] Cross - Reference to Related Applications

[0002] This application is a national stage entry of International Patent Application PCT / US2020 / 070313, filed on Jul. 27, 2020, designating the People's Republic of China and published in English as International Patent Publication WO2021 / 030826A1 on Feb. 18, 2021, which claims the benefit under Article 8 of the Patent Cooperation Treaty of U.S. Patent Application No. 16 / 541,944, filed on Aug. 15, 2019. Technical Field

[0003] The embodiments disclosed herein relate to microelectronic devices and electronic systems that include an oxide material between stacks of alternating layers of insulating and conductive materials, and to related methods. More specifically, embodiments of the present disclosure relate to microelectronic devices and electronic systems that include memory strings extending through stacks of alternating layers of insulating and conductive materials and include an oxide material that does not exhibit charge trapping characteristics, and to related methods of forming the microelectronic devices and electronic systems. Background Art

[0004] An ongoing goal in the semiconductor industry has been to increase the memory density of memory devices (e.g., the number of memory cells per memory die), such as non-volatile memory devices (e.g., NAND flash memory devices). To meet the demand for higher-capacity memories, designers have strived to increase the memory density (i.e., the number of memory cells in a given area of an integrated circuit die). One way to increase the memory density is to reduce the feature size of individual memory cells.

[0005] However, as the feature size is reduced, the thicknesses of different portions of a memory cell, such as a tunneling dielectric material, may also exhibit a similar size reduction. A thin tunneling dielectric material may result in an increased risk of failure of the tunneling dielectric material and an increased risk of charge leakage from the storage node of a memory cell.

[0006] Another approach to increasing the memory density in non-volatile memory devices is to utilize a vertical memory array (also referred to as a "three-dimensional (3D) memory array") architecture. Conventional vertical memory arrays include semiconductor pillars extending through openings in a stack of conductive structures (e.g., word lines, control gates) and dielectric material at each junction of the semiconductor pillars and the conductive structures. This configuration permits a greater number of transistors to be positioned in the cells of a die area compared to a structure with a conventional planar (e.g., two-dimensional) arrangement of transistors by building the array upward (e.g., longitudinally, vertically) on the die. As the demand for higher density of memory cells increases, the semiconductor pillars are patterned to have a smaller pitch between adjacent pillars. Additionally, multiple stacks including the stack of conductive structures and dielectric material can be patterned one after another to facilitate an increase in the number of memory cells in the device. SUMMARY OF THE INVENTION

[0007] In some embodiments, a microelectronic device includes: a stack of alternating layers of conductive material and insulating material, the stack including pillars of channel material extending through the alternating layers of the conductive material and the insulating material; conductive contacts located between adjacent stacks and in electrical communication with the channel material of the adjacent stacks; and an oxide material located between the adjacent stacks, the oxide material extending between the uppermost layer of a first stack and the lowermost layer of a second stack adjacent to the first stack.

[0008] In other embodiments, a method of forming a microelectronic device includes: forming a first stack including pillars of channel material extending through a stack of alternating layers of a first material and a second material; forming a nitride material adjacent to the first stack; forming an opening in the nitride material and forming a conductive contact in the opening; removing the nitride material; forming an oxide material adjacent to the conductive contact; and forming a second stack adjacent to the oxide material, the second stack including alternating layers of the first material and the second material.

[0009] In still other embodiments, an electronic system includes a first stack and a second stack. Each of the first stack and the second stack includes a stack of alternating layers of conductive material and insulating material and pillars of channel material extending through the alternating layers of the conductive material and the insulating material. The electronic system further includes a conductive contact between the channel material of the pillars of the first stack and the channel material of the pillars of the second stack and an oxide material adjacent to the conductive contact and located between the first stack and the second stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1ASimplified cross-sectional view of a microelectronic device according to an embodiment of the present disclosure;

[0011] Figure 1B is a simplified cross-sectional view of a microelectronic device taken along section line B-B of Figure 1A ;

[0012] Figure 1C Simplified cross-sectional view of a memory cell according to an embodiment of the present disclosure;

[0013] Figure 2 Simplified cross-sectional view of a microelectronic device according to an embodiment of the present disclosure;

[0014] Figures 3A - 3D Simplified cross-sectional view showing a method of forming a microelectronic device according to an embodiment of the present disclosure;

[0015] Figure 4 Simplified cross-sectional view showing a method of forming a microelectronic device according to other embodiments of the present disclosure;

[0016] Figure 5 Block diagram of an electronic system according to an embodiment of the present disclosure; and

[0017] Figure 6 is a processor-based system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] The diagrams included herein are not intended to be actual views of any particular system, microelectronic device, electronic system, or memory cell, but are merely idealized representations for describing the embodiments herein. Elements and features common between the diagrams may retain the same numerical designations, but for ease of the following description, the reference numerals begin with the numeral of the drawing in which the element is introduced or most fully described.

[0019] The following description provides specific details, such as material types, material thicknesses, and processing conditions, in order to provide a full description of the embodiments described herein. However, one of ordinary skill in the art should understand that the embodiments disclosed herein may be practiced without these specific details. In fact, the embodiments may be practiced in conjunction with conventional manufacturing techniques employed in the semiconductor industry. Additionally, the description provided herein does not form a complete description of a microelectronic device or an electronic system, or a complete description of the process flow for manufacturing a microelectronic device or an electronic system. The structures described below do not form a complete microelectronic device or an electronic system. Only those process actions and structures necessary to understand the embodiments described herein are described in detail below. Additional actions to form a complete microelectronic device or an electronic system may be performed by conventional techniques.

[0020] The materials described herein can be formed by conventional techniques, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). Alternatively, the materials can be grown in-situ. Depending on the specific material to be formed, the technique for depositing or growing the material can be selected by one of ordinary skill in the art. Unless the context indicates otherwise, material removal can be achieved by any suitable technique including but not limited to the following: etching, polishing planarization (e.g., chemical mechanical planarization), or other known methods.

[0021] As used herein, the terms “longitudinal,” “vertical,” “lateral,” and “horizontal” are with reference to the major plane of a substrate (e.g., a base material, a base structure, a base configuration, etc.) in or on which one or more structures and / or features are formed and are not necessarily defined by the earth's gravitational field. A “lateral” or “horizontal” direction is a direction generally parallel to the major plane of the substrate, while a “longitudinal” or “vertical” direction is a direction generally perpendicular to the major plane of the substrate. The major plane of the substrate is defined by a substrate surface having a relatively large area compared to other surfaces of the substrate.

[0022] As used herein, the term “substantially” with respect to a given parameter, property, or condition means and includes the degree to which a given parameter, property, or condition is understood by one of ordinary skill in the art to meet a degree of deviation (e.g., within an acceptable tolerance). As an example, depending on the specific parameter, property, or condition being substantially met, the parameter, property, or condition can meet at least 90.0%, meet at least 95.0%, meet at least 99.0%, meet at least 99.9%, or even meet 100.0%.

[0023] As used herein, “about” or “substantially” with reference to a numerical value of a particular parameter includes the recited numerical value and a degree of deviation from the recited numerical value that is understood by one of ordinary skill in the art to be within the acceptable tolerance of the particular parameter. For example, “about” or “substantially” with respect to a numerical value can include additional numerical values that are within the range of 90.0% to 110.0% of the recited numerical value, such as within the range of 95.0% to 105.0% of the recited numerical value, within the range of 97.5% to 102.5% of the recited numerical value, within the range of 99.0% to 101.0% of the recited numerical value, within the range of 99.5% to 100.5% of the recited numerical value, or within the range of 99.9% to 100.1% of the recited numerical value.

[0024] As used herein, spatial relative terms, such as "under", "below", "lower", "bottom", "above", "upper", "top", "front", "rear", "left", "right", etc., may be used for purposes of easy description to describe the relationship of one element or feature to another element or feature as shown in the figures. Unless otherwise specified, spatial relative terms are intended to cover different orientations of the material in addition to the orientation depicted in the figures. For example, if the material in the figures is inverted, an element described as "under" or "below" or "beneath" or "at the bottom" of other elements or features will be oriented "above" or "at the top" of those other elements or features. Thus, the term "under" can cover both upward and downward orientations depending on the context in which the term is used, which will be apparent to those of ordinary skill in the art. The material may be oriented in other ways (e.g., rotated 90 degrees, reversed, flipped, etc.), and the spatial relative descriptors used herein may be interpreted accordingly.

[0025] As used herein, "conductive material" may refer to: one or more metals, such as tungsten, titanium, nickel, platinum, palladium, ruthenium, aluminum, copper, molybdenum, gold; metal alloys; metal-containing materials (e.g., metal nitrides, metal silicides (tantalum silicide, tungsten silicide, nickel silicide, titanium silicide), metal carbides, metal oxides); conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.); polysilicon; other materials exhibiting conductivity; or combinations thereof. The conductive material may comprise at least one of the following: titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), elemental titanium (Ti), elemental platinum (Pt), elemental rhodium (Rh), elemental ruthenium (Ru), elemental molybdenum (Mo), elemental iridium (Ir), iridium oxide (IrO x ), elemental ruthenium (Ru), ruthenium oxide (RuO x ), elemental tungsten (W), elemental aluminum (Al), elemental copper (Cu), elemental gold (Au), elemental silver (Ag), alloys of the foregoing, or combinations thereof. The terms "conductive material" and "conducting material" may be used interchangeably herein.

[0026] According to embodiments described herein, a microelectronic device includes a stack that includes alternating layers of a conductive material (also characterized as an access line (e.g., a word line) or a gate electrode) and an insulating material (e.g., a dielectric material). A pillar having a channel material may extend through the stack and may form a memory cell string. For example, memory cells may be located proximate intersections of the channel material and layers of at least some of the conductive material. One or more of the dielectric materials (e.g., a tunneling dielectric material, a charge trapping material, a charge blocking material, or one or more of another material) may be located between the layers of the channel material and at least some of the conductive material. Another conductive material (e.g., an electrode material) may be located proximate some of the dielectric materials. In some embodiments, the electrode material is located between the dielectric materials. Memory cells associated with layers of different conductive materials may be isolated from each other at least by intervening layers of the insulating material.

[0027] Conductive contacts electrically couple the channel material of one stack to the channel material of an adjacent stack. In some embodiments, the volume between adjacent stacks is free of a charge trapping material, such as silicon nitride. For example, an insulating material such as an oxide material (e.g., silicon dioxide) may be located between adjacent stacks. The oxide material may facilitate decoupling between the channel materials of adjacent pillars. The oxide material may extend from one stack to an adjacent stack and may electrically isolate the conductive contacts that electrically couple the channel materials of adjacent stacks. In some embodiments, the oxide material substantially fills the volume between adjacent stacks and between the conductive contacts of adjacent pillars. In other embodiments, the oxide material fills the conductive contacts and at least a portion of one of the stacks (e.g., the insulating material of at least one of the stacks). Another conductive material is adjacent to the oxide material and fills the remaining volume between adjacent stacks and between adjacent conductive contacts filled with the oxide material.

[0028] The oxide material may reduce or prevent electrical coupling between adjacent pillars proximate the location between adjacent stacks. The oxide material may include a material that is not prone to charge trapping (e.g., electron trapping) and associated charge detrapping. At least in part due to the presence of the oxide material, pillars that include memory cell strings may exhibit improved device performance, such as reduced read and write offsets and increased operating windows compared to conventional memory cells. In some embodiments that include a conductive material adjacent to the oxide material, the conductive material may reduce or prevent interaction between the channel materials of adjacent pillars. In some embodiments, the conductive material may improve the string current of the memory cell string and may also improve the gate-induced drain leakage current (GIDL).

[0029] Figure 1AFIG. 0 is a simplified cross-sectional view of a microelectronic device 100 in accordance with an embodiment of the present disclosure. The microelectronic device 100 may include a first stack 103 adjacent to (e.g., over) a substrate material 102 and a second stack 105 adjacent to (e.g., over) the first stack 103. The substrate material 102 may include a substrate or structure on which additional materials may be formed. The substrate material 102 may be a semiconductor substrate, a substrate semiconductor layer on a support structure, a metal electrode, or a metal electrode on a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate material 102 may be a conventional silicon substrate or other bulk substrate including a layer of semiconductive material. As used herein, the term "bulk substrate" not only means and includes silicon wafers, but also means and includes silicon-on-insulator ("SOI") substrates such as silicon-on-sapphire ("SOS") substrates and silicon-on-glass ("SOG") substrates, silicon epitaxial layers on a substrate semiconductor base, and other semiconductor or optoelectronic materials such as silicon germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The substrate material 102 may be doped or undoped.

[0030] The first stack 103 and the second stack 105 may each independently include alternating layers of an insulating material 110 and a conductive material 112. For example, the microelectronic device 100 may include a stack 107, each stack 107 including an insulating material 110 and a conductive material 112.

[0031] Although Figure 1A FIG. 0 shows that the microelectronic device 100 includes only two stacks 103, 105, the present disclosure is not limited thereto.

[0032] In other embodiments, the microelectronic device 100 includes more than two stacks 103, 105, such as three stacks, four stacks, six stacks, eight stacks, or another number of stacks. Additionally, although Figure 1A FIG. 0 shows that the first stack 103 and the second stack 105 include three stacks 107, the present disclosure is not limited thereto. In other embodiments, the first stack 103 and the second stack 105 may each independently include more than at least about 32 stacks 107 or alternating layers of a conductive material 112 and an insulating material 110, such as at least about 64 stacks 107, at least about 128 stacks 107, or even at least about 256 stacks 107. In some embodiments, the first stack 103 and the second stack 105 include the same number of stacks 107. In other embodiments, the first stack 103 includes a different number of stacks 107 than the second stack 105.

[0033] A source 104 (e.g., a source region) may be located between the substrate material 102 and the first stack 103. An etch stop material 106 may be adjacent to the source 104, and a conductive material 108 may be adjacent to the etch stop material 106.

[0034] The source electrode 104 may comprise, for example, a semiconductor material doped with one of a P-type conductive material or an N-type conductive material. As used herein, the N-type conductive material may comprise, for example, polysilicon doped with at least one N-type dopant (e.g., arsenic ions, phosphorus ions, antimony ions). As used herein, the P-type conductive material may comprise, for example, polysilicon doped with at least one P-type dopant (e.g., boron ions). In some embodiments, the source electrode 104 comprises an N-type conductive material. In other embodiments, the source electrode 104 comprises tungsten, tungsten silicide, or another material.

[0035] The etch stop material 106 may comprise, for example, one or more of the following: aluminum oxide (Al 2 O 3 ), titanium dioxide (TiO 2 ), silicon carbide doped with nitrogen (SiCN), aluminum nitride, aluminum oxynitride, silicon carbide, or another material. In some embodiments, the etch stop material 106 comprises aluminum oxide. The etch stop material 106 may be formulated and configured to exhibit an etch selectivity with respect to the materials of the first stack 103 and the second stack 105 (e.g., with respect to the insulating material 110 and the conductive material 112). During the formation of the first stack 103 and the second stack 105, portions of the insulating material 110 and the conductive material 112 of the respective first stack 103 and second stack 105 may be removed without substantially removing the etch stop material 106.

[0036] The conductive material 108 may comprise a so-called select gate source material. The conductive material 108 may comprise a conductive material, such as: one or more metals, such as tungsten, titanium, nickel, chromium, cobalt, platinum, palladium, ruthenium, rhodium, iridium, tantalum, aluminum, copper, molybdenum, gold, silver; metal alloys; conductive metal-containing materials, (e.g., conductive metal nitrides (titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN)), conductive metal oxides (iridium oxide (IrO x ), ruthenium oxide (RuO x ), titanium dioxide), conductive metal silicides (tantalum silicide, tungsten silicide, nickel silicide, titanium silicide)); conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.); polysilicon; other materials exhibiting conductivity; alloys of the foregoing; or combinations of the foregoing. In some embodiments, the conductive material 108 comprises polysilicon (e.g., P-type polysilicon) or another material.

[0037] The insulating material 110 may comprise a dielectric material, such as silicon dioxide or other dielectric materials.

[0038] The conductive material 112 may include a conductive material, such as one or more of the materials described above with reference to the conductive material 108. In some embodiments, the conductive material 112 includes polysilicon. In some embodiments, the conductive material 112 has the same composition as the conductive material 108. The conductive material 112 may also be referred to herein as an access line (e.g., word line) or a gate electrode.

[0039] Continuing to refer to Figure 1A , the pillar 125 including the channel material 120 may extend through the first stack 103 and the second stack 105. The channel material 120 may be in electrical communication with the source 104. The channel material 120 may comprise a semiconductor material, such as polysilicon. In some embodiments, the channel material 120 includes p-type polysilicon. In other embodiments, the channel material 120 includes a metal oxide semiconductor material. In some embodiments, the channel material 120 includes polysilicon. The channel material 120 may be electrically isolated from the conductive material 108 and the conductive material 115 by an insulating material 145. The insulating material 145 may include a dielectric material. For example, the insulating material 145 may include one or more of the following: phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, nitride materials (e.g., silicon nitride (Si 3 N 4 )), oxynitrides (e.g., silicon oxynitride), another gate dielectric material, dielectric carbonitride materials (e.g., silicon carbonitride (SiCN)), or dielectric carbon oxynitride materials (e.g., silicon carbon oxynitride (SiOCN)).

[0040] In some embodiments, the pillar 125 further includes an electrically insulating material 122 located between portions of the channel material 120. The electrically insulating material 122 may comprise, for example: phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, nitride materials (e.g., silicon nitride (Si 3 N 4 )), oxynitrides (e.g., silicon oxynitride), another gate dielectric material, dielectric carbonitride materials (e.g., silicon carbonitride (SiCN)), dielectric carbon oxynitride materials (e.g., silicon carbon oxynitride (SiOCN)), or a combination thereof. In some embodiments, the electrically insulating material 122 includes silicon dioxide.

[0041] Memory cell 130 may be located at an intersection between channel material 120 and conductive material 112. Memory cell 130 may include, for example, dielectric material 124 (also referred to as a tunneling dielectric material) located between channel material 120 and electrode material 126 (which may also be referred to as a gate electrode, floating gate, or gate), and another dielectric material 128 (also referred to as a charge storage material) surrounding at least a portion of electrode material 126. In some embodiments, memory cell 130 may be referred to herein as a "floating gate" memory cell. As will be described with reference to Figure 1C as described, memory cell 130 may include other materials and may be referred to herein as a "charge trapping" memory cell.

[0042] Electrode material 126 may include a conductive material. As a non-limiting example, electrode material 126 may include: a conductively doped semiconductor material (e.g., conductively doped silicon, conductively doped germanium, conductively doped silicon-germanium, etc.); polysilicon; one or more metals such as tungsten, titanium, nickel, chromium, cobalt, platinum, palladium, ruthenium, rhodium, iridium, tantalum, aluminum, copper, molybdenum, gold, silver, or combinations thereof; metal alloys; conductive metal-containing materials, (e.g., conductive metal nitrides (titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN)), conductive metal oxides (iridium oxide (IrO x ), ruthenium oxide (RuO x ), titanium dioxide), conductive metal silicides (tantalum silicide, tungsten silicide, nickel silicide, titanium silicide)); alloys of the foregoing; or combinations of the foregoing. In some embodiments, electrode material 126 includes tungsten. In other embodiments, electrode material 126 includes polysilicon. In some such embodiments, the polysilicon may be doped and may include, for example, n-type doped polysilicon or p-type doped polysilicon.

[0043] Dielectric material 124 may include, for example, a tunneling oxide material. In some embodiments, dielectric material 124 includes silicon dioxide. However, the present disclosure is not limited thereto, and dielectric material 124 may include another material, such as one or more of the materials described above with reference to insulating material 145. In some embodiments, dielectric material 124 includes the same material composition as insulating material 145. Although Figure 1A illustrates dielectric material 124 located only on the side surfaces adjacent to conductive material 112 and not in contact with or located on the side surfaces of insulating material 110, the present disclosure is not limited thereto. In other embodiments, dielectric material 124 extends continuously through the entire first stack 103 and the entire second stack 105 to conductive contact 132. In some embodiments, dielectric material 124 may be grown on electrode material 126, for example, by an in-situ steam generation (ISSG) process to selectively oxidize the exposed portions of electrode material 126.

[0044] The other dielectric material 128 may include a charge trapping material, such as an oxide-nitride-oxide (ONO) structure. For example, the other dielectric material 128 may include a first oxide material, a silicon nitride material adjacent to the first oxide material, and a second oxide material adjacent to the silicon nitride material. The first oxide material and the second oxide material may include silicon dioxide, hafnium dioxide, zirconium oxide, or another material. In some embodiments, the first oxide material and the second oxide material have the same material composition. In some embodiments, the first oxide material and the second oxide material include silicon dioxide. In some embodiments, the other dielectric material 128 may also be referred to as an interpolydielectric (IPD) material.

[0045] Figure 1B For Figure 1A FIG. 8 is a simplified cross-sectional view of the microelectronic device 100 taken along the cross-sectional line B-B. The pillar 125 may include a circular cross-sectional shape. In some embodiments, the channel material 120 may surround the electrically insulating material 122 and may present a circular cross-sectional shape. The dielectric material 124 may surround the channel material 120 and may be positioned between the channel material 120 and the electrode material 126. The other dielectric material 128 may be positioned between the electrode material 126 and the conductive material 112.

[0046] Return reference Figure 1A , another conductive material 115 may be formed adjacent to the insulating material 110 of the uppermost stack 107. The conductive material 115 may include a so-called select gate drain (SGD) material. The conductive material 115 may include one or more of the materials described above with reference to the conductive material 108. In some embodiments, the conductive material 115 has the same material composition as the conductive material 108. The insulating material 114 may be formed adjacent to the conductive material 115. The insulating material 114 may be patterned, and the conductive contact 116 (also referred to herein as a conductive plug) may be adjacent to the channel material 120 and in electrical communication with the channel material.

[0047] The conductive line 118 (e.g., a data line, a bit line) may be adjacent to the conductive contact 116 and in electrical communication with the conductive contact.

[0048] In some embodiments, the channel material 120 may present a protrusion 140 at a position between the first stack 103 and the second stack 105. The distance D between opposite portions of the protrusion 140 1(For example, the diameter of the channel material 120 at the protrusion 140) may be greater than the distance between the opposing portions of the channel material 120 at other portions of the channel material 120. In other words, the channel material 120 may have a greater diameter near the protrusion 140 relative to other locations of the channel material 120.

[0049] The protrusion 140 may be the result of a method of forming the microelectronic device 100, such as a method of forming the channel material 120 to extend through the first stack 103 and the second stack 105 and forming the conductive contact 132 between the first stack 103 and the second stack 105.

[0050] The conductive contact 132 may electrically couple the channel material 120 of the pillar 125 of the first stack 103 to the channel material 120 of the corresponding pillar 125 of the second stack 105. In other words, the channel material 120 of the first stack 103 may be in electrical communication with the channel material 120 of the second stack 105 through the conductive contact 132. The conductive contact 132 may include a conductive material. In some embodiments, the conductive contact 132 includes polysilicon. In some embodiments, the conductive contact 132 includes the same material composition as the conductive material 112.

[0051] The conductive contact 132 may include a protrusion portion 134 that extends further from the underlying insulating material 110 (when viewed up and down in the Figure 1A view shown) than other portions of the corresponding conductive contact 132 (e.g., the central portion). In some embodiments, the distance D between the opposing sides of the conductive contact 132 at a location near the underlying insulating material 2 is less than the distance D between the opposing protrusion portions 134 of the corresponding conductive contact 132 3 .

[0052] The oxide material 136 may be positioned between the first stack 103 and the second stack 105. The oxide material 136 may include an electrically insulating material. In some embodiments, the oxide material 136 includes a material that does not exhibit charge trapping (e.g., electron trapping) and detrapping properties. For example, the oxide material 136 does not contain (e.g., is substantially free of) silicon nitride. In other words, the microelectronic device 100 does not contain silicon nitride at a location between the first stack 103 and the second stack 105.

[0053] The oxide material 136 may include one or more of the following: silicon dioxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, oxynitride (e.g., silicon oxynitride), aluminum oxide, hafnium dioxide, zirconium oxide, titanium trioxide, tantalum oxide, molybdenum oxide, or spin-on dielectric (SOD) (e.g., hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), polyimide, polytetrafluoroethylene (PTFE), spin-on polymer). The oxide material 136 may not include silicon nitride. In some embodiments, the oxide material 136 includes silicon dioxide. In some embodiments, at least a portion of the volume between the first stack 103 and the second stack 105 may include one or more voids. The one or more voids may be filled with one or more of oxygen, nitrogen, air, helium, or another gas. In some embodiments, the one or more voids are filled with oxygen and nitrogen.

[0054] The oxide material 136 may directly contact the first stack 103 and the second stack 105. In some embodiments, the oxide material 136 directly contacts the insulating material 110 of the first stack 103 and the insulating material 110 of the second stack 105 (e.g., where the second stack 105 does not include an etch stop material 106). For example, the oxide material 136 may be directly positioned between the uppermost insulating material 110 of the first stack 103 and the lowermost insulating material 110 of the second stack 105. In some embodiments, the oxide material 136 may directly contact the uppermost insulating material 110 of the first stack 103 and the lowermost insulating material 110 of the second stack 105. In other embodiments, the oxide material 136 directly contacts the insulating material 110 of the first stack 103 and directly contacts the etch stop material 106 that contacts the insulating material 110 of the second stack 105. In some embodiments, at least a portion of the oxide material 136 is directly laterally positioned between the conductive contacts 132 of adjacent pillars 125. Although Figure 1A the oxide material 136 has been described and shown as including directly contacting the uppermost insulating material 110 of the first stack 105 and the etch stop material 106 of the second stack 105, the present disclosure is not limited thereto. In other embodiments, the oxide material 136 may directly contact the uppermost conductive material of the first stack 103 and the lowermost conductive material 112 (or the etch stop material 106 of the second stack 105) of the second stack 105. In some such embodiments, the oxide material 136 is the only material between a portion of the uppermost conductive material 112 of the first stack 103 and a portion of the lowermost conductive material 112 of the second stack 105. In some embodiments, the oxide material 136 directly contacts the channel material adjacent to the protrusion 140.

[0055] The thickness T of the oxide material 136 1can be in the range of about 50 nm to about 200 nm, for example, in the range of about 50 nm to about 75 nm, in the range of about 75 nm to about 100 nm, in the range of about 100 nm to about 150 nm, or in the range of about 150 nm to about 200 nm. In some embodiments, the thickness T is about 100 nm.

[0056] In some embodiments, the thickness T of the oxide material 136 1 can be greater than the thickness of the layer of the insulating material 110. In some embodiments, the thickness T of the oxide material 136 1 is greater than the thickness of the layer of the conductive material 112. For example, the thickness T of each layer of the insulating material 110 2 can be in the ranges of about 10 nm to about 20 nm and about 20 nm to about 50 nm, for example, in the range of about 10 nm to about 20 nm, in the range of about 20 nm to about 30 nm, in the range of about 30 nm to about 40 nm, or in the range of about 40 nm to about 50 nm. The thickness T of each layer of the conductive material 112 3 can be in the range of about 10 nm to about 50 nm, for example, in the range of about 10 nm to about 20 nm, in the range of about 20 nm to about 30 nm, in the range of about 30 nm to about 40 nm, or in the range of about 40 nm to about 50 nm. In some embodiments, the thickness T of the oxide material 136 1 can be greater than the thickness of each of those in the stack 107 (i.e., the thickness T 2 and the thickness T 3 sum).

[0057] In some embodiments, the oxide material 136 can reduce or prevent (e.g., substantially prevent) coupling of the channel material 120 of adjacent pillars 125 at or near the location between the first stack 103 and the second stack 105. Additionally, the oxide material 136 can include a material composition that is formulated and configured to exhibit a reduced degree of charge trapping compared to conventional materials used between adjacent stack structures. For example, conventional microelectronic devices can include a silicon nitride material between adjacent stacks. Due to the relatively large gap between adjacent stacks, and specifically due to the relatively large gap between the conductive materials 112 of adjacent stacks (e.g., the uppermost conductive material 112 of the first stack 103 and the lowermost conductive material 112 of the second stack 105, which can be spaced apart from each other by at least the uppermost insulating material 110 of the first stack 103, the lowermost insulating material 110 of the second stack 105, and the oxide material 136 between the first stack 103 and the second stack 105), the silicon nitride material can trap charges (e.g., electrons) that could cause a pillar 125 containing the channel material 120 to couple to an adjacent pillar 125. In some cases, when a first pillar 125 is selected for programming (writing) and a second pillar 125 is prohibited, e.g., by applying a potential of about 0 V to the channel material 120 of the first pillar 125 and a potential (e.g., about 10 V) to the channel material 120 of the second pillar 125, electrons can be trapped in this silicon nitride material located between adjacent stacks between the first pillar 125 and the second pillar 125. The trapped charges (e.g., electrons) in the silicon nitride material can affect the threshold voltage of the memory cell 130 and can reduce the operating (e.g., read) window of the memory cell 130.

[0058] Additionally, charges may not be trapped in the oxide material 136. By comparison, the conventional device 100 can include a silicon nitride or other material between the first stack 103 and the second stack 105, which can trap charges and couple to the protrusions 140 that can be present in the channel material 120 due to various processing conditions (e.g., deposition of various materials, etching operations, cleaning operations) used to form the pillars 125. In other words, in a conventional device, the protrusions 140 can couple to the charge trapping material between adjacent stacks. Additionally, the protruding portion 134 of the conductive contact 132 can exhibit a relatively higher electric field (e.g., manifested as an increase in current density) compared to other portions of the conductive contact 132. In a conventional microelectronic device, the high electric field at the protruding portion 134 can facilitate injection of electrons or other charges into the silicon nitride material near the conductive contact 132 during the use and operation of the microelectronic device 100. The injected electrons or other charges can cause the operating window of the memory cell 130 to decrease.

[0059] Forming the oxide material 136 to include materials that do not trap charge (e.g., electrons) can reduce or prevent charge trapping within the channel material 120, such as near the protrusion 140 and at locations within the channel material near the protrusion portion 134. Accordingly, the microelectronic device 100 can include a column 125 that includes a memory cell string 130 that exhibits an operating window that is larger than that of conventional microelectronic devices due to adjacent columns 125 not being coupled to each other.

[0060] Although Figure 1A described and shown as including a particular type of memory cell 130 (e.g., a floating gate memory cell), the present disclosure is not limited thereto.

[0061] Figure 1C For there may be present in Figure 1A the microelectronic device 100 in place of the memory cell 130 ( Figure 1A ) a simplified cross-sectional view of a memory cell 150.

[0062] The memory cell 150 can include a so-called charge trapping material. In some such embodiments, the associated microelectronic device 100 can include a charge trapping NAND. The memory cell 150 can be referred to herein as a "charge trapping" memory cell.

[0063] Figure 1C For a simplified cross-sectional view of a memory cell 150 that can be interchangeably used with Figure 1A the memory cell 130 according to an embodiment of the present disclosure. The memory cell 150 can include a dielectric material 152 (e.g., a tunneling dielectric material), a charge trapping material 154, and a charge blocking material 156 located between the channel material 120 and the conductive material 112. The charge trapping material 154 can be directly positioned between the dielectric material 152 and the charge blocking material 156. In some embodiments, the dielectric material 152 directly contacts the channel material 120 and the charge trapping material 154. The charge blocking material 156 can directly contact the charge trapping material 154 and the conductive material 112 and can be directly adjacent to the charge trapping material and the conductive material.

[0064] Although Figure 1A described and shown as including the oxide material 136 between the first stack 103 and the second stack 105, the present disclosure is not limited thereto. In other embodiments, one or more other materials can be positioned between the first stack 103 and the second stack 105. Figure 2 For a simplified cross-sectional view of a microelectronic device 200 according to an embodiment of the present disclosure. The microelectronic device 200 can be associated with Figure 1AThe microelectronic device 200 is generally the same as the microelectronic device 100, except that the microelectronic device 200 may include one or more additional materials between the first stack 103 and the second stack 105.

[0065] The microelectronic device 200 includes an oxide material 160 between the first stack 103 and the second stack 105 to electrically isolate adjacent conductive contacts 132 from each other. In some embodiments, the oxide material 160 may not substantially fill the entire volume between the first stack 103 and the second stack 105, such as the volume between the etch stop material 106 adjacent to the second stack 105 and the upper insulating material 110 of the first stack 103. In some embodiments, the remaining volume between the first stack 103 and the second stack 105 may be filled with one or more gases, such as one or more of oxygen, nitrogen, air, helium, or another gas. In some embodiments, the one or more voids are filled with oxygen and nitrogen. In other embodiments, a conductive material 162 may also be located between adjacent pillars 125 and is electrically isolated from the adjacent pillars 125 and the associated conductive contacts 132 at least by the oxide material 160.

[0066] In some embodiments, the oxide material 160 may include an oxide lining around the sidewalls of the conductive contacts 132 and the sidewalls of the channel material 120 located between the first stack 103 and the second stack 105. In some embodiments, the oxide material 160 may be adjacent to (e.g., conformally overlying) the conductive contacts 132, the sidewalls of the channel material 120 located between the first stack 103 and the second stack 105, and the uppermost insulating material 110 of the first stack 103. The oxide material 160 may be adjacent to the protrusions 140 of the channel material 120 and the protruding portions 134 of the conductive contacts 132.

[0067] The oxide material 160 may be adjacent to the surface of the insulating material 110 of the first stack 103 and may be adjacent to the surfaces of the conductive contacts 132, the channel material 120, and the etch stop material 106. In other embodiments, the oxide material 160 extends adjacent to the surfaces of the conductive contacts 132 and the channel material 120 to the surface of the insulating material 110 of the second stack 105. As referred to above Figure 1AAs discussed with respect to oxide material 136, oxide material 160 can be directly located between the uppermost insulating material 110 of the first stack 103 and the lowermost insulating material 110 of the second stack 105. In some embodiments, oxide material 136 can directly contact the uppermost insulating material 110 of the first stack 103 and the lowermost insulating material 110 of the second stack 105. In other embodiments, oxide material 160 directly contacts the insulating material 110 of the first stack 103 and directly contacts the etch stop material 106 that contacts the insulating material 110 of the second stack 105. In some embodiments, at least a portion of oxide material 160 is directly laterally positioned between the conductive contacts 132 of adjacent pillars 125. In some such embodiments, the gap between the oxide materials 160 on the conductive contacts 132 of adjacent pillars 125 can be separated by a void. The void can be filled with one or more gases or can be filled with a conductive material 162. Although Figure 1A oxide material 160 has been described and shown as including directly contacting the uppermost insulating material 110 of the first stack 105 and the etch stop material 106 of the second stack 105, the present disclosure is not limited thereto. In other embodiments, oxide material 160 can directly contact the uppermost conductive material of the first stack 103 and the lowermost conductive material 112 (or the etch stop material 106 of the second stack 105) of the second stack 105.

[0068] Oxide material 160 can include the same materials as those described above with reference to oxide material 136 ( Figure 1A ). In some embodiments, oxide material 160 includes silicon dioxide.

[0069] Conductive material 162 can be adjacent to oxide material 160 and can fill the remaining volume between the first stack 103 and the second stack 105. Conductive material 162 can be adjacent to the surface of oxide material 160 near the first stack 103 and can be adjacent to oxide material 160 extending near the conductive contacts 132 and the channel material 120. Conductive material 162 can extend from oxide material 160 adjacent to the first stack 103 to the etch stop material 106 adjacent to the second stack 105. In other embodiments, conductive material 162 extends from oxide material 160 to the insulating material 110 of the second stack 105.

[0070] Conductive material 162 can comprise a conductive material. In some embodiments, conductive material 162 includes polysilicon. Conductive material 162 can be doped with one or more of boron, phosphorus, arsenic, antimony, or another material. In other embodiments, conductive material 162 includes tungsten. In some embodiments, conductive material 162 can include the same material composition as the conductive contacts 132.

[0071] The microelectronic device 200 may exhibit reduced charge trapping in the channel material 120, such as in the channel material near the protrusion 140 and at locations near the protrusion portion 134. Additionally, the conductive material 162 may facilitate shielding between the adjacent pillars 125 and the channel material 120 of the adjacent pillars 125. In other words, the conductive material 162 between the adjacent pillars 125 may reduce or prevent interaction between the channel materials 120 of the adjacent pillars 125.

[0072] In some embodiments, the conductive material 162 may improve the string current of the memory cell string 130 and may also improve the gate-induced drain leakage current (GIDL). The conductive material 162 may be in electrical communication with conductive contacts located in a so-called staircase structure of the microelectronic device. In use and operation, a voltage may be applied to the conductive material 162 near the channel material 120 of, for example, a selected memory string or a non-selected memory string.

[0073] Thus, in at least some embodiments, a microelectronic device includes: a stack including alternating layers of a conductive material and an insulating material, the stack including pillars containing channel material extending through the alternating layers of the conductive material and the insulating material; conductive contacts located between adjacent stacks and in electrical communication with the channel material of the adjacent stacks; and an oxide material located between the adjacent stacks, the oxide material extending between the uppermost layer of a first stack and the lowermost layer of a second stack adjacent to the first stack.

[0074] Figures 3A - 3D For an embodiment in accordance with the present disclosure showing a Figure 1A simplified cross-sectional view of a method of forming the microelectronic device 100. Referring Figure 3A , a first stack 103 ( Figure 1A ) may be formed adjacent to a substrate material 102, a source 104, an etch stop material 106, and a conductive material 108 to form a semiconductor structure 300. Alternating layers of an insulating material 110 and a conductive material 112 of the first stack 103 may be formed adjacent to the conductive material 108.

[0075] After forming the layers of the insulating material 110 and the conductive material 112, openings may be formed through the layers of the insulating material 110 and the conductive material 112 and the conductive material 108 to expose portions of the etch stop material 106. The exposed portions of the etch stop material 106 may be removed through the openings to expose portions of the source 104. For example, in some embodiments, portions of the insulating material 110, the conductive material 112, and the conductive material 108 may be removed in a single removal operation to form the openings, while a second removal operation may be used to remove the portions of the etch stop material 106.

[0076] In some embodiments, such as in a so-called "gate first" process, a memory cell 130 can be formed by removing portions of the conductive material 112 to form a recess. Other dielectric materials 128 can be formed in the recess and adjacent to the remaining portions of the conductive material 112. Electrode material 126 can be formed adjacent to the other dielectric materials 128, and dielectric material 124 can be formed adjacent to the electrode material 126. After forming the dielectric material 124, channel material 120 can be formed adjacent to the sides of the opening to form the memory cell 130. In some embodiments, after forming the channel material 120, an electrically insulating material 122 can be formed adjacent to the channel material 120.

[0077] After forming the channel material 120 and the electrically insulating material 122, portions of the channel material 120 and the electrically insulating material 122 can be removed from the surface of the uppermost insulating material 110.

[0078] A silicon nitride material 170 can be formed adjacent to the exposed (e.g., uppermost) insulating material 110. Refer to Figure 3B , an opening can be formed through the silicon nitride material 170 to expose the channel material 120. Conductive material can be formed in the opening and in electrical communication with the channel material 120 to form a conductive contact 132. The conductive contact 132 is shown in Figures 3A - 3D but does not include the protrusion portion 134 ( Figure 1A ). However, the conductive contact 132 can include the protrusion portion 134. An etch stop material 172 having an etch selectivity with respect to the silicon nitride material 170 can be formed adjacent to the conductive contact 132.

[0079] Refer to Figure 3C , substantially all of the silicon nitride material 170 can be removed to expose portions of the insulating material 110. The insulating material 110 can exhibit an etch selectivity with respect to the silicon nitride material 170. After removing the silicon nitride material 170, the conductive contact 132 and the etch stop material 172 can remain adjacent to the channel material 120 (e.g., above it).

[0080] Refer to Figure 3D , an oxide material 136 can be formed adjacent to the semiconductor structure 300, such as adjacent to the insulating material 110 (e.g., above it) and adjacent to the conductive contact 132 and the etch stop material 172 (e.g., on its sides). In some embodiments, after forming the oxide material 136, the semiconductor structure 300 can be subjected to a chemical mechanical planarization (CMP) process to expose portions of the etch stop material 172 through the oxide material 136. Although Figure 3D shows the oxide material 136 being formed directly on the uppermost insulating material 110, the present disclosure is not limited thereto. In other embodiments, the oxide material 136 is formed directly on the uppermost conductive material 110.

[0081] After forming and planarizing the oxide material 136, a second stack 105 ( Figure 1A ) may be formed adjacent to the semiconductor structure 300. For example, an etch stop material 106 ( Figure 1A ) may be formed adjacent to the oxide material 136, and a stack of alternating layers of an insulating material 110 and a conductive material 112 may be formed adjacent to the semiconductor structure 300. The second stack 105 may be formed in the same manner as the formation of the first stack 103 ( Figure 1A ). For example, openings may be formed in the stack of alternating layers of the insulating material 110 and the conductive material 112, portions of the conductive material 112 may be removed to form trenches, other dielectric materials 128 may be formed in the trenches, electrode materials 126 may be formed adjacent to the other dielectric materials 128, dielectric materials 124 may be formed adjacent to the electrode materials 126, and channel materials 120 may be formed adjacent to the dielectric materials 124.

[0082] After forming the pillars 125 ( Figure 1A ), conductive contacts 116 may pass through the insulating material 114 and be formed adjacent to (e.g., above) the pillars 125 and in a manner electrically connected to the channel materials 120 of the second stack 105 ( Figure 1A ). Conductive lines 118 may be formed in a manner electrically connected to the conductive contacts 116.

[0083] Although Figures 3A - 3D illustrates forming the semiconductor structure 300 to include the oxide material 136 to fill the volume between the first stack 103 ( Figure 1A ) and the second stack 105 ( Figure 1A ), the present disclosure is not limited thereto. Referring to Figure 3C and Figure 4 , after removing the silicon nitride material 170 ( Figure 3B ), the oxide material 160 (if present) may be formed adjacent to the conductive contacts 132 and the etch stop material 172 (e.g., above the conductive contacts and the etch stop material, on the sides of the conductive contacts and the etch stop material) in a conformal manner. For example, the oxide material 160 may form a liner above the uppermost insulating material 110, the conductive contacts 132, and the etch stop material 172. The oxide material 160 may be formed by one or more of, for example, CVD, ALD, plasma-enhanced ALD, PVD, PECVD, or LPCVD.

[0084] After forming the oxide material 160, a conductive material 162 may be formed adjacent to the surface of the oxide material 160, and the semiconductor structure 400 may be subjected to a CMP process. The second stack 105 ( Figure 2 ) may be adjacent to as referred to above in Figure 3DThe described conductive material 162 is formed to form a microelectronic device 200 as described in reference Figure 2 The described microelectronic device 200.

[0085] Although Figures 3A - 3D and Figure 4 has been described as a gate-first process, the present disclosure is not limited thereto. In other embodiments, the microelectronic devices 100, 200 may be formed by a so-called "replacement gate" process. In some such embodiments, rather than forming a stack as described above in reference Figure 3A to include alternating layers of insulating material 110 and conductive material 112, a stack including alternating layers of insulating material 110 and other insulating materials may be formed adjacent to conductive material 108 (e.g., Figure 3A the conductive material 112 may be replaced with other insulating materials). The other insulating materials may include electrically insulating materials that exhibit an etch selectivity relative to insulating material 110, such as silicon nitride. An opening may be formed through the stack of alternating layers of insulating material 110 and other insulating materials and through conductive material 108 and etch stop material 106. Channel material may be formed in the opening, such as throughout the opening or at least on the sidewalls of the opening. In some embodiments, a dielectric material (e.g., silicon dioxide) may fill the remainder of the opening. Additional openings may be formed through the alternating layers of insulating material and other insulating materials to expose source 104. The other insulating materials may be selectively removed relative to insulating material 110 to form a recess between adjacent layers of insulating material 110. After removing the other insulating materials, memory cell 130 may be formed in another opening, for example, by forming a dielectric material (e.g., charge storage material) in the recess, forming electrode material adjacent to the charge storage material, and forming insulating material in the remainder of the other opening. In other embodiments, other dielectric material 128 is formed in the recess, electrode material 126 is formed adjacent to other dielectric material 128, and dielectric material 124 is formed adjacent to electrode material 126. The microelectronic device may be completed as described above.

[0086] Thus, in at least one embodiment, a method of forming a microelectronic device includes: forming a first stack of channel material including a stack extending through alternating layers of a first material and a second material; forming a nitride material adjacent to the first stack; forming an opening in the nitride material and forming a conductive contact in the opening; removing the nitride material; forming an oxide material adjacent to the conductive contact; and forming a second stack adjacent to the oxide material, the second stack including alternating layers of the first material and the second material.

[0087] Microelectronic devices (e.g., microelectronic devices 100, 200) that include an oxide material 136 or an oxide material 160 and a conductive material 162 between a first stack 103 and a second stack 105 according to embodiments of the present disclosure may be used in embodiments of the electronic systems of the present disclosure. For example, Figure 5 is a block diagram of an exemplary electronic system 503 according to embodiments of the present disclosure. The electronic system 503 may include, for example, a computer or computer hardware components, a server or other network-connected hardware components, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi- or cellular-enabled tablet computer (e.g., or tablet computer), an e-book, a navigation device, etc. The electronic system 503 includes at least one memory device 505. The memory device 505 may include, for example, embodiments of the microelectronic devices (e.g., microelectronic devices 100, 200) described previously herein, the microelectronic devices including an oxide material (e.g., oxide material 136 or oxide material 160) located between adjacent stacks (e.g., first stack 103, second stack 105), the oxide material including a material that does not trap charge.

[0088] The electronic system 503 may further include at least one electronic signal processor device 507 (commonly referred to as a “microprocessor”). The electronic signal processor device 507 may optionally include embodiments of the microelectronic devices (e.g., microelectronic devices 100, 200) described previously herein. The electronic system 503 may further include one or more input devices 509 for a user to input information into the electronic system 503, such as a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system 503 may further include one or more output devices 511 for outputting information (e.g., visual or audio output) to the user, such as a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device 509 and the output device 511 may include a single touchscreen device that can be used both to input information into the electronic system 503 and to output visual information to the user. The input device 509 and the output device 511 may communicate electrically with one or more of the memory device 505 and the electronic signal processor device 507.

[0089] Reference Figure 6, depicts a processor-based system 600. The processor-based system 600 may include various electronic devices manufactured in accordance with embodiments of the present disclosure. The processor-based system 600 may be any one of a variety of types, such as, for example, a computer, a pager, a cellular phone, a personal assistant, a control circuit, or other electronic devices. The processor-based system 600 may include one or more processors 602 (e.g., microprocessors) to control the processing of system functions and requests in the processor-based system 600. The processor 602 and other sub-components of the processor-based system 600 may include microelectronic devices (e.g., microelectronic devices 100, 200) manufactured in accordance with embodiments of the present disclosure.

[0090] The processor-based system 600 may include a power supply 604 communicatively coupled to the processor 602. For example, if the processor-based system 600 is a portable system, the power supply 604 may include one or more of a fuel cell, a power purification device, a permanent battery, a replaceable battery, and a rechargeable battery. For example, the power supply 604 may also include an AC adapter; thus, the processor-based system 600 may be plugged into a wall outlet. For example, the power supply 604 may also include a DC adapter so that the processor-based system 600 may be plugged into a vehicle cigarette lighter or a vehicle power port.

[0091] Various other devices may be coupled to the processor 602 depending on the functions performed by the processor-based system 600. For example, a user interface 606 may be coupled to the processor 602. The user interface 606 may include input devices such as buttons, switches, keyboards, light pens, mice, digitizers and styli, touchscreens, voice recognition systems, microphones, or combinations thereof. A display 608 may also be coupled to the processor 602. The display 608 may include an LCD display, an SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a three-dimensional projection, an audio display, or combinations thereof. In addition, an RF subsystem / baseband processor 610 may also be coupled to the processor 602. The RF subsystem / baseband processor 610 may include an antenna coupled to an RF receiver and coupled to an RF transmitter (not shown). A communication port 612 or more than one communication port 612 may also be coupled to the processor 602. For example, the communication port 612 may be adapted to couple to one or more peripheral devices 614, such as a modem, a printer, a computer, a scanner, or a camera, or to a network, such as a local area network, a remote local area network, an intranet, or the Internet.

[0092] The processor 602 can control the processor-based system 600 by implementing software programs stored in the memory. For example, the software programs can include an operating system, database software, graphics software, word processing software, media editing software, or media playback software. The memory is operatively coupled to the processor 602 to store and facilitate the execution of various programs. For example, the processor 602 can be coupled to a system memory 616, which can include one or more of spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), racetrack memory, and other known memory types. The system memory 616 can include volatile memory, non-volatile memory, or a combination thereof. The system memory 616 is typically larger such that it can dynamically store loaded applications and data. In some embodiments, the system memory 616 can include microelectronic devices, such as the microelectronic devices described above (e.g., microelectronic devices 100, 200), or a combination thereof.

[0093] The processor 602 can also be coupled to a non-volatile memory 618, which does not imply that the system memory 616 must be volatile. The non-volatile memory 618 can include one or more of STT-MRAM, MRAM, read-only memory (ROM) such as EPROM, resistive read-only memory (RROM), and flash memory to be used in combination with the system memory 616. The size of the non-volatile memory 618 is typically selected to be only large enough to store any necessary operating system, application programs, and fixed data. Additionally, for example, the non-volatile memory 618 can include a mass storage device such as a disk drive memory, a hybrid drive including resistive memory, or other types of non-volatile solid-state memory. The non-volatile memory 618 can include microelectronic devices, such as the microelectronic devices described above (e.g., microelectronic devices 100, 200), or a combination thereof.

[0094] Thus, in at least some embodiments, an electronic system includes a first stack and a second stack. Each of the first stack and the second stack includes a stack of alternating layers of conductive material and insulating material, and columns including channel material extending through the alternating layers of the conductive material and the insulating material. The electronic system further includes a conductive contact between the channel material of the columns of the first stack and the channel material of the columns of the second stack, and an oxide material adjacent to the conductive contact and located between the first stack and the second stack.

[0095] Additional non-limiting example embodiments of the present disclosure are set forth below.

[0096] Example 1: A microelectronic device, comprising: a stack including alternating layers of a conductive material and an insulating material, the stack including columns containing a channel material extending through the alternating layers of the conductive material and the insulating material; conductive contacts located between adjacent stacks and in electrical communication with the channel material of the adjacent stacks; and an oxide material located between the adjacent stacks, the oxide material extending between the uppermost layer of a first stack and the lowermost layer of a second stack adjacent to the first stack.

[0097] Example 2: The microelectronic device according to Example 1, wherein the oxide material comprises silicon dioxide.

[0098] Example 3: The microelectronic device according to Example 1 or Example 2, further comprising a gaseous material adjacent to the oxide material.

[0099] Example 4: The microelectronic device according to any one of Examples 1 to 3, wherein the oxide material does not contain silicon nitride.

[0100] Example 5: The microelectronic device according to any one of Examples 1 to 4, wherein the oxide material contacts the channel material and the conductive contacts.

[0101] Example 6: The microelectronic device according to any one of Examples 1 to 5, wherein the oxide material directly contacts the insulating material of the uppermost layer of the first stack and the insulating material of the lowermost layer of the second stack.

[0102] Example 7: The microelectronic device according to any one of Examples 1 to 6, wherein the diameter of the channel material at a position between the adjacent stacks is larger than the diameter at a position within the adjacent stacks.

[0103] Example 8: The microelectronic device according to any one of Examples 1 to 7, wherein an upper portion of the conductive contact includes a protruding portion that extends further from a lower stack in the stack than other portions of the conductive contact.

[0104] Example 9: The microelectronic device according to any one of Examples 1 to 8, wherein the oxide material is positioned between the conductive contacts of adjacent columns.

[0105] Example 10: The microelectronic device according to any one of Examples 1 to 9, further comprising a conductive material adjacent to the oxide material and located between the conductive contacts of the adjacent columns.

[0106] Example 11: A method of forming a microelectronic device, the method comprising: forming a first stack of channel materials including a stack of alternating layers of a first material and a second material extending therethrough; forming a nitride material adjacent to the first stack; forming an opening in the nitride material and forming a conductive contact in the opening; removing the nitride material; forming an oxide material adjacent to the conductive contact; and forming a second stack adjacent to the oxide material, the second stack including alternating layers of the first material and the second material.

[0107] Example 12: The method according to Example 11, wherein forming the first stack includes: forming the stack including the alternating layers of the first material and the second material; forming an opening through the stack; and forming the channel material within the opening.

[0108] Example 13: The method according to Example 11 or Example 12, wherein forming the first stack includes: forming the stack including the alternating layers of the first material and the second material; removing a portion of the second material to form a groove; and forming a conductive material in the groove.

[0109] Example 14: The method according to any one of Examples 11 to 13, wherein forming the oxide material adjacent to the conductive contact includes forming silicon dioxide adjacent to the conductive contact.

[0110] Example 15: The method according to any one of Examples 11 to 14, further comprising forming a conductive material in contact with the oxide material between the first stack and the second stack.

[0111] Example 16: The method according to any one of Examples 11 to 15, wherein removing the nitride material and forming the second stack adjacent to the oxide material includes removing all of the nitride material between the first stack and the second stack.

[0112] Example 17: An electronic system, comprising: a first stack and a second stack, each of the first stack and the second stack including: a stack of alternating layers of a conductive material and an insulating material; and a column including channel material extending through the alternating layers of the conductive material and the insulating material; a conductive contact between the channel material of the column of the first stack and the channel material of the column of the second stack; and an oxide material adjacent to the conductive contact and between the first stack and the second stack.

[0113] Example 18: The electronic system according to Example 17 further includes a gas including one or both of oxygen and nitrogen located between the first stack and the second stack.

[0114] Example 19: The electronic system according to Example 17 or Example 18, wherein the thickness of the oxide material is greater than the thickness of the layer of the conductive material or the layer of the insulating material.

[0115] Example 20: The electronic system according to any one of Examples 17 to 19, wherein the first stack and the second stack include memory cell strings.

[0116] Example 21: The electronic system according to any one of Examples 17 to 20 further includes a dielectric material adjacent to the channel material, an electrode material adjacent to the dielectric material, and another dielectric material adjacent to the electrode material.

[0117] Example 22: The electronic system according to Example 21, wherein the another dielectric material is located between the electrode material and the conductive material of the alternating layer.

[0118] Example 23: The electronic system according to any one of Examples 17 to 22, wherein the oxide material directly contacts a lower portion of the first stack and an upper portion of the second stack.

[0119] Although certain illustrative embodiments have been described in conjunction with the figures, those of ordinary skill in the art will recognize and understand that the embodiments covered by the present disclosure are not limited to those expressly shown and described herein. Rather, many additions, deletions, and modifications can be made to the embodiments described herein without departing from the scope of the embodiments covered by the present disclosure (such as those claimed herein, including legal equivalents). Additionally, the features of one disclosed embodiment can be combined with the features of another disclosed embodiment and still be encompassed within the scope of the present disclosure.

Claims

1. A microelectronic device, which comprises: a stack of alternating layers of a conductive material and an insulating material, the stack comprising pillars of channel material extending through the alternating layers of the conductive material and the insulating material; conductive contacts located between adjacent stacks and in electrical communication with the channel material of the adjacent stacks; and an oxide material located between the adjacent stacks, the oxide material extending between the uppermost layer of a first stack and the lowermost layer of a second stack adjacent to the first stack, the oxide material directly contacting the insulating material of the uppermost layer of the first stack and the insulating material of the lowermost layer of the second stack.

2. The microelectronic device according to claim 1, wherein the oxide material comprises silicon dioxide.

3. The microelectronic device according to claim 1, which further comprises a gaseous material adjacent to the oxide material.

4. The microelectronic device according to claim 1, wherein the oxide material does not contain silicon nitride.

5. The microelectronic device according to claim 1, wherein the oxide material contacts the channel material and the conductive contacts.

6. The microelectronic device according to any one of claims 1 to 5, wherein the diameter of the channel material at a position between the adjacent stacks is larger than the diameter at a position within the adjacent stacks.

7. The microelectronic device according to any one of claims 1 to 5, wherein an upper portion of the conductive contact comprises a protruding portion that extends further from a lower stack in the stack than other portions of the conductive contact.

8. The microelectronic device according to any one of claims 1 to 5, wherein the oxide material is positioned between the conductive contacts of adjacent pillars.

9. The microelectronic device according to any one of claims 1 to 5, which further comprises a conductive material adjacent to the oxide material and located between the conductive contacts of adjacent pillars.

10. A method of forming a microelectronic device, the method comprises: forming a first stack of channel material comprising a stack of alternating layers of a first material and a second material, the channel material extending through the alternating layers; forming a nitride material adjacent to the first stack; forming an opening in the nitride material and forming a conductive contact in the opening; removing the nitride material; forming an oxide material adjacent to the conductive contact; and forming a second stack adjacent to the oxide material, the second stack comprising alternating layers of the first material and the second material.

11. The method according to claim 10, wherein forming the first stack comprises: forming the stack comprising the alternating layers of the first material and the second material; forming an opening through the stack; and forming the channel material within the opening.

12. The method according to claim 10, wherein forming the first stack comprises: forming the stack comprising the alternating layers of the first material and the second material; removing a portion of the second material to form a groove; and forming a conductive material in the groove.

13. The method according to claim 10, wherein forming an oxide material adjacent to the conductive contact includes forming silicon dioxide adjacent to the conductive contact.

14. The method according to any one of claims 10 to 13, further comprising forming a conductive material in contact with the oxide material between the first stack and the second stack.

15. The method according to any one of claims 10 to 13, wherein removing the nitride material and forming the second stack adjacent to the oxide material includes removing all of the nitride material between the first stack and the second stack.

16. An electronic system, which comprises: a first stack and a second stack, each of the first stack and the second stack comprising: a stack of alternating layers of conductive material and insulating material; and a pillar including channel material extending through the alternating layers of the conductive material and the insulating material; a conductive contact between the channel material of the pillar of the first stack and the channel material of the pillar of the second stack; and an oxide material adjacent to the conductive contact and located between the first stack and the second stack, wherein the position between the first stack and the second stack does not contain silicon nitride.

17. The electronic system according to claim 16, further comprising a gas including one or both of oxygen and nitrogen located between the first stack and the second stack.

18. The electronic system according to claim 16, wherein the thickness of the oxide material is greater than the thickness of the layer of the conductive material or the layer of the insulating material.

19. The electronic system according to claim 16, wherein the first stack and the second stack include memory cell strings.

20. The electronic system according to any one of claims 16 to 19, further comprising a dielectric material adjacent to the channel material, an electrode material adjacent to the dielectric material, and another dielectric material adjacent to the electrode material.

21. The electronic system according to claim 20, wherein the another dielectric material is positioned between the electrode material and the conductive material of the alternating layers.

22. The electronic system according to any one of claims 16 to 19, wherein the oxide material directly contacts a lower portion of the first stack and an upper portion of the second stack.

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