Command control methods, circuits, devices and related equipment

Abstract

This invention provides an instruction control method, circuit, device, and related equipment. The method includes: acquiring instruction information of a thread bundle to be processed, the thread bundle corresponding to a work item to be processed; determining, based on the instruction information, the number of thread bundles already acquired within a synchronous thread bundle group to which the thread bundle to be processed belongs, wherein the thread bundles within the synchronous thread bundle group are executed synchronously; determining whether the number of thread bundles matches a first preset value, wherein the first preset value is the total number of thread bundles within the synchronous thread bundle group to which the thread bundle to be processed belongs, and the first preset value is less than the number of work items within a work group to which the work item to be processed belongs; if they match, controlling the instruction execution of all thread bundles within the synchronous thread bundle group. This method can expand the types of tasks that a graphics processor can handle.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of data computing, specifically to an instruction control method, circuit, device, and related equipment. Background Technology

[0002] A graphics processing unit (GPU) is a microprocessor specifically designed for image and graphics-related computational tasks. Due to its high parallel processing capabilities, it has a significant advantage in performing block-parallel processing algorithms.

[0003] When a graphics processing unit (GPU) performs parallel data processing, memory barrier instructions are needed to control the progress of data processing. For example, in a GPU, all threads processed by the same computing core must reach a fixed node before subsequent instructions can be executed, thereby avoiding logical confusion caused by different data processing progress of different threads.

[0004] However, the hardware limitations of a single computing core restrict the number of threads that can process synchronously within that core, thus limiting the types of tasks a graphics processing unit (GPU) can handle. Therefore, providing an instruction processing method to expand the types of tasks a GPU can handle has become a pressing technical problem for those skilled in the art. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide an instruction control method, circuit, device, and related equipment that can expand the types of tasks that a graphics processor can handle.

[0006] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions.

[0007] In a first aspect, embodiments of the present invention provide an instruction control method, comprising:

[0008] Obtain instruction information for a thread bundle to be processed, wherein the thread bundle to be processed corresponds to a work item to be processed;

[0009] Based on the instruction information, determine the number of thread bundles already acquired within the synchronous thread bundle group to which the thread bundle to be processed belongs, and execute the thread bundles within the synchronous thread bundle group synchronously.

[0010] Determine whether the number of thread bundles matches a first preset value, wherein the first preset value is the number of all thread bundles in the synchronization thread bundle group to which the thread bundle to be processed belongs, and the first preset value is less than the number of work items in the work group to which the work item to be processed belongs.

[0011] If a match is found, the instructions controlling the execution of all thread bundles within the synchronized thread bundle group are executed.

[0012] Optionally, the method further includes:

[0013] If there is a mismatch, determine whether the thread bundle to be processed corresponds to the last work item in the work group to which the work item to be processed belongs. If so, control the execution of instructions for all thread bundles in the synchronization thread bundle group.

[0014] Optionally, determining the number of thread bundles within the synchronization thread bundle group to which the thread bundle to be processed belongs, based on the instruction information, includes:

[0015] Based on the instruction information, determine the synchronization thread bundle group to which the thread bundle to be processed belongs;

[0016] Update the number of acquired thread bundles in the synchronization thread bundle group based on the number of thread bundles to be processed.

[0017] The updated number of thread bundles is used as the number of thread bundles in the synchronization thread bundle group.

[0018] Optionally, in the step of determining the number of thread bundles within the synchronization thread bundle group to which the thread bundle to be processed belongs based on the instruction information, before the step of determining the synchronization thread bundle group to which the thread bundle to be processed belongs based on the instruction information, the method further includes:

[0019] Determine whether the instruction corresponding to the instruction information includes a thread bundle group barrier instruction. The thread bundle group barrier instruction is used to enable the thread bundle to be processed to execute synchronously with thread bundles belonging to the same synchronization thread bundle group; wherein, the thread bundle group barrier instruction includes the first preset value.

[0020] If so, execute the step of determining the synchronization thread bundle group to which the thread bundle to be processed belongs based on the instruction information.

[0021] Optionally, the extended field of the thread bundle barrier instruction includes switch information. When the first preset value is greater than or equal to the number of work items in the work group to which the work item to be processed belongs, the thread bundle barrier instruction is set to a closed state.

[0022] Optionally, when the value of the extended field of the thread bundle barrier instruction is equal to the second preset value, it indicates that the thread bundle barrier instruction is in a closed state.

[0023] Optionally, determining whether the number of thread bundles matches a first preset value includes:

[0024] Determine whether the number of thread bundles is greater than or equal to a first preset value. If so, the number of thread bundles matches the first preset value.

[0025] Secondly, embodiments of the present invention also provide an instruction control circuit, comprising:

[0026] The instruction information acquisition unit is used to acquire instruction information of the thread bundle to be processed, wherein the thread bundle to be processed corresponds to a work item to be processed.

[0027] The synchronization determination unit is configured to determine, based on the instruction information, the number of thread bundles already acquired within the synchronization thread bundle group to which the thread bundle to be processed belongs, and the thread bundles within the synchronization thread bundle group are executed synchronously; and to determine whether the number of thread bundles matches a first preset value, wherein the first preset value is the number of all thread bundles within the synchronization thread bundle group to which the thread bundle to be processed belongs, and the first preset value is less than the number of work items within the work group to which the work item to be processed belongs.

[0028] The instruction execution control unit is used to control the instruction execution of all thread bundles in the synchronized thread bundle group when the number of thread bundles matches a first preset value.

[0029] Optionally, the synchronization determination unit includes an electrically connected quantity determination subunit and a first multiplexer, wherein the quantity determination subunit is used to determine the number of thread bundles already acquired within the synchronization thread bundle group to which the thread bundle to be processed belongs, and to determine whether the number of thread bundles matches a first preset value, and outputs a first control signal when the number of thread bundles matches the first preset value; the first multiplexer is used to output an enable signal when the first control signal is acquired.

[0030] Optionally, the synchronization determination unit further includes a work item determination subunit. The work item determination subunit is used to determine whether the thread bundle to be processed corresponds to the last work item in the work group to which the work item to be processed belongs when the number of thread bundles does not match a first preset value, and outputs a second control signal when the thread bundle to be processed corresponds to the last work item in the work group to which the work item to be processed belongs; the first multiplexer is used to output an enable signal when the second control signal is acquired.

[0031] Optionally, the instruction execution control unit includes a second multiplexer, which is used to issue execution instructions for the thread bundles within the synchronized thread bundle group when an enable signal is received.

[0032] Optionally, the instruction information acquisition unit includes an instruction decoding module, which decodes the instructions.

[0033] Thirdly, embodiments of the present invention also provide an instruction control device, comprising:

[0034] The instruction information acquisition module is used to acquire instruction information of the thread bundle to be processed, wherein the thread bundle to be processed corresponds to a work item to be processed;

[0035] The synchronization determination module is used to determine, based on the instruction information, the number of thread bundles already acquired in the synchronization thread bundle group to which the thread bundle to be processed belongs, and the thread bundles in the synchronization thread bundle group are executed synchronously; and to determine whether the number of thread bundles matches a first preset value, wherein the first preset value is the number of all thread bundles in the synchronization thread bundle group to which the thread bundle to be processed belongs, and the first preset value is less than the number of work items in the work group to which the work item to be processed belongs.

[0036] The instruction execution control module is used to control the instruction execution of all thread bundles in the synchronized thread bundle group when the number of thread bundles matches a first preset value.

[0037] Fourthly, embodiments of the present invention also provide a graphics processor, including: an instruction scheduling module, the instruction scheduling module being configured to execute the above-described instruction control method.

[0038] Fifthly, embodiments of the present invention also provide a computer device, including: at least one memory and at least one processor; the memory stores one or more computer-executable instructions, and the processor invokes the one or more computer-executable instructions to execute the above-described instruction control method.

[0039] In a sixth aspect, embodiments of the present invention also provide a storage medium storing one or more computer-executable instructions, which are used to execute the above-described instruction control method.

[0040] This invention provides an instruction control method, circuit, device, and related equipment. The method includes: acquiring instruction information of a thread bundle to be processed, the thread bundle to be processed corresponding to a work item to be processed; determining the number of thread bundles in a synchronous thread bundle group to which the thread bundle to be processed belongs, based on the instruction information, wherein the thread bundles in the synchronous thread bundle group are executed synchronously; determining whether the number of thread bundles matches a first preset value, wherein the first preset value is less than the number of work items in the work group to which the work item to be processed belongs; if they match, controlling the thread bundles in the synchronous thread bundle group to synchronize.

[0041] As can be seen, in this embodiment of the invention, by grouping thread bundles, when the number of acquired thread bundles in the synchronous thread bundle group to which the thread bundle to be processed belongs matches the total number of thread bundles in the synchronous thread bundle group to which the thread bundle to be processed belongs, synchronous execution of all thread bundles in the synchronous thread bundle group is achieved. This eliminates the need to execute thread bundles corresponding to all work items of the same computing kernel simultaneously, allowing all thread bundles of the same computing kernel to be executed in groups without being limited by the hardware resources of the computing kernel. Therefore, the computing kernel in this embodiment of the invention can handle workgroups of various decomposition types. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of a method for decomposing a computational task;

[0044] Figure 2 This is a schematic diagram of the structure of a graphics processor provided in an embodiment of the present invention;

[0045] Figure 3 A schematic diagram of the allocation process for a matrix multiplication workgroup provided in an embodiment of the present invention;

[0046] Figure 4 Provided for embodiments of the present invention Figure 3 Another diagram illustrating the allocation process for the working group;

[0047] Figure 5 A flowchart illustrating the instruction control method provided in an embodiment of the present invention;

[0048] Figure 6 A flowchart illustrating step S110 provided in an embodiment of the present invention;

[0049] Figure 7 This is a schematic diagram of the structure of a thread bundle barrier instruction provided in an embodiment of the present invention;

[0050] Figure 8 A schematic diagram of the structure of an instruction control circuit provided in an embodiment of the present invention;

[0051] Figure 9 A block diagram of an instruction control device provided in an embodiment of the present invention;

[0052] Figure 10 A block diagram of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0053] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0054] It is understandable that when a graphics processing unit (GPU) processes a computational task in parallel, it can decompose the computational task into corresponding task items, so that each component in the GPU used for data processing can perform corresponding calculations based on each task item.

[0055] Figure 1 An exemplary diagram illustrates a method for decomposing a computational task. A computational task can be represented by a thread grid, which can be decomposed into multiple workgroups. Each workgroup can be further decomposed into multiple work items, where a work item can be understood as the smallest computational unit defined within a workgroup.

[0056] Figure 2 An exemplary schematic diagram of the structure of a graphics processing unit (GPU) is shown, such as... Figure 2 As shown, the graphics processor may include:

[0057] Multiple computing cores (also known as compute units, CUs), wherein a workgroup is assigned to a compute core to execute while the graphics processor is processing computational tasks. And a workgroup scheduling module for allocating and scheduling workgroups.

[0058] A computing kernel includes an instruction scheduling module and multiple parallel computing units (PUs in the diagram).

[0059] The parallel computing unit (PU) is the smallest unit in the GPU that performs parallel computing. It can include a set of vector-general-purpose register slices (VGPR) and a set of arithmetic and logic units (ALU). Specifically, the parallel computing unit can be a single-instruction-multiple-data (SIMD) structure, which can control multiple threads in a thread bundle to perform the same operation simultaneously by executing a single instruction.

[0060] A work item can be assigned to a parallel computing unit (PU) within a workgroup. The operation of a work item corresponds to a thread bundle (Line, also known as a wave or warp) within the PU. A thread bundle (Line) is a collection of multiple threads that execute in minimal parallelism on the GPU hardware; a thread bundle can contain up to 64 threads (Thread is the smallest unit of execution in the GPU). The instruction scheduling module is used to schedule the execution process of each thread bundle and manage the thread bundle queue corresponding to each work item.

[0061] refer to Figure 3 The diagram illustrates the allocation and processing of a matrix multiplication workgroup. It shows a workgroup for calculating the multiplication of matrices A and B, decomposed into four work items, each corresponding to a thread bundle: Line0, Line1, Line2, and Line3. Line0 calculates the data in matrix block A0 of matrix A and matrix block B0 of matrix B; Line1 calculates the data in matrix block A0 of matrix A and matrix block B1 of matrix B; Line2 calculates the data in matrix block A1 of matrix A and matrix block B0 of matrix B; and Line3 calculates the data in matrix block A1 of matrix A and matrix block B1 of matrix B.

[0062] Understandably, within the computing core of a graphics processing unit (GPU), the number of parallel computing units used to process thread bundles is limited, as is the capacity of the vector general-purpose register slice. Furthermore, the existence of memory barrier instructions necessitates that all thread bundles allocated to the same computing core must execute synchronously. Therefore, the number of work items decomposed within a workgroup assigned to a computing core needs to be adapted to the hardware configuration of the computing core, ensuring that each work item can be allocated corresponding hardware resources, thereby achieving synchronous execution of the thread bundles corresponding to each work item.

[0063] For example, when a computing core contains four parallel computing units, the workgroups allocated on that computing core can include a maximum of four work items. Otherwise, when executing instructions that interact with the parallel computing units, the hardware will not be able to distinguish the interaction data corresponding to multiple work items on the same parallel computing unit.

[0064] Clearly, the computing kernel in the above scheme is limited in the types of workgroups it can handle.

[0065] Based on this, embodiments of the present invention provide an instruction control method, circuit, device, and related equipment. The method includes: acquiring instruction information of a thread bundle to be processed, the thread bundle to be processed corresponding to a work item to be processed; determining the number of thread bundles in a synchronous thread bundle group to which the thread bundle to be processed belongs, based on the instruction information, wherein the thread bundles in the synchronous thread bundle group are executed synchronously; determining whether the number of thread bundles matches a first preset value, wherein the first preset value is less than the number of work items in the work group to which the work item to be processed belongs; if they match, controlling the thread bundles in the synchronous thread bundle group to synchronize.

[0066] As can be seen, in this embodiment of the invention, by grouping thread bundles, when the number of acquired thread bundles in the synchronous thread bundle group to which the thread bundle to be processed belongs matches the total number of thread bundles in the synchronous thread bundle group to which the thread bundle to be processed belongs, synchronous execution of all thread bundles in the synchronous thread bundle group is achieved. This eliminates the need to execute thread bundles corresponding to all work items of the same computing kernel simultaneously, allowing all thread bundles of the same computing kernel to be executed in groups without being limited by the hardware resources of the computing kernel. Therefore, the computing kernel in this embodiment of the invention can handle workgroups of various decomposition types.

[0067] It should be noted that in this embodiment of the invention, thread bundles are executed synchronously based on different synchronization thread bundle groups. This is applied to instructions executed to the same node within the same workgroup, thereby realizing the grouped execution of instructions located at the same node within the same workgroup. Memory barrier instructions are also effective. When it is necessary for all instructions within the same workgroup to be executed to the same node, memory barrier instructions can be used for control, thereby controlling the progress of thread bundles as a whole and avoiding possible logical confusion.

[0068] In an optional example, refer to Figure 2 The graphics processing unit shown contains four parallel computing units (PUs) within a single computing core, and correspondingly, this computing core can execute a maximum of four thread bundles (Lines) simultaneously. Figure 4 The diagram shown illustrates an allocation process, specifically for... Figure 3The diagram shows a matrix multiplication task group for calculating matrices A and B. Within this task, the same task group is divided into eight work items, with corresponding thread bundles: Line0, Line1, Line2, Line3, Line4, Line5, Line6, and Line7. In this embodiment, the thread bundles corresponding to these eight work items can be divided into two synchronous thread bundle groups, each containing four thread bundles. For example, Line0, Line1, Line2, and Line3 can be grouped into one synchronous thread bundle group LG1, and Line4, Line5, Line6, and Line7 can be grouped into another synchronous thread bundle group LG2.

[0069] Combination Figure 5 An exemplary flowchart of an instruction control method provided in an embodiment of the present invention is shown. The instruction control method can be applied to the instruction scheduling module of a computing kernel, such as... Figure 5 As shown, the instruction control method may include:

[0070] Step S100: Obtain instruction information for a thread bundle to be processed, wherein the thread bundle to be processed corresponds to a work item to be processed;

[0071] Here, the thread bundle to be processed corresponds to one of the multiple work items belonging to a work group, and this work item can be called the work item to be processed. Based on the corresponding processing process, the parallel computing unit can issue an instruction for the corresponding thread bundle to be processed. Accordingly, the instruction scheduling module can accept the instruction and obtain the instruction information of the instruction as the instruction information for the thread bundle to be processed.

[0072] In an optional example, the instruction can be parsed by the instruction scheduling module to obtain the instruction information.

[0073] Step S110: Based on the instruction information, determine the number of thread bundles already acquired within the synchronization thread bundle group to which the thread bundle to be processed belongs;

[0074] The thread bundles within the synchronized thread bundle group are executed synchronously.

[0075] The instruction information may include information about the issuer of the instruction, control information for the instruction, and feedback address information for the instruction. For example, in a read instruction, the corresponding instruction information may include information about the issuer that issued the instruction, control information for controlling the read operation, and feedback address information for writing the read data.

[0076] The thread bundle to be processed can belong to a synchronous thread bundle group, and the thread bundles in the synchronous thread bundle group are used for synchronous execution. After obtaining the instruction information of the thread bundle to be processed, the timing of executing the thread bundles in the synchronous thread bundle group can be determined based on the number of thread bundles that have been obtained and belong to the synchronous thread bundle group.

[0077] The thread bundles within the synchronization thread bundle group to which the acquired thread bundle to be processed belongs include the acquired thread bundles to be processed.

[0078] Step S120: Determine whether the number of thread bundles matches the first preset value;

[0079] Wherein, the first preset value is the number of all thread bundles in the synchronous thread bundle group to which the thread bundle to be processed belongs, which can also be understood as the maximum number of thread bundles in the synchronous thread bundle group. The first preset value is less than the number of work items in the work group to which the work item to be processed belongs.

[0080] It is understood that the embodiments of the present invention can be executed based on scenarios where there are a large number of work items in the work group to which the work item to be processed belongs. Accordingly, the number of all thread bundles in the synchronization thread bundle group to which the thread bundle to be processed belongs is less than the number of work items in the work group to which the work item to be processed belongs, thereby grouping the work items in the work group to which the work item to be processed belongs to avoid possible runtime errors.

[0081] In this embodiment of the invention, it can be determined whether all thread bundles in the synchronization thread bundle group to which the thread bundle to be processed belongs have been executed to the same node based on the number of thread bundles already acquired. Thus, when the number of acquired thread bundles is equal to the total number of thread bundles in the synchronization thread bundle group, subsequent instructions are executed.

[0082] In an optional example, step S120 may further be: determining whether the number of thread bundles is greater than or equal to a first preset value; if so, the number of thread bundles matches the first preset value, thereby performing synchronization operations on other thread bundles besides the thread bundle to be processed.

[0083] In this step, if the judgment result is yes, then step S130 is executed; if the judgment result is no, then the instruction of the thread bundle to be processed can continue to be executed. Alternatively, in an optional example, step S140 can be executed to further judge the thread bundle to be processed.

[0084] Step S130: Execute instructions to control all thread bundles within the synchronized thread bundle group;

[0085] It is understood that when the judgment result is yes, the instructions controlling the execution of all thread bundles within the synchronized thread bundle group are executed.

[0086] Based on the method in this example, it is possible to synchronously execute instructions of all thread bundles located within the same synchronous thread bundle, thereby enabling the grouping of thread bundles corresponding to work items within the same workgroup without being limited by the hardware resources of the computing kernel.

[0087] Step S140: Determine whether the thread bundle to be processed corresponds to the last work item in the work group to which the work item to be processed belongs.

[0088] It is understandable that when grouping work items in a workgroup, the work items are not necessarily evenly distributed. For example, when a workgroup is broken down into 6 work items, the thread bundles corresponding to these 6 work items can be divided into 2 synchronous thread bundle groups, one group containing 4 thread bundles and the other group containing 2 thread bundles.

[0089] Accordingly, it should be determined whether the thread bundle to be processed corresponds to the last work item in the work group to which the work item to be processed belongs. If so, it indicates that the thread bundle to be processed is the last thread bundle in that node. Thus, step S130 can be executed to control the execution of instructions of all thread bundles in the synchronization thread bundle group. If not, the instructions of the thread bundle to be processed continue to be executed.

[0090] It can be seen that when multiple work items in the same workgroup have thread bundles belonging to different synchronization thread bundle groups, the synchronous execution of different synchronization thread bundle groups can be achieved respectively.

[0091] It should be noted that in this embodiment of the invention, thread bundles are executed synchronously based on different synchronization thread bundle groups to ensure that instructions within the same workgroup that are executed to the same node are executed together. This achieves grouped execution of instructions located at the same node within the same workgroup. Memory barrier instructions are also effective, used to ensure that subsequent instructions are executed only after it has been determined that all grouped instructions within the same workgroup have been executed to the same node. This allows for overall control of the thread bundle's progress and avoids potential logical confusion. For example, for... Figure 4 In the workgroup, threads in synchronized thread bundle group LG1 are executed synchronously, and threads in synchronized thread bundle group LG2 are executed synchronously. When it is necessary for all instructions in the same workgroup to be executed simultaneously, a memory barrier instruction is used so that synchronized thread bundle group LG1 and synchronized thread bundle group LG2 both reach the same node before subsequent instructions are executed.

[0092] In this embodiment of the invention, by grouping thread bundles, when the number of acquired thread bundles in the synchronous thread bundle group to which the thread bundle to be processed belongs matches the total number of thread bundles in the synchronous thread bundle group, synchronous execution of all thread bundles in the synchronous thread bundle group is achieved. This eliminates the need to execute thread bundles corresponding to all work items of the same computing kernel simultaneously, allowing all thread bundles of the same computing kernel to be executed in groups without being limited by the hardware resources of the computing kernel. Therefore, the computing kernel in this embodiment of the invention can handle workgroups of various decomposition types.

[0093] In an optional implementation, thread synchronization within the same synchronized thread bundle can be performed based on thread bundle group barrier instructions. (See reference) Figure 6 An exemplary flowchart illustrating step S110 of an embodiment of the present invention is shown. Specifically, in an optional example, step S110 may include:

[0094] Step S111: Determine whether the instruction corresponding to the instruction information includes a thread bundle barrier instruction;

[0095] The thread bundle group barrier instruction is used to enable the thread bundle to be processed to execute synchronously with thread bundles belonging to the same synchronous thread bundle group.

[0096] It is understandable that when the instruction corresponding to the instruction information includes a thread bundle group barrier instruction, the execution of other instructions of the thread bundle can be suspended. When all the thread bundles in the synchronous thread bundle group to which the thread bundle belongs have executed to the thread bundle group barrier instruction, the subsequent instructions will be executed synchronously.

[0097] For example, when it is necessary to read data from an external storage device, the issued instruction can include the thread bundle group barrier instruction, thereby controlling all threads in the synchronized thread bundle group to execute the thread bundle group barrier instruction before performing the data reading operation.

[0098] It should be noted that when reading data from external storage devices, if the number of work items in the workgroup exceeds the maximum number of thread bundles that the computing kernel can execute synchronously, some work item thread bundles need to reuse hardware resources. If progress control is still only performed using memory barrier instructions, the read data should be stored in the corresponding computing kernel's storage unit (e.g., VGPR), resulting in logical data storage confusion. When thread bundles running repeatedly on the parallel computing unit retrieve the read data, the hardware cannot distinguish the data corresponding to multiple work items on the same parallel computing unit, thus generating corresponding read errors.

[0099] In this embodiment, thread bundles used for synchronization are grouped based on thread bundle group barrier instructions. After a group of thread bundle instructions is executed, the instructions of the synchronization thread bundle groups corresponding to other work items belonging to the same work group are executed to avoid the above-mentioned operational errors.

[0100] In one optional example, the number of thread bundle group barrier instructions obtained that belong to the same synchronization thread bundle group can be used to determine whether all thread bundles in the synchronization thread bundle group have been executed to the thread bundle group barrier instruction node. Thus, when the number of obtained thread bundle group barrier instructions is equal to the number of all thread bundles in the synchronization thread bundle group, subsequent instructions are executed.

[0101] Specifically, the thread bundle group barrier instruction includes a first preset value, which indicates the number of all thread bundles within the synchronization thread bundle group to which the thread bundle to be processed belongs. For example, if the synchronization thread bundle group can be set to include 4 thread bundles, then the number of thread bundles within the acquired synchronization thread bundle group can be determined based on the acquired thread bundle group barrier instruction, and then a judgment can be made based on the number of thread bundles.

[0102] In this step, if the instruction corresponding to the instruction information includes a thread bundle group barrier instruction, then step S112 is executed. If the instruction corresponding to the instruction information does not include a thread bundle group barrier instruction, then the instruction for the thread bundle to be processed continues to be executed.

[0103] It should be noted that this example uses the thread bundle group barrier instruction as an example to illustrate the solution. In other examples, other instructions can also be used to synchronize the execution of threads within the thread bundle group. For example, if the parsed instruction information contains instructions for interacting with external data, the corresponding steps can be automatically executed to achieve synchronized execution of threads within the thread bundle group. This invention does not impose specific limitations on this.

[0104] Step S112: Determine the synchronization thread bundle group to which the thread bundle to be processed belongs based on the instruction information.

[0105] After obtaining the instruction information, the synchronization thread bundle group of the thread bundle to be processed can be determined first, and then the number of thread bundles in the synchronization thread bundle group can be determined.

[0106] Specifically, the synchronous thread bundle group to which the thread bundle to be processed belongs can be determined based on the instruction issuer information and the instruction control information in the instruction information.

[0107] Step S113: Update the number of acquired thread bundles in the synchronization thread bundle group according to the number of thread bundles to be processed;

[0108] Since the thread bundle to be processed belongs to the synchronized thread bundle group, the number of thread bundles already acquired in the synchronized thread bundle group should be updated accordingly, so that the updated number of thread bundles shall prevail.

[0109] In this example, taking the number of thread bundles to be processed as 1, the number of thread bundles already acquired in the synchronization thread bundle group can be increased by 1 to obtain the updated number of thread bundles.

[0110] Step S114: Use the updated number of thread bundles as the number of thread bundles in the synchronization thread bundle group.

[0111] After the number of thread bundles is updated, the updated number of thread bundles is used as the number of thread bundles in the synchronization thread bundle group, and subsequent judgments are performed.

[0112] It can be seen that, based on the thread bundle group barrier instruction, the thread synchronization within the same synchronized thread bundle group can be effectively achieved, thereby enabling the grouped execution of instructions located on the same node within the same workgroup.

[0113] It should be noted that the above instruction control method can be applied to matrix operations, such as matrix multiplication. It can control the reading instructions when reading matrix information, so that the threads in the same synchronization thread group can execute the reading of matrix information synchronously.

[0114] Furthermore, based on the synchronous reading of matrix information, instruction control can be further implemented to determine the repetitive information that the thread bundles within the same synchronous thread bundle group need to read. This allows for data broadcasting after the matrix information is read, thereby improving data processing efficiency.

[0115] In an optional example, the thread bundle barrier instruction can be modified based on the format defined for memory barrier instructions, in conjunction with reference to [reference needed]. Figure 7 The diagram illustrates the structure of a thread bundle barrier instruction. In this instruction, bits 23 to 29 store instruction type data, indicating that the instruction is a thread bundle barrier instruction. Bits 16 to 22 store OP7, i.e., the instruction opcode. Bits 0 to 15 can be defined as an extended field. In this extended field, it can be defined that when it equals a first preset value, the instruction control method is executed based on the first preset value. At the same time, the thread bundle barrier instruction can also be set with switch information. For example, it can be defined that when it equals a second preset value, it represents that the thread bundle barrier instruction is in a closed state.

[0116] It is understood that when the first preset value is greater than or equal to the number of work items in the work group to which the work item to be processed belongs, that is, when the number of all thread bundles in the synchronized thread bundle group is greater than the number of work items in the work group, it is considered that the hardware resources of the graphics processor can synchronously execute the thread bundles corresponding to all work items in the work group, thereby the thread bundle group barrier instruction can be set to the closed state.

[0117] Specifically, taking a first preset value of 4 and a second preset value of 0 as an example, the definition of the extended domain includes:

[0118] Extended field = 0: Barrier all waves in the workgroup (blocks all thread waves in the workgroup)

[0119] Extended domain = 4: barrier 4 waves in the workgroup (blocking 4 thread bundles in the workgroup)

[0120] Understandably, the extended field can also define other values ​​to support more synchronization modes.

[0121] In an optional example, refer to Figure 8 The diagram shows a schematic of an instruction control circuit, which includes:

[0122] The instruction information acquisition unit 210 is used to acquire instruction information of a thread bundle to be processed, wherein the thread bundle to be processed corresponds to a work item to be processed.

[0123] The synchronization determination unit 220 is used to determine, according to the instruction information, the number of thread bundles already acquired in the synchronization thread bundle group to which the thread bundle to be processed belongs, and the thread bundles in the synchronization thread bundle group are executed synchronously; and to determine whether the number of thread bundles matches a first preset value, wherein the first preset value is the number of all thread bundles in the synchronization thread bundle group to which the thread bundle to be processed belongs, and the first preset value is less than the number of work items in the work group to which the work item to be processed belongs.

[0124] The instruction execution control unit 230 is used to control the execution of instructions for all thread bundles in the synchronized thread bundle group when the number of thread bundles matches a first preset value.

[0125] Specifically, the instruction information acquisition unit 210 includes an instruction decoding module, which decodes the instruction to obtain the instruction information of the received instruction of the thread bundle to be processed.

[0126] The synchronization determination unit 220 is connected to the instruction information acquisition unit 210. The synchronization determination unit 220 may include a quantity determination subunit 221 and a first multiplexer 222 (vertical trapezoid in the figure) connected to each other. The quantity determination subunit 221 can be used to determine the number of acquired thread bundles within the synchronization thread bundle group to which the thread bundle to be processed belongs, and to determine whether the number of thread bundles matches a first preset value. If the number of thread bundles matches the first preset value, a first control signal is output. In an optional example, the quantity determination subunit 221 may include a counter to determine the number of acquired thread bundles within the synchronization thread bundle group to which the thread bundle to be processed belongs. The first multiplexer 222 outputs an enable signal when it acquires the first control signal.

[0127] The synchronization determination unit 220 may further include a work item determination subunit 223. The work item determination subunit 223, when the number of thread bundles does not match a first preset value, determines whether the thread bundle to be processed corresponds to the last work item in the work group to which the work item to be processed belongs, and outputs a second control signal when the thread bundle to be processed corresponds to the last work item in the work group to which the work item to be processed belongs. Correspondingly, the first multiplexer 222 outputs an enable signal when it acquires the second control signal.

[0128] The instruction execution control unit 230 is connected to the synchronization determination unit and the instruction information acquisition unit, and may include a second multiplexer 231 (the horizontal trapezoid in the figure). The second multiplexer 231 is used to issue an execution instruction (e.g., a work item enable instruction) for the thread bundle within the synchronization thread bundle group when an enable signal is obtained.

[0129] The instruction execution control unit 230 can also issue execution instructions for the thread bundles within the synchronization thread bundle group when it receives an enable signal and simultaneously receives a corresponding instruction execution end signal. For example, when executing... Figure 4 When executing the two sets of synchronized thread bundles LG1 and LG2, it is necessary to obtain the enable signal and the signal indicating the end of instruction execution of the synchronized thread bundle LG1 at the same time, and then issue the execution instruction of the thread bundle in the synchronized thread bundle LG2.

[0130] Specifically, during the operation of the instruction control circuit, each Line (thread bundle) within the workgroup is first decoded. If the instruction is a Barrier (thread bundle group barrier instruction), the next instruction for that Line will be blocked until the release condition of the Barrier instruction is met. Taking a synchronous thread bundle group of four Lines as an example, a counter counts how many Lines have executed the Barrier instruction. When the counter value is less than the extended field value of the Barrier instruction, the Line that has executed the Barrier instruction is blocked. The circuit will then select a new Line that has not yet executed the Barrier instruction for execution. When the counter value is greater than or equal to the extended field value of the Barrier instruction, the blocked Line is released, and the circuit will no longer select a new Line for execution until a new group of Lines executes the Barrier instruction.

[0131] The instruction control device provided in the embodiments of the present invention will be described below. The device described below can be considered as the functional modules required by a computer device to implement the instruction control method provided in the embodiments of the present invention. The device described below can be referred to in correspondence with the method described above.

[0132] Figure 9 A block diagram of an instruction control device provided in an embodiment of the present invention is shown. Figure 9 As shown, the device may include:

[0133] The instruction information acquisition module 300 is used to acquire instruction information of the thread bundle to be processed, wherein the thread bundle to be processed corresponds to a work item to be processed.

[0134] The synchronization determination module 310 is used to determine, according to the instruction information, the number of thread bundles already acquired in the synchronization thread bundle group to which the thread bundle to be processed belongs, and the thread bundles in the synchronization thread bundle group are executed synchronously; and to determine whether the number of thread bundles matches a first preset value, wherein the first preset value is the number of all thread bundles in the synchronization thread bundle group to which the thread bundle to be processed belongs, and the first preset value is less than the number of work items in the work group to which the work item to be processed belongs.

[0135] The instruction execution control module 320 is used to control the instruction execution of all thread bundles in the synchronous thread bundle group when the number of thread bundles matches a first preset value.

[0136] In some embodiments, the command control device further includes:

[0137] The work item determination module 330 is used to determine whether the thread bundle to be processed corresponds to the last work item in the work group to which the work item to be processed belongs when the number of thread bundles does not match a first preset value; the instruction execution control module 320 is used to control the instruction execution of all thread bundles in the synchronization thread bundle group when the thread bundle to be processed corresponds to the last work item in the work group to which the work item to be processed belongs.

[0138] In some embodiments, the synchronization determination module 310 is configured to determine the number of thread bundles within the synchronization thread bundle group to which the thread bundle to be processed belongs, based on the instruction information, including:

[0139] Based on the instruction information, determine the synchronization thread bundle group to which the thread bundle to be processed belongs;

[0140] Update the number of acquired thread bundles in the synchronization thread bundle group based on the number of thread bundles to be processed.

[0141] The updated number of thread bundles is used as the number of thread bundles in the synchronization thread bundle group.

[0142] In some embodiments, the synchronization determination module 310 is configured to determine the number of thread bundles within the synchronization thread bundle group to which the thread bundle to be processed belongs, based on the instruction information, and further includes:

[0143] Determine whether the instruction corresponding to the instruction information includes a thread bundle group barrier instruction. The thread bundle group barrier instruction is used to enable the thread bundle to be processed to execute synchronously with thread bundles belonging to the same synchronization thread bundle group; wherein, the thread bundle group barrier instruction includes the first preset value.

[0144] If so, execute the step of determining the synchronization thread bundle group to which the thread bundle to be processed belongs based on the instruction information.

[0145] In some embodiments, the extended domain of the thread bundle barrier instruction includes switch information, and the thread bundle barrier instruction is set to a closed state when the first preset value is greater than or equal to the number of work items in the work group to which the work item to be processed belongs.

[0146] In some embodiments, when the value of the extended field of the thread bundle barrier instruction is equal to a second preset value, it indicates that the thread bundle barrier instruction is in a closed state.

[0147] In some embodiments, the synchronization determination module 310 is used to determine whether the number of thread bundles matches a first preset value, including:

[0148] Determine whether the number of thread bundles is greater than or equal to a first preset value. If so, the number of thread bundles matches the first preset value.

[0149] This invention also provides a graphics processor, and in some embodiments, the architecture of the graphics processor can be combined with... Figure 2 As shown, the graphics processor may include an instruction scheduling module. This instruction scheduling module can be configured to execute the instruction control method provided in this embodiment of the invention.

[0150] This invention also provides a computer device, which may include at least one memory and at least one processor; the memory stores one or more computer-executable instructions, and the processor invokes the one or more computer-executable instructions to execute the instruction control method provided in this invention.

[0151] Optional, Figure 10 A block diagram of a computer device provided in an embodiment of the present invention is shown, such as Figure 10 As shown, the mobile terminal may include: at least one processor 1, at least one communication interface 2, at least one memory 3, and at least one communication bus 4;

[0152] In this embodiment of the invention, the number of processor 1, communication interface 2, memory 3, and communication bus 4 is at least one, and processor 1, communication interface 2, and memory 3 communicate with each other through communication bus 4; obviously, the communication connection diagram of processor 1, communication interface 2, memory 3, and communication bus 4 shown in the figure is only optional.

[0153] Optionally, communication interface 2 can be an interface for a communication module used for network communication;

[0154] Processor 1 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention.

[0155] Memory 3 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0156] The memory 3 stores one or more computer-executable instructions, and the processor 1 calls the one or more computer-executable instructions to execute the instruction control method provided in this embodiment of the invention.

[0157] This invention also provides a storage medium that stores one or more computer-executable instructions, which are used to execute the instruction control method described above.

[0158] The foregoing describes multiple embodiments of the present invention. The optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed or made public by the present invention.

[0159] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A command control method, characterized in that, include: Obtain instruction information for a thread bundle to be processed, wherein the thread bundle to be processed corresponds to a work item to be processed; Based on the instruction information, determine the number of thread bundles already acquired within the synchronous thread bundle group to which the thread bundle to be processed belongs, and execute the thread bundles within the synchronous thread bundle group synchronously. Determine whether the number of thread bundles matches a first preset value, wherein the first preset value is the number of all thread bundles in the synchronization thread bundle group to which the thread bundle to be processed belongs, and the first preset value is less than the number of work items in the work group to which the work item to be processed belongs. If a match is found, the instructions of all thread bundles within the synchronized thread bundle group are executed. If a match is not found, it is determined whether the thread bundle to be processed corresponds to the last work item in the work group to which the work item to be processed belongs. If so, the instructions of all thread bundles within the synchronized thread bundle group are executed.

2. The method according to claim 1, characterized in that, The step of determining the number of thread bundles within the synchronization thread bundle group to which the thread bundle to be processed belongs, based on the instruction information, includes: Based on the instruction information, determine the synchronization thread bundle group to which the thread bundle to be processed belongs; Update the number of acquired thread bundles in the synchronization thread bundle group based on the number of thread bundles to be processed. The updated number of thread bundles is used as the number of thread bundles in the synchronization thread bundle group.

3. The method according to claim 2, characterized in that, In the step of determining the number of thread bundles within the synchronization thread bundle group to which the thread bundle to be processed belongs based on the instruction information, before the step of determining the synchronization thread bundle group to which the thread bundle to be processed belongs based on the instruction information, the method further includes: Determine whether the instruction corresponding to the instruction information includes a thread bundle group barrier instruction. The thread bundle group barrier instruction is used to enable the thread bundle to be processed to execute synchronously with thread bundles belonging to the same synchronization thread bundle group; wherein, the thread bundle group barrier instruction includes the first preset value. If so, execute the step of determining the synchronization thread bundle group to which the thread bundle to be processed belongs based on the instruction information.

4. The method according to claim 3, characterized in that, The extended domain of the thread bundle barrier instruction includes switch information. When the first preset value is greater than or equal to the number of work items in the work group to which the work item to be processed belongs, the thread bundle barrier instruction is set to the off state.

5. The method according to claim 4, characterized in that, When the value of the extended field of the thread bundle barrier instruction is equal to the second preset value, it means that the thread bundle barrier instruction is in a closed state.

6. The method according to claim 1, characterized in that, The step of determining whether the number of thread bundles matches a first preset value includes: Determine whether the number of thread bundles is greater than or equal to a first preset value. If so, the number of thread bundles matches the first preset value.

7. A command control circuit, characterized in that, include: The instruction information acquisition unit is used to acquire instruction information of the thread bundle to be processed, wherein the thread bundle to be processed corresponds to a work item to be processed. The synchronization determination unit is used to determine, based on the instruction information, the number of thread bundles already acquired in the synchronization thread bundle group to which the thread bundle to be processed belongs, and the thread bundles in the synchronization thread bundle group are executed synchronously. Furthermore, it is determined whether the number of thread bundles matches a first preset value, wherein the first preset value is the number of all thread bundles in the synchronization thread bundle group to which the thread bundle to be processed belongs, and the first preset value is less than the number of work items in the work group to which the work item to be processed belongs. The instruction execution control unit is configured to control the instruction execution of all thread bundles in the synchronized thread bundle group when the number of thread bundles matches a first preset value, and to control the instruction execution of all thread bundles in the synchronized thread bundle group when the number of thread bundles does not match the first preset value, and the thread bundle to be processed is the last work item in the work group to which the work item to be processed belongs.

8. The circuit according to claim 7, characterized in that, The synchronization determination unit includes an electrical connection quantity determination subunit and a first multiplexer. The quantity determination subunit is used to determine the number of thread bundles already acquired within the synchronization thread bundle group to which the thread bundle to be processed belongs, and to determine whether the number of thread bundles matches a first preset value. When the number of thread bundles matches the first preset value, the subunit outputs a first control signal. The first multiplexer is used to output an enable signal when the first control signal is acquired.

9. The circuit according to claim 8, characterized in that, The synchronization determination unit further includes a work item determination subunit. The work item determination subunit is used to determine whether the thread bundle to be processed corresponds to the last work item in the work group to which the work item to be processed belongs when the number of thread bundles does not match a first preset value. When the thread bundle to be processed corresponds to the last work item in the work group to which the work item to be processed belongs, the subunit outputs a second control signal. The first multiplexer is used to output an enable signal when the second control signal is acquired.

10. The circuit according to claim 8 or 9, characterized in that, The instruction execution control unit includes a second multiplexer, which is used to issue execution instructions for thread bundles within a synchronized thread bundle group when an enable signal is received.

11. The circuit according to claim 7, characterized in that, The instruction information acquisition unit includes an instruction decoding module, which decodes the instructions.

12. A command control device, characterized in that, include: The instruction information acquisition module is used to acquire instruction information of the thread bundle to be processed, wherein the thread bundle to be processed corresponds to a work item to be processed; The synchronization determination module is used to determine the number of acquired thread bundles in the synchronization thread bundle group to which the thread bundle to be processed belongs, based on the instruction information, and the thread bundles in the synchronization thread bundle group are executed synchronously. Furthermore, it is determined whether the number of thread bundles matches a first preset value, wherein the first preset value is the number of all thread bundles in the synchronization thread bundle group to which the thread bundle to be processed belongs, and the first preset value is less than the number of work items in the work group to which the work item to be processed belongs. The instruction execution control module is used to control the instruction execution of all thread bundles in the synchronous thread bundle group when the number of thread bundles matches a first preset value, and to determine whether the thread bundle to be processed corresponds to the last work item in the work group to which the work item to be processed belongs when the number of thread bundles does not match the first preset value; if so, to control the instruction execution of all thread bundles in the synchronous thread bundle group.

13. A graphics processor, characterized in that, include: An instruction scheduling module, configured to execute the instruction control method as described in any one of claims 1-6.

14. A computer device, characterized in that, include: At least one memory and at least one processor; The memory stores one or more computer-executable instructions, and the processor invokes the one or more computer-executable instructions to execute the instruction control method as described in any one of claims 1-6.

15. A storage medium, characterized in that, The storage medium stores one or more computer-executable instructions, which are used to execute the instruction control method as described in any one of claims 1-6.

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