Method and device for verifying consistency of hardware and software of multimedia chip

Abstract

The application discloses a hardware and software consistency verification method and device of a multimedia chip, and relates to the technical field of chip development.The method comprises the following steps: obtaining test case parameter information set by a user through a template table, converting the test case parameter information through a first script to generate a cfg configuration information file; converting the cfg configuration information file through a second script to generate a hardware configuration file based on a UVM sequence and a software configuration file based on a C program; obtaining a multimedia file based on binary code provided by an FPGA software verification platform, combining the software configuration file based on the C program to generate a software configuration file in a txt format; and inputting the software configuration file in the txt format and the hardware configuration file based on the UVM sequence as input excitation into an EDA simulation verification platform. By using the application, the accuracy and reliability of test scene reproduction are improved, and the chip development period is shortened.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip development technical field, and particularly relates to a multimedia chip software and hardware consistency verification method and device. BACKGROUND

[0002] In the silicon front-end verification of a multimedia chip (IC), FPGA (Field Programmable Gate Array) verification and EDA (Electronic Design Automation) verification undertake different roles and functions and complement each other. FPGA verification and EDA verification adopt different verification devices and verification methods: FPGA verification is a mainstream and mature chip verification method of current prototype verification, which verifies the function of a chip by transplanting RTL to a field programmable gate array, and can start the development of a driver after the basic function verification of the chip is passed; EDA verification is to instantiate a DUT (Device Under Test) in a verification environment, and verify the function or performance of the DUT by applying excitation to the DUT, taking the commonly used UVM (Universal Verification Methodology) verification in chip design as an example, the test case is based on the system verilog language, and the excitation is generated in the form of UVM sequence.

[0003] Since it is difficult to debug in FPGA software verification, in actual FPGA debugging, scene reproduction is usually performed by using EDA simulation to facilitate bug positioning and debugging, and the above process often needs EDA simulation verification personnel to establish a test case (case) consistent with the corresponding FPGA scene to facilitate fast scene reproduction. On the one hand, the establishment of the test case consumes time and energy, resulting in some repetitive labor, and the transmission of configuration information consumes a lot of time iteration, affecting the verification efficiency of the whole chip; on the other hand, the configuration information may be inconsistent when the verification personnel writes the test case, resulting in an increased error probability.

[0004] To sum up, how to quickly generate test information consistent with the FPGA scene to improve the efficiency of debug is a technical problem to be solved at present. SUMMARY

[0005] The present application aims at overcoming the deficiencies of the prior art, and provides a hardware and software consistency verification method and device for a multimedia chip. By using the present application, EDA simulation verification personnel no longer need to manually convert and establish test cases in FPGA software verification (in order to reproduce the test scene corresponding to the test case in the aforementioned FPGA software verification in the EDA simulation verification platform), but only need to fill in the test case information through the template table, thereby improving the accuracy and reliability of the test scene reproduction, and further shortening the chip development cycle.

[0006] To achieve the above-mentioned goal, the present application provides the following technical solutions:

[0007] A hardware and software consistency verification method for a multimedia chip, comprising the following steps:

[0008] Obtain the test case information set by the user through a template table, and convert the test case information in the table through a first script to generate a configuration information file in cfg text format;

[0009] Convert the aforementioned configuration information file in cfg text format through a second script to generate a hardware configuration file based on UVM sequence and a software configuration file based on C program, respectively;

[0010] Obtain a multimedia file based on binary code provided by an FPGA software verification platform, and generate a software configuration file in txt format after combining the aforementioned software configuration file based on C program;

[0011] Input the aforementioned software configuration file in txt format as input excitation to an EDA simulation verification platform, and input the aforementioned hardware configuration file based on UVM sequence as input excitation to the EDA simulation verification platform.

[0012] Further, the first script and the second script are python scripts, and the multimedia file is a bin format file.

[0013] Further, the template table is an excel table or a word table;

[0014] The preset fields of the template table at least include a case number name field, a test input information field, a case function field, and a test output information field.

[0015] Further, the multimedia chip is a video processing chip, at this time, the test input information field includes an input size field and an input format field, and the test output information field includes an output size field and an output format field.

[0016] Further, a test list including a plurality of test cases is established according to application scene requirements of the multimedia chip, and parameters and functions of each test case in the test list are subdivided; different application scenes correspond to different test cases, and different test cases correspond to different template tables.

[0017] Further, an application scene list is also provided, and the application scenes in the application scene list have a mapping relationship with the test cases in the test list.

[0018] The application scene list is output through a user graphical interface, and a target application scene selected by the user from the application scene list is collected; after the test case information corresponding to the target application scene is obtained according to the mapping relationship, the template table of the test case is obtained and output for the user to set the test case information through the template table.

[0019] The application further provides a hardware and software consistency verification device of a multimedia chip, comprising the following structure:

[0020] A test case information collection module is configured to obtain the test case information set by the user through the template table;

[0021] A first information conversion module is configured to convert the test case information in the table through a first script to generate a configuration information file in a cfg text format;

[0022] A second information conversion module is configured to convert the configuration information file in the cfg text format through a second script to generate a hardware configuration file based on a UVM sequence and a software configuration file based on a C program, respectively;

[0023] An input stream data configuration module is configured to obtain a multimedia file based on a binary code provided by an FPGA software verification platform, generate a software configuration file in a txt format in combination with the software configuration file based on the C program, input the software configuration file in the txt format as an input stimulus to an EDA simulation verification platform, and input the hardware configuration file based on the UVM sequence as an input stimulus to the EDA simulation verification platform.

[0024] Further, the first script and the second script are python scripts, and the multimedia file is a bin format file.

[0025] Further, the template table is an excel table or a word table; and the preset fields of the template table at least include a case number name field, a test input information field, a case function field and a test output information field.

[0026] Further, the multimedia chip is a video processing chip, at this time, the test input information field includes an input size field and an input format field, and the test output information field includes an output size field and an output format field.

[0027] Compared with the prior art, the present application has the following advantages and positive effects: the test case information set by the user is obtained through the template table, the test case information is automatically converted into the hardware and software configuration information file by using the script extraction, and the input excitation for the EDA simulation verification platform test is automatically generated based on the binary code of the multimedia file provided by the software verification party. According to the present application, the EDA simulation verification personnel no longer need to manually convert and establish the test case in the FPGA software verification (in order to reproduce the test scene corresponding to the test case in the FPGA software verification in the EDA simulation verification platform), but only need to fill in the test case information through the template table, thereby improving the accuracy and reliability of the test scene reproduction, and further shortening the chip development cycle. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 An information processing schematic diagram of the hardware and software consistency verification method of the multimedia chip provided by the embodiment of the present application.

[0029] Figure 2 A data structure schematic diagram of the template table provided by the embodiment of the present application.

[0030] Figure 3 An information processing schematic diagram of the software configuration file combined with the multimedia file to generate the input data in txt format.

[0031] Figure 4 A UVM verification component in the EDA simulation verification platform provided by the embodiment of the present application. DETAILED DESCRIPTION

[0032] The multimedia chip software and hardware consistency verification method and device disclosed by the present application is further described in detail below in combination with the drawings and specific embodiments. It should be noted that the technical features or combinations of technical features described in the following embodiments should not be considered in isolation, and they can be combined with each other to achieve better technical effects. In the drawings of the following embodiments, the same reference numerals appearing in different drawings represent the same features or components, which can be applied to different embodiments. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0033] It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to the present specification are only used to cooperate with the content disclosed in the specification, so that those skilled in the art can understand and read, and are not used to limit the conditions for implementing the application. Any modification of structure, change of proportion relationship or adjustment of size, which does not affect the effect and purpose of the application, should be within the scope of the disclosed technology. The scope of the preferred embodiments of the present application includes additional implementations, in which the functions can be performed in a substantially simultaneous manner or in reverse order according to the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0034] Techniques, methods, and equipment known to those of ordinary skill in the relevant art can not be discussed in detail, but in appropriate cases, the techniques, methods, and equipment should be considered part of the specification. In all examples shown and discussed here, any specific value should be interpreted as merely exemplary, not as a limitation. Therefore, other examples of exemplary embodiments can have different values. Embodiments

[0035] The present application provides a multimedia chip software and hardware consistency verification method, comprising the following steps:

[0036] S100, obtaining the test case information set by the user through the template table, and converting the test case information in the table through the first script to generate a configuration information file in cfg text format.

[0037] Referring to Figure 1 As shown, the first script can be a python script, and the test case information in the table is extracted through the first python script to generate a configuration information file in cfg text format. The test case information includes parameter information and function line information of the test case.

[0038] The configuration information file in cfg text format can include parameter configuration information file and register configuration information file, such as Figure 1Parameter configuration information file x.cfg and register configuration information file x_register.cfg in the parameter configuration information file x.

[0039] The x.cfg file stores two items of parameter and parameter value.

[0040] As an example but not limitation, the file format of the parameter configuration information file x.cfg can be as follows:

[0041] xxx_work = 1

[0042] xxx_lane_num = 2

[0043] xxx_data_type = 6'h2b

[0044] ...

[0045] The xxx_register.cfg file stores two items of register address and register value, which are used to configure the register address of the chip register and the corresponding register value information. The above two items are stored in the configuration information file in a list form, the first column is used to store the register address, and the second column is used to store the corresponding register value.

[0046] As an example but not limitation, the file format of the register configuration information file xxx_register.cfg can be as follows:

[0047] 0x100 0x1

[0048] 0x200 0x2

[0049] 0x300 0xf

[0050] ...

[0051] The template table can adopt an excel table or a word table.

[0052] Specifically, the preset fields of the template table at least include a case number name field, a test input information field, a case function field and a test output information field.

[0053] Referring to Figure 2 As shown in the video processing chip, for example, the case number of the test case in a certain scene is case0, the test input information field can include an input size field and an input format field, the input size information is 1080p, and the input format information is yuv420; the function information is function A enabled, function B enabled, and function C enabled; the test output information field can include an output size field and an output format field, the output size information is 720p, and the output format information is yuv422.

[0054] In the embodiment, preferably, a test list including multiple test cases can be established according to the application scene requirement of the multimedia chip, and parameters and function lines of each test case are subdivided in the test list; different application scenes correspond to different test cases, and different test cases correspond to different template tables.

[0055] In addition, an application scene list can be provided, and the application scenes in the application scene list have a mapping relationship with the test cases in the test list. At this time, the application scene list can be output through a user graphical interface (GUI), and the target application scene selected by the user from the application scene list is collected. After the test case information corresponding to the target application scene is obtained according to the mapping relationship, the template table of the test case is obtained and output for the user to set the test case information through the template table.

[0056] S200, the configuration information file in the cfg text format is converted by the second script to generate a hardware configuration file based on a UVM sequence and a software configuration file based on a C program.

[0057] The second script can also be a python script, and the configuration information file in the cfg text format is converted by the second python script to obtain the hardware configuration file and the software configuration file of the test case.

[0058] The hardware configuration file is a UVM sequence based on a system verilog language. The UVM sequence is a UVMsequence. In the test case (case) of UVM (universal verification methodology), running different test cases is essentially running different sequences, i.e., sequence (seq). Each test case corresponds to a respective sequence.

[0059] Taking seq1 as an example, the following language is used to describe in the UVM test case: Uvm_config_db#(uvm_object_wrapper)::set(this,”env.i_agent.sequencer.run_phase”,”default_sequence”, seq1::get_type()).

[0060] The software configuration file is a C program based on a software description language C language.

[0061] S300, a multimedia file based on binary code provided by an FPGA software verification platform is obtained, and a software configuration file in a txt format is generated after combining the software configuration file based on the C program.

[0062] The multimedia file is a binary code provided for FPGA software verification, usually in a bin format file, such as Figure 3 x.bin in

[0063] In combination with the aforementioned C program-based software configuration file and the multimedia file x.bin, the binary code in the multimedia file x.bin can be converted by a software model to generate a software configuration file in txt format, such as Figure 3 x_a.txt, x_b.txt, x_c.txt in The generated x_a.txt, x_b.txt, x_c.txt files can be directly input into an EDA simulation verification platform for verification testing.

[0064] According to the configuration information of the aforementioned example parameter configuration information file x.cfg and register configuration information file x_register.cfg, the x_a.txt file format is as follows: 01000010 00110110 00111111

[0068] …

[0069] The x_b.txt file format is as follows: 0100 0011 0011

[0073] …

[0074] The x_c.txt file format is as follows: 01 10 11

[0078] …

[0079] S400, input the aforementioned txt format software configuration file as an input stimulus into an EDA simulation verification platform, and input the aforementioned UVM sequence-based hardware configuration file as an input stimulus into an EDA simulation verification platform.

[0080] Referring to Figure 4 , sequence1 (or seq1), sequence2 (or seq2), sequence3 (or seq3), and sequence4 (or seq4) correspond to different test cases respectively, and the input stimulus is various input sequences.

[0081] As an example and not a limitation, taking sequence1 as an example, the format of Seq1 can be as follows:

[0082] Class seq1 extends uvm_sequence_item;

[0083] Rand int intput_size;

[0084] Rand int input_type;

[0085] Rand int input_func_a;

[0086] Rand int input_func_b;

[0087] Rand int input_func_c

[0088] `uvm_object_utils_begin(seq1)

[0089] `uvm_field_int()

[0090] `uvm_field_int()

[0091] `uvm_field_int()

[0092] `uvm_field_int()

[0093] `uvm_field_int()

[0094] `uvm_object_utils_end

[0095] Constraint valid{

[0096] Payload.size inside {[1:10]};

[0097] }

[0098] Function new(string name=””);

[0099] Super.new(name);

[0100] endfunction

[0101] endclass

[0102] When running the test case of UVM in the EDA simulation verification platform, the verification component can usually include the following components: register model, sequence, adapter, sequencer, driver and monitor, In_agent for encapsulation and instantiation of the sequencer, driver and monitor, and all the above components are derived from the class in UVM.

[0103] The sequence sequence is used to generate transaction data transaction according to the test case.

[0104] The adapter adapter is used to convert the register model into the form matched with the sequencer through the variable generated by the sequence.

[0105] The sequencer sequencer is used to manage the sequence generator and generate valid sequence.

[0106] The driver driver is used to apply test excitation and data conversion to the DUT port.

[0107] The monitor monitor is used to monitor the output data of the DUT and perform data conversion.

[0108] The above technical solution provided by the present application is especially suitable for the case of reproducing the test case of the FPGA software verification platform through the EDA simulation verification platform, and the verification personnel only need to fill in the corresponding template table to quickly generate the software and hardware configuration information consistent with the FPGA test case, without manually configuring the software and hardware information, and the consistency of the FPGA test excitation and the EDA test excitation information can be ensured, so as to quickly reproduce the scene and debug.

[0109] Another embodiment of the present application also provides a soft and hardware consistency verification device of a multimedia chip.

[0110] The soft and hardware consistency verification device comprises a test case information acquisition module, a first information conversion module, a second information conversion module and an input stream data configuration module.

[0111] The test case information acquisition module is used to acquire the test case information set by the user through the template table.

[0112] The first information conversion module is used to convert the test case information in the table through the first script to generate a configuration information file in the cfg text format.

[0113] The second information conversion module is configured to convert the configuration information file in the cfg text format by using a second script to generate a hardware configuration file based on a UVM sequence and a software configuration file based on a C program.

[0114] The input stream data configuration module is configured to obtain a multimedia file based on binary code provided by an FPGA software verification platform, combine the software configuration file based on the C program to generate a software configuration file in a txt format, input the software configuration file in the txt format as input stimulus to an EDA simulation verification platform, and input the hardware configuration file based on the UVM sequence as input stimulus to the EDA simulation verification platform.

[0115] In the embodiment, the first script and the second script are python scripts, and the multimedia file is a bin format file. The template table is an excel table or a word table, and the preset fields of the template table include at least a case number name field, a test input information field, a case function field, and a test output information field. Taking a video processing chip as an example, the test input information field includes an input size field and an input format field, and the test output information field includes an output size field and an output format field.

[0116] In the embodiment, a test list including a plurality of test cases can also be established according to the application scenario requirements of the multimedia chip, and parameters and function rows of each test case in the test list are subdivided. Different application scenarios correspond to different test cases, and different test cases correspond to different template tables.

[0117] In addition, an application scenario list can also be provided, and the application scenarios in the application scenario list have a mapping relationship with the test cases in the test list. At this time, the application scenario list can be output through a user graphical interface (GUI), and the target application scenario selected by the user from the application scenario list can be collected. After the test case information corresponding to the target application scenario is obtained according to the mapping relationship, the template table of the test case is obtained and output for the user to set the test case information through the template table.

[0118] Other technical features refer to the foregoing embodiments, which will not be described here.

[0119] In the above description, the disclosure of the application is not intended to be limited to the aspects described. Rather, the components can be selectively combined in any number of ways, as operative and optional, within the scope of the intended target protection of the disclosure. In addition, terms like "include," "comprise," and "have" should be construed as inclusive or open-ended, rather than exclusive or closed, unless specifically defined as such. All technical, scientific, or other terms have the meaning as understood by those skilled in the art, unless specifically defined to the contrary. Common terms found in dictionaries are not to be interpreted too ideally or too unrealistically in the context of the relevant technical documents, unless specifically defined as such by the disclosure. Any changes, modifications, made by those of ordinary skill in the art based on the above disclosure are within the scope of protection of the claims.

Claims

1. A method for verifying software and hardware consistency of a multimedia chip, characterized in that The method comprises the steps of: obtaining test case information set by a user through a template table, and converting the test case information in the table through a first script to generate a configuration information file in a cfg text format; preset fields of the template table at least include a case number name field, a test input information field, a case function field and a test output information field; wherein a test list including multiple test cases is established according to multimedia chip application scenario requirements, and parameters and function rows are subdivided for each test case in the test list; different application scenarios correspond to different test cases, and different test cases correspond to different template tables; converting the aforementioned configuration information file in the cfg text format through a second script to respectively generate a hardware configuration file based on a UVM sequence and a software configuration file based on a C program; obtaining a multimedia file based on binary code provided by an FPGA software verification platform, and generating a software configuration file in a txt format in combination with the aforementioned software configuration file based on the C program; inputting the aforementioned software configuration file in the txt format as an input stimulus into an EDA simulation verification platform, and inputting the aforementioned hardware configuration file based on the UVM sequence as an input stimulus into the EDA simulation verification platform.

2. The method of claim 1, wherein: The first script and the second script are python scripts, and the multimedia file is a bin format file.

3. The method of claim 1, wherein: The template table is an excel table or a word table.

4. The method of claim 3, wherein: The multimedia chip is a video processing chip, at this time, the test input information field includes an input size field and an input format field, and the test output information field includes an output size field and an output format field.

5. The method of claim 1, wherein: An application scenario list is further provided, and application scenarios in the application scenario list have a mapping relationship with test cases in the test list; an application scenario list is output through a user graphical interaction interface, a target application scenario selected by a user from the application scenario list is collected, test case information corresponding to the target application scenario is obtained according to the aforementioned mapping relationship, and a template table of the test case is output for the user to set test case information through the template table.

6. A device for verifying hardware-software consistency of a multimedia chip, characterized in that The method comprises the steps of: a test case information collection module for obtaining test case information set by a user through a template table; preset fields of the template table at least include a case number name field, a test input information field, a case function field and a test output information field; wherein a test list including multiple test cases is established according to multimedia chip application scenario requirements, and parameters and function rows are subdivided for each test case in the test list; different application scenarios correspond to different test cases, and different test cases correspond to different template tables; a first information conversion module for converting test case information in a table through a first script to generate a configuration information file in a cfg text format; a second information conversion module for converting the aforementioned configuration information file in the cfg text format through a second script to respectively generate a hardware configuration file based on a UVM sequence and a software configuration file based on a C program; The input stream data configuration module is configured to obtain a multimedia file based on binary code provided by an FPGA software verification platform, combine a software configuration file based on a C program to generate a software configuration file in a txt format, input the software configuration file in the txt format as an input stimulus to an EDA simulation verification platform, and input a hardware configuration file based on a UVM sequence as an input stimulus to the EDA simulation verification platform.

7. The apparatus of claim 6, wherein: The first script and the second script are python scripts, and the multimedia file is a bin format file.

8. The apparatus of claim 6, wherein: The template table is an excel table or a word table.

9. The apparatus of claim 8, wherein: The multimedia chip is a video processing chip, and at this time, the test input information field includes an input size field and an input format field, and the test output information field includes an output size field and an output format field.

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